chiselverify / chiselverify Star 160 Code Issues Pull requests Discussions A dynamic verification library for Chisel. testing coverage scala verification chisel constrained-random-verification functional-coverage bus-functional-model chisel-test timed-assertions Updated Nov 9, 2024 Scala
akaeba / eSpiMasterBfm Star 8 Code Issues Pull requests Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master master vhdl intel testbench vhdl93 bfm vhdl-code espi bus-functional-model enhanced-spi Updated Jun 21, 2025 VHDL
sjo99-kr / DDRMemoryController Star 3 Code Issues Pull requests Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench system-verilog memory-controller bus-functional-model uvm-verification Updated Feb 23, 2026 Verilog