M.S. Student | Computer Architecture | interconnection networks | RISC-V | CSNL @ KAIST
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KAIST
- South Korea, Daejoen
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13:01
(UTC +09:00) - https://icn.kaist.ac.kr/
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CVA6-branch-predictor-extension
CVA6-branch-predictor-extension PublicForked from openhwgroup/cva6
Implementation of TAGE and GShare branch predictors for the CVA6 (Ariane) open-source RISC-V core.
Assembly
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DDRMemoryController
DDRMemoryController PublicMulti-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench
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16x16_systolic-array-processor
16x16_systolic-array-processor Publicsystolic_array_processor for CNN, DNN, GEMM (16x16 PE array)
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Preprocessing_Accelerator_for_Frequency_domain_based_CNN_Models
Preprocessing_Accelerator_for_Frequency_domain_based_CNN_Models PublicPreprocessing_Accelerator for Frequency domain CNN model
Verilog 1
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