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1. MrPoloGit/LiveLLNN MrPoloGit/LiveLLNN Public

   LiveLLNN is a heterogeneous architecture designed for run-time reconfiguration on SoC FPGAs based on LUT-Based Logic Neural Networks (LLNNs).

   Jupyter Notebook 1

2. ORFS-SMT-RepairTiming ORFS-SMT-RepairTiming Public

   A PyZ3-based closed-loop SMT solver for optimal buffer resizing in OpenROAD-flow-scripts using non-linear formal timing models.

   Python

3. vivaldi vivaldi Public

   A mini FPGA synthesizer built for the Nexys Video Artix-7 FPGA from Digilent.

   SystemVerilog 5

4. manim-digital manim-digital Public

   A Manim library that implements combinational and sequential digital logic components.

   Python 1

5. FPGA-UART-ALU FPGA-UART-ALU Public

   Forked from sifferman/verilog_template

   An FPGA ALU that can perform 32-bit addition, multiplication, and division over UART.

   SystemVerilog

6. rphlhuang.github.io rphlhuang.github.io Public

   Raphael's personal website, portfolio, and blog.

   JavaScript 1