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Update the X2-85 gpu's register protect count configuration with the correct count_max value to avoid blocking the entire MMIO region from the UMD. Protect configurations are a bit complicated on A8xx. There are 2 set of protect registers with different counts: Global and Pipe-specific. The last-span-unbound feature is available only on the Pipe-specific protect registers. Due to this, we cannot use the BUILD_BUG sanity check for A8x protect configurations, so remove the A840 entry from there. Link: https://lore.kernel.org/lkml/20260225-glymur-protect-fix-v1-1-0deddedf9277@oss.qualcomm.com/ Fixes: 01ff3bf ("drm/msm/a8xx: Add support for Adreno X2-85 GPU") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
This reverts commit 54bffff.
… Port" This reverts commit 5586aac.
…nodes" This reverts commit 3484af1.
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Revert below changes causing display issues on all targets :
Revert "FROMLIST: drm/msm: enable separate_gpu_kms by default
Revert "FROMLIST: arm64: dts: qcom: lemans-ride: Enable mdss1 display
Revert "FROMLIST: arm64: dts: qcom: lemans: add mdss1 display device
Also update tech/mm/gpu branch to support GPU on Glymur