- Waterloo, Canada
- in/eric-pearson-linked-in
Pinned Loading
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croc
croc PublicForked from pulp-platform/croc
forked tiny tapeout tracable riscV soc with build and sim environments. I've integrated a nist800-232 cipher adding control and dma in systemverilog with tests in C.
SystemVerilog
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FlatFury
FlatFury PublicPCIe fpga project on the LiteFury Xilinx Artix-7 fpga dev board, Verilog created from scratch with a simplified flat hierarchy using the AXI4 pcie core.
Verilog
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sha256-fpga
sha256-fpga PublicSet of increasing speed SHA2 hash designs fitting in an Altera 10M25 fpga. Measured 8 Mhz SHA2 double hashes. I can see the steps to get to peta/terra hash rate realm asics.
SystemVerilog
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CrossLink_LCD
CrossLink_LCD PublicLattice FPGA verilog design using a CrossLink D-PHY cores for Mipi Dsi Tx of 2x4lane LCD display, total 8Gbps
Verilog
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launch_control_chip
launch_control_chip PublicA model rocket launch control chip in a 3mm x 3mm package. A better push button?
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