gdb/amdgcn: Dynamically select which bits to use to hold CORE_ADDR

[amd-shahab]

Relies on dbgapi's PR: Add AMD_DBGAPI_PROCESS_INFO_SIGNIFICANT_ADDRESS_BITS

To support the various address-spaces from AMDGPU, amdgpu-tdep implements gdbarch hooks to encode the address-space ID in the top bits of a CORE_ADDR. Exactly which bits to use out of the CORE_ADDR is currently statically built into GDB. However, for AMDGPU, the "flat" address-space (also known as generic) is configured by the driver, and it is not part of the ABI which bits out of the top byte are used or not to carry meaning.

To address this, librocm-dbgapi >= 0.80 provides a mask of bits which carry information for the current process. GDB can use this mask to deduce which bits out of a CORE_ADDR can safely be used to encode address space IDs.

This patch provides an implementation for GDB to encode the address-space ID into the top bits reported as unused by dbgapi. Note that dbgapi reports which bits can be used by any address space, including "global". This means that the unused bits must be the top ones, and we should account for the fact that "normalized" addresses are sign extended in the top bits. This means that the top bits of a valid address can be either all 0s or all 1s. For this reason, we do not support encoding an address space ID whose binary representation on the available bits of a CORE_ADDR is all 1s, so the all 1s case can be reserved for sign-extended addresses.

Bug: AIROCGDB-26
Change-Id: I4cbb41a922443d64003ebc6415547c02ab43afcf

[amd-shahab]

• rebase
• use .try_emplace() instead of .emplace()
• rename invalidate_cache...() to amdgpu_observer_inferior_appeared().