Implement T1-1-41: erf erf erf.py pixel_shuffle pixel_shuffle matrix…#774

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LaiQuan-conquer wants to merge 27 commits intoInfiniTensor:mainfrom

LaiQuan-conquer:2025-autumn-LaiQuan-conquer-T1-1-41

Commits on Dec 13, 2025

Implement T1-1-41: erf erf erf.py pixel_shuffle pixel_shuffle matrix_power matrix_power erfc erfc erfinv erfinv
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Commits on Mar 5, 2026

Merge branch 'InfiniTensor:main' into 2025-autumn-LaiQuan-conquer-T1-1-41
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Add implementation plan

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Ignore RLCR state directory

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Commits on Mar 6, 2026

Ignore and untrack plan.md for RLCR

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Build: fix nv-gpu compile blockers

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MatrixPower: GPU-resident NVIDIA implementation

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PixelShuffle: make NVIDIA kernel stride-aware

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MatrixPower: handle strided tensors on NVIDIA

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Harness: add infiniop-vs-torch NVIDIA validator

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infiniop: export C API for erf/erfc/erfinv/matrix_power/pixel_shuffle

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TensorDescriptor: fix hasBroadcastDim indexing

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Harness: add negative stride validation cases

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cpu: fix matrix_power workspace/params; include <limits> for erfinv

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matrix_power/pixel_shuffle: tighten CPU descriptor validation; fix metax/moore dtype bytes

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metax/moore: validate pixel_shuffle; sync matrix_power H2D; erfinv domain NaN

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metax: close namespaces in erf/erfc/erfinv

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matrix_power(cpu): use provided workspace for fp16/bf16

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infiniop.h: include erf/erfc/erfinv/matrix_power/pixel_shuffle

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validate: use current CUDA device; improve Windows path regex

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pixel_shuffle: include metax/moore kernel common for cuda_bfloat16

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matrix_power: include metax/moore kernel common for CHECK_* macros

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cuda: fix erf/erfc/erfinv half/bf16 float conversion

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nvidia: no-op on empty tensors for matrix_power/pixel_shuffle

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metax/moore: pixel_shuffle no-op on empty outputs

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matrix_power(cpu): no workspace needed for n==0

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Commits on Mar 7, 2026

Enable infiniop dispatch fallback and hybrid erfinv

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