diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 39001ce99c023..268fc6b05d4b4 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -11,30 +11,6 @@ &{/} { model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; - dp2-connector { - compatible = "dp-connector"; - label = "eDP2"; - type = "full-size"; - - port { - dp2_connector_in: endpoint { - remote-endpoint = <&mdss1_dp0_out>; - }; - }; - }; - - dp3-connector { - compatible = "dp-connector"; - label = "eDP3"; - type = "full-size"; - - port { - dp3_connector_in: endpoint { - remote-endpoint = <&mdss1_dp1_out>; - }; - }; - }; - vreg_0p9: regulator-0v9 { compatible = "regulator-fixed"; regulator-name = "VREG_0P9"; @@ -165,43 +141,6 @@ }; }; - -&mdss1 { - status = "okay"; -}; - -&mdss1_dp0 { - pinctrl-0 = <&dp2_hot_plug_det>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mdss1_dp1 { - pinctrl-0 = <&dp3_hot_plug_det>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mdss1_dp0_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&dp2_connector_in>; -}; - -&mdss1_dp1_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&dp3_connector_in>; -}; - -&mdss1_dp0_phy { - status = "okay"; -}; - -&mdss1_dp1_phy { - status = "okay"; -}; - &pcie0 { iommu-map = <0x0 &pcie_smmu 0x0 0x1>, <0x100 &pcie_smmu 0x1 0x1>, @@ -296,18 +235,6 @@ }; &tlmm { - dp2_hot_plug_det: dp2-hot-plug-det-state { - pins = "gpio104"; - function = "edp2_hot"; - bias-disable; - }; - - dp3_hot_plug_det: dp3-hot-plug-det-state { - pins = "gpio103"; - function = "edp3_hot"; - bias-disable; - }; - ethernet1_default: ethernet1-default-state { ethernet1-mdc-pins { pins = "gpio20"; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index c72a01fdc75de..e020cc85089d3 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -180,30 +180,6 @@ }; }; - dp2-connector { - compatible = "dp-connector"; - label = "eDP2"; - type = "full-size"; - - port { - dp2_connector_in: endpoint { - remote-endpoint = <&mdss1_dp0_out>; - }; - }; - }; - - dp3-connector { - compatible = "dp-connector"; - label = "eDP3"; - type = "full-size"; - - port { - dp3_connector_in: endpoint { - remote-endpoint = <&mdss1_dp1_out>; - }; - }; - }; - dp-dsi0-connector { compatible = "dp-connector"; label = "DSI0"; @@ -663,50 +639,6 @@ status = "okay"; }; -&mdss1 { - status = "okay"; -}; - -&mdss1_dp0 { - pinctrl-0 = <&dp2_hot_plug_det>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&mdss1_dp0_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&dp2_connector_in>; -}; - -&mdss1_dp0_phy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l4a>; - - status = "okay"; -}; - -&mdss1_dp1 { - pinctrl-0 = <&dp3_hot_plug_det>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&mdss1_dp1_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&dp3_connector_in>; -}; - -&mdss1_dp1_phy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l4a>; - - status = "okay"; -}; - &pmm8654au_0_gpios { gpio-line-names = "DS_EN", "POFF_COMPLETE", @@ -888,18 +820,6 @@ bias-disable; }; - dp2_hot_plug_det: dp2-hot-plug-det-state { - pins = "gpio104"; - function = "edp2_hot"; - bias-disable; - }; - - dp3_hot_plug_det: dp3-hot-plug-det-state { - pins = "gpio103"; - function = "edp3_hot"; - bias-disable; - }; - io_expander_intr_active: io-expander-intr-active-state { pins = "gpio98"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 77fc3c9bd35b7..3ed95caa9ac59 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -7064,317 +7064,6 @@ }; }; - mdss1: display-subsystem@22000000 { - compatible = "qcom,sa8775p-mdss"; - reg = <0x0 0x22000000 0x0 0x1000>; - reg-names = "mdss"; - - interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "mdp0-mem", - "mdp1-mem", - "cpu-cfg"; - - resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; - - power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; - - clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP1_HF_AXI_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - iommus = <&apps_smmu 0x1800 0x402>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - status = "disabled"; - - display-controller@22001000 { - compatible = "qcom,sa8775p-dpu"; - reg = <0x0 0x22001000 0x0 0x8f000>, - <0x0 0x220b0000 0x0 0x3000>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP1_HF_AXI_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdss1_mdp_opp_table>; - power-domains = <&rpmhpd SA8775P_MMCX>; - - interrupt-parent = <&mdss1>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dpu1_intf0_out: endpoint { - remote-endpoint = <&mdss1_dp0_in>; - }; - }; - - port@1 { - reg = <1>; - - dpu1_intf4_out: endpoint { - remote-endpoint = <&mdss1_dp1_in>; - }; - }; - }; - - mdss1_mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-375000000 { - opp-hz = /bits/ 64 <375000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-575000000 { - opp-hz = /bits/ 64 <575000000>; - required-opps = <&rpmhpd_opp_turbo>; - }; - - opp-650000000 { - opp-hz = /bits/ 64 <650000000>; - required-opps = <&rpmhpd_opp_turbo_l1>; - }; - }; - }; - - mdss1_dp0_phy: phy@220c2a00 { - compatible = "qcom,sa8775p-edp-phy"; - - reg = <0x0 0x220c2a00 0x0 0x200>, - <0x0 0x220c2200 0x0 0xd0>, - <0x0 0x220c2600 0x0 0xd0>, - <0x0 0x220c2000 0x0 0x1c8>; - - clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_EDP_REF_CLKREF_EN>; - clock-names = "aux", - "cfg_ahb", - "ref"; - - #clock-cells = <1>; - #phy-cells = <0>; - - status = "disabled"; - }; - - mdss1_dp1_phy: phy@220c5a00 { - compatible = "qcom,sa8775p-edp-phy"; - - reg = <0x0 0x220c5a00 0x0 0x200>, - <0x0 0x220c5200 0x0 0xd0>, - <0x0 0x220c5600 0x0 0xd0>, - <0x0 0x220c5000 0x0 0x1c8>; - - clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_EDP_REF_CLKREF_EN>; - clock-names = "aux", - "cfg_ahb", - "ref"; - - #clock-cells = <1>; - #phy-cells = <0>; - - status = "disabled"; - }; - - mdss1_dp0: displayport-controller@22154000 { - compatible = "qcom,sa8775p-dp"; - - reg = <0x0 0x22154000 0x0 0x104>, - <0x0 0x22154200 0x0 0x0c0>, - <0x0 0x22155000 0x0 0x770>, - <0x0 0x22156000 0x0 0x09c>, - <0x0 0x22157000 0x0 0x09c>, - <0x0 0x22158000 0x0 0x09c>, - <0x0 0x22159000 0x0 0x09c>, - <0x0 0x2215a000 0x0 0x23c>, - <0x0 0x2215b000 0x0 0x23c>; - - interrupt-parent = <&mdss1>; - interrupts = <12>; - - clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; - clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel", - "stream_1_pixel", - "stream_2_pixel", - "stream_3_pixel"; - assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp0_phy 0>, - <&mdss1_dp0_phy 1>, - <&mdss1_dp0_phy 1>, - <&mdss1_dp0_phy 1>, - <&mdss1_dp0_phy 1>; - phys = <&mdss1_dp0_phy>; - phy-names = "dp"; - - operating-points-v2 = <&mdss1_dp_opp_table>; - power-domains = <&rpmhpd SA8775P_MMCX>; - - #sound-dai-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mdss1_dp0_in: endpoint { - remote-endpoint = <&dpu1_intf0_out>; - }; - }; - - port@1 { - reg = <1>; - - mdss1_dp0_out: endpoint { }; - }; - }; - - mdss1_dp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - mdss1_dp1: displayport-controller@2215c000 { - compatible = "qcom,sa8775p-dp"; - - reg = <0x0 0x2215c000 0x0 0x104>, - <0x0 0x2215c200 0x0 0x0c0>, - <0x0 0x2215d000 0x0 0x770>, - <0x0 0x2215e000 0x0 0x09c>, - <0x0 0x2215f000 0x0 0x09c>, - <0x0 0x22160000 0x0 0x09c>, - <0x0 0x22161000 0x0 0x09c>, - <0x0 0x22162000 0x0 0x23c>, - <0x0 0x22163000 0x0 0x23c>; - - interrupt-parent = <&mdss1>; - interrupts = <13>; - - clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; - clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel", - "stream_1_pixel"; - assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, - <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp1_phy 0>, - <&mdss1_dp1_phy 1>, - <&mdss1_dp1_phy 1>; - phys = <&mdss1_dp1_phy>; - phy-names = "dp"; - - operating-points-v2 = <&mdss1_dp_opp_table>; - power-domains = <&rpmhpd SA8775P_MMCX>; - - #sound-dai-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mdss1_dp1_in: endpoint { - remote-endpoint = <&dpu1_intf4_out>; - }; - }; - - port@1 { - reg = <1>; - - mdss1_dp1_out: endpoint { }; - }; - }; - - }; - }; - dispcc1: clock-controller@22100000 { compatible = "qcom,sa8775p-dispcc1"; reg = <0x0 0x22100000 0x0 0x20000>; @@ -7382,13 +7071,13 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, - <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, + <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd SA8775P_MMCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + status = "disabled"; }; ethernet1: ethernet@23000000 { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 550a53a7865eb..38561f26837e3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1759,7 +1759,7 @@ static const u32 x285_protect_regs[] = { A6XX_PROTECT_NORDWR(0x27c06, 0x0000), }; -DECLARE_ADRENO_PROTECT(x285_protect, 64); +DECLARE_ADRENO_PROTECT(x285_protect, 15); static const struct adreno_reglist_pipe a840_nonctxt_regs[] = { { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, @@ -1966,5 +1966,4 @@ static inline __always_unused void __build_asserts(void) BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); - BUILD_BUG_ON(a840_protect.count > a840_protect.count_max); } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 6474cd0d46c75..e5ab1e28851df 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -54,7 +54,7 @@ static bool modeset = true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); module_param(modeset, bool, 0600); -static bool separate_gpu_kms = true; +static bool separate_gpu_kms; MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0=single DRM device for both GPU and display (default), 1=two DRM devices)"); module_param(separate_gpu_kms, bool, 0400);