diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine-qps615.dtsi b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine-qps615.dtsi
new file mode 100644
index 000000000000..049879c430ed
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine-qps615.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&i2c18 {
+	eeprom@52 {
+		nvmem-layout {
+			mac_addr2: mac-addr@6 {
+				reg = <0x6 0x6>;
+			};
+			mac_addr3: mac-addr@c {
+				reg = <0xc 0x6>;
+			};
+		};
+	};
+};
+
+&pcieport0 {
+	pcie@0,0 {
+		pcie@3,0 {
+			pci@0,0 {
+				nvmem-cells = <&mac_addr2>;
+				nvmem-cell-names = "mac-address";
+				pinctrl-names = "default";
+				pinctrl-0 = <&aqr_intn_wol_sig>;
+				phy-rst-som-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
+				interrupts-extended = <&tlmm 56 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				qcom,always-on-supply;
+				qcom,phy-rst-delay-us = <221000>;
+
+				qcom,iommu-group = <&eth0_pci_iommu_group>;
+				eth0_pci_iommu_group: eth0_pci_iommu_group {
+					qcom,iommu-dma = "atomic";
+				};
+			};
+
+			pci@0,1 {
+				nvmem-cells = <&mac_addr3>;
+				nvmem-cell-names = "mac-address";
+				pinctrl-names = "default";
+				pinctrl-0 = <&napa_intn_wol_sig>;
+				phy-rst-som-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+				interrupts-extended = <&tlmm 57 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				qcom,always-on-supply;
+				qcom,phy-rst-delay-us = <20000>;
+
+				qcom,iommu-group = <&eth1_pci_iommu_group>;
+				eth1_pci_iommu_group: eth1_pci_iommu_group {
+					qcom,iommu-dma = "atomic";
+				};
+			};
+		};
+	};
+};
+
+&tlmm {
+	qps615_intn_wol {
+		aqr_intn_wol_sig: aqr-intn-wol-sig {
+			pins = "gpio56";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+		napa_intn_wol_sig: napa-intn-wol-sig {
+			pins = "gpio57";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
index 268fc6b05d4b..d2d544994054 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
@@ -261,3 +261,5 @@
 		output-high;
 	};
 };
+
+#include "lemans-evk-ifp-mezzanine-qps615.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine-qps615.dtsi b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine-qps615.dtsi
new file mode 100644
index 000000000000..0013dfe69a9d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine-qps615.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&eeprom1 {
+	nvmem-layout {
+		mac_addr1: mac-addr@0 {
+			reg = <0x0 0x6>;
+		};
+
+		mac_addr2: mac-addr@6 {
+			reg = <0x6 0x6>;
+		};
+	};
+};
+
+&pcieport0 {
+	pcie@0,0 {
+		pcie@3,0 {
+			pci@0,0 {
+				nvmem-cells = <&mac_addr1>;
+				nvmem-cell-names = "mac-address";
+				pinctrl-names = "default";
+				pinctrl-0 = <&aqr_intn_wol_sig>;
+				phy-rst-som-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+				interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				qcom,always-on-supply;
+				qcom,phy-rst-delay-us = <221000>;
+
+				qcom,iommu-group = <&eth0_pci_iommu_group>;
+				eth0_pci_iommu_group: eth0_pci_iommu_group {
+					qcom,iommu-dma = "atomic";
+				};
+			};
+
+			pci@0,1 {
+				nvmem-cells = <&mac_addr2>;
+				nvmem-cell-names = "mac-address";
+				pinctrl-names = "default";
+				pinctrl-0 = <&napa_intn_wol_sig>;
+				phy-rst-som-gpios = <&expander5 0 GPIO_ACTIVE_HIGH>;
+				interrupts-extended = <&tlmm 39 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				qcom,always-on-supply;
+				qcom,phy-rst-delay-us = <20000>;
+
+				qcom,iommu-group = <&eth1_pci_iommu_group>;
+				eth1_pci_iommu_group: eth1_pci_iommu_group {
+					qcom,iommu-dma = "atomic";
+				};
+			};
+		};
+	};
+};
+
+&tlmm {
+	qps615_intn_wol {
+		aqr_intn_wol_sig: aqr-intn-wol-sig {
+			pins = "gpio40";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+
+		napa_intn_wol_sig: napa-intn-wol-sig {
+			pins = "gpio39";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
index e6beb4393430..66b9e24f9937 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
@@ -147,3 +147,5 @@
 		output-high;
 	};
 };
+
+#include "monaco-evk-ifp-mezzanine-qps615.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-qps615.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-qps615.dtsi
new file mode 100644
index 000000000000..4746aa1a1d6e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-qps615.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/ {
+	qep_vreg: qep_vreg {
+		compatible = "regulator-fixed";
+		regulator-name = "qep_vreg";
+		gpio = <&pm7325_gpios 8 0>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		enable-active-high;
+	};
+
+	aqr_vreg: aqr_vreg {
+		compatible = "regulator-fixed";
+		regulator-name = "aqr_vreg";
+		gpio = <&pm7250b_gpios 4 0>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		enable-active-high;
+	};
+};
+
+&pcie1_port0 {
+	pcie@0,0 {
+		pcie@3,0 {
+			pci@0,0 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&aqr_intn_wol_sig>;
+				qcom,phy-rst-gpio-id = <0>;
+				interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				phy-supply = <&aqr_vreg>;
+				qcom,phy-rst-delay-us = <221000>;
+
+				qcom,iommu-group = <&eth0_pci_iommu_group>;
+				eth0_pci_iommu_group: eth0_pci_iommu_group {
+					qcom,iommu-dma = "atomic";
+				};
+			};
+
+			pci@0,1 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&napa_intn_wol_sig>;
+				qcom,phy-rst-gpio-id = <1>;
+				interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				phy-supply = <&qep_vreg>;
+				qcom,phy-rst-delay-us = <20000>;
+
+				qcom,iommu-group = <&eth1_pci_iommu_group>;
+				eth1_pci_iommu_group: eth1_pci_iommu_group {
+					qcom,iommu-dma = "atomic";
+				};
+			};
+		};
+	};
+};
+
+&tlmm {
+	qps615_intn_wol {
+		aqr_intn_wol_sig: aqr_intn_wol_sig {
+			mux {
+				pins = "gpio141";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio141";
+				input-enable;
+				bias-disable;
+			};
+		};
+
+		napa_intn_wol_sig: napa_intn_wol_sig {
+			mux {
+				pins = "gpio101";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio101";
+				input-enable;
+				bias-disable;
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 55b1d16d4f85..878605cfc61c 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -2072,3 +2072,5 @@
 	compatible = "qcom,qcm6490-lpassaudiocc";
 	/delete-property/ power-domains;
 };
+
+#include "qcs6490-rb3gen2-qps615.dtsi"