From 5dddc19811e55132f15ead7f3501883269b75613 Mon Sep 17 00:00:00 2001 From: ByungChang Cha Date: Sat, 14 Feb 2026 02:05:34 -0500 Subject: [PATCH 1/3] feat: Implement RAM Preload for 60fps playback & Host Streaming support --- .agent/workflows/run_video_player.md | 29 + .qsys_edit/soc_system_schematic.nlv | 68 +- DC_FIFO.qip | 5 + DC_FIFO.v | 209 + DC_FIFO_bb.v | 129 + DE10_NANO_SoC_GHRD.qsf | 4 + README.md | 10 + RTL/DE10_NANO_SoC_GHRD.v | 90 +- RTL/async_fifo.v | 46 + RTL/dma_check | 134 + RTL/fifo_check | 76 + RTL/hdmi_sync_gen.v | 241 +- RTL/simple_dcfifo.v | 119 + RTL/sync_check | 240 + RTL/video_dma_master.v | 188 + RTL/video_pipeline.v | 174 + TRYERROR.md | 75 + cr_ie_info.json | 22 + doc/RESULT.md | 124 +- doc/TODO.md | 58 +- doc/VIDEO_PLAYBACK.md | 281 + linux_software/.gitignore | 7 + linux_software/frame_loader/Makefile | 17 + linux_software/frame_loader/frame_loader.c | 71 + linux_software/image_converter/color.png | Bin 0 -> 1858 bytes linux_software/image_converter/img2raw.py | 39 + nios_software/nios_ddr3_test_bsp/settings.bsp | 4 +- nios_software/video_app2/burst_master_test.c | 8 +- nios_software/video_app2/burst_master_test.h | 4 +- nios_software/video_app2/hdmi_control.c | 148 +- nios_software/video_app2/hdmi_control.h | 16 +- nios_software/video_app2/main.c | 42 +- nios_software/video_app2/video_app2.map | 2241 +- nios_software/video_app2/video_app2.objdump | 20753 +++++++++------- run_tests.sh | 5 + sim_build/video_pipeline.vvp | 1728 ++ soc_system.qsys | 13 +- soc_system/soc_system_bb.v | 42 +- soc_system/soc_system_inst.v | 22 +- soc_system/soc_system_inst.vhd | 44 +- test_compile.vvp | 1602 ++ ...st_dma_master.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 837 bytes .../test_fifo.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 813 bytes ...hdmi_pipeline.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 838 bytes ...est_video_dma.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 846 bytes ...o_integration.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 950 bytes ...ideo_pipeline.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 941 bytes ...tb_dma_master.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 4553 bytes .../tb_fifo.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 5287 bytes ...hdmi_sync_gen.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 3522 bytes ...eo_dma_master.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 2921 bytes ...o_integration.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 5261 bytes ...ideo_pipeline.cpython-310-pytest-9.0.2.pyc | Bin 0 -> 2642 bytes tests/cocotb/bin2bmp.py | 100 + tests/cocotb/check_raw.py | 17 + tests/cocotb/hdmi_output.bin.old | Bin 0 -> 2457600 bytes tests/cocotb/tb_dma_master.py | 190 + tests/cocotb/tb_fifo.py | 155 + tests/cocotb/tb_hdmi_sync_gen.py | 78 + tests/cocotb/tb_video_dma_master.py | 64 + tests/cocotb/tb_video_integration.py | 219 + tests/cocotb/tb_video_pipeline.py | 60 + tests/sim_build/hdmi_sync_gen.vvp | 1019 + tests/sim_build/simple_dcfifo.vvp | 217 + tests/sim_build/video_dma_master.vvp | 314 + tests/sim_build/video_pipeline.vvp | 1726 ++ tests/test_dma_master.py | 24 + tests/test_fifo.py | 24 + tests/test_hdmi_pipeline.py | 23 + tests/test_video_dma.py | 22 + tests/test_video_integration.py | 29 + tests/test_video_pipeline.py | 27 + 72 files changed, 22777 insertions(+), 10659 deletions(-) create mode 100644 .agent/workflows/run_video_player.md create mode 100644 DC_FIFO.qip create mode 100644 DC_FIFO.v create mode 100644 DC_FIFO_bb.v create mode 100644 RTL/async_fifo.v create mode 100644 RTL/dma_check create mode 100644 RTL/fifo_check create mode 100644 RTL/simple_dcfifo.v create mode 100644 RTL/sync_check create mode 100644 RTL/video_dma_master.v create mode 100644 RTL/video_pipeline.v create mode 100644 TRYERROR.md create mode 100644 cr_ie_info.json create mode 100644 doc/VIDEO_PLAYBACK.md create mode 100644 linux_software/.gitignore create mode 100644 linux_software/frame_loader/Makefile create mode 100644 linux_software/frame_loader/frame_loader.c create mode 100644 linux_software/image_converter/color.png create mode 100644 linux_software/image_converter/img2raw.py create mode 100644 run_tests.sh create mode 100644 sim_build/video_pipeline.vvp create mode 100644 test_compile.vvp create mode 100644 tests/__pycache__/test_dma_master.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/__pycache__/test_fifo.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/__pycache__/test_hdmi_pipeline.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/__pycache__/test_video_dma.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/__pycache__/test_video_integration.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/__pycache__/test_video_pipeline.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/cocotb/__pycache__/tb_dma_master.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/cocotb/__pycache__/tb_fifo.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/cocotb/__pycache__/tb_hdmi_sync_gen.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/cocotb/__pycache__/tb_video_dma_master.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/cocotb/__pycache__/tb_video_integration.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/cocotb/__pycache__/tb_video_pipeline.cpython-310-pytest-9.0.2.pyc create mode 100644 tests/cocotb/bin2bmp.py create mode 100644 tests/cocotb/check_raw.py create mode 100644 tests/cocotb/hdmi_output.bin.old create mode 100644 tests/cocotb/tb_dma_master.py create mode 100644 tests/cocotb/tb_fifo.py create mode 100644 tests/cocotb/tb_hdmi_sync_gen.py create mode 100644 tests/cocotb/tb_video_dma_master.py create mode 100644 tests/cocotb/tb_video_integration.py create mode 100644 tests/cocotb/tb_video_pipeline.py create mode 100644 tests/sim_build/hdmi_sync_gen.vvp create mode 100644 tests/sim_build/simple_dcfifo.vvp create mode 100644 tests/sim_build/video_dma_master.vvp create mode 100644 tests/sim_build/video_pipeline.vvp create mode 100644 tests/test_dma_master.py create mode 100644 tests/test_fifo.py create mode 100644 tests/test_hdmi_pipeline.py create mode 100644 tests/test_video_dma.py create mode 100644 tests/test_video_integration.py create mode 100644 tests/test_video_pipeline.py diff --git a/.agent/workflows/run_video_player.md b/.agent/workflows/run_video_player.md new file mode 100644 index 0000000..4d0a79a --- /dev/null +++ b/.agent/workflows/run_video_player.md @@ -0,0 +1,29 @@ +--- +description: How to compile and run the Linux Video Player +--- + +## 1. Prepare the Environment +Ensure you have a C compiler (`gcc`) installed on your DE10-Nano or a cross-compiler on your host. + +## 2. Transfer Files +Copy the following files to your DE10-Nano (e.g., using `scp`): +* `video_player.c` +* `video_qhd.bin` (Generated by `video2raw.py` on your PC) + +## 3. Compile the Player +Run this command on the DE10-Nano: +```bash +gcc -o video_player video_player.c -O3 +``` +// turbo +## 4. Run the Player +Execute the player with root privileges (required for `/dev/mem` access): +```bash +sudo ./video_player +``` + +## 5. (Optional) Run Python Conversion on PC +To generate the raw video file from an MP4: +```bash +python video2raw.py input_video.mp4 +``` diff --git a/.qsys_edit/soc_system_schematic.nlv b/.qsys_edit/soc_system_schematic.nlv index 20e2164..c439eb5 100644 --- a/.qsys_edit/soc_system_schematic.nlv +++ b/.qsys_edit/soc_system_schematic.nlv @@ -4,20 +4,20 @@ preplace inst soc_system.pll_reconfig -pg 1 -lvl 6 -y 430 preplace inst soc_system.clk_0 -pg 1 -lvl 1 -y 200 preplace inst soc_system.hps_0.clk_0 -pg 1 preplace inst soc_system.nios2_gen2_0.cpu -pg 1 -preplace inst soc_system.pll_0 -pg 1 -lvl 2 -y 460 +preplace inst soc_system.pll_0 -pg 1 -lvl 2 -y 480 preplace inst soc_system.burst_master_0 -pg 1 -lvl 5 -y 1010 preplace inst soc_system.hps_0.axi_sdram -pg 1 preplace inst soc_system -pg 1 -lvl 1 -y 40 -regy -20 preplace inst soc_system.nios2_gen2_0.reset_bridge -pg 1 preplace inst soc_system.hps_0.timer0 -pg 1 -preplace inst soc_system.i2c_hdmi -pg 1 -lvl 6 -y 300 +preplace inst soc_system.i2c_hdmi -pg 1 -lvl 6 -y 290 preplace inst soc_system.hps_0.timer1 -pg 1 preplace inst soc_system.hps_0.i2c0 -pg 1 preplace inst soc_system.address_span_extender_0 -pg 1 -lvl 3 -y 700 preplace inst soc_system.hps_0.timer2 -pg 1 preplace inst soc_system.hps_0.wd_timer0 -pg 1 preplace inst soc_system.hps_0.i2c1 -pg 1 -preplace inst soc_system.video_dma -pg 1 -lvl 2 -y 600 +preplace inst soc_system.video_dma -pg 1 -lvl 2 -y 660 preplace inst soc_system.hps_0.timer3 -pg 1 preplace inst soc_system.hps_0.wd_timer1 -pg 1 preplace inst soc_system.hps_0.i2c2 -pg 1 @@ -42,9 +42,10 @@ preplace inst soc_system.hps_0.l3regs -pg 1 preplace inst soc_system.hps_0.sdmmc -pg 1 preplace inst soc_system.button_pio -pg 1 -lvl 4 -y 100 preplace inst soc_system.hps_0.axi_ocram -pg 1 -preplace inst soc_system.sysid_qsys -pg 1 -lvl 4 -y 570 +preplace inst soc_system.sysid_qsys -pg 1 -lvl 4 -y 540 preplace inst soc_system.nios2_gen2_0.clock_bridge -pg 1 preplace inst soc_system.nios2_gen2_0 -pg 1 -lvl 2 -y 50 +preplace inst soc_system.hdmi_sync_mm -pg 1 -lvl 6 -y 90 preplace inst soc_system.led_pio -pg 1 -lvl 4 -y 380 preplace inst soc_system.hps_0.arm_gic_0 -pg 1 preplace inst soc_system.hps_0.rstmgr -pg 1 @@ -56,12 +57,12 @@ preplace inst soc_system.mm_bridge_0 -pg 1 -lvl 3 -y 480 preplace inst soc_system.pll_locked -pg 1 -lvl 6 -y 570 preplace inst soc_system.hps_0.nand0 -pg 1 preplace inst soc_system.hps_0.gmac0 -pg 1 -preplace inst soc_system.hps_0 -pg 1 -lvl 4 -y 680 +preplace inst soc_system.hps_0 -pg 1 -lvl 4 -y 670 preplace inst soc_system.hps_0.hps_io.border -pg 1 preplace inst soc_system.hps_0.gmac1 -pg 1 preplace inst soc_system.hps_0.eosc1 -pg 1 preplace inst soc_system.hps_0.fpgamgr -pg 1 -preplace inst soc_system.dipsw_pio -pg 1 -lvl 4 -y 240 +preplace inst soc_system.dipsw_pio -pg 1 -lvl 4 -y 220 preplace inst soc_system.hps_0.dcan0 -pg 1 preplace inst soc_system.hps_0.eosc2 -pg 1 preplace inst soc_system.jtag_uart -pg 1 -lvl 3 -y 70 @@ -71,33 +72,34 @@ preplace inst soc_system.hps_0.f2s_sdram_ref_clk -pg 1 preplace inst soc_system.hps_0.dma -pg 1 preplace inst soc_system.hps_0.sdrctl -pg 1 preplace inst soc_system.hps_0.bridges -pg 1 -preplace inst soc_system.timer_0 -pg 1 -lvl 3 -y 280 +preplace inst soc_system.timer_0 -pg 1 -lvl 3 -y 260 preplace inst soc_system.burst_master_4_0 -pg 1 -lvl 6 -y 960 -preplace netloc POINT_TO_POINTsoc_system(SLAVE)pll_0.reconfig_from_pll,(SLAVE)pll_reconfig.reconfig_from_pll) 1 1 5 590 450 NJ 450 NJ 520 NJ 540 2210 -preplace netloc FAN_OUTsoc_system(SLAVE)button_pio.s1,(SLAVE)led_pio.s1,(SLAVE)dipsw_pio.s1,(MASTER)mm_bridge_0.m0,(SLAVE)sysid_qsys.control_slave) 1 3 1 1400 -preplace netloc INTERCONNECTsoc_system(SLAVE)timer_0.s1,(MASTER)burst_master_0.read_master,(SLAVE)i2c_hdmi.csr,(MASTER)hps_0.h2f_axi_master,(SLAVE)burst_master_0.csr_slave,(SLAVE)nios2_gen2_0.debug_mem_slave,(MASTER)nios2_gen2_0.data_master,(SLAVE)address_span_extender_0.windowed_slave,(MASTER)nios2_gen2_0.instruction_master,(SLAVE)pll_locked.s1,(SLAVE)onchip_memory2_0.s1,(SLAVE)burst_master_4_0.cs_slave,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)address_span_extender_0.cntl,(SLAVE)pll_reconfig.mgmt_avalon_slave) 1 1 5 590 190 970 1040 NJ 1040 1870 810 2190 +preplace netloc POINT_TO_POINTsoc_system(SLAVE)pll_0.reconfig_from_pll,(SLAVE)pll_reconfig.reconfig_from_pll) 1 1 5 510 470 NJ 470 NJ 530 NJ 540 2150 +preplace netloc EXPORTsoc_system(MASTER)soc_system.pll_outclk,(MASTER)pll_0.outclk0) 1 2 5 NJ 450 NJ 490 NJ 420 NJ 420 NJ +preplace netloc EXPORTsoc_system(SLAVE)soc_system.clk,(SLAVE)clk_0.clk_in) 1 0 1 NJ +preplace netloc FAN_OUTsoc_system(SLAVE)dipsw_pio.irq,(SLAVE)button_pio.irq,(MASTER)hps_0.f2h_irq0) 1 3 2 1380 990 1750 preplace netloc EXPORTsoc_system(SLAVE)soc_system.reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ -preplace netloc EXPORTsoc_system(SLAVE)hps_0.memory,(SLAVE)soc_system.memory) 1 0 4 NJ 890 NJ 890 NJ 890 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.hps_0_f2h_debug_reset_req,(SLAVE)hps_0.f2h_debug_reset_req) 1 0 4 NJ 830 NJ 830 NJ 830 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.hps_0_f2h_stm_hw_events,(SLAVE)hps_0.f2h_stm_hw_events) 1 0 4 NJ 910 NJ 910 NJ 910 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.hps_0_f2h_cold_reset_req,(SLAVE)hps_0.f2h_cold_reset_req) 1 0 4 NJ 810 NJ 810 NJ 810 NJ -preplace netloc EXPORTsoc_system(SLAVE)button_pio.external_connection,(SLAVE)soc_system.button_pio_external_connection) 1 0 4 NJ 190 NJ 250 NJ 250 NJ -preplace netloc EXPORTsoc_system(SLAVE)clk_0.clk_in,(SLAVE)soc_system.clk) 1 0 1 NJ -preplace netloc POINT_TO_POINTsoc_system(SLAVE)mm_bridge_0.s0,(MASTER)hps_0.h2f_lw_axi_master) 1 2 3 1050 1000 NJ 1000 1810 -preplace netloc INTERCONNECTsoc_system(SLAVE)mm_bridge_0.reset,(SLAVE)sysid_qsys.reset,(SLAVE)button_pio.reset,(SLAVE)jtag_uart.reset,(SLAVE)video_dma.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)nios2_gen2_0.reset,(SLAVE)i2c_hdmi.reset_sink,(SLAVE)burst_master_4_0.reset,(MASTER)clk_0.clk_reset,(SLAVE)burst_master_0.reset,(SLAVE)address_span_extender_0.reset,(SLAVE)pll_reconfig.mgmt_reset,(SLAVE)pll_locked.reset,(SLAVE)led_pio.reset,(MASTER)nios2_gen2_0.debug_reset_request,(SLAVE)pll_0.reset,(SLAVE)dipsw_pio.reset,(SLAVE)timer_0.reset) 1 1 5 530 330 1010 690 1440 1080 1910 1000 2150 -preplace netloc POINT_TO_POINTsoc_system(SLAVE)pll_reconfig.reconfig_to_pll,(SLAVE)pll_0.reconfig_to_pll) 1 1 5 550 430 NJ 430 NJ 500 NJ 520 N -preplace netloc FAN_OUTsoc_system(MASTER)nios2_gen2_0.irq,(SLAVE)jtag_uart.irq,(SLAVE)timer_0.irq,(SLAVE)i2c_hdmi.interrupt_sender) 1 2 4 990 270 NJ 230 NJ 230 2210 -preplace netloc FAN_OUTsoc_system(SLAVE)dipsw_pio.irq,(MASTER)hps_0.f2h_irq0,(SLAVE)button_pio.irq) 1 3 2 1480 1020 1830 +preplace netloc EXPORTsoc_system(SLAVE)button_pio.external_connection,(SLAVE)soc_system.button_pio_external_connection) 1 0 4 NJ 190 NJ 230 NJ 230 NJ +preplace netloc EXPORTsoc_system(SLAVE)hps_0.f2h_cold_reset_req,(SLAVE)soc_system.hps_0_f2h_cold_reset_req) 1 0 4 NJ 810 NJ 810 NJ 810 NJ +preplace netloc INTERCONNECTsoc_system(SLAVE)i2c_hdmi.reset_sink,(SLAVE)jtag_uart.reset,(SLAVE)video_dma.reset,(SLAVE)dipsw_pio.reset,(SLAVE)burst_master_0.reset,(SLAVE)timer_0.reset,(MASTER)clk_0.clk_reset,(SLAVE)hdmi_sync_mm.reset,(SLAVE)pll_reconfig.mgmt_reset,(SLAVE)burst_master_4_0.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)pll_locked.reset,(SLAVE)led_pio.reset,(SLAVE)mm_bridge_0.reset,(SLAVE)address_span_extender_0.reset,(MASTER)nios2_gen2_0.debug_reset_request,(SLAVE)nios2_gen2_0.reset,(SLAVE)pll_0.reset,(SLAVE)sysid_qsys.reset,(SLAVE)button_pio.reset) 1 1 5 410 630 910 930 1240 1090 1830 980 2090 +preplace netloc POINT_TO_POINTsoc_system(SLAVE)pll_0.locked,(SLAVE)pll_locked.external_connection) 1 1 5 490 650 NJ 570 NJ 630 NJ 600 NJ +preplace netloc EXPORTsoc_system(MASTER)soc_system.hdmi_sync_master,(MASTER)hdmi_sync_mm.m0) 1 6 1 NJ +preplace netloc POINT_TO_POINTsoc_system(SLAVE)mm_bridge_0.s0,(MASTER)hps_0.h2f_lw_axi_master) 1 2 3 970 1030 NJ 1030 1730 +preplace netloc EXPORTsoc_system(SLAVE)hps_0.f2h_debug_reset_req,(SLAVE)soc_system.hps_0_f2h_debug_reset_req) 1 0 4 NJ 830 NJ 830 NJ 830 NJ +preplace netloc POINT_TO_POINTsoc_system(SLAVE)pll_reconfig.reconfig_to_pll,(SLAVE)pll_0.reconfig_to_pll) 1 1 5 470 430 NJ 430 NJ 510 NJ 520 N +preplace netloc EXPORTsoc_system(SLAVE)soc_system.memory,(SLAVE)hps_0.memory) 1 0 4 NJ 870 NJ 870 NJ 870 NJ preplace netloc EXPORTsoc_system(SLAVE)soc_system.led_pio_external_connection,(SLAVE)led_pio.external_connection) 1 0 4 NJ 410 NJ 410 NJ 410 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.dipsw_pio_external_connection,(SLAVE)dipsw_pio.external_connection) 1 0 4 NJ 170 NJ 230 NJ 230 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.video_dma_s,(SLAVE)video_dma.s0) 1 0 2 NJ 650 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.hps_0_hps_io,(SLAVE)hps_0.hps_io) 1 0 4 NJ 870 NJ 870 NJ 870 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.hps_0_f2h_warm_reset_req,(SLAVE)hps_0.f2h_warm_reset_req) 1 0 4 NJ 850 NJ 850 NJ 850 NJ -preplace netloc POINT_TO_POINTsoc_system(SLAVE)pll_locked.external_connection,(SLAVE)pll_0.locked) 1 1 5 570 590 NJ 570 NJ 560 NJ 600 N -preplace netloc FAN_OUTsoc_system(SLAVE)dipsw_pio.clk,(SLAVE)pll_0.refclk,(MASTER)clk_0.clk,(SLAVE)hps_0.f2h_sdram0_clock,(SLAVE)button_pio.clk,(SLAVE)address_span_extender_0.clock,(SLAVE)hps_0.f2h_sdram1_clock,(SLAVE)timer_0.clk,(SLAVE)burst_master_4_0.clock,(SLAVE)hps_0.h2f_axi_clock,(SLAVE)video_dma.clk,(SLAVE)onchip_memory2_0.clk1,(SLAVE)pll_locked.clk,(SLAVE)hps_0.h2f_lw_axi_clock,(SLAVE)jtag_uart.clk,(SLAVE)mm_bridge_0.clk,(SLAVE)burst_master_0.clock,(SLAVE)i2c_hdmi.clock,(SLAVE)nios2_gen2_0.clk,(SLAVE)hps_0.f2h_axi_clock,(SLAVE)led_pio.clk,(SLAVE)sysid_qsys.clk,(SLAVE)pll_reconfig.mgmt_clk) 1 1 5 510 210 1030 180 1360 1060 1850 970 2170 -preplace netloc FAN_INsoc_system(MASTER)burst_master_0.write_master_1,(SLAVE)hps_0.f2h_axi_slave,(MASTER)video_dma.m0,(MASTER)burst_master_4_0.read_master,(MASTER)burst_master_4_0.write_master,(MASTER)address_span_extender_0.expanded_master) 1 2 5 950 670 1280 1100 NJ 950 2130 1050 2410 -preplace netloc EXPORTsoc_system(MASTER)hps_0.h2f_reset,(MASTER)soc_system.hps_0_h2f_reset) 1 4 3 NJ 850 NJ 850 NJ -preplace netloc EXPORTsoc_system(MASTER)pll_0.outclk0,(MASTER)soc_system.pll_outclk) 1 2 5 NJ 470 NJ 540 NJ 560 NJ 560 NJ -preplace netloc EXPORTsoc_system(SLAVE)soc_system.i2c_hdmi,(SLAVE)i2c_hdmi.i2c_serial) 1 0 6 NJ 390 NJ 390 NJ 390 NJ 370 NJ 370 NJ -levelinfo -pg 1 0 200 2560 -levelinfo -hier soc_system 210 320 710 1100 1620 1940 2240 2430 +preplace netloc FAN_OUTsoc_system(SLAVE)button_pio.s1,(SLAVE)dipsw_pio.s1,(SLAVE)sysid_qsys.control_slave,(SLAVE)led_pio.s1,(MASTER)mm_bridge_0.m0) 1 3 1 1200 +preplace netloc FAN_OUTsoc_system(MASTER)nios2_gen2_0.irq,(SLAVE)jtag_uart.irq,(SLAVE)i2c_hdmi.interrupt_sender,(SLAVE)timer_0.irq) 1 2 4 890 250 NJ 350 NJ 350 2050 +preplace netloc FAN_OUTsoc_system(MASTER)clk_0.clk,(SLAVE)pll_locked.clk,(SLAVE)hps_0.f2h_axi_clock,(SLAVE)hdmi_sync_mm.clk,(SLAVE)pll_reconfig.mgmt_clk,(SLAVE)pll_0.refclk,(SLAVE)sysid_qsys.clk,(SLAVE)timer_0.clk,(SLAVE)nios2_gen2_0.clk,(SLAVE)i2c_hdmi.clock,(SLAVE)hps_0.f2h_sdram1_clock,(SLAVE)led_pio.clk,(SLAVE)video_dma.clk,(SLAVE)address_span_extender_0.clock,(SLAVE)hps_0.h2f_lw_axi_clock,(SLAVE)onchip_memory2_0.clk1,(SLAVE)hps_0.f2h_sdram0_clock,(SLAVE)hps_0.h2f_axi_clock,(SLAVE)button_pio.clk,(SLAVE)dipsw_pio.clk,(SLAVE)burst_master_0.clock,(SLAVE)burst_master_4_0.clock,(SLAVE)jtag_uart.clk,(SLAVE)mm_bridge_0.clk) 1 1 5 450 610 950 690 1320 1070 1790 940 2130 +preplace netloc EXPORTsoc_system(SLAVE)soc_system.dipsw_pio_external_connection,(SLAVE)dipsw_pio.external_connection) 1 0 4 NJ 170 NJ 210 NJ 210 NJ +preplace netloc EXPORTsoc_system(SLAVE)soc_system.video_dma_s,(SLAVE)video_dma.s0) 1 0 2 NJ 710 NJ +preplace netloc EXPORTsoc_system(SLAVE)soc_system.hps_0_hps_io,(SLAVE)hps_0.hps_io) 1 0 4 NJ 910 NJ 910 NJ 910 NJ +preplace netloc EXPORTsoc_system(SLAVE)soc_system.hps_0_f2h_warm_reset_req,(SLAVE)hps_0.f2h_warm_reset_req) 1 0 4 NJ 890 NJ 890 NJ 890 NJ +preplace netloc FAN_INsoc_system(SLAVE)hps_0.f2h_axi_slave,(MASTER)burst_master_0.write_master_1,(MASTER)address_span_extender_0.expanded_master,(MASTER)burst_master_4_0.write_master,(MASTER)burst_master_4_0.read_master,(MASTER)video_dma.m0) 1 2 5 890 670 1200 1050 NJ 1000 2150 950 2360 +preplace netloc EXPORTsoc_system(SLAVE)i2c_hdmi.i2c_serial,(SLAVE)soc_system.i2c_hdmi) 1 0 6 NJ 370 NJ 370 NJ 370 NJ 370 NJ 370 NJ +preplace netloc EXPORTsoc_system(MASTER)soc_system.hps_0_h2f_reset,(MASTER)hps_0.h2f_reset) 1 4 3 NJ 840 NJ 840 NJ +preplace netloc INTERCONNECTsoc_system(SLAVE)burst_master_4_0.cs_slave,(SLAVE)address_span_extender_0.windowed_slave,(SLAVE)i2c_hdmi.csr,(SLAVE)nios2_gen2_0.debug_mem_slave,(MASTER)burst_master_0.read_master,(SLAVE)address_span_extender_0.cntl,(SLAVE)pll_reconfig.mgmt_avalon_slave,(SLAVE)onchip_memory2_0.s1,(MASTER)hps_0.h2f_axi_master,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)burst_master_0.csr_slave,(SLAVE)pll_locked.s1,(MASTER)nios2_gen2_0.instruction_master,(MASTER)nios2_gen2_0.data_master,(SLAVE)hdmi_sync_mm.s0,(SLAVE)timer_0.s1) 1 1 5 510 190 870 950 NJ 1010 1770 960 2110 +preplace netloc EXPORTsoc_system(SLAVE)hps_0.f2h_stm_hw_events,(SLAVE)soc_system.hps_0_f2h_stm_hw_events) 1 0 4 NJ 850 NJ 850 NJ 850 NJ +levelinfo -pg 1 0 200 2510 +levelinfo -hier soc_system 210 240 630 1020 1540 1860 2190 2380 diff --git a/DC_FIFO.qip b/DC_FIFO.qip new file mode 100644 index 0000000..ed3aecb --- /dev/null +++ b/DC_FIFO.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "20.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "DC_FIFO.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "DC_FIFO_bb.v"] diff --git a/DC_FIFO.v b/DC_FIFO.v new file mode 100644 index 0000000..c809302 --- /dev/null +++ b/DC_FIFO.v @@ -0,0 +1,209 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: DC_FIFO.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ + +`ifdef COCOTB_SIM +module DC_FIFO ( + input wire [31:0] data, + input wire rdclk, + input wire rdreq, + input wire wrclk, + input wire wrreq, + output wire [31:0] q, + output wire rdempty, + output wire wrfull, + output wire [8:0] wrusedw +); + // Simulation Behavioral Model + reg [31:0] mem [0:511]; + reg [9:0] wr_ptr = 0, rd_ptr = 0; + + always @(posedge wrclk) begin + if (wrreq && !wrfull) begin + mem[wr_ptr[8:0]] <= data; + wr_ptr <= wr_ptr + 1; + end + end + + always @(posedge rdclk) begin + if (rdreq && !rdempty) begin + rd_ptr <= rd_ptr + 1; + end + end + + assign q = mem[rd_ptr[8:0]]; + assign rdempty = (wr_ptr == rd_ptr); + assign wrfull = (wr_ptr[8:0] == rd_ptr[8:0]) && (wr_ptr[9] != rd_ptr[9]); + assign wrusedw = wr_ptr - rd_ptr; + +endmodule +`else +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 20.1.1 Build 720 11/11/2020 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2020 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module DC_FIFO ( + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + wrfull, + wrusedw); + + input [31:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [31:0] q; + output rdempty; + output wrfull; + output [8:0] wrusedw; + + wire [31:0] sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire [8:0] sub_wire3; + wire [31:0] q = sub_wire0[31:0]; + wire rdempty = sub_wire1; + wire wrfull = sub_wire2; + wire [8:0] wrusedw = sub_wire3[8:0]; + + dcfifo dcfifo_component ( + .data (data), + .rdclk (rdclk), + .rdreq (rdreq), + .wrclk (wrclk), + .wrreq (wrreq), + .q (sub_wire0), + .rdempty (sub_wire1), + .wrfull (sub_wire2), + .wrusedw (sub_wire3), + .aclr (), + .eccstatus (), + .rdfull (), + .rdusedw (), + .wrempty ()); + defparam + dcfifo_component.intended_device_family = "Cyclone V", + dcfifo_component.lpm_numwords = 512, + dcfifo_component.lpm_showahead = "OFF", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 32, + dcfifo_component.lpm_widthu = 9, + dcfifo_component.overflow_checking = "ON", + dcfifo_component.rdsync_delaypipe = 4, + dcfifo_component.underflow_checking = "ON", + dcfifo_component.use_eab = "ON", + dcfifo_component.wrsync_delaypipe = 4; + + +endmodule +`endif +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "512" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "32" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "32" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]" +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/DC_FIFO_bb.v b/DC_FIFO_bb.v new file mode 100644 index 0000000..eb0a72b --- /dev/null +++ b/DC_FIFO_bb.v @@ -0,0 +1,129 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: DC_FIFO.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 20.1.1 Build 720 11/11/2020 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2020 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + +module DC_FIFO ( + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + wrfull, + wrusedw); + + input [31:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [31:0] q; + output rdempty; + output wrfull; + output [8:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "512" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "32" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "32" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]" +// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL DC_FIFO_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/DE10_NANO_SoC_GHRD.qsf b/DE10_NANO_SoC_GHRD.qsf index f8785a0..5c68a80 100644 --- a/DE10_NANO_SoC_GHRD.qsf +++ b/DE10_NANO_SoC_GHRD.qsf @@ -473,6 +473,10 @@ set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name ECO_REGENERATE_REPORT ON +set_global_assignment -name VERILOG_FILE RTL/simple_dcfifo.v +set_global_assignment -name VERILOG_FILE RTL/video_pipeline.v +set_global_assignment -name VERILOG_FILE RTL/video_dma_master.v +set_global_assignment -name VERILOG_FILE RTL/async_fifo.v set_global_assignment -name SDC_FILE DE10_NANO_SOC_GHRD.sdc set_global_assignment -name VERILOG_FILE RTL/DE10_NANO_SoC_GHRD.v set_global_assignment -name VERILOG_FILE RTL/burst_master.v diff --git a/README.md b/README.md index cc385cd..1709019 100644 --- a/README.md +++ b/README.md @@ -14,6 +14,14 @@ By utilizing the **FPGA-to-HPS AXI Bridge**, we bypass the common preloader/brid - **Advanced HDMI Control**: Implemented sophisticated gamma correction (sRGB, Inverse Gamma 2.2) and custom character tile-rendering (Mode 7). - **Stable Address Mapping**: Fixed Avalon-MM byte-to-word addressing issues, ensuring reliable register control. +### ๐ŸŽฌ Video Playback (New!) +- **qHD Resolution (960ร—540@60Hz)**: Optimized for 50MHz bus bandwidth (124 MB/s vs 200 MB/s available) +- **Static Image Display**: Nios II software loads and displays images from DDR3 +- **Linux Video Playback**: High-performance "Store-and-Forward" architecture (RAM Preload) +- **Network Streaming**: Support for piping video from host PC via SSH (`cat | ssh`) +- **Dual-Clock Architecture**: Separate CSR (50MHz) and Pixel (37.8MHz) clocks with proper CDC +- **V-Sync Synchronization**: Tear-free frame updates via hardware latching + ## ๐Ÿ— System Architecture ```mermaid graph LR @@ -46,6 +54,7 @@ graph LR | | **Hardware DMA (BM4/Pipe)** | **125.00 MB/s** | **~585x Speedup** | ## ๐Ÿ“– Documentation +- [VIDEO_PLAYBACK.md](doc/VIDEO_PLAYBACK.md): **โญ NEW** - qHD video playback implementation, Linux integration, and performance analysis. - [DESIGN.md](doc/DESIGN.md): Comprehensive system architecture and DDR-to-HDMI pipeline specification. - [NIOS.md](doc/NIOS.md): Detailed Interactive Menu tree structure and control logic. - [BURST_DMA.md](doc/BURST_DMA.md): Detailed debugging history, performance benchmarks, and memory protection strategies. @@ -54,3 +63,4 @@ graph LR - [TODO.md](doc/TODO.md): Project roadmap and remaining tasks. - [soc_system.qsys](./soc_system.qsys): Platform Designer (Qsys) hardware configuration. - [nios_software/](./nios_software/): Nios II benchmark and verification source code. +- [linux_software/](./linux_software/): Linux HPS applications for video playback. diff --git a/RTL/DE10_NANO_SoC_GHRD.v b/RTL/DE10_NANO_SoC_GHRD.v index 45ec846..305ff73 100644 --- a/RTL/DE10_NANO_SoC_GHRD.v +++ b/RTL/DE10_NANO_SoC_GHRD.v @@ -99,16 +99,15 @@ module DE10_NANO_SoC_GHRD( wire [27:0] stm_hw_events; wire fpga_clk_50; + assign fpga_clk_50 = FPGA_CLK1_50; + // Video DMA Interface Wires wire dma_waitrequest; wire [31:0] dma_readdata; wire dma_readdatavalid; wire [7:0] dma_burstcount; - wire [31:0] dma_writedata; wire [31:0] dma_address; - wire dma_write; wire dma_read; - wire [3:0] dma_byteenable; // HDMI Sync Gen Control Interface (Exported from Qsys) wire [2:0] hsg_s_address; @@ -118,15 +117,38 @@ module DE10_NANO_SoC_GHRD( wire [31:0] hsg_s_readdata; wire hsg_s_readdatavalid; + // HDMI I2C Wires + // HDMI I2C Wires wire hdmi_i2c_sda_in; wire hdmi_i2c_scl_in; wire hdmi_i2c_sda_oe; wire hdmi_i2c_scl_oe; // connection of internal logics - assign LED[7:1] = fpga_led_internal; - assign fpga_clk_50=FPGA_CLK1_50; - assign stm_hw_events = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons}; +// assign LED[7:1] = fpga_led_internal; // Removed old connection + assign LED[0] = led_level; // Heartbeat + + // Debug LEDs from Video Pipeline + // LED[1]: DMA Busy + // LED[2]: DMA Done (Toggle) + // LED[3]: FIFO Not Empty + // LED[4]: FIFO Full + // LED[5]: DMA Start Pulse (50MHz) + // LED[6]: DMA Start Toggle (74MHz) + // LED[7]: DMA Cont Mode + + // video_pipeline debug_leds mapping: + // [0] Busy, [1] Done, [2] !Empty, [3] Full, [4] Start(50), [5] Start(74), [6] Cont, [7] VSync + + assign LED[1] = pipeline_debug[0]; // Busy + assign LED[2] = pipeline_debug[1]; // Done + assign LED[3] = pipeline_debug[3]; // FIFO Full (Warning) + assign LED[4] = pipeline_debug[4]; // Start Pulse 50MHz + assign LED[5] = pipeline_debug[5]; // Start Toggle 74MHz + assign LED[6] = pipeline_debug[6]; // Cont Mode + assign LED[7] = pipeline_debug[7]; // V-Sync Edge + + assign stm_hw_events = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons}; @@ -225,12 +247,13 @@ soc_system u0 ( .video_dma_s_waitrequest (dma_waitrequest), // video_dma_s.waitrequest .video_dma_s_readdata (dma_readdata), // .readdata .video_dma_s_readdatavalid (dma_readdatavalid), // .readdatavalid - .video_dma_s_burstcount (dma_burstcount), // .burstcount - .video_dma_s_writedata (dma_writedata), // .writedata + .video_dma_s_burstcount ({1'b0, dma_burstcount}),// .burstcount + .video_dma_s_writedata (32'd0), // .writedata .video_dma_s_address (dma_address), // .address - .video_dma_s_write (dma_write), // .write + .video_dma_s_write (1'b0), // .write .video_dma_s_read (dma_read), // .read - .video_dma_s_byteenable (dma_byteenable), // .byteenable + .video_dma_s_byteenable (4'h0), // .byteenable + .video_dma_s_debugaccess (1'b0), // .debugaccess // HDMI I2C .i2c_hdmi_sda_in (hdmi_i2c_sda_in), // i2c_hdmi.sda_in @@ -239,7 +262,7 @@ soc_system u0 ( .i2c_hdmi_scl_oe (hdmi_i2c_scl_oe), // .scl_oe // HDMI Sync Gen Control (Master Exported) - .hdmi_sync_master_waitrequest (1'b0), // Waitrequest: Always ready + .hdmi_sync_master_waitrequest (1'b0), .hdmi_sync_master_readdata (hsg_s_readdata), // .readdata .hdmi_sync_master_readdatavalid (hsg_s_readdatavalid), // .readdatavalid .hdmi_sync_master_burstcount (), // .burstcount (Not used) @@ -252,23 +275,40 @@ soc_system u0 ( ); // HDMI Sync & Pattern Generator (Solid Red) -hdmi_sync_gen u_hdmi_sync ( - .clk (HDMI_TX_CLK), // 74.25 MHz from Qsys PLL - .reset_n (hps_fpga_reset_n), // Reset from HPS - .hdmi_d (HDMI_TX_D), // 24-bit Data - .hdmi_de (HDMI_TX_DE), // Display Enable - .hdmi_hs (HDMI_TX_HS), // H-Sync - .hdmi_vs (HDMI_TX_VS), // V-Sync +// HDMI Video Pipeline (Includes DMA Master & Sync Gen) +video_pipeline u_pipeline ( + // Clocks & Reset + .clk_50 (fpga_clk_50), // 50 MHz for DMA & CSR + .clk_hdmi (HDMI_TX_CLK), // ~37.8 MHz for Video + .reset_n (hps_fpga_reset_n), + + // Avalon-MM Master Interface (DMA to DDR3) + .m_waitrequest (dma_waitrequest), + .m_readdata (dma_readdata), + .m_readdatavalid (dma_readdatavalid), + .m_address (dma_address), + .m_read (dma_read), + .m_burstcount (dma_burstcount), + + // Avalon-MM Slave Interface (CSR from Nios II) + .s_address (hsg_s_address), + .s_read (hsg_s_read), + .s_write (hsg_s_write), + .s_writedata (hsg_s_writedata), + .s_readdata (hsg_s_readdata), + .s_readdatavalid (hsg_s_readdatavalid), + + // HDMI Physical Output Signals + .hdmi_d (HDMI_TX_D), + .hdmi_de (HDMI_TX_DE), + .hdmi_hs (HDMI_TX_HS), + .hdmi_vs (HDMI_TX_VS), - // Control Interface - .avs_address (hsg_s_address), // 3-bit local address - .avs_read (hsg_s_read), // Read Request - .avs_write (hsg_s_write), // Write Request - .avs_writedata (hsg_s_writedata), // Write Data - .avs_readdata (hsg_s_readdata), // Read Data - .avs_readdatavalid (hsg_s_readdatavalid) // Read Data Valid + .debug_leds (pipeline_debug) ); +wire [7:0] pipeline_debug; + // HDMI I2C Tri-state Buffer assign HDMI_I2C_SCL = hdmi_i2c_scl_oe ? 1'b0 : 1'bz; assign hdmi_i2c_scl_in = HDMI_I2C_SCL; diff --git a/RTL/async_fifo.v b/RTL/async_fifo.v new file mode 100644 index 0000000..dc16502 --- /dev/null +++ b/RTL/async_fifo.v @@ -0,0 +1,46 @@ +`timescale 1ns/1ps + +module async_fifo #( + parameter DATA_WIDTH = 32, + parameter ADDR_WIDTH = 9 +)( + input wire wr_clk, + input wire wr_rst_n, + input wire wr_en, + input wire [DATA_WIDTH-1:0] wr_data, + output wire [ADDR_WIDTH-1:0] wr_used, + + input wire rd_clk, + input wire rd_rst_n, + input wire rd_en, + output wire [DATA_WIDTH-1:0] rd_data, + output wire rd_empty +); + // Behavioral Model for Simulation + localparam DEPTH = 1 << ADDR_WIDTH; + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + reg [ADDR_WIDTH:0] wr_ptr, rd_ptr; + + // Simplistic CDC for simulation (not for synthesis!) + always @(posedge wr_clk or negedge wr_rst_n) begin + if (!wr_rst_n) begin + wr_ptr <= 0; + end else if (wr_en && (wr_ptr - rd_ptr < DEPTH)) begin + mem[wr_ptr[ADDR_WIDTH-1:0]] <= wr_data; + wr_ptr <= wr_ptr + 1; + end + end + + always @(posedge rd_clk or negedge rd_rst_n) begin + if (!rd_rst_n) begin + rd_ptr <= 0; + end else if (rd_en && (wr_ptr != rd_ptr)) begin + rd_ptr <= rd_ptr + 1; + end + end + + assign rd_data = mem[rd_ptr[ADDR_WIDTH-1:0]]; + assign rd_empty = (wr_ptr == rd_ptr); + assign wr_used = wr_ptr - rd_ptr; + +endmodule diff --git a/RTL/dma_check b/RTL/dma_check new file mode 100644 index 0000000..ede45d9 --- /dev/null +++ b/RTL/dma_check @@ -0,0 +1,134 @@ +/* + * 1364-1995 Verilog generated by Icarus Verilog VLOG95 Code Generator, + * Version: 11.0 (stable) () + * Converted using TYPICAL delays and without signed support. + */ + +`timescale 1ns/1ps +/* This module was originally defined in file video_dma_master.v at line 3. */ +module video_dma_master(clk, reset_n, start_addr, dma_start, dma_cont_en, dma_done, busy, vsync_edge, m_waitrequest, m_readdata, m_readdatavalid, m_address, m_read, m_burstcount, fifo_used, fifo_wr_en, fifo_wr_data); + input clk; + input reset_n; + input [31:0] start_addr; + input dma_start; + input dma_cont_en; + output dma_done; + output busy; + input vsync_edge; + input m_waitrequest; + input [31:0] m_readdata; + input m_readdatavalid; + output [31:0] m_address; + output m_read; + output [7:0] m_burstcount; + input [8:0] fifo_used; + output fifo_wr_en; + output [31:0] fifo_wr_data; + + parameter BURST_LEN = 8'h40; + parameter CHECK_FIFO = 2'h1; + parameter FIFO_DEPTH = 512; + parameter FRAME_SIZE_WORDS = 921600; + parameter H_RES = 1280; + parameter IDLE = 2'h0; + parameter ISSUE_READ = 2'h2; + parameter V_RES = 720; + parameter WAIT_END = 2'h3; + + wire busy; + wire clk; + reg [31:0] current_read_addr; + wire dma_cont_en; + reg dma_done; + wire dma_start; + wire [8:0] fifo_used; + wire [31:0] fifo_wr_data; + wire fifo_wr_en; + reg frame_active; + reg is_cont_mode; + reg [31:0] m_address; + wire [7:0] m_burstcount; + reg m_read; + wire [31:0] m_readdata; + wire m_readdatavalid; + wire m_waitrequest; + reg [9:0] pending_bursts; + wire reset_n; + wire [31:0] start_addr; + reg [1:0] state; + wire vsync_edge; + reg [31:0] words_commanded; + reg [31:0] words_received; + + + assign m_burstcount = BURST_LEN; + + assign fifo_wr_en = m_readdatavalid; + assign fifo_wr_data = m_readdata; + assign busy = frame_active; + + always @(posedge clk or negedge reset_n) if ((!reset_n)) begin + state <= IDLE; + m_address <= 32'h00000000; + m_read <= 1'b0; + current_read_addr <= 32'h00000000; + words_commanded <= 32'h00000000; + is_cont_mode <= 1'b0; + frame_active <= 1'b0; + pending_bursts <= 10'h000; + end + else begin + case (state) + IDLE: begin + m_read <= 1'b0; + words_commanded <= 32'h00000000; + if (dma_start) begin + current_read_addr <= start_addr; + is_cont_mode <= 1'b0; + frame_active <= 1'b1; + state <= CHECK_FIFO; + end + else if ((dma_cont_en && vsync_edge)) begin + current_read_addr <= start_addr; + is_cont_mode <= 1'b1; + frame_active <= 1'b1; + state <= CHECK_FIFO; + end + else frame_active <= 1'b0; + end + CHECK_FIFO: begin + m_read <= 1'b0; + if ((words_commanded >= FRAME_SIZE_WORDS)) state <= WAIT_END; + else if (((fifo_used + (words_commanded - words_received)) <= 32'h000001be)) begin + m_address <= current_read_addr; + m_read <= 1'b1; + state <= ISSUE_READ; + end + end + ISSUE_READ: if ((!m_waitrequest)) begin + m_read <= 1'b0; + current_read_addr <= (current_read_addr + 32'h00000100); + words_commanded <= (words_commanded + BURST_LEN); + state <= CHECK_FIFO; + end + WAIT_END: begin + m_read <= 1'b0; + if ((words_received >= FRAME_SIZE_WORDS)) begin + state <= IDLE; + frame_active <= 1'b0; + end + end + endcase + if (((is_cont_mode && (!dma_cont_en)) && (state == IDLE))) is_cont_mode <= 1'b0; + end + + always @(posedge clk or negedge reset_n) if ((!reset_n)) words_received <= 32'h00000000; + else begin + if (((state == IDLE) && (dma_start || (dma_cont_en && vsync_edge)))) words_received <= 32'h00000000; + if (m_readdatavalid) words_received <= (words_received + 32'h00000001); + end + + always @(posedge clk or negedge reset_n) if ((!reset_n)) dma_done <= 1'b0; + else if ((m_readdatavalid && (words_received == 64'h00000000000e0fff))) dma_done <= 1'b1; + else dma_done <= 1'b0; +endmodule /* video_dma_master */ diff --git a/RTL/fifo_check b/RTL/fifo_check new file mode 100644 index 0000000..745ec50 --- /dev/null +++ b/RTL/fifo_check @@ -0,0 +1,76 @@ +/* + * 1364-1995 Verilog generated by Icarus Verilog VLOG95 Code Generator, + * Version: 11.0 (stable) () + * Converted using TYPICAL delays and without signed support. + */ + +`timescale 1ns/1ps +/* This module was originally defined in file simple_dcfifo.v at line 3. */ +module simple_dcfifo(wrclk, data, wrreq, wrusedw, wrfull, rdclk, rdreq, q, rdempty); + input wrclk; + input [31:0] data; + input wrreq; + output [8:0] wrusedw; + output wrfull; + input rdclk; + input rdreq; + output [31:0] q; + output rdempty; + + parameter ADDR_WIDTH = 9; + parameter DATA_WIDTH = 32; + + wire [31:0] data; + integer i; + reg [31:0] mem [511:0]; + reg [31:0] q; + reg [9:0] rd_ptr_bin; + reg [9:0] rd_ptr_gray; + reg [9:0] rd_ptr_gray_sync1; + reg [9:0] rd_ptr_gray_sync2; + wire rdclk; + wire rdempty; + wire rdreq; + reg [9:0] wr_ptr_bin; + reg [9:0] wr_ptr_gray; + reg [9:0] wr_ptr_gray_sync1; + reg [9:0] wr_ptr_gray_sync2; + wire wrclk; + wire wrfull; + wire wrreq; + wire [8:0] wrusedw; + + + assign wrusedw = (wr_ptr_bin[8:0] - rd_ptr_gray_sync2[8:0]); + assign wrfull = (wr_ptr_gray == {(~ rd_ptr_gray_sync2[9:8]), rd_ptr_gray_sync2[7:0]}); + assign rdempty = (rd_ptr_gray == wr_ptr_gray_sync2); + + always @(posedge wrclk) begin + rd_ptr_gray_sync1 <= rd_ptr_gray; + rd_ptr_gray_sync2 <= rd_ptr_gray_sync1; + end + + always @(posedge rdclk) begin + wr_ptr_gray_sync1 <= wr_ptr_gray; + wr_ptr_gray_sync2 <= wr_ptr_gray_sync1; + end + + initial begin + wr_ptr_bin = 0; + wr_ptr_gray = 0; + rd_ptr_bin = 0; + rd_ptr_gray = 0; + end + + always @(posedge wrclk) if ((wrreq && (!wrfull))) begin + mem[wr_ptr_bin[8:0]] <= data; + wr_ptr_bin <= (wr_ptr_bin + 10'h001); + wr_ptr_gray <= ((wr_ptr_bin + 32'h00000001) ^ ((wr_ptr_bin + 32'h00000001) >> 32'h00000001)); + end + + always @(posedge rdclk) if ((rdreq && (!rdempty))) begin + q <= mem[rd_ptr_bin[8:0]]; + rd_ptr_bin <= (rd_ptr_bin + 10'h001); + rd_ptr_gray <= ((rd_ptr_bin + 32'h00000001) ^ ((rd_ptr_bin + 32'h00000001) >> 32'h00000001)); + end +endmodule /* simple_dcfifo */ diff --git a/RTL/hdmi_sync_gen.v b/RTL/hdmi_sync_gen.v index 74f2c29..ca3cec1 100644 --- a/RTL/hdmi_sync_gen.v +++ b/RTL/hdmi_sync_gen.v @@ -1,33 +1,82 @@ +`timescale 1ns/1ps -// 720p (1280x720 @ 60Hz) HDMI Sync Generator -// Pixel Clock: 74.25 MHz +// 960x540 (qHD @ 60Hz) HDMI Sync Generator +// Pixel Clock: ~37.8 MHz module hdmi_sync_gen ( - input wire clk, // 74.25 MHz + input wire clk, // CSR Clock (50 MHz) + input wire clk_pixel, // HDMI Pixel Clock (~37.8 MHz) input wire reset_n, - // HDMI Signals + // HDMI Signals (Pixel Domain) output reg [23:0] hdmi_d, output reg hdmi_de, output reg hdmi_hs, output reg hdmi_vs, - // Avalon-MM Slave Interface for Control + // Avalon-MM Slave Interface (CSR Domain) input wire [2:0] avs_address, input wire avs_read, input wire avs_write, input wire [31:0] avs_writedata, output wire [31:0] avs_readdata, - output reg avs_readdatavalid + output reg avs_readdatavalid, + + // Status (CSR Domain) + output wire [31:0] reg_mode_out, + output wire dma_enable_out, + output wire [31:0] shadow_ptr_out, + + // Stream Interface (Pixel Domain) + input wire [23:0] stream_data_in, + output wire stream_rd_en, + + // Status from DMA (CSR Domain) + input wire dma_busy, + input wire dma_done_in, + + // Control to DMA (CSR Domain) + output wire dma_start_out, + output wire dma_cont_en_out, + output reg vs_toggle // Toggle from Pixel Domain ); // Control Registers - reg [31:0] reg_mode; // Addr 0: Mode selection - reg [31:0] reg_gamma_ctrl; // Addr 1: Bit 0 = Gamma Enable - reg [31:0] reg_lut_addr; // Addr 2: LUT Address (0-255) - reg [31:0] reg_lut_data; // Addr 3: LUT Data (8-bit) + reg [31:0] reg_mode; // Addr 0: Mode selection + reg [31:0] reg_global_ctrl; // Addr 1: [31]Busy(R), [30]Done(RW1C), [2]Start(W), [1]Cont(RW), [0]Gamma(RW) + reg [31:0] reg_lut_addr; // Addr 2: LUT Address (0-255) + reg [31:0] reg_lut_data; // Addr 3: LUT Data (8-bit) reg [31:0] reg_bitmap_addr; // Addr 4: Bitmap Update Addr (0-15) reg [31:0] reg_bitmap_data; // Addr 5: Bitmap Update Data (16-bit) + reg [31:0] reg_frame_ptr; // Addr 6: Frame Pointer (DDR3 Address) + reg [31:0] shadow_ptr; // Internal Shadow Pointer + + reg dma_start_pulse; + reg dma_done_sticky; + + assign reg_mode_out = reg_mode; + assign dma_enable_out = reg_global_ctrl[1]; // Continuous Mode + assign dma_cont_en_out = reg_global_ctrl[1]; + assign dma_start_out = dma_start_pulse; + assign shadow_ptr_out = shadow_ptr; + reg [11:0] h_cnt; + reg [11:0] v_cnt; + reg visible_d1; + reg hs_d1; + reg vs_d1; + + initial begin + h_cnt = 0; + v_cnt = 0; + visible_d1 = 0; + hs_d1 = 0; + vs_d1 = 0; + hdmi_d = 0; + hdmi_de = 0; + hdmi_hs = 1; + hdmi_vs = 1; + vs_toggle = 0; + end // Character Bitmap Memory (16x16) // Each entry is one row (16 bits) @@ -38,38 +87,61 @@ module hdmi_sync_gen ( // Read Logic: Explicit Case for Address Decoding reg [31:0] read_data_mux; - assign avs_readdata = read_data_mux; + reg [31:0] avs_readdata_reg; + assign avs_readdata = avs_readdata_reg; always @(*) begin case (avs_address) 3'd0: read_data_mux = reg_mode; - 3'd1: read_data_mux = reg_gamma_ctrl; + 3'd1: read_data_mux = {dma_busy, dma_done_sticky, 28'd0, reg_global_ctrl[1], reg_global_ctrl[0]}; 3'd2: read_data_mux = reg_lut_addr; 3'd3: read_data_mux = reg_lut_data; 3'd4: read_data_mux = reg_bitmap_addr; 3'd5: read_data_mux = reg_bitmap_data; + 3'd6: read_data_mux = reg_frame_ptr; default: read_data_mux = 32'd0; endcase end + // Avalon-MM WaitRequest Logic + // We can handle writes immediately (1 cycle), but for robustness with CDC, + // let's add a simple wait state machine or just drive waitrequest low after 1 cycle. + // Actually, for this simple slave, we can just be always ready (waitrequest=0) + // BUT, if the Nios is too fast, we might need it. + // Let's implement a simple 1-cycle wait for READs to ensure data is stable. + always @(posedge clk or negedge reset_n) begin if (!reset_n) begin reg_mode <= 32'd0; - reg_gamma_ctrl <= 32'd0; // Default: Gamma Disabled + reg_global_ctrl <= 32'd0; reg_lut_addr <= 32'd0; reg_lut_data <= 32'd0; + reg_frame_ptr <= 32'h30000000; avs_readdatavalid <= 1'b0; - // Initialize bitmap to 0 - char_bitmap[0] <= 16'd0; char_bitmap[1] <= 16'd0; char_bitmap[2] <= 16'd0; char_bitmap[3] <= 16'd0; + dma_start_pulse <= 1'b0; + dma_done_sticky <= 1'b0; + dma_done_sticky <= 1'b0; + // Initialize bitmap to 0... [Omitted] + char_bitmap[0] <= 16'd0; char_bitmap[1] <= 16'd0; char_bitmap[2] <= 16'd0; char_bitmap[3] <= 16'd0; char_bitmap[4] <= 16'd0; char_bitmap[5] <= 16'd0; char_bitmap[6] <= 16'd0; char_bitmap[7] <= 16'd0; char_bitmap[8] <= 16'd0; char_bitmap[9] <= 16'd0; char_bitmap[10] <= 16'd0; char_bitmap[11] <= 16'd0; char_bitmap[12] <= 16'd0; char_bitmap[13] <= 16'd0; char_bitmap[14] <= 16'd0; char_bitmap[15] <= 16'd0; end else begin - // Write Logic + dma_start_pulse <= 1'b0; + + dma_start_pulse <= 1'b0; + + // Set done sticky on DMA signal + if (dma_done_in) dma_done_sticky <= 1'b1; + if (avs_write) begin case (avs_address) 3'd0: reg_mode <= avs_writedata; - 3'd1: reg_gamma_ctrl <= avs_writedata; + 3'd1: begin + reg_global_ctrl[1:0] <= avs_writedata[1:0]; + if (avs_writedata[2]) dma_start_pulse <= 1'b1; + if (avs_writedata[30]) dma_done_sticky <= 1'b0; + end 3'd2: reg_lut_addr <= avs_writedata; 3'd3: begin reg_lut_data <= avs_writedata; @@ -80,33 +152,39 @@ module hdmi_sync_gen ( reg_bitmap_data <= avs_writedata; char_bitmap[reg_bitmap_addr[3:0]] <= avs_writedata[15:0]; end + 3'd6: reg_frame_ptr <= avs_writedata; default: ; endcase end // Read Valid Logic (1-cycle latency) avs_readdatavalid <= avs_read; + + // Register Read Data to align with Valid (T+1) + // If read is asserted, capture the mux output for the next cycle + if (avs_read) begin + avs_readdata_reg <= read_data_mux; + end end end - // 720p Timing Parameters - parameter H_VISIBLE = 1280; - parameter H_FRONT = 110; - parameter H_SYNC = 40; - parameter H_BACK = 220; - parameter H_TOTAL = 1650; + // 960x540 (qHD) Timing Parameters + parameter H_VISIBLE = 960; + parameter H_FRONT = 48; + parameter H_SYNC = 32; + parameter H_BACK = 80; + parameter H_TOTAL = 1120; - parameter V_VISIBLE = 720; - parameter V_FRONT = 5; + parameter V_VISIBLE = 540; + parameter V_FRONT = 3; parameter V_SYNC = 5; - parameter V_BACK = 20; - parameter V_TOTAL = 750; + parameter V_BACK = 15; + parameter V_TOTAL = 563; - reg [11:0] h_cnt; - reg [11:0] v_cnt; // Horizontal Counter - always @(posedge clk or negedge reset_n) begin + // Horizontal Counter + always @(posedge clk_pixel or negedge reset_n) begin if (!reset_n) h_cnt <= 12'd0; else if (h_cnt == H_TOTAL - 1) @@ -116,7 +194,7 @@ module hdmi_sync_gen ( end // Vertical Counter - always @(posedge clk or negedge reset_n) begin + always @(posedge clk_pixel or negedge reset_n) begin if (!reset_n) v_cnt <= 12'd0; else if (h_cnt == H_TOTAL - 1) begin @@ -132,20 +210,49 @@ module hdmi_sync_gen ( wire hs_wire = (h_cnt >= (H_VISIBLE + H_FRONT) && h_cnt < (H_VISIBLE + H_FRONT + H_SYNC)); wire vs_wire = (v_cnt >= (V_VISIBLE + V_FRONT) && v_cnt < (V_VISIBLE + V_FRONT + V_SYNC)); - always @(posedge clk or negedge reset_n) begin + // Pipeline Registers for DE and Data synchronization (clk_pixel domain) + + always @(posedge clk_pixel or negedge reset_n) begin if (!reset_n) begin - hdmi_hs <= 1'b0; - hdmi_vs <= 1'b0; + hdmi_hs <= 1'b1; + hdmi_vs <= 1'b1; hdmi_de <= 1'b0; + visible_d1 <= 1'b0; + hs_d1 <= 1'b0; + vs_d1 <= 1'b0; + vs_toggle <= 1'b0; + end else begin + // Shift pipeline + visible_d1 <= visible; + hs_d1 <= hs_wire; + vs_d1 <= vs_wire; + + // Output registers (2-cycle delayed from internal counters) + // Using Active-LOW syncs + hdmi_hs <= ~hs_d1; + hdmi_vs <= ~vs_d1; + hdmi_de <= visible_d1; + + // VSync toggle for CDC (DMA needs this edge in 50MHz domain) + if (vs_wire && !vs_d1) vs_toggle <= ~vs_toggle; + end + end + + // Shadow Pointer Update logic (CDC: vs_wire sync to clk) + reg [2:0] vs_sync_sh; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + vs_sync_sh <= 3'b0; + shadow_ptr <= 32'h30000000; end else begin - hdmi_hs <= hs_wire; - hdmi_vs <= vs_wire; - hdmi_de <= visible; + vs_sync_sh <= {vs_sync_sh[1:0], vs_wire}; + if (vs_sync_sh[1] && !vs_sync_sh[2]) begin // Sampling rising edge of VSync in clk domain + shadow_ptr <= reg_frame_ptr; + end end end // Pixel Data Generation Based on Mode - wire [7:0] plain_r, plain_g, plain_b; reg [23:0] pre_gamma_d; // LUT Logic (Apply only if Gamma Enable is 1) @@ -153,15 +260,17 @@ module hdmi_sync_gen ( wire [7:0] gamma_g = lut_mem[pre_gamma_d[15:8]]; wire [7:0] gamma_b = lut_mem[pre_gamma_d[7:0]]; - wire [7:0] gray = h_cnt[7:0]; - wire grid_line = (h_cnt[5:0] == 6'd0) || (v_cnt[5:0] == 6'd0); - wire [2:0] bar_idx = (h_cnt < 160) ? 3'd0 : - (h_cnt < 320) ? 3'd1 : - (h_cnt < 480) ? 3'd2 : - (h_cnt < 640) ? 3'd3 : - (h_cnt < 800) ? 3'd4 : - (h_cnt < 960) ? 3'd5 : - (h_cnt < 1120) ? 3'd6 : 3'd7; + wire [7:0] gray = (h_cnt < H_VISIBLE) ? ( (h_cnt * 255) / (H_VISIBLE-1) ) : 8'd0; + wire grid_line = ( (h_cnt < H_VISIBLE) && (v_cnt < V_VISIBLE) ) && ( ((h_cnt % 60) == 0) || ((v_cnt % 60) == 0) ); + + // Resolution-aware bar index calculation (8 bars) + wire [2:0] bar_idx = (h_cnt < 1*H_VISIBLE/8) ? 3'd0 : + (h_cnt < 2*H_VISIBLE/8) ? 3'd1 : + (h_cnt < 3*H_VISIBLE/8) ? 3'd2 : + (h_cnt < 4*H_VISIBLE/8) ? 3'd3 : + (h_cnt < 5*H_VISIBLE/8) ? 3'd4 : + (h_cnt < 6*H_VISIBLE/8) ? 3'd5 : + (h_cnt < 7*H_VISIBLE/8) ? 3'd6 : 3'd7; wire [7:0] gray8_val = {bar_idx, 5'd0}; // Each step is 32 // Character Tile Logic (16x16 Scaling 4x -> 64x64 Tile) @@ -169,37 +278,49 @@ module hdmi_sync_gen ( wire [3:0] char_col_idx = h_cnt[5:2]; // 0-15 wire [15:0] current_row_bits = char_bitmap[char_row_idx]; wire char_pixel = current_row_bits[15 - char_col_idx]; // Leftmost bit is col 0 + // Dynamic Color for Character Rendering (Rainbow effect based on coordinates) wire [7:0] fancy_r = h_cnt[7:0] + v_cnt[7:0]; wire [7:0] fancy_g = h_cnt[9:2]; wire [7:0] fancy_b = v_cnt[9:2]; wire [23:0] char_color = char_pixel ? {fancy_r, fancy_g, fancy_b} : 24'h000000; + + // Stream RD Enable: Read from FIFO only in visible area when mode is 8 + // Stream RD Enable: Read from FIFO only in visible area when mode is 8 + // FIFO read has 1-cycle latency, and hdmi_d adds another 1-cycle latency. + // So we read at T=0 (visible), data valid at T=1, latch into hdmi_d at T=1, + // and hdmi_de goes high at T=2. + assign stream_rd_en = (visible && v_cnt < V_VISIBLE && (reg_mode[3:0] == 4'd8)); + // Pixel Data Generation (Combinational based on H/V counters) always @(*) begin - case (reg_mode[2:0]) - 3'd0: pre_gamma_d = 24'hFF0000; // Red - 3'd1: pre_gamma_d = 24'h00FF00; // Green - 3'd2: pre_gamma_d = 24'h0000FF; // Blue - 3'd3: pre_gamma_d = {gray, gray, gray}; // Grayscale Ramp - 3'd4: pre_gamma_d = grid_line ? 24'hFFFFFF : 24'h000000; // Grid - 3'd5: pre_gamma_d = 24'hFFFFFF; // Solid White - 3'd6: pre_gamma_d = {gray8_val, gray8_val, gray8_val}; // 8-level Gray Scale - 3'd7: pre_gamma_d = char_color; // Character Tile 4x + case (reg_mode[3:0]) + 4'd0: pre_gamma_d = 24'hFF0000; // Red + 4'd1: pre_gamma_d = 24'h00FF00; // Green + 4'd2: pre_gamma_d = 24'h0000FF; // Blue + 4'd3: pre_gamma_d = {gray, gray, gray}; // Grayscale Ramp + 4'd4: pre_gamma_d = grid_line ? 24'hFFFFFF : 24'h000000; // Grid + 4'd5: pre_gamma_d = 24'hFFFFFF; // Solid White + 4'd6: pre_gamma_d = {gray8_val, gray8_val, gray8_val}; // 8-level Gray Scale + 4'd7: pre_gamma_d = char_color; // Character Tile 4x + 4'd8: pre_gamma_d = stream_data_in; // DMA Stream default: pre_gamma_d = 24'hFFFFFF; // White endcase end - always @(posedge clk or negedge reset_n) begin + // Final Output Stage (clk_pixel Domain) + always @(posedge clk_pixel or negedge reset_n) begin if (!reset_n) begin hdmi_d <= 24'h000000; end else begin - if (visible) begin // Use 'visible' wire to align with hdmi_de register update - if (reg_gamma_ctrl[0]) + if (visible_d1) begin + // If Gamma is enabled (Bit 0 of global ctrl) + if (reg_global_ctrl[0]) hdmi_d <= {gamma_r, gamma_g, gamma_b}; else hdmi_d <= pre_gamma_d; end else begin - hdmi_d <= 24'h000000; // Blank + hdmi_d <= 24'h000000; // Blanking end end end diff --git a/RTL/simple_dcfifo.v b/RTL/simple_dcfifo.v new file mode 100644 index 0000000..ab89834 --- /dev/null +++ b/RTL/simple_dcfifo.v @@ -0,0 +1,119 @@ +`timescale 1ns/1ps + +module simple_dcfifo #( + parameter DATA_WIDTH = 32, + parameter ADDR_WIDTH = 9 // 512 depth +)( + input wire wrclk, + input wire [DATA_WIDTH-1:0] data, + input wire wrreq, + output wire [ADDR_WIDTH-1:0] wrusedw, + output wire wrfull, + + input wire rdclk, + input wire rdreq, + output reg [DATA_WIDTH-1:0] q, + output wire rdempty +); + + // ---------------------------------------------------------------- + // 1. Pointers & CDC + // ---------------------------------------------------------------- + // Pointers are ADDR_WIDTH+1 bits to distinguish Full/Empty + reg [ADDR_WIDTH:0] wr_ptr_bin; + reg [ADDR_WIDTH:0] wr_ptr_gray; + reg [ADDR_WIDTH:0] rd_ptr_bin; + reg [ADDR_WIDTH:0] rd_ptr_gray; + + reg [ADDR_WIDTH:0] wr_ptr_gray_sync1, wr_ptr_gray_sync2; + reg [ADDR_WIDTH:0] rd_ptr_gray_sync1, rd_ptr_gray_sync2; + + // ---------------------------------------------------------------- + // 2. Memory (Infer Block RAM) + // ---------------------------------------------------------------- + reg [DATA_WIDTH-1:0] mem [(1<> 1); + end + endfunction + + function [ADDR_WIDTH:0] gray2bin; + input [ADDR_WIDTH:0] gray; + integer i; + begin + gray2bin[ADDR_WIDTH] = gray[ADDR_WIDTH]; + for (i = ADDR_WIDTH-1; i >= 0; i = i - 1) + gray2bin[i] = gray2bin[i+1] ^ gray[i]; + end + endfunction + + // ---------------------------------------------------------------- + // 5. Initial for Simulation + // ---------------------------------------------------------------- + integer i; + initial begin + wr_ptr_bin = 0; wr_ptr_gray = 0; + rd_ptr_bin = 0; rd_ptr_gray = 0; + wr_ptr_gray_sync1 = 0; wr_ptr_gray_sync2 = 0; + rd_ptr_gray_sync1 = 0; rd_ptr_gray_sync2 = 0; + q = 0; // Initialize output to 0 to avoid X + end + + // ---------------------------------------------------------------- + // 6. Write Logic & Usage Calculation + // ---------------------------------------------------------------- + wire [ADDR_WIDTH:0] rd_ptr_bin_sync = gray2bin(rd_ptr_gray_sync2); + + // Check Full: Gray code comparison + // Full if top 2 bits differ, rest match + assign wrfull = (wr_ptr_gray == {~rd_ptr_gray_sync2[ADDR_WIDTH:ADDR_WIDTH-1], rd_ptr_gray_sync2[ADDR_WIDTH-2:0]}); + + // Used Words: Subtract Binary Pointers + wire [ADDR_WIDTH:0] used_diff = wr_ptr_bin - rd_ptr_bin_sync; + + // Saturate to Max Value (all 1s) if actual usage is Full (bit ADDR_WIDTH is 1) + // This protects against wrapping to 0 which would confuse the DMA Master + assign wrusedw = (used_diff[ADDR_WIDTH]) ? {ADDR_WIDTH{1'b1}} : used_diff[ADDR_WIDTH-1:0]; + + always @(posedge wrclk) begin + if (wrreq && !wrfull) begin + mem[wr_ptr_bin[ADDR_WIDTH-1:0]] <= data; + wr_ptr_bin <= wr_ptr_bin + 1; + wr_ptr_gray <= bin2gray(wr_ptr_bin + 1); + end + end + + // ---------------------------------------------------------------- + // 7. Read Logic + // ---------------------------------------------------------------- + // Check Empty: Gray code pointers match exactly + assign rdempty = (rd_ptr_gray == wr_ptr_gray_sync2); + + always @(posedge rdclk) begin + if (rdreq && !rdempty) begin + q <= mem[rd_ptr_bin[ADDR_WIDTH-1:0]]; + rd_ptr_bin <= rd_ptr_bin + 1; + rd_ptr_gray <= bin2gray(rd_ptr_bin + 1); + end + end + +endmodule diff --git a/RTL/sync_check b/RTL/sync_check new file mode 100644 index 0000000..a62babc --- /dev/null +++ b/RTL/sync_check @@ -0,0 +1,240 @@ +/* + * 1364-1995 Verilog generated by Icarus Verilog VLOG95 Code Generator, + * Version: 11.0 (stable) () + * Converted using TYPICAL delays and without signed support. + */ + +`timescale 1ns/1ps +/* This module was originally defined in file hdmi_sync_gen.v at line 6. */ +module hdmi_sync_gen(clk, reset_n, hdmi_d, hdmi_de, hdmi_hs, hdmi_vs, avs_address, avs_read, avs_write, avs_writedata, avs_readdata, avs_readdatavalid, reg_mode_out, dma_enable_out, shadow_ptr_out, stream_data_in, stream_rd_en, dma_busy, dma_done_in, dma_start_out, dma_cont_en_out); + input clk; + input reset_n; + output [23:0] hdmi_d; + output hdmi_de; + output hdmi_hs; + output hdmi_vs; + input [2:0] avs_address; + input avs_read; + input avs_write; + input [31:0] avs_writedata; + output [31:0] avs_readdata; + output avs_readdatavalid; + output [31:0] reg_mode_out; + output dma_enable_out; + output [31:0] shadow_ptr_out; + input [23:0] stream_data_in; + output stream_rd_en; + input dma_busy; + input dma_done_in; + output dma_start_out; + output dma_cont_en_out; + + parameter H_BACK = 220; + parameter H_FRONT = 110; + parameter H_SYNC = 40; + parameter H_TOTAL = 1650; + parameter H_VISIBLE = 1280; + parameter V_BACK = 20; + parameter V_FRONT = 5; + parameter V_SYNC = 5; + parameter V_TOTAL = 750; + parameter V_VISIBLE = 720; + + wire [2:0] avs_address; + wire avs_read; + wire [31:0] avs_readdata; + reg avs_readdatavalid; + wire avs_write; + wire [31:0] avs_writedata; + wire [2:0] bar_idx; + reg [15:0] char_bitmap [0:15]; + wire [3:0] char_col_idx; + wire [23:0] char_color; + wire char_pixel; + wire [3:0] char_row_idx; + wire clk; + wire [15:0] current_row_bits; + wire dma_busy; + wire dma_cont_en_out; + wire dma_done_in; + reg dma_done_sticky; + wire dma_enable_out; + wire dma_start_out; + reg dma_start_pulse; + wire [7:0] fancy_b; + wire [7:0] fancy_g; + wire [7:0] fancy_r; + wire [7:0] gamma_b; + wire [7:0] gamma_g; + wire [7:0] gamma_r; + wire [7:0] gray; + wire [7:0] gray8_val; + wire grid_line; + reg [11:0] h_cnt; + reg [23:0] hdmi_d; + reg hdmi_de; + reg hdmi_hs; + reg hdmi_vs; + wire hs_wire; + reg [7:0] lut_mem [0:255]; + reg [23:0] pre_gamma_d; + reg [31:0] read_data_mux; + reg [31:0] reg_bitmap_addr; + reg [31:0] reg_bitmap_data; + reg [31:0] reg_frame_ptr; + reg [31:0] reg_global_ctrl; + reg [31:0] reg_lut_addr; + reg [31:0] reg_lut_data; + reg [31:0] reg_mode; + wire [31:0] reg_mode_out; + wire reset_n; + reg [31:0] shadow_ptr; + wire [31:0] shadow_ptr_out; + wire [23:0] stream_data_in; + wire stream_rd_en; + reg [11:0] v_cnt; + wire visible; + wire vs_edge; + reg vs_prev; + reg vs_toggle; + wire vs_wire; + + + assign dma_enable_out = reg_global_ctrl[1]; + assign dma_cont_en_out = reg_global_ctrl[1]; + assign gray = h_cnt[7:0]; + assign bar_idx = ((32'h000000a0 > {20'h00000, h_cnt}) ? 3'h0 : ((32'h00000140 > {20'h00000, h_cnt}) ? 3'h1 : ((32'h000001e0 > {20'h00000, h_cnt}) ? 3'h2 : ((32'h00000280 > {20'h00000, h_cnt}) ? 3'h3 : ((32'h00000320 > {20'h00000, h_cnt}) ? 3'h4 : ((32'h000003c0 > {20'h00000, h_cnt}) ? 3'h5 : ((32'h00000460 > {20'h00000, h_cnt}) ? 3'h6 : 3'h7))))))); + assign gray8_val = {bar_idx, 5'h00}; + assign char_row_idx = v_cnt[5:2]; + assign char_col_idx = h_cnt[5:2]; + assign char_pixel = current_row_bits[(32'h0000000f - {28'h0000000, char_col_idx})]; + assign fancy_r = (h_cnt[7:0] + v_cnt[7:0]); + assign fancy_g = h_cnt[9:2]; + assign fancy_b = v_cnt[9:2]; + assign char_color = (char_pixel ? {fancy_r, fancy_g, fancy_b} : 24'h000000); + assign reg_mode_out = reg_mode; + assign dma_start_out = dma_start_pulse; + assign shadow_ptr_out = shadow_ptr; + assign avs_readdata = read_data_mux; + assign visible = ((H_VISIBLE > {20'h00000, h_cnt}) & (V_VISIBLE > {20'h00000, v_cnt})); + assign hs_wire = (({20'h00000, h_cnt} >= 32'h0000056e) & (32'h00000596 > {20'h00000, h_cnt})); + assign vs_wire = (({20'h00000, v_cnt} >= 32'h000002d5) & (32'h000002da > {20'h00000, v_cnt})); + assign vs_edge = (vs_wire & (~|vs_prev)); + assign gamma_r = lut_mem[{2'h0, pre_gamma_d[23:16]} + 0]; + assign gamma_g = lut_mem[{2'h0, pre_gamma_d[15:8]} + 0]; + assign gamma_b = lut_mem[{2'h0, pre_gamma_d[7:0]} + 0]; + assign grid_line = ((h_cnt[5:0] == 6'h00) | (v_cnt[5:0] == 6'h00)); + assign current_row_bits = char_bitmap[{2'h0, char_row_idx} + 0]; + assign stream_rd_en = (visible & (reg_mode[3:0] == 4'h8)); + + always @(avs_address or reg_mode or dma_busy or dma_done_sticky or reg_global_ctrl or reg_lut_addr or reg_lut_data or reg_bitmap_addr or reg_bitmap_data or reg_frame_ptr) case (avs_address) + 3'h0: read_data_mux = reg_mode; + 3'h1: read_data_mux = {dma_busy, dma_done_sticky, 28'h0000000, reg_global_ctrl[1], reg_global_ctrl[0]}; + 3'h2: read_data_mux = reg_lut_addr; + 3'h3: read_data_mux = reg_lut_data; + 3'h4: read_data_mux = reg_bitmap_addr; + 3'h5: read_data_mux = reg_bitmap_data; + 3'h6: read_data_mux = reg_frame_ptr; + default: read_data_mux = 32'h00000000; + endcase + + always @(posedge clk or negedge reset_n) if ((!reset_n)) begin + reg_mode <= 32'h00000000; + reg_global_ctrl <= 32'h00000000; + reg_lut_addr <= 32'h00000000; + reg_lut_data <= 32'h00000000; + reg_frame_ptr <= 32'h30000000; + avs_readdatavalid <= 1'b0; + dma_start_pulse <= 1'b0; + dma_done_sticky <= 1'b0; + char_bitmap[0] <= 16'h0000; + char_bitmap[1] <= 16'h0000; + char_bitmap[2] <= 16'h0000; + char_bitmap[3] <= 16'h0000; + char_bitmap[4] <= 16'h0000; + char_bitmap[5] <= 16'h0000; + char_bitmap[6] <= 16'h0000; + char_bitmap[7] <= 16'h0000; + char_bitmap[8] <= 16'h0000; + char_bitmap[9] <= 16'h0000; + char_bitmap[10] <= 16'h0000; + char_bitmap[11] <= 16'h0000; + char_bitmap[12] <= 16'h0000; + char_bitmap[13] <= 16'h0000; + char_bitmap[14] <= 16'h0000; + char_bitmap[15] <= 16'h0000; + end + else begin + dma_start_pulse <= 1'b0; + if (dma_done_in) dma_done_sticky <= 1'b1; + if (avs_write) case (avs_address) + 3'h0: reg_mode <= avs_writedata; + 3'h1: begin + reg_global_ctrl <= avs_writedata; + if (avs_writedata[2]) dma_start_pulse <= 1'b1; + if (avs_writedata[30]) dma_done_sticky <= 1'b0; + end + 3'h2: reg_lut_addr <= avs_writedata; + 3'h3: begin + reg_lut_data <= avs_writedata; + lut_mem[reg_lut_addr[7:0]] <= avs_writedata[7:0]; + end + 3'h4: reg_bitmap_addr <= avs_writedata; + 3'h5: begin + reg_bitmap_data <= avs_writedata; + char_bitmap[reg_bitmap_addr[3:0]] <= avs_writedata[15:0]; + end + 3'h6: reg_frame_ptr <= avs_writedata; + default:; + endcase + avs_readdatavalid <= avs_read; + end + + always @(posedge clk or negedge reset_n) if ((!reset_n)) h_cnt <= 12'h000; + else if ((h_cnt == 32'h00000671)) h_cnt <= 12'h000; + else h_cnt <= (h_cnt + 12'h001); + + always @(posedge clk or negedge reset_n) if ((!reset_n)) v_cnt <= 12'h000; + else if ((h_cnt == 32'h00000671)) if ((v_cnt == 32'h000002ed)) v_cnt <= 12'h000; + else v_cnt <= (v_cnt + 12'h001); + + always @(posedge clk or negedge reset_n) if ((!reset_n)) begin + hdmi_hs <= 1'b0; + hdmi_vs <= 1'b0; + hdmi_de <= 1'b0; + vs_prev <= 1'b0; + end + else begin + hdmi_hs <= hs_wire; + hdmi_vs <= vs_wire; + hdmi_de <= visible; + vs_prev <= vs_wire; + end + + always @(posedge clk or negedge reset_n) if ((!reset_n)) begin + shadow_ptr <= 32'h30000000; + vs_toggle <= 1'b0; + end + else if (vs_edge) begin + shadow_ptr <= reg_frame_ptr; + vs_toggle <= (~vs_toggle); + end + + always @(reg_mode or gray or grid_line or gray8_val or char_color) case (reg_mode[3:0]) + 4'h0: pre_gamma_d = 24'hff0000; + 4'h1: pre_gamma_d = 24'h00ff00; + 4'h2: pre_gamma_d = 24'h0000ff; + 4'h3: pre_gamma_d = {gray, gray, gray}; + 4'h4: pre_gamma_d = (grid_line ? 24'hffffff : 24'h000000); + 4'h5: pre_gamma_d = 24'hffffff; + 4'h6: pre_gamma_d = {gray8_val, gray8_val, gray8_val}; + 4'h7: pre_gamma_d = char_color; + default: pre_gamma_d = 24'hffffff; + endcase + + always @(posedge clk or negedge reset_n) if ((!reset_n)) hdmi_d <= 24'h000000; + else if (visible) if (reg_global_ctrl[0]) hdmi_d <= {gamma_r, gamma_g, gamma_b}; + else if ((reg_mode[3:0] == 4'h8)) hdmi_d <= stream_data_in; + else hdmi_d <= pre_gamma_d; + else hdmi_d <= 24'h000000; +endmodule /* hdmi_sync_gen */ diff --git a/RTL/video_dma_master.v b/RTL/video_dma_master.v new file mode 100644 index 0000000..3f710d7 --- /dev/null +++ b/RTL/video_dma_master.v @@ -0,0 +1,188 @@ +`timescale 1ns/1ps + +module video_dma_master ( + input wire clk, + input wire reset_n, + input wire [31:0] start_addr, + + // Control & Status + input wire dma_start, // Pulse to start a single frame transfer + input wire dma_cont_en, // Continuous mode enable + output reg dma_done, // Pulse when one frame is finished + output wire busy, + input wire vsync_edge, // Trigger for new frame in continuous mode + + // Avalon-MM Master Interface + input wire m_waitrequest, + input wire [31:0] m_readdata, + input wire m_readdatavalid, + output reg [31:0] m_address, + output reg m_read, + output wire [7:0] m_burstcount, + + // FIFO Interface (Write side) + input wire [8:0] fifo_used, + output wire fifo_wr_en, + output wire [31:0] fifo_wr_data +); + + // Initial Parameters + parameter BURST_LEN = 8'd64; // Burst size (256 bytes) + parameter FIFO_DEPTH = 512; // FIFO size in words + parameter H_RES = 1280; + parameter V_RES = 720; + parameter FRAME_SIZE_WORDS = H_RES * V_RES; // Total 32-bit words per frame + + // FSM States + localparam IDLE = 2'b00; + localparam CHECK_FIFO= 2'b01; // Check if we can issue a read command + localparam ISSUE_READ= 2'b10; // Issue Avalon Read Command + localparam WAIT_END = 2'b11; // Wait for all data to return + + reg [1:0] state; + reg [31:0] current_read_addr; + + // Counters for Flow Control + reg [31:0] words_commanded; // Total words requested so far + reg [31:0] words_received; // Total words received so far from Avalon + reg [9:0] pending_bursts; // Number of bursts issued but not fully received + + reg is_cont_mode; + reg frame_active; // Starts on Trigger, Ends when words_received == FRAME_SIZE + + // Assignments + assign m_burstcount = BURST_LEN; + assign fifo_wr_en = m_readdatavalid; + assign fifo_wr_data = m_readdata; + assign busy = frame_active; + + // ------------------------------------------------------------------ + // 1. Main Control FSM (Command Issuer) + // ------------------------------------------------------------------ + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + state <= IDLE; + m_address <= 32'd0; + m_read <= 1'b0; + current_read_addr <= 32'd0; + words_commanded <= 32'd0; + is_cont_mode <= 1'b0; + frame_active <= 1'b0; + pending_bursts <= 10'd0; + end else begin + // Default signals + // Default signals + // dma_done is driven by separate logic + + // Pending Bursts Counter + // Increment on Command Issue success + // Decrement on Burst Completion? No, decrement on every word received is hard. + // Let's track pending words instead? + // Simpler: pending_words = words_commanded - words_received. + + case (state) + IDLE: begin + m_read <= 1'b0; + words_commanded <= 32'd0; + + // Trigger Logic + if (dma_start) begin + current_read_addr <= start_addr; + is_cont_mode <= 1'b0; + frame_active <= 1'b1; + state <= CHECK_FIFO; + end else if (dma_cont_en && vsync_edge) begin + current_read_addr <= start_addr; + is_cont_mode <= 1'b1; + frame_active <= 1'b1; + state <= CHECK_FIFO; + end else begin + frame_active <= 1'b0; + end + end + + CHECK_FIFO: begin + m_read <= 1'b0; + + // 1. Check if we have issued all commands for this frame + if (words_commanded >= FRAME_SIZE_WORDS) begin + state <= WAIT_END; + end + // 2. Check FIFO Overflow Risk + // Condition: (Used + Pending_from_commands) < (Depth - Command_Size) + // pending_words = words_commanded - words_received (Calculated below) + // If FIFO has space for at least one more burst: + else if ((fifo_used + (words_commanded - words_received)) <= (FIFO_DEPTH - BURST_LEN - 2)) begin + // Safe to issue a read + m_address <= current_read_addr; + m_read <= 1'b1; + state <= ISSUE_READ; + end + // Else: Wait here until data is drained from FIFO or received + end + + ISSUE_READ: begin + if (!m_waitrequest) begin + // Command Accepted + m_read <= 1'b0; + current_read_addr <= current_read_addr + (BURST_LEN * 4); + words_commanded <= words_commanded + BURST_LEN; + state <= CHECK_FIFO; + end + // Else: Stay in ISSUE_READ with m_read high + end + + WAIT_END: begin + m_read <= 1'b0; + // Wait for Data Receiver to catch up + if (words_received >= FRAME_SIZE_WORDS) begin + state <= IDLE; + // frame_active will be cleared by data logic or here? + // Let's clear it here. + frame_active <= 1'b0; + end + end + endcase + + // Emergency Stop (Only in Continuous Mode, between frames or forceful?) + if (is_cont_mode && !dma_cont_en && state == IDLE) begin + is_cont_mode <= 1'b0; + end + end + end + + // ------------------------------------------------------------------ + // 2. Data Receiver and Done Logic + // ------------------------------------------------------------------ + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + words_received <= 32'd0; + end else begin + // Reset received count when starting a new frame + if (state == IDLE && (dma_start || (dma_cont_en && vsync_edge))) begin + words_received <= 32'd0; + end + + // Count valid data + if (m_readdatavalid) begin + words_received <= words_received + 1; + end + end + end + + // ------------------------------------------------------------------ + // 3. Done Pulse Generation + // ------------------------------------------------------------------ + always @(posedge clk or negedge reset_n) begin + if (!reset_n) dma_done <= 1'b0; + else begin + // Fire Done when we just finished receiving the last word + if (m_readdatavalid && (words_received == FRAME_SIZE_WORDS - 1)) begin + dma_done <= 1'b1; + end else begin + dma_done <= 1'b0; + end + end + end + +endmodule diff --git a/RTL/video_pipeline.v b/RTL/video_pipeline.v new file mode 100644 index 0000000..bce7845 --- /dev/null +++ b/RTL/video_pipeline.v @@ -0,0 +1,174 @@ +`timescale 1ns/1ps + +module video_pipeline ( + // Clocks & Reset + input wire clk_50, // DMA & FIFO Write Clock + input wire clk_hdmi, // HDMI Pixel Clock (~37.8 MHz) + input wire reset_n, + + // Avalon-MM Master Interface (to DDR3) + input wire m_waitrequest, + input wire [31:0] m_readdata, + input wire m_readdatavalid, + output wire [31:0] m_address, + output wire m_read, + output wire [7:0] m_burstcount, + + // Avalon-MM Slave Interface (Control from Nios II) + input wire [2:0] s_address, + input wire s_read, + input wire s_write, + input wire [31:0] s_writedata, + output wire [31:0] s_readdata, + output wire s_readdatavalid, + + // HDMI Physical Output Signals + output wire [23:0] hdmi_d, + output wire hdmi_de, + output wire hdmi_hs, + output wire hdmi_vs, + // Debug LEDs + output wire [7:0] debug_leds +); + + // Internal connections + // hdmi_d, hdmi_de, hdmi_hs, hdmi_vs are output ports + + wire vs_toggle_raw; // New VSync Toggle from Sync Gen + + // Internal signals (Missing declarations added) + wire [31:0] shadow_ptr; + wire [8:0] fifo_used; + wire fifo_wr_en; + wire [31:0] fifo_wr_data; + wire fifo_full; + wire fifo_rd_en; + wire [31:0] fifo_rd_data; + wire fifo_empty; + wire dma_busy; + wire dma_en; + wire [31:0] reg_mode; + wire dma_done_50; + // wire dma_start_74; // Removed, using direct connection + // wire dma_cont_74; // Removed, using direct connection + + // Pipeline status (Internal) + wire [7:0] pipeline_debug; + + // 1. CDC (V-Sync, Start, Cont, Done) + // 1.1 V-Sync: 74MHz -> 50MHz (Using Toggle from Sync Gen) + reg [2:0] vsync_toggle_sync_50; + always @(posedge clk_50 or negedge reset_n) begin + if (!reset_n) vsync_toggle_sync_50 <= 3'b0; + else vsync_toggle_sync_50 <= {vsync_toggle_sync_50[1:0], vs_toggle_raw}; + end + wire vsync_edge_sync = vsync_toggle_sync_50[2] ^ vsync_toggle_sync_50[1]; // Edge Detect + + // 1.2 Start & Cont: 50MHz -> 50MHz (Direct Connection) + // No CDC needed as both CSR (Nios) and DMA Master are on clk_50 + wire dma_start_direct; + wire dma_cont_direct; + + // 1.3 Done: 50MHz -> 50MHz (Direct Connection) + wire dma_done_direct; + assign dma_done_direct = dma_done_50; + + // 2. Video DMA Master (Reads from DDR3) + video_dma_master #( + .H_RES(960), + .V_RES(540) + ) u_dma_master ( + .clk (clk_50), + .reset_n (reset_n), + .start_addr (shadow_ptr), + .dma_start (dma_start_direct), + .dma_cont_en (dma_cont_direct), + .dma_done (dma_done_50), + .vsync_edge (vsync_edge_sync), + .m_waitrequest (m_waitrequest), + .m_readdata (m_readdata), + .m_readdatavalid (m_readdatavalid), + .m_address (m_address), + .m_read (m_read), + .m_burstcount (m_burstcount), + .fifo_used (fifo_used), + .fifo_wr_en (fifo_wr_en), + .fifo_wr_data (fifo_wr_data), + .busy (dma_busy) + ); + + // 3. Simple Dual Clock FIFO (Verilog Only) + simple_dcfifo #( + .DATA_WIDTH(32), + .ADDR_WIDTH(9) // 512 depth + ) u_simple_fifo ( + .wrclk (clk_50), + .data (fifo_wr_data), + .wrreq (fifo_wr_en), + .wrusedw (fifo_used), + .wrfull (fifo_full), + + .rdclk (clk_hdmi), + .rdreq (fifo_rd_en), + .q (fifo_rd_data), + .rdempty (fifo_empty) + ); + + // 4. HDMI Sync & Pattern Generator + hdmi_sync_gen u_hdmi_sync ( + .clk (clk_50), // CSR Clock + .clk_pixel (clk_hdmi), // Pixel Clock + .reset_n (reset_n), + .hdmi_d (hdmi_d), + .hdmi_de (hdmi_de), + .hdmi_hs (hdmi_hs), + .hdmi_vs (hdmi_vs), + + .avs_address (s_address), + .avs_read (s_read), + .avs_write (s_write), + .avs_writedata (s_writedata), + .avs_readdata (s_readdata), + .avs_readdatavalid (s_readdatavalid), + + .stream_data_in (fifo_rd_data[23:0]), + .stream_rd_en (fifo_rd_en), + + .shadow_ptr_out (shadow_ptr), + .reg_mode_out (reg_mode), + .dma_enable_out (dma_en), + + .dma_busy (dma_busy), + .dma_done_in (dma_done_direct), + .dma_start_out (dma_start_direct), + .dma_cont_en_out (dma_cont_direct), + .vs_toggle (vs_toggle_raw) + ); + + // Debug LED Logic (Stretched Pulses for visibility) + // dma_start_pulse is 1 clock wide. We need to stretch it or toggle it to see on LED. + // Let's just output raw signals, user can use logic analyzer or scope if needed, + // or trust the toggle nature of some signals. + // Debug LED Logic (Modified for Data Path Debugging) + // [0] FIFO Write Enable (Pulse) - Should flicker if data arrives + // [1] FIFO Read Enable (Pulse) - Should flicker if HDMI reads + // [2] FIFO Used MSB (Wait, local signal fifo_used is 9-bit) - Is FIFO filling up? + // [3] FIFO Empty (Active High) + // [4] DMA Start (Pulse 50MHz) + // [5] DMA Start Toggle (74MHz) + // [6] DMA Done (Toggle) + // [7] V-Sync Edge + + // We need to bring out internal signals from dma_master or assume them from assignments + // In video_pipeline, fifo_wr_en comes from u_dma_master. + + assign debug_leds[0] = fifo_wr_en; // Data arriving from DDR3? + assign debug_leds[1] = fifo_rd_en; // HDMI consuming data? + assign debug_leds[2] = fifo_used[8]; // FIFO Half Full? (If 1, overflow risk) + assign debug_leds[3] = fifo_empty; // Is FIFO empty? (Should be 0 during play) + assign debug_leds[4] = dma_start_direct; + assign debug_leds[5] = dma_cont_direct; + assign debug_leds[6] = dma_done_direct; // Keep this! + assign debug_leds[7] = vsync_edge_sync; + +endmodule diff --git a/TRYERROR.md b/TRYERROR.md new file mode 100644 index 0000000..7a999f1 --- /dev/null +++ b/TRYERROR.md @@ -0,0 +1,75 @@ +# Debugging Log: Video DMA & FIFO Integration + +This document records the issues encountered and solutions implemented during the verification of the Video DMA pipeline. + +## 1. FIFO Usage Calculation Error (Critical RTL Bug) +- **Component**: `RTL/simple_dcfifo.v` +- **Symptom**: DMA Master would unpredictably stop reading from memory (stuck in `CHECK_FIFO` state) or overflow the FIFO. +- **Root Cause**: Invalid arithmetic operation mixing different coding schemes. The logic subtracted a **Gray Code** pointer directly from a **Binary** pointer to calculate usage (`wrusedw`). + ```verilog + // BAD CODE + assign wrusedw = wr_ptr_bin - rd_ptr_gray_sync; + ``` + Since Gray codes are not weighted (e.g., 3 is `0010`, 4 is `0110`), subtraction yields meaningless results. +- **Fix**: Implemented a `gray2bin` function to convert the synchronized read pointer back to binary before subtraction. + ```verilog + // FIXED CODE + wire [ADDR_WIDTH:0] rd_ptr_bin_sync = gray2bin(rd_ptr_gray_sync2); + assign wrusedw = (used_diff[ADDR_WIDTH]) ? {ADDR_WIDTH{1'b1}} : used_diff[ADDR_WIDTH-1:0]; // Includes saturation + ``` + +## 2. Implicit Net Declaration & Truncation +- **Component**: `RTL/video_pipeline.v` +- **Symptom**: Integration tests ran but data verification failed completely (received garbage or zeros). +- **Root Cause**: Missing `wire` declarations for multi-bit internal signals. + Verilog defaults undeclared signals to **1-bit wire**. + The 32-bit `fifo_wr_data` and 9-bit `fifo_used` signals were implicitly declared as 1-bit, causing the upper bits to be silently discarded. +- **Fix**: Added explicit wire declarations for all internal interconnects. + ```verilog + wire [31:0] fifo_wr_data; + wire [8:0] fifo_used; + // ... + ``` + +## 3. Simulation 'X' Propagation +- **Component**: `RTL/simple_dcfifo.v` & `cocotb` +- **Symptom**: Python testbench crashed with `ValueError: Cannot convert Logic('X') to bool`. +- **Root Cause**: In hardware, registers power up to unknown states ('X'). While real hardware eventually settles or uses Reset, the simulation (Cocotb) strictly enforces 4-state logic. The FIFO output `q` was 'X' until the first read, crashing the testbench comparators. +- **Fix**: Added an `initial` block to Initialize output registers to `0` for simulation purposes. + ```verilog + initial begin + q = 0; // Prevent X propagation + end + ``` + +## 4. Testbench Bus Contention +- **Component**: `tests/cocotb/tb_dma_master.py` (Avalon Memory Model) +- **Symptom**: Data read from memory was corrupted or lost during burst transfers. +- **Root Cause**: The initial testbench spawned a new independent logic thread (`cocotb.start_soon`) for *every* read request. When the DMA pipeline issued multiple requests quickly, these threads tried to drive the shared `m_readdata` bus signals simultaneously (Bus Contention). +- **Fix**: Refactored the memory model to use a **Queue**. + 1. `Monitor`: Pushes Read Requests into a `Queue`. + 2. `Driver`: A single thread pulls requests from the `Queue` and drives the response bus sequentially. + +## 5. Clock Domain Crossing & Latency +- **Component**: `tests/cocotb/tb_video_integration.py` +- **Symptom**: Pixel data mismatch at the very start of the frame (Pixel 0 was wrong). +- **Root Cause**: The Asynchronous FIFO has a inherent **1-cycle read latency**. When `rdreq` goes high, data appears on `q` one clock later. The testbench was checking `q` on the same cycle as `rdreq`. +- **Fix**: Updated the testbench pixel checker to be "latency tolerant", identifying the start of the frame sequence (`0, 1, 2...`) even if it is delayed by a cycle. + +## 6. HDMI Pipeline Depth Mismatch (1-Pixel Shift) +- **Component**: `RTL/hdmi_sync_gen.v` +- **Symptom**: In simulation, pixels appeared shifted to the right by 1-2 positions (e.g., Pixel 960 appearing as the last pixel of Line 0). +- **Root Cause**: The control signals (`DE`, `HS`, `VS`) were registered through 3 pipeline stages, while the pixel data path (FIFO output + internal registration) only had a 2-cycle latency. This caused control signals to lag behind the data. +- **Fix**: Reduced the pipeline depth for `hdmi_de`, `hdmi_hs`, and `hdmi_vs` to **2 stages** in `hdmi_sync_gen.v`. + +## 7. DMA Multi-Frame Wrap-around Failure +- **Component**: `RTL/video_dma_master.v` +- **Symptom**: Frame 0 verified correctly, but Frame 1 started from the wrong memory address (mid-image). +- **Root Cause**: The DMA master had hardcoded `H_RES=1280` and `V_RES=720` as default parameters. Since these were not overridden in `video_pipeline.v`, the DMA never reached its "end of frame" count (921,600 words) to trigger the address reset on the next V-Sync. +- **Fix**: Updated `video_pipeline.v` to pass the correct parameters (`960x540`, ~518,400 words). + +## 8. Testbench Sampling Fidelity (Cocotb) +- **Component**: `tests/cocotb/tb_video_integration.py` +- **Symptom**: Unstable simulation results; sometimes shifted by 1 pixel, sometimes correct. +- **Root Cause**: Sampling registered signals (`hdmi_d`, `hdmi_de`) exactly on the `RisingEdge` is prone to race conditions in simulation (delta-cycle issues). +- **Fix**: Implemented the `await ReadOnly()` trigger after `RisingEdge` to ensure sampling occurs only after all signals have stabilized for the current delta cycle. diff --git a/cr_ie_info.json b/cr_ie_info.json new file mode 100644 index 0000000..0ea5c1d --- /dev/null +++ b/cr_ie_info.json @@ -0,0 +1,22 @@ +{ + "system" : { + "platform" : "windows64", + "os_name" : "Windows 10", + "os_version" : "10.0" + }, + "error" : { + "executable" : "quartus_map", + "comment" : "not_applicable", + "error_message" : "The required design file DC_FIFO.v is missing", + "source_file" : "/quartus/sld/sci/sci_opencore_spec_reader.cpp", + "line" : "1402", + "stack_trace" : "\t0x7ffd6620f0e1: sld_sci + 0x3f0e1 (?parse_file@SCI_OPENCORE_FILE_PARSER@@QEAA_NPEBD0_N@Z + 0x6e1)\n\t0x7ffd6620cc30: sld_sci + 0x3cc30 (??0SCI_OSR_PPE@@QEAA@PEBD00_N@Z + 0x220)\n\t0x7ffd672cc113: synth_sgn + 0xbc113 (?register_ocp_entity@SGN_EXTRACTOR@@AEAA_NKV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@VFIO_PATH@@PEBD@Z + 0x333)\n\t0x7ffd672cbd90: synth_sgn + 0xbbd90 (?register_ocp_entity@SGN_EXTRACTOR@@AEAAXKPEAVHDB_ENTITY@@@Z + 0x100)\n\t0x7ffd672c9ce6: synth_sgn + 0xb9ce6 (?recurse_into_newly_extracted_netlist@SGN_EXTRACTOR@@AEAAXPEAVHDB_ENTITY@@PEAVHDB_INSTANCE_NAME@@KPEAVSGN_WRAPPER_INFO@@@Z + 0xa6)\n\t0x7ffd672ca6bb: synth_sgn + 0xba6bb (?recursive_extraction@SGN_EXTRACTOR@@AEAAKPEAVHDB_INSTANCE_NAME@@PEAVSGN_WRAPPER_INFO@@PEBD@Z + 0x25b)\n\t0x7ffd672c9faf: synth_sgn + 0xb9faf (?recurse_into_newly_extracted_netlist@SGN_EXTRACTOR@@AEAAXPEAVHDB_ENTITY@@PEAVHDB_INSTANCE_NAME@@KPEAVSGN_WRAPPER_INFO@@@Z + 0x36f)\n\t0x7ffd672ca6bb: synth_sgn + 0xba6bb (?recursive_extraction@SGN_EXTRACTOR@@AEAAKPEAVHDB_INSTANCE_NAME@@PEAVSGN_WRAPPER_INFO@@PEBD@Z + 0x25b)\n\t0x7ffd672c9faf: synth_sgn + 0xb9faf (?recurse_into_newly_extracted_netlist@SGN_EXTRACTOR@@AEAAXPEAVHDB_ENTITY@@PEAVHDB_INSTANCE_NAME@@KPEAVSGN_WRAPPER_INFO@@@Z + 0x36f)\n\t0x7ffd672ca6bb: synth_sgn + 0xba6bb (?recursive_extraction@SGN_EXTRACTOR@@AEAAKPEAVHDB_INSTANCE_NAME@@PEAVSGN_WRAPPER_INFO@@PEBD@Z + 0x25b)\n\t0x7ffd672c3888: synth_sgn + 0xb3888 (?extract@SGN_EXTRACTOR@@QEAAXXZ + 0x1e8)\n\t0x7ffd672228e2: synth_sgn + 0x128e2 (?sgn_elaboration@@YA?AW4SGN_STATE_ENUM@@PEAVCMP_FACADE@@@Z + 0x162)\n\t0x7ff6c1204466: quartus_map + 0x4466 (?qsyn_execute_sgn@@YA?AW4SGN_STATE_ENUM@@PEAVCMP_FACADE@@AEAV?$vector@V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@V?$allocator@V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@@2@@std@@AEBV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@4@PEAVTHR_NAMED_PIPE@@3@Z + 0x1f6)\n\t0x7ff6c1214246: quartus_map + 0x14246 (?execute_core@QSYN_FRAMEWORK@@AEAA_NPEAVTHR_NAMED_PIPE@@0@Z + 0x136)\n\t0x7ff6c1213d2b: quartus_map + 0x13d2b (?execute@QSYN_FRAMEWORK@@UEAA_NXZ + 0x49b)\n\t0x7ffda802150c: comp_qexe + 0x1150c (qexe_do_normal + 0x1ec)\n\t0x7ffda8026622: comp_qexe + 0x16622 (qexe_run + 0x432)\n\t0x7ffda8027371: comp_qexe + 0x17371 (?qexe_standard_main@@YAHPEAVQEXE_FRAMEWORK@@PEAPEBUQEXE_OPTION_DEFINITION@@HPEAPEBD@Z + 0xc1)\n\t0x7ff6c121b42b: quartus_map + 0x1b42b (?qsyn_main@@YAHHPEAPEBD@Z + 0x53b)\n\t0x7ffde70d3258: CCL_MSG + 0x13258 (?msg_main_thread@@YAPEAXPEAX@Z + 0x18)\n\t0x7ffde70d4a5e: CCL_MSG + 0x14a5e (?msg_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x6e)\n\t0x7ffdeb1f6af0: ccl_mem + 0x16af0 (?mem_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x70)\n\t0x7ffde70d2af1: CCL_MSG + 0x12af1 (?msg_exe_main@@YAHHPEAPEBDP6AHH0@Z@Z + 0xa1)\n\t0x7ff6c122a236: quartus_map + 0x2a236 (__tmainCRTStartup + 0x10e)\n\t0x7ffe1b37e8d6: KERNEL32 + 0x2e8d6 (BaseThreadInitThunk + 0x16)\n\t0x7ffe1ca8c40b: ntdll + 0x8c40b (RtlUserThreadStart + 0x2b)\n", + "subsystem" : "SCI" + }, + "quartus" : { + "quartus_bits" : "64", + "version" : "20.1.1", + "build" : "720", + "edition" : "Lite Edition" + } +} \ No newline at end of file diff --git a/doc/RESULT.md b/doc/RESULT.md index 33bc649..db5044a 100644 --- a/doc/RESULT.md +++ b/doc/RESULT.md @@ -1,10 +1,12 @@ -# Video Processing Pipeline Analysis Results +# Video Processing Pipeline - Test Results -This document records the performance benchmarks and hardware initialization status of the DE10-Nano video processing pipeline. - -## 1. DMA# Performance Benchmark Results [โฌ…๏ธ Back to README](../README.md) - (2026-02-12) + +This document records the performance benchmarks and hardware verification results for the DE10-Nano video processing pipeline. + +## 1. DMA Performance Benchmarks + +### Burst Master Performance (2026-02-12) | Test Case | Size | Software (cycles) | Hardware (cycles) | MB/s (HW) | Speedup | | :--- | :--- | :--- | :--- | :--- | :--- | @@ -14,13 +16,51 @@ This document records the performance benchmarks and hardware initialization sta > [!NOTE] > DMA (Burst Master 4) significantly offloads the CPU, providing over 500x speedup for 1MB transfers. -## 2. Hardware Initialization Status +## 2. Video Output Verification + +### 540p (qHD) Implementation (2026-02-14) + +**Resolution:** 960ร—540 @ 60Hz +**Pixel Clock:** 37.8336 MHz +**Bandwidth Required:** 124 MB/s (62% of 50MHz bus capacity) + +#### โœ… Verified Features + +| Feature | Status | Details | +|---------|--------|---------| +| **Static Image Display** | โœ… Pass | Nios II successfully loads and displays images from DDR3 | +| **Video Playback (Linux)** | โœ… Pass | HPS double-buffered streaming via `/dev/mem` | +| **V-Sync Synchronization** | โœ… Pass | Tear-free frame pointer latching confirmed | +| **Gamma Correction** | โœ… Pass | sRGB and Inverse Gamma 2.2 LUTs working correctly | +| **Pattern Generation** | โœ… Pass | All 8 modes (Color, Grid, Character Tile, etc.) | +| **Dual-Clock CDC** | โœ… Pass | CSR (50MHz) and Pixel (37.8MHz) domains stable | + +#### Performance Notes -- **HDMI PLL**: Locked at 74.25 MHz (720p60 target) +- **Initial Playback:** 60fps sustained (Linux page cache active) +- **Sustained Playback:** 10-15fps (SD card bottleneck: ~20 MB/s vs 124 MB/s required) +- **RAM Preload Mode (New):** โœ… **60fps Stable** (Duration limit: ~4.1s) +- **Frame Buffer Size:** 2,073,600 bytes (~2MB per frame) +- **Memory Layout:** Reserved Base @ 0x20000000 (512MB Capacity) + +## 3. Hardware Initialization Status + +### Current Configuration + +- **HDMI PLL**: Locked at 37.8336 MHz (540p60) - **ADV7513 IC**: Configured via I2C successfully -- **Memory Map**: Nios II & DMA isolated at 0x20000000 (512MB offset) +- **Memory Map**: Frame buffers at 0x30000000 (512MB reserved) +- **HPS Bridge**: LWHPS2FPGA connected to HDMI CSR @ 0xFF240000 -## 3. Official Execution Log +### Qsys Connectivity + +``` +hps_0.h2f_lw_axi_master โ†’ mm_bridge_0.s0 โ†’ hdmi_sync_mm.s0 (Base: 0x40000) +``` + +## 4. Execution Logs + +### DMA Benchmark Log ```text --- [TEST 1] OCM to DDR DMA (burst_master_0) --- @@ -37,18 +77,70 @@ Starting HW DMA (1MB)... Done (393942 cycles, ~126.9 MB/s) Speedup: 525 x Verifying HW Output... SUCCESS: DDR to DDR Verified! (Coeff=800) +``` -Waiting for PLL Lock (74.25 MHz)... +### HDMI Initialization Log + +```text +Waiting for PLL Lock (37.83 MHz)... PLL Locked! Initializing ADV7513 HDMI Transmitter... HDMI Controller Configured. Ready for Video! -Generating 720p Color Bar Pattern in DDR3... Done! (Total 921600 pixels written) +Generating 540p Pattern in DDR3... Done! (Total 518400 pixels written) +``` ---- [NEW] RTL Pattern & Gamma Enhancement Verified --- -- **Mode 7 (Character Tile)**: Confirmed Dynamic Rainbow Coloring (Rainbow effect). -- **Gamma Correction**: Verified sRGB and Inverse Gamma LUT loading. -- **Timing Stability**: Confirmed zero timing violations after SDC update. +### Video Playback Log (Linux) + +```text +DE10-Nano Linux Video Player (Double Buffered / RAM Preload) +Video: video_qhd.bin (960x540) +Mapped Frame Buffers: + Buffer A (Virtual): 0xb6f00000 (Physical: 0x30000000) + Buffer B (Virtual): 0xb7100000 (Physical: 0x30200000) +Mapped CSR Base: 0xb6e00000 +Started Playback (Double Buffering)... +......... ``` +## 5. Advanced Features Validation + +### Gamma Correction โœ… + +- **Mode 7 (Character Tile)**: Confirmed dynamic rainbow coloring effect +- **Gamma LUT Loading**: sRGB and Inverse Gamma 2.2 verified +- **Real-time Toggle**: Gamma enable/disable via CSR working + +### Timing Analysis โœ… + +- **Setup Slack**: Positive (no violations) +- **Hold Slack**: Positive (no violations) +- **Clock Domain Crossing**: Properly constrained via SDC +- **V-Sync Latching**: Shadow pointer updates confirmed on rising edge + +## 6. Known Limitations + +- **SD Card Bandwidth**: Sustained playback limited to ~10-15fps + - Required: 124 MB/s + - Available: ~20 MB/s +- **Memory Constraint**: 512MB DDR3 reserved (max ~250 frames for preload) +- **No Audio**: Video-only implementation + +## 7. Next Steps + +### Phase 4: Bandwidth Expansion + +**Target:** Enable 720p@60Hz (222 MB/s requirement) + +**Approach:** +- Expand bus width from 4-byte to 8/16-byte +- Keep clock frequency constant (50 MHz) +- Target bandwidth: 400 MB/s (8-byte @ 50MHz) + +**Benefits:** +- 720p@60Hz with 80% headroom +- Improved performance margin +- Future-proof for higher resolutions + --- -*Created by Nios II Performance Monitoring Unit.* + +*Last Updated: 2026-02-14* diff --git a/doc/TODO.md b/doc/TODO.md index ca3a15e..3f19f84 100644 --- a/doc/TODO.md +++ b/doc/TODO.md @@ -3,12 +3,12 @@ This roadmap outlines the steps to build a high-performance video pipeline, from basic color bars to advanced real-time image processing. -## Phase 1: Foundation (Nios II Pattern & DMA) [x] +## Phase 1: Foundation (Nios II Pattern & DMA) โœ… - [x] **DDR3 Pattern Generation**: Write Nios II code to fill DDR3 (0x2000_0000) with 720p color bar. - [x] **Hardware DMA Master**: Implement and verify `burst_master` for high-speed DDR3 access. - [x] **Performance Benchmarking**: Verify 500x speedup compared to software copy. -## Phase 2: Hardware Extension (RTL Sync Gen & Advanced Control) [x] +## Phase 2: Hardware Extension (RTL Sync Gen & Advanced Control) โœ… - [x] **Custom Sync Gen**: Implement `hdmi_sync_gen.v` with H/V sync and DE. - [x] **RTL Patterns**: Add built-in patterns (Grid, Grayscale, Character Tile) to the Sync Gen. - [x] **Advanced Gamma Correction**: Implement sRGB and Inverse Gamma 2.2 LUTs. @@ -16,23 +16,55 @@ This roadmap outlines the steps to build a high-performance video pipeline, from - [x] **Timing & Addressing Fix**: Resolve SDC timing violations and Avalon-MM address mapping bugs. - [x] **Dynamic Coloring**: Implement coordinate-based rainbow effects for character rendering. -## Phase 3: DMA Video Output (Next Step) [/] -- [ ] **MM2ST Video Pipeline**: Integrate the DMA Master with a Stream-to-Video bridge. -- [ ] **Frame Buffer Control**: Implement Nios II logic to manage double-buffering in DDR3. -- [ ] **Stable Video Output**: Verify jitter-free 720p video stream from DDR3 to HDMI monitor. +## Phase 3: qHD Video Output โœ… +- [x] **Resolution Optimization**: Downgrade from 720p to qHD (960ร—540@60Hz) for bandwidth compliance. +- [x] **Dual-Clock Architecture**: Separate CSR (50MHz) and Pixel (37.8MHz) clock domains with CDC. +- [x] **Static Image Display**: Nios II loads and displays images from DDR3 via DMA. +- [x] **Linux Video Player**: HPS streams video using double-buffered `/dev/mem` access. +- [x] **V-Sync Synchronization**: Frame pointer latching for tear-free updates. +- [x] **Qsys HPS Bridge**: Connect `h2f_lw_axi_master` to HDMI CSR for Linux control. -## Phase 4: Real-time Processing (Line Buffer & Filters) -- [ ] **Line Buffer Design**: Implement dual-port RAM based line buffers for 3x3 windowing. +## Phase 4: Video Playback Optimization & Bandwidth Expansion โณ +- [ ] **Bus Width Expansion**: Increase from 4-byte to 8/16-byte bus (target: 400 MB/s @ 50MHz) + - Goal: Enable 720p@60Hz (222 MB/s) with headroom + - Keep clock frequency constant (50 MHz) + - Modify Avalon-MM interface width in burst_master +- [ ] **RAM Preload Mode**: Restore preload strategy for 60fps on short videos (4-5 sec). +- [ ] **Resolution Scaling**: Add 480p/360p modes for sustained SD card streaming. +- [ ] **Video Compression Support**: Integrate H.264/MJPEG hardware decoder. +- [ ] **Audio Integration**: Add I2S audio playback synchronized with video. +- [ ] **Performance Profiling**: Measure and optimize read latency with `ftrace`. + +## Phase 5: Real-time Processing (Line Buffer & Filters) +- [ ] **Line Buffer Design**: Implement dual-port RAM based line buffers for 3ร—3 windowing. - [ ] **Processing Core**: Implement `video_processing_core.v`. - [ ] **Grayscale/Thresholding**: Basic pixel-wise processing. - [ ] **Sobel Edge Detection**: High-speed spatial filtering using the line buffers. + - [ ] **Gaussian Blur**: Smoothing filter for noise reduction. +- [ ] **Real-time Toggle**: Switch between processed and raw video via control register. -## Phase 5: High-End Quality & Integration +## Phase 6: Advanced Features - [ ] **Spatial Dithering**: Implement Bayer Matrix based dithering to reduce banding. -- [ ] **Linux Integration**: Map the video pipeline as a standard Linux display device (DRM/KMS). -- [ ] **AI Acceleration**: Integrate hardware-based AI recognition core. +- [ ] **Linux DRM/KMS Integration**: Map the video pipeline as a standard Linux display device. +- [ ] **Camera Input**: Add MIPI CSI-2 camera interface for live processing. +- [ ] **AI Acceleration**: Integrate hardware-based AI recognition core (YOLO, etc.). +- [ ] **Multi-stream**: Support multiple video sources with hardware compositing. -## Hardware/Qsys Requirements (Common) [x] -- [x] **Clocking**: 74.25 MHz Pixel Clock PLL + SDC Constraints. +## Hardware/Qsys Requirements (Common) โœ… +- [x] **Clocking**: 37.83 MHz Pixel Clock PLL + SDC Constraints. - [x] **I2C Control**: ADV7513 initialization via Nios II. - [x] **Top-level Wiring**: HDMI_TX pins assignment in `DE10_NANO_SoC_GHRD.v`. +- [x] **HPS Bridge**: Lightweight AXI bridge for Linux CSR access. + +## Known Issues & Limitations +- **SD Card Bottleneck**: Raw video requires 124 MB/s, SD card provides ~20 MB/s + - Impact: Sustained playback limited to ~10-15 fps + - Workaround: Use RAM preload for short clips or lower resolution +- **Memory Constraint**: 512MB DDR3 reserved for video limits preload to ~250 frames +- **No Audio**: Current implementation is video-only + +## Documentation Status +- [x] VIDEO_PLAYBACK.md created with comprehensive implementation details +- [x] README.md updated with qHD achievements +- [ ] Create performance benchmark document with detailed measurements +- [ ] Add troubleshooting guide for common issues diff --git a/doc/VIDEO_PLAYBACK.md b/doc/VIDEO_PLAYBACK.md new file mode 100644 index 0000000..be5b62b --- /dev/null +++ b/doc/VIDEO_PLAYBACK.md @@ -0,0 +1,281 @@ +# ๐ŸŽฌ Video Playback Implementation + +## Overview + +This document describes the implementation of **qHD (960x540@60Hz) video playback** on the DE10-Nano FPGA board, featuring both static image display and dynamic video streaming from Linux. + +## ๐Ÿ“ Resolution: qHD (960x540) + +### Why qHD? + +The original target was 720p (1280x720@60Hz), requiring **222 MB/s** bandwidth: +``` +1280 ร— 720 ร— 4 bytes ร— 60 fps = 222 MB/s +``` + +However, the 50MHz system bus provides only **200 MB/s**: +``` +50 MHz ร— 4 bytes = 200 MB/s +``` + +To maintain stable 60Hz output with margin, we downgraded to **qHD (960ร—540)**: +``` +960 ร— 540 ร— 4 bytes ร— 60 fps = 124 MB/s โœ… (62% of available bandwidth) +``` + +### Timing Parameters + +| Parameter | Value | +|-----------|-------| +| **Pixel Clock** | 37.8336 MHz | +| **H_VISIBLE** | 960 | +| **H_FRONT** | 48 | +| **H_SYNC** | 32 | +| **H_BACK** | 80 | +| **H_TOTAL** | 1120 | +| **V_VISIBLE** | 540 | +| **V_FRONT** | 3 | +| **V_SYNC** | 5 | +| **V_BACK** | 15 | +| **V_TOTAL** | 563 | +| **Frame Rate** | 60.00 Hz | + +## ๐Ÿ–ผ๏ธ Static Image Display + +### Nios II Software + +The Nios II processor can load static images from DDR3 memory and display them on HDMI output. + +**Memory Map:** +- Frame Buffer Address: `0x30000000` (Reserved 512MB region in Linux) +- Frame Size: `960 ร— 540 ร— 4 = 2,073,600 bytes` (~2MB) + +**Software Flow:** +1. Load image data to DDR3 via DMA (`burst_master`) +2. Configure HDMI sync generator registers +3. Set mode to DMA stream (Mode 8) +4. Set frame pointer to `0x30000000` +5. Enable continuous DMA mode + +## ๐ŸŽฅ Linux Video Playback + +### Architecture + +```mermaid +graph LR + A[MP4 Video] -->|video2raw.py| B[Raw RGB Binary] + B -->|SD Card| C[DE10-Nano Linux] + C -->|video_player.c| D[DDR3 Memory
0x30000000] + D -->|DMA Read| E[HDMI Output] + F[HPS CSR
0xFF240000] -.->|Frame Pointer
Update| E +``` + +### Components + +#### 1. Video Conversion (`video2raw.py`) + +Converts standard video files (MP4, AVI) to raw RGB format suitable for the FPGA. + +**Features:** +- Resizes to qHD (960ร—540) +- Converts to BGRA format (32-bit per pixel) +- Frame limiting option (`--frames N`) + +**Usage:** +```bash +python video2raw.py input.mp4 --frames 300 +``` + +**Output:** +- File: `video_qhd.bin` +- Size: ~600MB for 300 frames (5 seconds) + +#### 2. Video Player (`video_player.c`) + +Linux application that streams video frames from SD card to DDR3 using double buffering. + +**Memory Mapping:** +- Frame Buffer A: `0x30000000` (Physical) +- Frame Buffer B: `0x30200000` (Physical, +2MB offset) +- HDMI CSR: `0xFF240000` (Physical, via LWHPS2FPGA Bridge) + +**Double Buffering Flow:** +``` +1. Load Frame N into Back Buffer (A or B) +2. Update HDMI Frame Pointer CSR โ†’ Back Buffer Address +3. Swap Front/Back indices +4. Wait ~16.6ms (60 fps target) +5. Repeat +``` + +**Key Implementation Details:** +- **Circular Read:** Automatically loops video by rewinding file on EOF +- **Adaptive Sleep:** Adjusts sleep time based on actual read duration: + ```c + sleep_time = 16.6ms - (read_time + register_update_time) + ``` +- **Direct Memory Access:** Uses `/dev/mem` with `mmap()` for zero-copy transfers + +**Compilation:** +```bash +gcc -o video_player video_player.c -O3 +``` + +**Execution:** +```bash +sudo ./video_player video_qhd.bin +``` + +## ๐ŸŽฌ Video Playback Implementation (RAM Preload Method) + +### Overview + +To overcome the **SD Card Bandwidth Bottleneck (~20MB/s)**, the video player now uses a **Store-and-Forward** architecture (RAM Preload). +Instead of streaming from the SD card in real-time, the entire video clip is loaded into the **512MB Reserved DDR3 Memory** before playback starts. + +**Advantages:** +- โœ… **Perfect 60fps Playback:** No I/O latency during playback. +- โœ… **Network Streaming Support:** Can pipe video directly from PC via SSH (`cat | ssh`). +- โŒ **Duration Limit:** Max ~4.1 seconds (250 frames) due to 512MB RAM limit. + +--- + +### Usage Guide + +#### 1. Host Streaming (Recommended) ๐Ÿ“ก + +Stream video file from your PC directly to the FPGA memory via SSH. No SD card copying required! + +**Windows (CMD):** +```cmd +type video_qhd.bin | ssh root@192.168.x.x "./video_player -" +``` + +**Linux / macOS:** +```bash +cat video_qhd.bin | ssh root@192.168.x.x "./video_player -" +``` + +*Note: The `-` argument tells the player to read from Standard Input (stdin).* + +#### 2. Local File Playback +If the file is already on the SD card: +```bash +./video_player video_qhd.bin +``` + +--- + +### Technical Implementation + +#### Architecture +1. **Load Phase:** Reads input stream (File or Stdin) and writes sequentially to DDR3 at `0x20000000`. + - Displays a progress bar (e.g., "Loaded: 50MB"). +2. **Play Phase:** Loops through the loaded frames in DDR3, updating the HDMI Frame Pointer CSR every 16.6ms. + +#### Memory Map +- **Reserved RAM Base:** `0x20000000` (Upper 512MB of 1GB System RAM) +- **Frame Size:** 2,073,600 bytes (960x540 RGBA) +- **Capacity:** ~258 Frames (Total 535MB, capped at 512MB safely) + +#### Kernel Configuration +The Linux Kernel must be configured to reserve the upper 512MB: +- **Boot Args:** `mem=512M` +- **Result:** Linux uses `0x00000000-0x1FFFFFFF`, Video Player uses `0x20000000-0x3FFFFFFF`. + +--- + +### Legacy Method (Direct SD Streaming) - *Deprecated* +*Previous attempts to stream directly from SD card failed to maintain 60fps due to 20MB/s read speed vs 124MB/s required bandwidth.* + +## โš ๏ธ Performance Limitations + +### SD Card Bottleneck + +**Required Bandwidth:** 124 MB/s (for 60fps qHD) +**Typical SD Card Read Speed:** 20-40 MB/s + +**Observed Behavior:** +1. **Initial Phase:** Smooth playback (Linux page cache providing buffered data) +2. **Sustained Phase:** Stuttering (~10-15 fps actual) as cache depletes + +**Mitigation Options:** +1. **RAM Preload (Removed):** Load entire video into DDR3 before playback + - Pros: Perfect 60fps, no SD access during playback + - Cons: Limited to ~250 frames (4 seconds) due to 512MB memory limit +2. **Lower Resolution:** Reduce to 480p or lower to fit SD card bandwidth +3. **Accept Lower FPS:** Current implementation for long video support + +## ๐Ÿ”ง Hardware Modifications + +### RTL Changes + +#### 1. Dual-Clock Architecture ([hdmi_sync_gen.v](file:///C:/Workspace/quartus/video_processing/RTL/hdmi_sync_gen.v)) +- `clk` (50MHz): CSR register access +- `clk_pixel` (37.8MHz): HDMI timing generation +- Proper Clock Domain Crossing (CDC) using synchronizer chains + +#### 2. Frame Pointer Latching +```verilog +// Shadow pointer updates on V-Sync edge (CSR domain) +always @(posedge clk) begin + if (vs_sync_sh[1] && !vs_sync_sh[2]) begin + shadow_ptr <= reg_frame_ptr; // Atomic swap + end +end +``` + +This ensures tear-free video by synchronizing frame pointer updates with vertical blanking. + +#### 3. HDMI Sync Polarity +```verilog +hdmi_hs <= ~hs_d1; // Active-LOW +hdmi_vs <= ~vs_d1; // Active-LOW +``` + +### Verification + +Extensive Cocotb testbenches validated: +- โœ… Dual-clock domain synchronization +- โœ… DMA read timing alignment +- โœ… FIFO depth sufficiency (1024 entries) +- โœ… Multi-frame capture correctness +- โœ… V-Sync based frame pointer latching + +## ๐Ÿ“Š Results + +### โœ… Achievements + +| Feature | Status | Details | +|---------|--------|---------| +| **Static Image (Nios II)** | โœ… Working | 960ร—540 RGB images via DMA | +| **Video Playback (Linux)** | โœ… Working | Double-buffered streaming | +| **Frame Rate (Cached)** | โœ… 60fps | Initial smooth playback | +| **Frame Rate (Sustained)** | โš ๏ธ 10-15fps | SD card limited | +| **V-Sync Synchronization** | โœ… Working | No tearing observed | +| **Seamless Loop** | โœ… Working | Circular file reading | + +### ๐Ÿ“ธ Test Results + +- Successfully displayed test patterns (color bars, gradients, character tiles) +- Loaded and displayed static PNG/BMP images +- Streamed 30-second MP4 video (with expected fps drop after cache exhaustion) +- Verified register access from both Nios II and Linux HPS + +## ๐Ÿ“ Lessons Learned + +1. **Bandwidth Budgeting:** Always verify bus bandwidth vs. pixel clock requirements early +2. **Clock Domain Crossing:** Essential for stable dual-clock video pipelines +3. **V-Sync Synchronization:** Critical for tear-free updates when changing frame buffers +4. **SD Card Limits:** Raw video requires massive bandwidth; compression or lower resolution needed for sustained playback +5. **Bridge Configuration:** Platform Designer connections must include all relevant masters (HPS, Nios, DMA) + +## ๐Ÿ”— References + +- [HDMI Timing Calculator](http://tinyvga.com/vga-timing) +- [ADV7513 Programming Guide](https://www.analog.com/media/en/technical-documentation/user-guides/ADV7513_Programming_Guide.pdf) +- [Cyclone V HPS Technical Reference Manual](https://www.intel.com/content/www/us/en/docs/programmable/683126/current/hard-processor-system-technical-reference.html) + +--- + +**[โ† Back to README](../README.md)** diff --git a/linux_software/.gitignore b/linux_software/.gitignore new file mode 100644 index 0000000..2ab0a6d --- /dev/null +++ b/linux_software/.gitignore @@ -0,0 +1,7 @@ +*.bin +*.mp4 +*.raw +*.ts +*.bmp +*.o +video_player diff --git a/linux_software/frame_loader/Makefile b/linux_software/frame_loader/Makefile new file mode 100644 index 0000000..45a7a5a --- /dev/null +++ b/linux_software/frame_loader/Makefile @@ -0,0 +1,17 @@ +TARGET = frame_loader +SRC = frame_loader.c + +CROSS_COMPILE = arm-linux-gnueabihf- +CC = $(CROSS_COMPILE)gcc +CFLAGS = -g -Wall +LDFLAGS = -g -Wall + +.PHONY: all clean + +all: $(TARGET) + +$(TARGET): $(SRC) + $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) + +clean: + rm -f $(TARGET) diff --git a/linux_software/frame_loader/frame_loader.c b/linux_software/frame_loader/frame_loader.c new file mode 100644 index 0000000..a19863a --- /dev/null +++ b/linux_software/frame_loader/frame_loader.c @@ -0,0 +1,71 @@ +#include +#include +#include +#include +#include +#include + +#define HW_REGS_BASE (0x00000000) +#define HW_REGS_SPAN (0x40000000) +#define HW_REGS_MASK (HW_REGS_SPAN - 1) + +#define FRAME_BUFFER_BASE 0x30000000 +#define FRAME_WIDTH 1280 +#define FRAME_HEIGHT 720 +#define FRAME_SIZE (FRAME_WIDTH * FRAME_HEIGHT * 4) + +int main(int argc, char **argv) { + void *virtual_base; + int fd; + uint32_t *frame_ptr; + + if (argc < 2) { + printf("Usage: %s \n", argv[0]); + printf("Example: %s test.raw\n", argv[0]); + return 1; + } + + // Open /dev/mem + if ((fd = open("/dev/mem", (O_RDWR | O_SYNC))) == -1) { + perror("Error: could not open \"/dev/mem\""); + return 1; + } + + // Memory map the physical address + virtual_base = mmap(NULL, HW_REGS_SPAN, (PROT_READ | PROT_WRITE), MAP_SHARED, + fd, HW_REGS_BASE); + if (virtual_base == MAP_FAILED) { + perror("Error: mmap() failed"); + close(fd); + return 1; + } + + // Get pointer to the frame buffer + frame_ptr = (uint32_t *)((uint8_t *)virtual_base + FRAME_BUFFER_BASE); + + // load file + FILE *file = fopen(argv[1], "rb"); + if (!file) { + perror("Error: could not open image file"); + munmap(virtual_base, HW_REGS_SPAN); + close(fd); + return 1; + } + + printf("Loading %s to Physical Address 0x%08X...\n", argv[1], + FRAME_BUFFER_BASE); + size_t read_bytes = fread(frame_ptr, 1, FRAME_SIZE, file); + printf("Successfully loaded %zu bytes.\n", read_bytes); + + fclose(file); + + // Clean up + if (munmap(virtual_base, HW_REGS_SPAN) != 0) { + perror("Error: munmap() failed"); + close(fd); + return 1; + } + + close(fd); + return 0; +} diff --git a/linux_software/image_converter/color.png b/linux_software/image_converter/color.png new file mode 100644 index 0000000000000000000000000000000000000000..1b6ed0b5209fcc6be66189e942265d409b036478 GIT binary patch literal 1858 zcmeAS@N?(olHy`uVBq!ia0y~yU|GVzz%+q_87MOCSWq&MY7FoRab;itil{O${Ac*1 z#_;bykY;26B1Xo4e;I-7|4fYkS(q69GyVI^%zTH1;V;WSR+j&_m404PX1HSc(&~ih ziF^O`?z8FrWl;ai_~-9`mVduh|AUMJ>Sq1V@E2&}e@2%7Ot=64WBC7%`TxKF|G`54 z|KIr!=1h|Q%*MdLR^#d77*cWT?UjSPhYSQ59BeyZ;O`zoca?wK=uZ zZPMZ&XKYmw4nMNT%j)kBn|&{{&W5kAJs+NZ_ndD0+ERPvW5)68%&tva8m7(AIa4Gd zh(V2YhDd`a;|vnmQ&~o?8l_qqZSeGD02hWR32>wrHUHnRb4y99Z(5sh4p=ENc)I$z JtaD0e0s!x5_NV{= literal 0 HcmV?d00001 diff --git a/linux_software/image_converter/img2raw.py b/linux_software/image_converter/img2raw.py new file mode 100644 index 0000000..5a1c23b --- /dev/null +++ b/linux_software/image_converter/img2raw.py @@ -0,0 +1,39 @@ +import sys +import os +from PIL import Image + +def convert_image_to_raw(input_path, output_path): + # Target Resolution 540p + WIDTH = 960 + HEIGHT = 540 + + try: + # Open and Resize Image + img = Image.open(input_path) + img = img.resize((WIDTH, HEIGHT), Image.Resampling.LANCZOS) + + # Ensure RGB format + img = img.convert('RGB') + + print(f"Converting {input_path} ({img.size}) to {output_path}...") + + with open(output_path, 'wb') as f: + for y in range(HEIGHT): + for x in range(WIDTH): + r, g, b = img.getpixel((x, y)) + # Format: 32-bit XRGB (0x00RRGGBB) + # Lower 24 bits are used in our hardware (hdmi_sync_gen.v) + pixel_data = bytearray([b, g, r, 0x00]) # Little Endian for ARM/Nios + f.write(pixel_data) + + print(f"Successfully created {output_path} ({os.path.getsize(output_path)} bytes)") + + except Exception as e: + print(f"Error: {e}") + +if __name__ == "__main__": + if len(sys.argv) < 3: + print("Usage: python img2raw.py ") + sys.exit(1) + + convert_image_to_raw(sys.argv[1], sys.argv[2]) diff --git a/nios_software/nios_ddr3_test_bsp/settings.bsp b/nios_software/nios_ddr3_test_bsp/settings.bsp index 04c5bd6..a235454 100644 --- a/nios_software/nios_ddr3_test_bsp/settings.bsp +++ b/nios_software/nios_ddr3_test_bsp/settings.bsp @@ -2,8 +2,8 @@ hal default - Feb 12, 2026 2:08:12 PM - 1770923292090 + Feb 13, 2026 11:20:55 PM + 1771042855764 C:\Workspace\quartus\video_processing\nios_software\nios_ddr3_test_bsp settings.bsp ..\..\soc_system.sopcinfo diff --git a/nios_software/video_app2/burst_master_test.c b/nios_software/video_app2/burst_master_test.c index 94ee7a1..d25d527 100644 --- a/nios_software/video_app2/burst_master_test.c +++ b/nios_software/video_app2/burst_master_test.c @@ -4,7 +4,7 @@ static unsigned int ocm_src_buffer[OCM_TEST_WORDS] __attribute__((aligned(32))); -void run_ocm_to_ddr_test(unsigned int csr_base) { +void run_ocm_to_ddr_test(unsigned int csr_base, unsigned int ddr_base) { printf("\n--- [TEST 1] OCM to DDR DMA (burst_master_0) ---\n"); unsigned int *src_ptr = ocm_src_buffer; @@ -38,7 +38,7 @@ void run_ocm_to_ddr_test(unsigned int csr_base) { printf("Starting HW DMA (4KB x 100)... "); unsigned long long hw_t_start = get_total_cycles(); - unsigned int ddr_phys_base = 0x20000000; + unsigned int ddr_phys_base = 0x30000000; for (int j = 0; j < 100; j++) { IOWR_32DIRECT(csr_base, REG_SRC_ADDR, src_phys); IOWR_32DIRECT(csr_base, REG_DST_ADDR, ddr_phys_base); @@ -76,7 +76,7 @@ void run_ocm_to_ddr_test(unsigned int csr_base) { printf("FAILURE: %d errors in OCM test.\n", errors); } -void run_ddr_to_ddr_test(unsigned int csr_base) { +void run_ddr_to_ddr_test(unsigned int csr_base, unsigned int ddr_base) { printf("\n--- [TEST 2] DDR to DDR DMA (Burst Master 4) ---\n"); printf("Transfer Size: 1 MB\n"); @@ -120,7 +120,7 @@ void run_ddr_to_ddr_test(unsigned int csr_base) { printf("Starting HW DMA (1MB)... "); unsigned long long hw_t_start = get_total_cycles(); - unsigned int ddr_phys_base = 0x20000000; + unsigned int ddr_phys_base = 0x30000000; IOWR_32DIRECT(csr_base, REG_SRC_ADDR, ddr_phys_base + src_offset); IOWR_32DIRECT(csr_base, REG_DST_ADDR, ddr_phys_base + dst_hw_offset); IOWR_32DIRECT(csr_base, REG_LEN, DDR_TEST_WORDS * 4); diff --git a/nios_software/video_app2/burst_master_test.h b/nios_software/video_app2/burst_master_test.h index fcbc5e9..38da9fe 100644 --- a/nios_software/video_app2/burst_master_test.h +++ b/nios_software/video_app2/burst_master_test.h @@ -14,7 +14,7 @@ #define REG_WR_BURST (6 * 4) #define REG_COEFF (7 * 4) -void run_ocm_to_ddr_test(unsigned int csr_base); -void run_ddr_to_ddr_test(unsigned int csr_base); +void run_ocm_to_ddr_test(unsigned int csr_base, unsigned int ddr_base); +void run_ddr_to_ddr_test(unsigned int csr_base, unsigned int ddr_base); #endif /* BURST_MASTER_TEST_H_ */ diff --git a/nios_software/video_app2/hdmi_control.c b/nios_software/video_app2/hdmi_control.c index 92adf74..07559ee 100644 --- a/nios_software/video_app2/hdmi_control.c +++ b/nios_software/video_app2/hdmi_control.c @@ -2,12 +2,16 @@ #include "common.h" #include #include +#include void generate_color_bar_pattern() { - printf("\nGenerating 720p Color Bar Pattern in DDR3... "); + printf("\nGenerating 540p Color Bar Pattern in DDR3... "); + // Window Base is now mapped to 0x30000000 in main.c unsigned int *fb = (unsigned int *)DDR3_WINDOW_BASE; - const int width = 1280; - const int height = 720; + printf("[DEBUG] Frame Buffer Addr: 0x%08X (Physical: 0x30000000)\n", + (unsigned int)fb); + const int width = 960; + const int height = 540; const int bar_width = width / 8; const unsigned int colors[8] = {0xFFFFFF, 0xFFFF00, 0x00FFFF, 0x00FF00, @@ -24,6 +28,13 @@ void generate_color_bar_pattern() { alt_dcache_flush_all(); printf("Done! (Total %d pixels written)\n", width * height); + + // [DEBUG] Verify Write Back + volatile unsigned int *check_fb = (volatile unsigned int *)fb; + printf("[DEBUG] Verify @ 0x%08X: Wrote 0x%08X, Read 0x%08X\n", + (unsigned int)fb, 0xFFFFFF, check_fb[0]); + printf("[DEBUG] Verify @ 0x%08X: Wrote 0xFFFF00, Read 0x%08X\n", + (unsigned int)&fb[width / 8], check_fb[width / 8]); } void run_gamma_submenu() { @@ -89,15 +100,19 @@ void change_rtl_pattern() { void load_gamma_table(float gamma_val) { printf("Calculating and Loading Gamma Table (index^1/%.1f)... \n", gamma_val); - float inv_gamma = 1.0f / gamma_val; + if (gamma_val <= 0.1f) + gamma_val = 2.2f; // Safety check + double inv_gamma = 1.0 / (double)gamma_val; for (int i = 0; i < 256; i++) { - float normalized = (float)i / 255.0f; - float corrected = powf(normalized, inv_gamma); - unsigned char val = (unsigned char)(corrected * 255.0f + 0.5f); + double normalized = (double)i / 255.0; + double corrected = pow(normalized, inv_gamma); + unsigned char val = (unsigned char)(corrected * 255.0 + 0.5); IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_LUT_ADDR, i); + usleep(10); // Short delay for hardware stability IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_LUT_DATA, val); + usleep(10); // Ensure write is complete // Print values (16 per line) printf("%3d ", val); @@ -108,28 +123,36 @@ void load_gamma_table(float gamma_val) { } void set_gamma_enable(int enable) { - IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_GAMMA_CTRL, - enable ? 1 : 0); + unsigned int ctrl = + IORD_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL); + if (enable) + ctrl |= AS_GAMMA_EN_MSK; + else + ctrl &= ~AS_GAMMA_EN_MSK; + + IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL, ctrl); printf("Gamma Correction %s\n", enable ? "Enabled" : "Disabled"); } void load_srgb_gamma_table() { printf("Calculating and Loading sRGB Gamma Table...\n"); for (int i = 0; i < 256; i++) { - float normalized = (float)i / 255.0f; - float corrected; + double normalized = (double)i / 255.0; + double corrected; // sRGB Forward Transformation (Linear to sRGB space) - if (normalized <= 0.0031308f) { - corrected = 12.92f * normalized; + if (normalized <= 0.0031308) { + corrected = 12.92 * normalized; } else { - corrected = 1.055f * powf(normalized, 1.0f / 2.4f) - 0.055f; + corrected = 1.055 * pow(normalized, 1.0 / 2.4) - 0.055; } - unsigned char val = (unsigned char)(corrected * 255.0f + 0.5f); + unsigned char val = (unsigned char)(corrected * 255.0 + 0.5); IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_LUT_ADDR, i); + usleep(10); IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_LUT_DATA, val); + usleep(10); printf("%3d ", val); if ((i + 1) % 16 == 0) @@ -142,12 +165,14 @@ void load_inverse_gamma_table() { printf("Calculating and Loading Inverse Gamma Table (x^2.2) for Linear " "Panels...\n"); for (int i = 0; i < 256; i++) { - float normalized = (float)i / 255.0f; - float corrected = powf(normalized, 2.2f); - unsigned char val = (unsigned char)(corrected * 255.0f + 0.5f); + double normalized = (double)i / 255.0; + double corrected = pow(normalized, 2.2); + unsigned char val = (unsigned char)(corrected * 255.0 + 0.5); IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_LUT_ADDR, i); + usleep(10); IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_LUT_DATA, val); + usleep(10); } printf("Inverse Gamma Loaded.\n"); } @@ -180,3 +205,90 @@ void load_char_bitmap() { } printf("Done.\n"); } + +void dma_start_single() { + unsigned int ctrl = + IORD_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL); + // Pulse Start Bit (Bit 2) + IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL, + ctrl | AS_DMA_START_MSK); + printf("DMA Single Frame Transfer Started.\n"); +} + +void dma_set_continuous(int enable) { + unsigned int ctrl = + IORD_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL); + if (enable) { + IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL, + ctrl | AS_DMA_CONT_MSK); + printf("DMA Continuous Mode: ENABLED\n"); + } else { + IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL, + ctrl & ~AS_DMA_CONT_MSK); + printf("DMA Continuous Mode: DISABLED\n"); + } +} + +void print_dma_status() { + unsigned int ctrl = + IORD_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL); + printf("\n--- DMA Status ---\n"); + printf(" Busy: %s\n", (ctrl & AS_DMA_BUSY_MSK) ? "YES" : "NO"); + printf(" Done: %s\n", + (ctrl & AS_DMA_DONE_MSK) ? "YES (Read-to-Clear)" : "NO"); + printf(" Cont: %s\n", (ctrl & AS_DMA_CONT_MSK) ? "ON" : "OFF"); +} + +void run_dma_debug_submenu() { + static int dma_mode_active = 0; // 0: Pattern, 1: DMA + static int cont_active = 0; + + while (1) { + unsigned int ctrl = + IORD_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_DMA_CTRL); + unsigned int mode = + IORD_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_PATTERN_MODE); + dma_mode_active = (mode == 8); + cont_active = (ctrl & AS_DMA_CONT_MSK) ? 1 : 0; + + printf("\n========= DMA DEBUG MENU =========\n"); + printf(" [1] Toggle Source : [%s]\n", + dma_mode_active ? "DMA (DDR3)" : "Test Pattern"); + printf(" [2] Toggle Cont Mode : [%s]\n", + cont_active ? "ENABLED" : "DISABLED"); + printf(" [3] Trigger Single : [START PULSE]\n"); + printf(" [4] Refresh Status : [Busy:%s, Done:%s]\n", + (ctrl & AS_DMA_BUSY_MSK) ? "Y" : "N", + (ctrl & AS_DMA_DONE_MSK) ? "Y" : "N"); + printf(" [b] Back to Main Menu\n"); + printf("----------------------------------\n"); + printf("Select option: "); + + char c = get_char_polled(); + printf("%c\n", c); + + if (c == 'b') + break; + switch (c) { + case '1': + dma_mode_active = !dma_mode_active; + IOWR_32DIRECT(HDMI_SYNC_GEN_BASE | CACHE_BYPASS_MASK, REG_PATTERN_MODE, + dma_mode_active ? 8 : 0); + printf("Source switched to %s\n", dma_mode_active ? "DMA" : "Pattern 0"); + break; + case '2': + cont_active = !cont_active; + dma_set_continuous(cont_active); + break; + case '3': + dma_start_single(); + break; + case '4': + print_dma_status(); + break; + default: + printf("Invalid choice!\n"); + break; + } + } +} diff --git a/nios_software/video_app2/hdmi_control.h b/nios_software/video_app2/hdmi_control.h index e1e018f..f1b0c0e 100644 --- a/nios_software/video_app2/hdmi_control.h +++ b/nios_software/video_app2/hdmi_control.h @@ -3,11 +3,19 @@ #define HDMI_SYNC_GEN_BASE 0x20020 #define REG_PATTERN_MODE (0 * 4) -#define REG_GAMMA_CTRL (1 * 4) +#define REG_DMA_CTRL (1 * 4) // [31]Busy, [30]Done, [2]Start, [1]Cont, [0]Gamma #define REG_LUT_ADDR (2 * 4) #define REG_LUT_DATA (3 * 4) #define REG_BITMAP_ADDR (4 * 4) #define REG_BITMAP_DATA (5 * 4) +#define REG_FRAME_PTR (6 * 4) + +// DMA Control Bit Masks +#define AS_DMA_BUSY_MSK (1 << 31) +#define AS_DMA_DONE_MSK (1 << 30) +#define AS_DMA_START_MSK (1 << 2) +#define AS_DMA_CONT_MSK (1 << 1) +#define AS_GAMMA_EN_MSK (1 << 0) void generate_color_bar_pattern(); void change_rtl_pattern(); @@ -18,4 +26,10 @@ void load_char_bitmap(); void load_srgb_gamma_table(); void load_inverse_gamma_table(); +// New DMA Control Functions +void dma_start_single(); +void dma_set_continuous(int enable); +void print_dma_status(); +void run_dma_debug_submenu(); + #endif /* HDMI_CONTROL_H_ */ diff --git a/nios_software/video_app2/main.c b/nios_software/video_app2/main.c index 2f18101..f7fbb8c 100644 --- a/nios_software/video_app2/main.c +++ b/nios_software/video_app2/main.c @@ -13,6 +13,7 @@ void print_menu() { printf(" [4] Generate 720p Color Bar Pattern in DDR3\n"); printf(" [5] Change RTL Test Pattern (Red, Green, Blue, etc.)\n"); printf(" [6] Gamma Correction Settings (Table, Toggle, Standard)\n"); + printf(" [8] DMA & Video Source Debug Submenu\n"); printf(" [C] Load Custom Character Bitmap\n"); printf(" [r] Reset RTL Pattern Generator\n"); printf(" [q] Quit\n"); @@ -22,7 +23,6 @@ void print_menu() { void run_interactive_menu() { char choice; - static int gamma_en = 0; while (1) { print_menu(); choice = 0; @@ -33,11 +33,28 @@ void run_interactive_menu() { switch (choice) { case '1': - run_ocm_to_ddr_test(BURST_MASTER_0_BASE | CACHE_BYPASS_MASK); + // Switch Window to 0x20000000 for Benchmark + IOWR_32DIRECT(ADDRESS_SPAN_EXTENDER_0_CNTL_BASE, 0, 0x20000000); + printf("[Switch] Window mapped to 0x20000000 for Benchmark\n"); + + run_ocm_to_ddr_test(BURST_MASTER_0_BASE | CACHE_BYPASS_MASK, 0x20000000); + + // Restore Window to 0x30000000 for Video + IOWR_32DIRECT(ADDRESS_SPAN_EXTENDER_0_CNTL_BASE, 0, 0x30000000); + printf("[Restore] Window mapped to 0x30000000 for Video\n"); break; case '2': #ifdef BURST_MASTER_4_0_BASE - run_ddr_to_ddr_test(BURST_MASTER_4_0_BASE | CACHE_BYPASS_MASK); + // Switch Window to 0x20000000 for Benchmark + IOWR_32DIRECT(ADDRESS_SPAN_EXTENDER_0_CNTL_BASE, 0, 0x20000000); + printf("[Switch] Window mapped to 0x20000000 for Benchmark\n"); + + run_ddr_to_ddr_test(BURST_MASTER_4_0_BASE | CACHE_BYPASS_MASK, + 0x20000000); + + // Restore Window to 0x30000000 for Video + IOWR_32DIRECT(ADDRESS_SPAN_EXTENDER_0_CNTL_BASE, 0, 0x30000000); + printf("[Restore] Window mapped to 0x30000000 for Video\n"); #else printf("Error: BURST_MASTER_4_0 not found in system.h\n"); #endif @@ -51,6 +68,9 @@ void run_interactive_menu() { case '5': change_rtl_pattern(); break; + case '8': + run_dma_debug_submenu(); + break; case '6': run_gamma_submenu(); break; @@ -94,13 +114,27 @@ int main() { } #ifdef ADDRESS_SPAN_EXTENDER_0_CNTL_BASE - unsigned int ddr_phys_base = 0x20000000; + // HW default DMA address is 0x30000000. + // Window Size is 128MB. + // So we map the window start to 0x30000000 directly. + unsigned int ddr_phys_base = 0x30000000; printf("Initializing Span Extender to 0x%08X... ", ddr_phys_base); IOWR_32DIRECT(ADDRESS_SPAN_EXTENDER_0_CNTL_BASE, 0, ddr_phys_base); IOWR_32DIRECT(ADDRESS_SPAN_EXTENDER_0_CNTL_BASE, 4, 0); printf("Done.\n"); #endif +#ifdef PLL_LOCKED_BASE + printf("Checking PLL Lock Status... "); + unsigned int pll_locked = IORD_32DIRECT(PLL_LOCKED_BASE, 0); + if (pll_locked & 1) { + printf("LOCKED (0x%x)\n", pll_locked); + } else { + printf("FAILED (0x%x)\n", pll_locked); + printf("WARNING: HDMI Clock might be dead!\n"); + } +#endif + run_interactive_menu(); return 0; } diff --git a/nios_software/video_app2/video_app2.map b/nios_software/video_app2/video_app2.map index 21077e7..0e72813 100644 --- a/nios_software/video_app2/video_app2.map +++ b/nios_software/video_app2/video_app2.map @@ -1,53 +1,55 @@ Archive member included to satisfy reference by file (symbol) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) - obj/default/hdmi_control.o (powf) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-ef_pow.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) (__ieee754_powf) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-ef_sqrt.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-ef_pow.o) (__ieee754_sqrtf) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) + obj/default/hdmi_control.o (pow) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-e_pow.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) (__ieee754_pow) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-e_sqrt.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-e_pow.o) (__ieee754_sqrt) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-s_lib_ver.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) (__fdlib_version) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-sf_rint.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) (rintf) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-sf_scalbn.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-ef_pow.o) (scalbnf) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) (__fdlib_version) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-s_rint.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) (rint) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-s_scalbn.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-e_pow.o) (scalbn) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_muldi3.o) obj/default/burst_master_test.o (__muldi3) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_fixunssfsi.o) - obj/default/hdmi_control.o (__fixunssfsi) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_fixunsdfsi.o) + obj/default/hdmi_control.o (__fixunsdfsi) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_udivdi3.o) obj/default/burst_master_test.o (__udivdi3) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(lib2-divmod.o) obj/default/hdmi_control.o (__divsi3) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(addsf3.o) - obj/default/hdmi_control.o (__addsf3) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(divsf3.o) - obj/default/hdmi_control.o (__divsf3) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(eqsf2.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) (__eqsf2) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(gesf2.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-ef_pow.o) (__gesf2) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(lesf2.o) obj/default/hdmi_control.o (__lesf2) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(mulsf3.o) - obj/default/hdmi_control.o (__mulsf3) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(subsf3.o) - obj/default/hdmi_control.o (__subsf3) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(unordsf2.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) (__unordsf2) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(fixsfsi.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_fixunssfsi.o) (__fixsfsi) -d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(floatsisf.o) - obj/default/hdmi_control.o (__floatsisf) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(adddf3.o) + obj/default/hdmi_control.o (__adddf3) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(divdf3.o) + obj/default/hdmi_control.o (__divdf3) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(eqdf2.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) (__eqdf2) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(gedf2.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-e_pow.o) (__gedf2) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(ledf2.o) + obj/default/hdmi_control.o (__ledf2) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(muldf3.o) + obj/default/hdmi_control.o (__muldf3) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(subdf3.o) + obj/default/hdmi_control.o (__subdf3) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(unorddf2.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) (__unorddf2) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(fixdfsi.o) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_fixunsdfsi.o) (__fixdfsi) +d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(floatsidf.o) + obj/default/hdmi_control.o (__floatsidf) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(extendsfdf2.o) obj/default/hdmi_control.o (__extendsfdf2) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_clz.o) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_udivdi3.o) (__clz_tab) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_clzsi2.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(addsf3.o) (__clzsi2) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(adddf3.o) (__clzsi2) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-errno.o) - d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) (__errno) + d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) (__errno) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-impure.o) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-errno.o) (_impure_ptr) d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-memcpy.o) @@ -248,7 +250,7 @@ LOAD d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nio 0x0000000000000238 PROVIDE (__ram_exceptions_end = ABSOLUTE (.)) 0x0000000000000020 PROVIDE (__flash_exceptions_start = LOADADDR (.exceptions)) -.text 0x0000000000000238 0x89b0 +.text 0x0000000000000238 0xaa94 [!provide] PROVIDE (stext = ABSOLUTE (.)) *(.interp) *(.hash) @@ -295,273 +297,280 @@ LOAD d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nio *(.text .stub .text.* .gnu.linkonce.t.*) .text 0x0000000000000238 0x4c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp//obj/HAL/src/crt0.o 0x0000000000000238 _start - .text 0x0000000000000284 0x908 obj/default/burst_master_test.o + .text 0x0000000000000284 0x910 obj/default/burst_master_test.o 0x0000000000000284 run_ocm_to_ddr_test - 0x000000000000069c run_ddr_to_ddr_test - .text 0x0000000000000b8c 0x188 obj/default/common.o - 0x0000000000000b8c get_char_polled - 0x0000000000000bc4 get_char_async - 0x0000000000000c04 get_total_cycles - .text 0x0000000000000d14 0x214 obj/default/hdmi_config.o - 0x0000000000000d14 hdmi_i2c_write - 0x0000000000000d8c hdmi_init - .text 0x0000000000000f28 0x850 obj/default/hdmi_control.o - 0x0000000000000f28 generate_color_bar_pattern - 0x0000000000001088 run_gamma_submenu - 0x00000000000011c0 change_rtl_pattern - 0x00000000000012e0 load_gamma_table - 0x0000000000001418 set_gamma_enable - 0x0000000000001484 load_srgb_gamma_table - 0x00000000000015f0 load_inverse_gamma_table - 0x00000000000016d0 load_char_bitmap - .text 0x0000000000001778 0x3e8 obj/default/main.o - 0x0000000000001778 print_menu - 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0x0000000000005be0 alt_avalon_i2c_open - 0x0000000000005c20 alt_avalon_i2c_enable - 0x0000000000005cb8 alt_avalon_i2c_disable - 0x0000000000005d04 alt_avalon_i2c_master_config_get - 0x0000000000005db4 alt_avalon_i2c_master_config_set - 0x0000000000005e80 alt_avalon_i2c_master_config_speed_get - 0x0000000000005f14 alt_avalon_i2c_master_config_speed_set - 0x0000000000006010 alt_avalon_i2c_is_busy - 0x0000000000006054 alt_avalon_i2c_rx_read_available - 0x0000000000006100 alt_avalon_i2c_rx_read - 0x00000000000061a8 alt_avalon_i2c_cmd_write - 0x0000000000006294 alt_avalon_i2c_send_address - 0x0000000000006384 alt_avalon_i2c_master_target_get - 0x00000000000063bc alt_avalon_i2c_master_target_set - 0x00000000000063f0 alt_avalon_i2c_check_nack - 0x000000000000643c alt_avalon_i2c_check_arblost - 0x0000000000006488 alt_avalon_i2c_interrupt_transaction_status - 0x00000000000065bc alt_avalon_i2c_master_tx - 0x00000000000066a4 alt_avalon_i2c_master_rx - 0x00000000000067e0 alt_avalon_i2c_master_tx_rx - 0x00000000000069a8 alt_avalon_i2c_master_transmit - 0x0000000000006b64 alt_avalon_i2c_master_transmit_using_interrupts - 0x0000000000006d6c alt_avalon_i2c_master_receive - 0x0000000000006f78 alt_avalon_i2c_master_receive_using_interrupts - 0x0000000000007164 alt_avalon_i2c_int_status_get - 0x00000000000071bc alt_avalon_i2c_int_raw_status_get - 0x0000000000007200 alt_avalon_i2c_int_clear - 0x000000000000723c alt_avalon_i2c_int_disable - 0x00000000000072a8 alt_avalon_i2c_int_enable - 0x0000000000007310 alt_avalon_i2c_enabled_ints_get - 0x0000000000007354 alt_avalon_i2c_rx_fifo_threshold_get - 0x00000000000073a0 alt_avalon_i2c_rx_fifo_threshold_set - 0x0000000000007404 alt_avalon_i2c_tfr_cmd_fifo_threshold_get - 0x0000000000007450 alt_avalon_i2c_tfr_cmd_fifo_threshold_set - .text 0x00000000000074b4 0xc0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) - 0x00000000000074b4 altera_avalon_jtag_uart_read_fd - 0x0000000000007514 altera_avalon_jtag_uart_write_fd - .text 0x0000000000007574 0xec c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) - 0x0000000000007574 altera_avalon_jtag_uart_read - .text 0x0000000000007660 0x94 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) - 0x0000000000007660 altera_avalon_jtag_uart_write - .text 0x00000000000076f4 0x108 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o) - 0x0000000000007770 alt_avalon_timer_sc_init - .text 0x00000000000077fc 0x158 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_busy_sleep.o) - 0x00000000000077fc alt_busy_sleep - .text 0x0000000000007954 0x118 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_close.o) - 0x000000000000799c close - .text 0x0000000000007a6c 0x2c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev.o) - .text 0x0000000000007a98 0xf0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) - 0x0000000000007ae0 alt_dev_llist_insert - .text 0x0000000000007b88 0x64 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_do_ctors.o) - 0x0000000000007b88 _do_ctors - .text 0x0000000000007bec 0x64 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_do_dtors.o) - 0x0000000000007bec _do_dtors - .text 0x0000000000007c50 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_errno.o) - .text 0x0000000000007c50 0x90 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_find_dev.o) - 0x0000000000007c50 alt_find_dev - .text 0x0000000000007ce0 0x34 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_icache_flush_all.o) - 0x0000000000007ce0 alt_icache_flush_all - .text 0x0000000000007d14 0x1c8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic.o) - 0x0000000000007d14 alt_ic_isr_register - 0x0000000000007d64 alt_ic_irq_enable - 0x0000000000007df8 alt_ic_irq_disable - 0x0000000000007e90 alt_ic_irq_enabled - .text 0x0000000000007edc 0xe8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic_isr_register.o) - 0x0000000000007edc alt_iic_isr_register - .text 0x0000000000007fc4 0x12c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_io_redirect.o) - 0x0000000000008074 alt_io_redirect - .text 0x00000000000080f0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_entry.o) - .text 0x00000000000080f0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_handler.o) - .text 0x00000000000080f0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_vars.o) - .text 0x00000000000080f0 0x25c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_open.o) - 0x00000000000081f4 open - .text 0x000000000000834c 0x22c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_printf.o) - 0x000000000000834c alt_printf - .text 0x0000000000008578 0x30 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_putchar.o) - 0x0000000000008578 alt_putchar - .text 0x00000000000085a8 0x58 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_release_fd.o) - 0x00000000000085a8 alt_release_fd - .text 0x0000000000008600 0x24 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o) - 0x0000000000008600 altera_nios2_gen2_irq_init - .text 0x0000000000008624 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exception_entry.o) - .text 0x0000000000008624 0x110 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_find_file.o) - 0x0000000000008624 alt_find_file - .text 0x0000000000008734 0xa8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_get_fd.o) - 0x0000000000008734 alt_get_fd - .text 0x00000000000087dc 0x90 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_icache_flush.o) - 0x00000000000087dc alt_icache_flush - .text 0x000000000000886c 0x98 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) - 0x000000000000886c alt_exception_cause_generated_bad_addr - .text 0x0000000000008904 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-atexit.o) - .text.atexit 0x0000000000008904 0x14 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-atexit.o) - 0x0000000000008904 atexit - .text 0x0000000000008918 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-exit.o) - .text.exit 0x0000000000008918 0x20 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-exit.o) - 0x0000000000008918 exit - .text 0x0000000000008938 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-memcmp.o) - .text.memcmp 0x0000000000008938 0x30 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-memcmp.o) - 0x0000000000008938 memcmp - .text 0x0000000000008968 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__atexit.o) + 0x0000000000007398 0x50 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-writer.o) + 0x0000000000007398 _write_r + .text 0x00000000000073e8 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-int_errno.o) + .text 0x00000000000073e8 0x4c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + 0x00000000000073e8 alt_dcache_flush_all + .text 0x0000000000007434 0xec c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_load.o) + 0x000000000000749c alt_load + .text 0x0000000000007520 0x7c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_main.o) + 0x0000000000007520 alt_main + .text 0x000000000000759c 0x1ac c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_tick.o) + 0x000000000000759c alt_alarm_stop + 0x0000000000007640 alt_tick + .text 0x0000000000007748 0x30 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_usleep.o) + 0x0000000000007748 usleep + .text 0x0000000000007778 0x140 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_write.o) + 0x00000000000077c0 write + .text 0x00000000000078b8 0xcc c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_sys_init.o) + 0x00000000000078f0 alt_irq_init + 0x000000000000792c alt_sys_init + .text 0x0000000000007984 0x1c14 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_i2c.o) + 0x0000000000007a94 alt_avalon_i2c_register_optional_irq_handler + 0x0000000000007b84 alt_avalon_i2c_register_callback + 0x0000000000007bd8 alt_avalon_i2c_init + 0x0000000000007cc4 alt_avalon_i2c_open + 0x0000000000007d04 alt_avalon_i2c_enable + 0x0000000000007d9c alt_avalon_i2c_disable + 0x0000000000007de8 alt_avalon_i2c_master_config_get + 0x0000000000007e98 alt_avalon_i2c_master_config_set + 0x0000000000007f64 alt_avalon_i2c_master_config_speed_get + 0x0000000000007ff8 alt_avalon_i2c_master_config_speed_set + 0x00000000000080f4 alt_avalon_i2c_is_busy + 0x0000000000008138 alt_avalon_i2c_rx_read_available + 0x00000000000081e4 alt_avalon_i2c_rx_read + 0x000000000000828c alt_avalon_i2c_cmd_write + 0x0000000000008378 alt_avalon_i2c_send_address + 0x0000000000008468 alt_avalon_i2c_master_target_get + 0x00000000000084a0 alt_avalon_i2c_master_target_set + 0x00000000000084d4 alt_avalon_i2c_check_nack + 0x0000000000008520 alt_avalon_i2c_check_arblost + 0x000000000000856c alt_avalon_i2c_interrupt_transaction_status + 0x00000000000086a0 alt_avalon_i2c_master_tx + 0x0000000000008788 alt_avalon_i2c_master_rx + 0x00000000000088c4 alt_avalon_i2c_master_tx_rx + 0x0000000000008a8c alt_avalon_i2c_master_transmit + 0x0000000000008c48 alt_avalon_i2c_master_transmit_using_interrupts + 0x0000000000008e50 alt_avalon_i2c_master_receive + 0x000000000000905c alt_avalon_i2c_master_receive_using_interrupts + 0x0000000000009248 alt_avalon_i2c_int_status_get + 0x00000000000092a0 alt_avalon_i2c_int_raw_status_get + 0x00000000000092e4 alt_avalon_i2c_int_clear + 0x0000000000009320 alt_avalon_i2c_int_disable + 0x000000000000938c alt_avalon_i2c_int_enable + 0x00000000000093f4 alt_avalon_i2c_enabled_ints_get + 0x0000000000009438 alt_avalon_i2c_rx_fifo_threshold_get + 0x0000000000009484 alt_avalon_i2c_rx_fifo_threshold_set + 0x00000000000094e8 alt_avalon_i2c_tfr_cmd_fifo_threshold_get + 0x0000000000009534 alt_avalon_i2c_tfr_cmd_fifo_threshold_set + .text 0x0000000000009598 0xc0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + 0x0000000000009598 altera_avalon_jtag_uart_read_fd + 0x00000000000095f8 altera_avalon_jtag_uart_write_fd + .text 0x0000000000009658 0xec c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + 0x0000000000009658 altera_avalon_jtag_uart_read + .text 0x0000000000009744 0x94 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + 0x0000000000009744 altera_avalon_jtag_uart_write + .text 0x00000000000097d8 0x108 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o) + 0x0000000000009854 alt_avalon_timer_sc_init + .text 0x00000000000098e0 0x158 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_busy_sleep.o) + 0x00000000000098e0 alt_busy_sleep + .text 0x0000000000009a38 0x118 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_close.o) + 0x0000000000009a80 close + .text 0x0000000000009b50 0x2c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev.o) + .text 0x0000000000009b7c 0xf0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + 0x0000000000009bc4 alt_dev_llist_insert + .text 0x0000000000009c6c 0x64 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_do_ctors.o) + 0x0000000000009c6c _do_ctors + .text 0x0000000000009cd0 0x64 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_do_dtors.o) + 0x0000000000009cd0 _do_dtors + .text 0x0000000000009d34 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_errno.o) + .text 0x0000000000009d34 0x90 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_find_dev.o) + 0x0000000000009d34 alt_find_dev + .text 0x0000000000009dc4 0x34 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + 0x0000000000009dc4 alt_icache_flush_all + .text 0x0000000000009df8 0x1c8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic.o) + 0x0000000000009df8 alt_ic_isr_register + 0x0000000000009e48 alt_ic_irq_enable + 0x0000000000009edc alt_ic_irq_disable + 0x0000000000009f74 alt_ic_irq_enabled + .text 0x0000000000009fc0 0xe8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + 0x0000000000009fc0 alt_iic_isr_register + .text 0x000000000000a0a8 0x12c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_io_redirect.o) + 0x000000000000a158 alt_io_redirect + .text 0x000000000000a1d4 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_entry.o) + .text 0x000000000000a1d4 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_handler.o) + .text 0x000000000000a1d4 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_vars.o) + .text 0x000000000000a1d4 0x25c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_open.o) + 0x000000000000a2d8 open + .text 0x000000000000a430 0x22c c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_printf.o) + 0x000000000000a430 alt_printf + .text 0x000000000000a65c 0x30 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_putchar.o) + 0x000000000000a65c alt_putchar + .text 0x000000000000a68c 0x58 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_release_fd.o) + 0x000000000000a68c alt_release_fd + .text 0x000000000000a6e4 0x24 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o) + 0x000000000000a6e4 altera_nios2_gen2_irq_init + .text 0x000000000000a708 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exception_entry.o) + .text 0x000000000000a708 0x110 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_find_file.o) + 0x000000000000a708 alt_find_file + .text 0x000000000000a818 0xa8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_get_fd.o) + 0x000000000000a818 alt_get_fd + .text 0x000000000000a8c0 0x90 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_icache_flush.o) + 0x000000000000a8c0 alt_icache_flush + .text 0x000000000000a950 0x98 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) + 0x000000000000a950 alt_exception_cause_generated_bad_addr + .text 0x000000000000a9e8 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-atexit.o) + .text.atexit 0x000000000000a9e8 0x14 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-atexit.o) + 0x000000000000a9e8 atexit + .text 0x000000000000a9fc 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-exit.o) + .text.exit 0x000000000000a9fc 0x20 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-exit.o) + 0x000000000000a9fc exit + .text 0x000000000000aa1c 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-memcmp.o) + .text.memcmp 0x000000000000aa1c 0x30 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-memcmp.o) + 0x000000000000aa1c memcmp + .text 0x000000000000aa4c 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__atexit.o) .text.__register_exitproc - 0x0000000000008968 0x11c d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__atexit.o) - 0x0000000000008968 __register_exitproc - .text 0x0000000000008a84 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__call_atexit.o) + 0x000000000000aa4c 0x11c d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__atexit.o) + 0x000000000000aa4c __register_exitproc + .text 0x000000000000ab68 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__call_atexit.o) .text.__call_exitprocs - 0x0000000000008a84 0x12c d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__call_atexit.o) - 0x0000000000008a84 __call_exitprocs - .text 0x0000000000008bb0 0x38 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exit.o) - 0x0000000000008bb0 _exit + 0x000000000000ab68 0x12c d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__call_atexit.o) + 0x000000000000ab68 __call_exitprocs + .text 0x000000000000ac94 0x38 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exit.o) + 0x000000000000ac94 _exit *(.gnu.warning.*) *(.fini) [!provide] PROVIDE (__etext = ABSOLUTE (.)) [!provide] PROVIDE (_etext = ABSOLUTE (.)) [!provide] PROVIDE (etext = ABSOLUTE (.)) *(.eh_frame_hdr) - 0x0000000000008be8 . = ALIGN (0x4) + 0x000000000000accc . = ALIGN (0x4) [!provide] PROVIDE (__preinit_array_start = ABSOLUTE (.)) *(.preinit_array) [!provide] PROVIDE (__preinit_array_end = ABSOLUTE (.)) @@ -574,303 +583,304 @@ LOAD d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nio *(.eh_frame) *(.gcc_except_table .gcc_except_table.*) *(.dynamic) - 0x0000000000008be8 PROVIDE (__CTOR_LIST__ = ABSOLUTE (.)) + 0x000000000000accc PROVIDE (__CTOR_LIST__ = ABSOLUTE (.)) *(.ctors) *(SORT_BY_NAME(.ctors.*)) - 0x0000000000008be8 PROVIDE (__CTOR_END__ = ABSOLUTE (.)) - 0x0000000000008be8 PROVIDE (__DTOR_LIST__ = ABSOLUTE (.)) + 0x000000000000accc PROVIDE (__CTOR_END__ = ABSOLUTE (.)) + 0x000000000000accc PROVIDE (__DTOR_LIST__ = ABSOLUTE (.)) *(.dtors) *(SORT_BY_NAME(.dtors.*)) - 0x0000000000008be8 PROVIDE (__DTOR_END__ = ABSOLUTE (.)) + 0x000000000000accc PROVIDE (__DTOR_END__ = ABSOLUTE (.)) *(.jcr) - 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.rodata 0x000000000000aea0 0xf1 obj/default/hdmi_config.o + *fill* 0x000000000000af91 0x3 + .rodata 0x000000000000af94 0x66c obj/default/hdmi_control.o + .rodata 0x000000000000b600 0x3eb obj/default/main.o + *fill* 0x000000000000b9eb 0x1 + .rodata.TWO52 0x000000000000b9ec 0x10 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-s_rint.o) + .rodata 0x000000000000b9fc 0x100 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_clz.o) + 0x000000000000b9fc __clz_tab .rodata._puts_r.str1.4 - 0x000000000000965c 0x2 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-puts.o) - *fill* 0x000000000000965e 0x2 - .rodata 0x0000000000009660 0xf c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_main.o) - *fill* 0x000000000000966f 0x1 - .rodata 0x0000000000009670 0x1f c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_sys_init.o) - *fill* 0x000000000000968f 0x1 - .rodata 0x0000000000009690 0x1d c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_i2c.o) - *fill* 0x00000000000096ad 0x3 - .rodata 0x00000000000096b0 0xa c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev.o) + 0x000000000000bafc 0x2 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-puts.o) + *fill* 0x000000000000bafe 0x2 + .rodata 0x000000000000bb00 0xf c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_main.o) + *fill* 0x000000000000bb0f 0x1 + .rodata 0x000000000000bb10 0x1f c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_sys_init.o) + *fill* 0x000000000000bb2f 0x1 + .rodata 0x000000000000bb30 0x1d c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_i2c.o) + *fill* 0x000000000000bb4d 0x3 + .rodata 0x000000000000bb50 0xa c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev.o) *(.rodata1) - 0x00000000000096bc . = ALIGN (0x4) - *fill* 0x00000000000096ba 0x2 - 0x00000000000096bc PROVIDE (__ram_rodata_end = ABSOLUTE (.)) - 0x0000000000008be8 PROVIDE (__flash_rodata_start = LOADADDR (.rodata)) + 0x000000000000bb5c . = ALIGN (0x4) + *fill* 0x000000000000bb5a 0x2 + 0x000000000000bb5c PROVIDE (__ram_rodata_end = ABSOLUTE (.)) + 0x000000000000accc PROVIDE (__flash_rodata_start = LOADADDR (.rodata)) -.rwdata 0x00000000000096bc 0x330 load address 0x00000000000099ec - 0x00000000000096bc PROVIDE (__ram_rwdata_start = ABSOLUTE (.)) - 0x00000000000096bc . = ALIGN (0x4) +.rwdata 0x000000000000bb5c 0x328 load address 0x000000000000be84 + 0x000000000000bb5c PROVIDE (__ram_rwdata_start = ABSOLUTE (.)) + 0x000000000000bb5c . = ALIGN (0x4) *(.got.plt) *(.got) *(.data1) *(.data .data.* .gnu.linkonce.d.*) - .data 0x00000000000096bc 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp//obj/HAL/src/crt0.o - .data 0x00000000000096bc 0x0 obj/default/burst_master_test.o - .data 0x00000000000096bc 0x0 obj/default/common.o - .data 0x00000000000096bc 0x0 obj/default/hdmi_config.o - .data 0x00000000000096bc 0x0 obj/default/hdmi_control.o - .data 0x00000000000096bc 0x0 obj/default/main.o - .data 0x00000000000096bc 0x0 obj/default/mem_verify.o - .data 0x00000000000096bc 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) - .data 0x00000000000096bc 0x0 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c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + .data 0x000000000000be4c 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic.o) + .data 0x000000000000be4c 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + .data 0x000000000000be4c 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_io_redirect.o) + .data 0x000000000000be4c 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_entry.o) + .data 0x000000000000be4c 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_handler.o) + .data 0x000000000000be4c 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_vars.o) + .data 0x000000000000be4c 0x0 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c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_vars.o) - 0x00000000000099e8 alt_priority_mask + 0x000000000000be54 0x4 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-impure.o) + 0x000000000000be54 _impure_ptr + .sdata 0x000000000000be58 0x8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_tick.o) + 0x000000000000be58 alt_alarm_list + .sdata 0x000000000000be60 0x8 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_i2c.o) + 0x000000000000be60 alt_avalon_i2c_list + .sdata 0x000000000000be68 0x14 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev.o) + 0x000000000000be68 alt_fs_list + 0x000000000000be70 alt_dev_list + 0x000000000000be78 alt_max_fd + .sdata 0x000000000000be7c 0x4 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_errno.o) + 0x000000000000be7c alt_errno + .sdata 0x000000000000be80 0x4 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_vars.o) + 0x000000000000be80 alt_priority_mask *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - 0x00000000000099ec . = ALIGN (0x4) - 0x00000000000099ec _edata = ABSOLUTE (.) + 0x000000000000be84 . = ALIGN (0x4) + 0x000000000000be84 _edata = ABSOLUTE (.) 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d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-vfprintf.o) + .bss 0x000000000000d1e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-fvwrite_small_dev.o) + .bss 0x000000000000d1e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-putc.o) + .bss 0x000000000000d1e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-writer.o) + .bss 0x000000000000d1e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-int_errno.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_load.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_main.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_tick.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_usleep.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_write.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_sys_init.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_i2c.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_timer_sc.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_busy_sleep.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_close.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_do_ctors.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_do_dtors.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_errno.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_find_dev.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_io_redirect.o) + .bss 0x000000000000d1e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_entry.o) + .bss 0x000000000000d1e0 0x100 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_handler.o) + 0x000000000000d1e0 alt_irq + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_vars.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_open.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_printf.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_putchar.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_release_fd.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exception_entry.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_find_file.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_get_fd.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_icache_flush.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) + .bss 0x000000000000d2e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-atexit.o) + .bss 0x000000000000d2e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-exit.o) + .bss 0x000000000000d2e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-memcmp.o) + .bss 0x000000000000d2e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__atexit.o) + .bss 0x000000000000d2e0 0x0 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__call_atexit.o) + .bss 0x000000000000d2e0 0x0 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exit.o) *(COMMON) - 0x000000000000ae60 . = ALIGN (0x4) - 0x000000000000ae60 __bss_end = ABSOLUTE (.) + 0x000000000000d2e0 . = ALIGN (0x4) + 0x000000000000d2e0 __bss_end = ABSOLUTE (.) .onchip_memory2_0 - 0x000000000000ae60 0x0 + 0x000000000000d2e0 0x0 [!provide] PROVIDE (_alt_partition_onchip_memory2_0_start = ABSOLUTE (.)) *(.onchip_memory2_0 .onchip_memory2_0. onchip_memory2_0.*) - 0x000000000000ae60 . = ALIGN (0x4) + 0x000000000000d2e0 . = ALIGN (0x4) [!provide] PROVIDE (_alt_partition_onchip_memory2_0_end = ABSOLUTE (.)) - 0x000000000000ae60 _end = ABSOLUTE (.) - 0x000000000000ae60 end = ABSOLUTE (.) - 0x000000000000ae60 __alt_stack_base = ABSOLUTE (.) + 0x000000000000d2e0 _end = ABSOLUTE (.) + 0x000000000000d2e0 end = ABSOLUTE (.) + 0x000000000000d2e0 __alt_stack_base = ABSOLUTE (.) [!provide] PROVIDE (_alt_partition_onchip_memory2_0_load_addr = LOADADDR (.onchip_memory2_0)) .stab @@ -900,26 +910,27 @@ LOAD d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nio .comment 0x000000000000002d 0x2e obj/default/hdmi_control.o .comment 0x000000000000002d 0x2e obj/default/main.o .comment 0x000000000000002d 0x2e obj/default/mem_verify.o - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-wf_pow.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-ef_pow.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-ef_sqrt.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-w_pow.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-e_pow.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-e_sqrt.o) .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-s_lib_ver.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-sf_rint.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-sf_scalbn.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-s_rint.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a(lib_a-s_scalbn.o) .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_muldi3.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_fixunssfsi.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_fixunsdfsi.o) .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(_udivdi3.o) .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(lib2-divmod.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(addsf3.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(divsf3.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(eqsf2.o) - .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(gesf2.o) .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(lesf2.o) - .comment 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.comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(eqdf2.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(gedf2.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(ledf2.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(muldf3.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(subdf3.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(unorddf2.o) + .comment 0x000000000000002d 0x2e d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1\libgcc.a(fixdfsi.o) + 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c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_release_fd.o) 0x1d9 (size before relaxing) - .debug_str 0x0000000000002eb8 0x3b c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o) + .debug_str 0x000000000000307e 0x3b c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_nios2_gen2_irq.o) 0x166 (size before relaxing) - .debug_str 0x0000000000002ef3 0x1e c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exception_entry.o) + .debug_str 0x00000000000030b9 0x1e c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exception_entry.o) 0x74 (size before relaxing) - .debug_str 0x0000000000002f11 0x26 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_find_file.o) + .debug_str 0x00000000000030d7 0x26 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0x0000000000001540 0x10 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-writer.o) + .debug_ranges 0x0000000000001550 0x18 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + .debug_ranges 0x0000000000001568 0x28 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_entry.o) + .debug_ranges 0x0000000000001590 0x10 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_irq_handler.o) + .debug_ranges 0x00000000000015a0 0x30 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_exception_entry.o) + .debug_ranges 0x00000000000015d0 0x18 c:/Workspace/quartus/video_processing/nios_software/nios_ddr3_test_bsp/\libhal_bsp.a(alt_instruction_exception_entry.o) + .debug_ranges 0x00000000000015e8 0x10 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-atexit.o) + .debug_ranges 0x00000000000015f8 0x10 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-exit.o) + .debug_ranges 0x0000000000001608 0x10 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-memcmp.o) + .debug_ranges 0x0000000000001618 0x10 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__atexit.o) + .debug_ranges 0x0000000000001628 0x28 d:/intelfpga_lite/20.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/10.1.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libsmallc.a(lib_a-__call_atexit.o) diff --git a/nios_software/video_app2/video_app2.objdump b/nios_software/video_app2/video_app2.objdump index 2bd32fb..eb4fd26 100644 --- a/nios_software/video_app2/video_app2.objdump +++ b/nios_software/video_app2/video_app2.objdump @@ -9,11 +9,11 @@ Program Header: LOAD off 0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12 filesz 0x00000020 memsz 0x00000020 flags r-x LOAD off 0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12 - filesz 0x0000969c memsz 0x0000969c flags r-x - LOAD off 0x0000a6bc vaddr 0x000096bc paddr 0x000099ec align 2**12 - filesz 0x00000330 memsz 0x00000330 flags rw- - LOAD off 0x0000ad1c vaddr 0x00009d1c paddr 0x00009d1c align 2**12 - filesz 0x00000000 memsz 0x00001144 flags rw- + filesz 0x0000bb3c memsz 0x0000bb3c flags r-x + LOAD off 0x0000cb5c vaddr 0x0000bb5c paddr 0x0000be84 align 2**12 + filesz 0x00000328 memsz 0x00000328 flags rw- + LOAD off 0x0000d1ac vaddr 0x0000c1ac paddr 0x0000c1ac align 2**12 + filesz 0x00000000 memsz 0x00001134 flags rw- Sections: Idx Name Size VMA LMA File off Algn @@ -21,62 +21,62 @@ Idx Name Size VMA LMA File off Algn CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .exceptions 00000218 00000020 00000020 00001020 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .text 000089b0 00000238 00000238 00001238 2**2 + 2 .text 0000aa94 00000238 00000238 00001238 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 3 .rodata 00000ad4 00008be8 00008be8 00009be8 2**2 + 3 .rodata 00000e90 0000accc 0000accc 0000bccc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 4 .rwdata 00000330 000096bc 000099ec 0000a6bc 2**2 + 4 .rwdata 00000328 0000bb5c 0000be84 0000cb5c 2**2 CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA - 5 .bss 00001144 00009d1c 00009d1c 0000ad1c 2**5 + 5 .bss 00001134 0000c1ac 0000c1ac 0000d1ac 2**5 ALLOC, SMALL_DATA - 6 .onchip_memory2_0 00000000 0000ae60 0000ae60 0000a9ec 2**0 + 6 .onchip_memory2_0 00000000 0000d2e0 0000d2e0 0000ce84 2**0 CONTENTS - 7 .comment 0000002d 00000000 00000000 0000a9ec 2**0 + 7 .comment 0000002d 00000000 00000000 0000ce84 2**0 CONTENTS, READONLY - 8 .debug_aranges 00000a18 00000000 00000000 0000aa20 2**3 + 8 .debug_aranges 00000a38 00000000 00000000 0000ceb8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 9 .debug_info 0000f762 00000000 00000000 0000b438 2**0 + 9 .debug_info 00010983 00000000 00000000 0000d8f0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 10 .debug_abbrev 0000556e 00000000 00000000 0001ab9a 2**0 + 10 .debug_abbrev 00005776 00000000 00000000 0001e273 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 11 .debug_line 00008d54 00000000 00000000 00020108 2**0 + 11 .debug_line 0000a9bc 00000000 00000000 000239e9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 12 .debug_frame 000017c0 00000000 00000000 00028e5c 2**2 + 12 .debug_frame 000017d0 00000000 00000000 0002e3a8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_str 00003697 00000000 00000000 0002a61c 2**0 + 13 .debug_str 0000385d 00000000 00000000 0002fb78 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_loc 00008a1c 00000000 00000000 0002dcb3 2**0 + 14 .debug_loc 0000d509 00000000 00000000 000333d5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_alt_sim_info 00000060 00000000 00000000 000366d0 2**2 + 15 .debug_alt_sim_info 00000060 00000000 00000000 000408e0 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_ranges 00001098 00000000 00000000 00036730 2**3 + 16 .debug_ranges 00001650 00000000 00000000 00040940 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .thread_model 00000003 00000000 00000000 0003a350 2**0 + 17 .thread_model 00000003 00000000 00000000 00044c18 2**0 CONTENTS, READONLY - 18 .cpu 0000000c 00000000 00000000 0003a353 2**0 + 18 .cpu 0000000c 00000000 00000000 00044c1b 2**0 CONTENTS, READONLY - 19 .qsys 00000001 00000000 00000000 0003a35f 2**0 + 19 .qsys 00000001 00000000 00000000 00044c27 2**0 CONTENTS, READONLY - 20 .simulation_enabled 00000001 00000000 00000000 0003a360 2**0 + 20 .simulation_enabled 00000001 00000000 00000000 00044c28 2**0 CONTENTS, READONLY - 21 .stderr_dev 00000009 00000000 00000000 0003a361 2**0 + 21 .stderr_dev 00000009 00000000 00000000 00044c29 2**0 CONTENTS, READONLY - 22 .stdin_dev 00000009 00000000 00000000 0003a36a 2**0 + 22 .stdin_dev 00000009 00000000 00000000 00044c32 2**0 CONTENTS, READONLY - 23 .stdout_dev 00000009 00000000 00000000 0003a373 2**0 + 23 .stdout_dev 00000009 00000000 00000000 00044c3b 2**0 CONTENTS, READONLY - 24 .sopc_system_name 0000000a 00000000 00000000 0003a37c 2**0 + 24 .sopc_system_name 0000000a 00000000 00000000 00044c44 2**0 CONTENTS, READONLY - 25 .sopcinfo 003201de 00000000 00000000 0003a386 2**0 + 25 .sopcinfo 003201db 00000000 00000000 00044c4e 2**0 CONTENTS, READONLY SYMBOL TABLE: 00000000 l d .entry 00000000 .entry 00000020 l d .exceptions 00000000 .exceptions 00000238 l d .text 00000000 .text -00008be8 l d .rodata 00000000 .rodata -000096bc l d .rwdata 00000000 .rwdata -00009d1c l d .bss 00000000 .bss -0000ae60 l d .onchip_memory2_0 00000000 .onchip_memory2_0 +0000accc l d .rodata 00000000 .rodata +0000bb5c l d .rwdata 00000000 .rwdata +0000c1ac l d .bss 00000000 .bss +0000d2e0 l d .onchip_memory2_0 00000000 .onchip_memory2_0 00000000 l d .comment 00000000 .comment 00000000 l d .debug_aranges 00000000 .debug_aranges 00000000 l d .debug_info 00000000 .debug_info @@ -92,80 +92,82 @@ SYMBOL TABLE: 00000000 l df *ABS* 00000000 alt_irq_handler.c 00000000 l df *ABS* 00000000 alt_instruction_exception_entry.c 00000000 l df *ABS* 00000000 burst_master_test.c -00009d60 l O .bss 00001000 ocm_src_buffer +0000c1e0 l O .bss 00001000 ocm_src_buffer 00000000 l df *ABS* 00000000 common.c 00000000 l df *ABS* 00000000 hdmi_config.c -00009d1c l O .bss 00000004 i2c_dev +0000c1ac l O .bss 00000004 i2c_dev 00000000 l df *ABS* 00000000 hdmi_control.c -00009d20 l O .bss 00000004 gamma_en.0 +0000c1b0 l O .bss 00000004 gamma_en.2 +0000c1b4 l O .bss 00000004 dma_mode_active.1 +0000c1b8 l O .bss 00000004 cont_active.0 00000000 l df *ABS* 00000000 main.c -00009d24 l O .bss 00000004 gamma_en.0 00000000 l df *ABS* 00000000 mem_verify.c -00000000 l df *ABS* 00000000 wf_pow.c -00000000 l df *ABS* 00000000 ef_pow.c -00000000 l df *ABS* 00000000 ef_sqrt.c +00000000 l df *ABS* 00000000 w_pow.c +00000000 l df *ABS* 00000000 e_pow.c +00000000 l df *ABS* 00000000 e_sqrt.c 00000000 l df *ABS* 00000000 s_lib_ver.c -00000000 l df *ABS* 00000000 sf_rint.c -000099b0 l O .rwdata 00000008 TWO23 -00000000 l df *ABS* 00000000 sf_scalbn.c +00000000 l df *ABS* 00000000 s_rint.c +0000b9ec l O .rodata 00000010 TWO52 +00000000 l df *ABS* 00000000 s_scalbn.c 00000000 l df *ABS* 00000000 libgcc2.c 00000000 l df *ABS* 00000000 libgcc2.c 00000000 l df *ABS* 00000000 libgcc2.c 00000000 l df *ABS* 00000000 lib2-divmod.c -00000000 l df *ABS* 00000000 addsf3.c -00000000 l df *ABS* 00000000 divsf3.c -00000000 l df *ABS* 00000000 eqsf2.c -00000000 l df *ABS* 00000000 gesf2.c 00000000 l df *ABS* 00000000 lesf2.c -00000000 l df *ABS* 00000000 mulsf3.c -00000000 l df *ABS* 00000000 subsf3.c -00000000 l df *ABS* 00000000 unordsf2.c -00000000 l df *ABS* 00000000 fixsfsi.c -00000000 l df *ABS* 00000000 floatsisf.c +00000000 l df *ABS* 00000000 adddf3.c +00000000 l df *ABS* 00000000 divdf3.c +00000000 l df *ABS* 00000000 eqdf2.c +00000000 l df *ABS* 00000000 gedf2.c +00000000 l df *ABS* 00000000 ledf2.c +00000000 l df *ABS* 00000000 muldf3.c +00000000 l df *ABS* 00000000 subdf3.c +00000000 l df *ABS* 00000000 unorddf2.c +00000000 l df *ABS* 00000000 fixdfsi.c +00000000 l df *ABS* 00000000 floatsidf.c 00000000 l df *ABS* 00000000 extendsfdf2.c 00000000 l df *ABS* 00000000 libgcc2.c 00000000 l df *ABS* 00000000 libgcc2.c 00000000 l df *ABS* 00000000 errno.c 00000000 l df *ABS* 00000000 impure.c -000096bc l O .rwdata 000000e4 impure_data +0000bb5c l O .rwdata 000000e4 impure_data 00000000 l df *ABS* 00000000 memcpy.c 00000000 l df *ABS* 00000000 printf.c 00000000 l df *ABS* 00000000 putchar.c 00000000 l df *ABS* 00000000 puts.c 00000000 l df *ABS* 00000000 strlen.c 00000000 l df *ABS* 00000000 vfprintf.c -00004bf8 l F .text 0000006c print_repeat +00006cdc l F .text 0000006c print_repeat 00000000 l df *ABS* 00000000 fvwrite_small_dev.c 00000000 l df *ABS* 00000000 putc.c 00000000 l df *ABS* 00000000 writer.c 00000000 l df *ABS* 00000000 int_errno.c 00000000 l df *ABS* 00000000 alt_dcache_flush_all.c 00000000 l df *ABS* 00000000 alt_load.c -00005350 l F .text 00000068 alt_load_section +00007434 l F .text 00000068 alt_load_section 00000000 l df *ABS* 00000000 alt_main.c 00000000 l df *ABS* 00000000 alt_tick.c 00000000 l df *ABS* 00000000 alt_usleep.c 00000000 l df *ABS* 00000000 alt_write.c -00005694 l F .text 00000048 alt_get_errno +00007778 l F .text 00000048 alt_get_errno 00000000 l df *ABS* 00000000 alt_sys_init.c -000057d4 l F .text 00000038 alt_dev_reg -000097a0 l O .rwdata 00000038 i2c_hdmi -000097d8 l O .rwdata 0000002c jtag_uart +000078b8 l F .text 00000038 alt_dev_reg +0000bc40 l O .rwdata 00000038 i2c_hdmi +0000bc78 l O .rwdata 0000002c jtag_uart 00000000 l df *ABS* 00000000 altera_avalon_i2c.c -000058a0 l F .text 00000110 optional_irq_callback -00005a00 l F .text 000000a0 alt_avalon_i2c_irq +00007984 l F .text 00000110 optional_irq_callback +00007ae4 l F .text 000000a0 alt_avalon_i2c_irq 00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_fd.c 00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_read.c 00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_write.c 00000000 l df *ABS* 00000000 altera_avalon_timer_sc.c -000076f4 l F .text 0000007c alt_avalon_timer_sc_irq +000097d8 l F .text 0000007c alt_avalon_timer_sc_irq 00000000 l df *ABS* 00000000 alt_busy_sleep.c 00000000 l df *ABS* 00000000 alt_close.c -00007954 l F .text 00000048 alt_get_errno +00009a38 l F .text 00000048 alt_get_errno 00000000 l df *ABS* 00000000 alt_dev.c -00007a6c l F .text 0000002c alt_dev_null_write +00009b50 l F .text 0000002c alt_dev_null_write 00000000 l df *ABS* 00000000 alt_dev_llist_insert.c -00007a98 l F .text 00000048 alt_get_errno +00009b7c l F .text 00000048 alt_get_errno 00000000 l df *ABS* 00000000 alt_do_ctors.c 00000000 l df *ABS* 00000000 alt_do_dtors.c 00000000 l df *ABS* 00000000 alt_errno.c @@ -174,11 +176,11 @@ SYMBOL TABLE: 00000000 l df *ABS* 00000000 alt_iic.c 00000000 l df *ABS* 00000000 alt_iic_isr_register.c 00000000 l df *ABS* 00000000 alt_io_redirect.c -00007fc4 l F .text 000000b0 alt_open_fd +0000a0a8 l F .text 000000b0 alt_open_fd 00000000 l df *ABS* 00000000 alt_irq_vars.c 00000000 l df *ABS* 00000000 alt_open.c -000080f0 l F .text 00000048 alt_get_errno -00008138 l F .text 000000bc alt_file_locked +0000a1d4 l F .text 00000048 alt_get_errno +0000a21c l F .text 000000bc alt_file_locked 00000000 l df *ABS* 00000000 alt_printf.c 00000000 l df *ABS* 00000000 alt_putchar.c 00000000 l df *ABS* 00000000 alt_release_fd.c @@ -192,196 +194,202 @@ SYMBOL TABLE: 00000000 l df *ABS* 00000000 __atexit.c 00000000 l df *ABS* 00000000 __call_atexit.c 00000000 l df *ABS* 00000000 alt_exit.c -00009d44 g O .bss 00000004 alt_instruction_exception_handler -00004b34 g F .text 00000018 putchar -0000543c g F .text 0000007c alt_main -00004b4c g F .text 00000080 _puts_r -0000ad60 g O .bss 00000100 alt_irq -000099ec g *ABS* 00000000 __flash_rwdata_start -00004ae4 g F .text 00000048 printf -00000284 g F .text 00000418 run_ocm_to_ddr_test -00006100 g F .text 000000a8 alt_avalon_i2c_rx_read -0000392c g F .text 000003f4 .hidden __divsf3 -00007310 g F .text 00000044 alt_avalon_i2c_enabled_ints_get -00005e80 g F .text 00000094 alt_avalon_i2c_master_config_speed_get -00001b60 g F .text 00000298 powf -00006b64 g F .text 00000208 alt_avalon_i2c_master_transmit_using_interrupts -00004790 g F .text 00000070 .hidden __fixsfsi -000015f0 g F .text 000000e0 load_inverse_gamma_table -00008600 g F .text 00000024 altera_nios2_gen2_irq_init -00004a74 g F .text 0000000c __errno +0000c1d8 g O .bss 00000004 alt_instruction_exception_handler +00006c18 g F .text 00000018 putchar +00007520 g F .text 0000007c alt_main +00006c30 g F .text 00000080 _puts_r +00001ac0 g F .text 000000cc print_dma_status +0000d1e0 g O .bss 00000100 alt_irq +0000be84 g *ABS* 00000000 __flash_rwdata_start +00005704 g F .text 00000080 .hidden __eqdf2 +00006bc8 g F .text 00000048 printf +00000284 g F .text 0000041c run_ocm_to_ddr_test +000081e4 g F .text 000000a8 alt_avalon_i2c_rx_read +000093f4 g F .text 00000044 alt_avalon_i2c_enabled_ints_get +00007f64 g F .text 00000094 alt_avalon_i2c_master_config_speed_get +00008c48 g F .text 00000208 alt_avalon_i2c_master_transmit_using_interrupts +00001800 g F .text 00000140 load_inverse_gamma_table +00005784 g F .text 000000e8 .hidden __gtdf2 +0000a6e4 g F .text 00000024 altera_nios2_gen2_irq_init +00006b58 g F .text 0000000c __errno 00000000 g F .entry 0000001c __reset 00000020 g *ABS* 00000000 __flash_exceptions_start -00009d28 g O .bss 00000004 errno -00009d30 g O .bss 00000004 alt_argv -000119ac g *ABS* 00000000 _gp -00005664 g F .text 00000030 usleep -00007354 g F .text 0000004c alt_avalon_i2c_rx_fifo_threshold_get -000042b0 g F .text 00000494 .hidden __subsf3 -00006010 g F .text 00000044 alt_avalon_i2c_is_busy -0000982c g O .rwdata 00000180 alt_fd_list -00004b2c g F .text 00000008 _putchar_r -00005db4 g F .text 000000cc alt_avalon_i2c_master_config_set -00007c50 g F .text 00000090 alt_find_dev -00004a80 g F .text 00000028 memcpy -00000f28 g F .text 00000160 generate_color_bar_pattern -00008074 g F .text 0000007c alt_io_redirect -00008be8 g *ABS* 00000000 __DTOR_END__ -000069a8 g F .text 000001bc alt_avalon_i2c_master_transmit -00004bcc g F .text 00000010 puts -0000886c g F .text 00000098 alt_exception_cause_generated_bad_addr -00007574 g F .text 000000ec altera_avalon_jtag_uart_read -00004aa8 g F .text 0000003c _printf_r +0000c1bc g O .bss 00000004 errno +0000c1c4 g O .bss 00000004 alt_argv +00013e4c g *ABS* 00000000 _gp +00007748 g F .text 00000030 usleep +00009438 g F .text 0000004c alt_avalon_i2c_rx_fifo_threshold_get +000080f4 g F .text 00000044 alt_avalon_i2c_is_busy +0000bccc g O .rwdata 00000180 alt_fd_list +00006c10 g F .text 00000008 _putchar_r +00007e98 g F .text 000000cc alt_avalon_i2c_master_config_set +00009d34 g F .text 00000090 alt_find_dev +00006b64 g F .text 00000028 memcpy +00000f30 g F .text 000001f8 generate_color_bar_pattern +00006950 g F .text 000000b8 .hidden __floatsidf +0000a158 g F .text 0000007c alt_io_redirect +0000586c g F .text 000000e8 .hidden __ltdf2 +0000accc g *ABS* 00000000 __DTOR_END__ +00008a8c g F .text 000001bc alt_avalon_i2c_master_transmit +00006cb0 g F .text 00000010 puts +0000a950 g F .text 00000098 alt_exception_cause_generated_bad_addr +00009658 g F .text 000000ec altera_avalon_jtag_uart_read +00006b8c g F .text 0000003c _printf_r 00000000 g *ABS* 00000000 __alt_mem_onchip_memory2_0 -00003400 g F .text 00000064 .hidden __udivsi3 -00003e48 g F .text 000000b4 .hidden __lesf2 -000087dc g F .text 00000090 alt_icache_flush -00005c20 g F .text 00000098 alt_avalon_i2c_enable -0000723c g F .text 0000006c alt_avalon_i2c_int_disable -000099e0 g O .rwdata 00000004 alt_max_fd -0000069c g F .text 000004f0 run_ddr_to_ddr_test -00006d6c g F .text 0000020c alt_avalon_i2c_master_receive -00004924 g F .text 000000fc .hidden __extendsfdf2 -00003d20 g F .text 00000070 .hidden __nesf2 -000099ac g O .rwdata 00000004 __fdlib_version -000072a8 g F .text 00000068 alt_avalon_i2c_int_enable -000099b8 g O .rwdata 00000004 _global_impure_ptr -0000ae60 g *ABS* 00000000 __bss_end -00007edc g F .text 000000e8 alt_iic_isr_register -00001830 g F .text 0000020c run_interactive_menu -0000555c g F .text 00000108 alt_tick -00002d7c g F .text 00000590 .hidden __udivdi3 -00007164 g F .text 00000058 alt_avalon_i2c_int_status_get -00007e90 g F .text 0000004c alt_ic_irq_enabled -000054b8 g F .text 000000a4 alt_alarm_stop -00005aa0 g F .text 00000054 alt_avalon_i2c_register_callback -00009d40 g O .bss 00000004 alt_irq_active -00005af4 g F .text 000000ec alt_avalon_i2c_init +00004444 g F .text 00000064 .hidden __udivsi3 +00004504 g F .text 000000b4 .hidden __lesf2 +00003d4c g F .text 00000074 .hidden __fixunsdfsi +0000a8c0 g F .text 00000090 alt_icache_flush +00007d04 g F .text 00000098 alt_avalon_i2c_enable +00009320 g F .text 0000006c alt_avalon_i2c_int_disable +0000be78 g O .rwdata 00000004 alt_max_fd +000006a0 g F .text 000004f4 run_ddr_to_ddr_test +00008e50 g F .text 0000020c alt_avalon_i2c_master_receive +00006a08 g F .text 000000fc .hidden __extendsfdf2 +000045b8 g F .text 000008f0 .hidden __adddf3 +0000be4c g O .rwdata 00000004 __fdlib_version +0000938c g F .text 00000068 alt_avalon_i2c_int_enable +0000be50 g O .rwdata 00000004 _global_impure_ptr +0000d2e0 g *ABS* 00000000 __bss_end +00009fc0 g F .text 000000e8 alt_iic_isr_register +00001e98 g F .text 0000027c run_interactive_menu +00007640 g F .text 00000108 alt_tick +00003dc0 g F .text 00000590 .hidden __udivdi3 +00009248 g F .text 00000058 alt_avalon_i2c_int_status_get +00009f74 g F .text 0000004c alt_ic_irq_enabled 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00000040 get_char_async +0000bca4 g O .rwdata 00000028 alt_dev_null +000015ec g F .text 00000214 load_srgb_gamma_table +00003950 g F .text 000001dc rint +00000c0c g F .text 00000110 get_total_cycles +00001380 g F .text 000001d4 load_gamma_table +000073e8 g F .text 0000004c alt_dcache_flush_all +00001a3c g F .text 00000084 dma_set_continuous +000068d0 g F .text 00000080 .hidden __fixdfsi +0000be84 g *ABS* 00000000 __ram_rwdata_end +0000be70 g O .rwdata 00000008 alt_dev_list +000077c0 g F .text 000000f8 write +00007344 g F .text 00000054 _putc_r +00008520 g F .text 0000004c alt_avalon_i2c_check_arblost +000092e4 g F .text 0000003c alt_avalon_i2c_int_clear +0000bb5c g *ABS* 00000000 __ram_rodata_end +0000586c g F .text 000000e8 .hidden __ledf2 +0000be60 g O .rwdata 00000008 alt_avalon_i2c_list +000044a8 g F .text 0000005c .hidden __umodsi3 +0000d2e0 g *ABS* 00000000 end +00000bcc g F .text 00000040 get_char_async 000001c4 g F .exceptions 00000074 alt_instruction_exception_entry -00005be0 g F .text 00000040 alt_avalon_i2c_open -00008be8 g *ABS* 00000000 __CTOR_LIST__ +00007cc4 g F .text 00000040 alt_avalon_i2c_open +0000accc g *ABS* 00000000 __CTOR_LIST__ 000186a0 g *ABS* 00000000 __alt_stack_pointer -000065bc g F .text 000000e8 alt_avalon_i2c_master_tx -00007770 g F .text 0000008c alt_avalon_timer_sc_init -00004a20 g F .text 00000054 .hidden __clzsi2 -00007660 g F .text 00000094 altera_avalon_jtag_uart_write -00004c64 g F .text 000004ec ___vfprintf_internal_r -0000834c g F .text 0000022c alt_printf -00001778 g F .text 000000b8 print_menu -00008a84 g F .text 0000012c __call_exitprocs -000011c0 g F .text 00000120 change_rtl_pattern -000059b0 g F .text 00000050 alt_avalon_i2c_register_optional_irq_handler +000086a0 g F .text 000000e8 alt_avalon_i2c_master_tx +00009854 g F .text 0000008c alt_avalon_timer_sc_init +00006b04 g F .text 00000054 .hidden __clzsi2 +00009744 g F .text 00000094 altera_avalon_jtag_uart_write +00006d48 g F .text 000004ec ___vfprintf_internal_r +0000a430 g F .text 0000022c alt_printf +00001dd4 g F .text 000000c4 print_menu +0000ab68 g F .text 0000012c __call_exitprocs +00001260 g F .text 00000120 change_rtl_pattern +00007a94 g F .text 00000050 alt_avalon_i2c_register_optional_irq_handler 00000238 g F .text 0000004c _start -00009d38 g O .bss 00000004 _alt_tick_rate -00006f78 g F .text 000001ec alt_avalon_i2c_master_receive_using_interrupts -000073a0 g F .text 00000064 alt_avalon_i2c_rx_fifo_threshold_set -00009d3c g O .bss 00000004 _alt_nticks -00005848 g F .text 00000058 alt_sys_init -00004800 g F .text 00000124 .hidden __floatsisf -00008968 g F .text 0000011c __register_exitproc -000067e0 g F .text 000001c8 alt_avalon_i2c_master_tx_rx -000096bc g *ABS* 00000000 __ram_rwdata_start -00008be8 g *ABS* 00000000 __ram_rodata_start -00003d20 g F .text 00000070 .hidden __eqsf2 -000074b4 g F .text 00000060 altera_avalon_jtag_uart_read_fd -00008734 g F .text 000000a8 alt_get_fd -000077fc g F .text 00000158 alt_busy_sleep -00008938 g F .text 00000030 memcmp -00006054 g F .text 000000ac alt_avalon_i2c_rx_read_available -0000ae60 g *ABS* 00000000 __alt_stack_base -00001df8 g F .text 00000b00 __ieee754_powf -00008624 g F .text 00000110 alt_find_file -00007ae0 g F .text 000000a8 alt_dev_llist_insert -00006488 g F .text 00000134 alt_avalon_i2c_interrupt_transaction_status -000063f0 g F .text 0000004c alt_avalon_i2c_check_nack -00002b70 g F .text 0000014c scalbnf -00005168 g F .text 000000a8 __sfvwrite_small_dev -00009d1c g *ABS* 00000000 __bss_start -000028f8 g F .text 00000150 __ieee754_sqrtf -00001a3c g F .text 00000124 main -000063bc g F .text 00000034 alt_avalon_i2c_master_target_set -00009d34 g O .bss 00000004 alt_envp -00007514 g F .text 00000060 altera_avalon_jtag_uart_write_fd -000071bc g F .text 00000044 alt_avalon_i2c_int_raw_status_get -00003e48 g F .text 000000b4 .hidden __ltsf2 -000099e4 g O .rwdata 00000004 alt_errno -00005210 g F .text 00000050 putc -0000330c g F .text 00000080 .hidden __divsi3 -00008be8 g *ABS* 00000000 __CTOR_END__ -00003efc g F .text 000003b4 .hidden __mulsf3 -00000b8c g F .text 00000038 get_char_polled -00008be8 g *ABS* 00000000 __flash_rodata_start -00008be8 g *ABS* 00000000 __DTOR_LIST__ -0000580c g F .text 0000003c alt_irq_init -000085a8 g F .text 00000058 alt_release_fd -0000955c g O .rodata 00000100 .hidden __clz_tab -00008904 g F .text 00000014 atexit -00003d90 g F .text 000000b8 .hidden __gesf2 -000052b4 g F .text 00000050 _write_r -000099bc g O .rwdata 00000004 _impure_ptr -00009d2c g O .bss 00000004 alt_argc -00007bec g F .text 00000064 _do_dtors -00006384 g F .text 00000038 alt_avalon_i2c_master_target_get -00006294 g F .text 000000f0 alt_avalon_i2c_send_address -000016d0 g F .text 000000a8 load_char_bitmap +0000c1cc g O .bss 00000004 _alt_tick_rate +0000905c g F .text 000001ec alt_avalon_i2c_master_receive_using_interrupts +00009484 g F .text 00000064 alt_avalon_i2c_rx_fifo_threshold_set +0000c1d0 g O .bss 00000004 _alt_nticks +0000792c g F .text 00000058 alt_sys_init +0000aa4c g F .text 0000011c __register_exitproc +000088c4 g F .text 000001c8 alt_avalon_i2c_master_tx_rx +00002624 g F .text 000010c0 __ieee754_pow +0000228c g F .text 00000398 pow +0000bb5c g *ABS* 00000000 __ram_rwdata_start +0000accc g *ABS* 00000000 __ram_rodata_start +00009598 g F .text 00000060 altera_avalon_jtag_uart_read_fd +0000a818 g F .text 000000a8 alt_get_fd +000098e0 g F .text 00000158 alt_busy_sleep +0000aa1c g F .text 00000030 memcmp +00008138 g F .text 000000ac alt_avalon_i2c_rx_read_available +0000d2e0 g *ABS* 00000000 __alt_stack_base +00004ea8 g F .text 0000085c .hidden __divdf3 +00005954 g F .text 00000674 .hidden __muldf3 +0000a708 g F .text 00000110 alt_find_file +00009bc4 g F .text 000000a8 alt_dev_llist_insert +0000856c g F .text 00000134 alt_avalon_i2c_interrupt_transaction_status +000084d4 g F .text 0000004c alt_avalon_i2c_check_nack +0000724c g F .text 000000a8 __sfvwrite_small_dev +0000c1ac g *ABS* 00000000 __bss_start +00002114 g F .text 00000178 main +000084a0 g F .text 00000034 alt_avalon_i2c_master_target_set +0000c1c8 g O .bss 00000004 alt_envp +000095f8 g F .text 00000060 altera_avalon_jtag_uart_write_fd +00001b8c g F .text 00000248 run_dma_debug_submenu +000092a0 g F .text 00000044 alt_avalon_i2c_int_raw_status_get +00004504 g F .text 000000b4 .hidden __ltsf2 +0000be7c g O .rwdata 00000004 alt_errno +000072f4 g F .text 00000050 putc +00004350 g F .text 00000080 .hidden __divsi3 +0000accc g *ABS* 00000000 __CTOR_END__ +00000b94 g F .text 00000038 get_char_polled +0000accc g *ABS* 00000000 __flash_rodata_start +0000accc g *ABS* 00000000 __DTOR_LIST__ +00005704 g F .text 00000080 .hidden __nedf2 +000078f0 g F .text 0000003c alt_irq_init +0000a68c g F .text 00000058 alt_release_fd +0000b9fc g O .rodata 00000100 .hidden __clz_tab +0000a9e8 g F .text 00000014 atexit +00007398 g F .text 00000050 _write_r +0000be54 g O .rwdata 00000004 _impure_ptr +0000c1c0 g O .bss 00000004 alt_argc +00003b2c g F .text 000001c0 scalbn +00009cd0 g F .text 00000064 _do_dtors +00008468 g F .text 00000038 alt_avalon_i2c_master_target_get +00008378 g F .text 000000f0 alt_avalon_i2c_send_address +00001940 g F .text 000000a8 load_char_bitmap 00000020 g .exceptions 00000000 alt_irq_entry -000099d0 g O .rwdata 00000008 alt_fs_list -00000d14 g F .text 00000078 hdmi_i2c_write +0000be68 g O .rwdata 00000008 alt_fs_list +00000d1c g F .text 00000078 hdmi_i2c_write 00000020 g *ABS* 00000000 __ram_exceptions_start -00000d8c g F .text 0000019c hdmi_init -00007450 g F .text 00000064 alt_avalon_i2c_tfr_cmd_fifo_threshold_set -00007d14 g F .text 00000050 alt_ic_isr_register -00005cb8 g F .text 0000004c alt_avalon_i2c_disable -000099ec g *ABS* 00000000 _edata -0000ae60 g *ABS* 00000000 _end -00004744 g F .text 0000004c .hidden __unordsf2 +00000d94 g F .text 0000019c hdmi_init +000036e4 g F .text 0000026c __ieee754_sqrt +00009534 g F .text 00000064 alt_avalon_i2c_tfr_cmd_fifo_threshold_set +00009df8 g F .text 00000050 alt_ic_isr_register +00007d9c g F .text 0000004c alt_avalon_i2c_disable +0000be84 g *ABS* 00000000 _edata +0000d2e0 g *ABS* 00000000 _end 00000238 g *ABS* 00000000 __ram_exceptions_end -00005d04 g F .text 000000b0 alt_avalon_i2c_master_config_get -00007df8 g F .text 00000098 alt_ic_irq_disable -00008918 g F .text 00000020 exit -0000338c g F .text 00000074 .hidden __modsi3 +00007de8 g F .text 000000b0 alt_avalon_i2c_master_config_get +00009edc g F .text 00000098 alt_ic_irq_disable +000019e8 g F .text 00000054 dma_start_single +0000a9fc g F .text 00000020 exit +000043d0 g F .text 00000074 .hidden __modsi3 000186a0 g *ABS* 00000000 __alt_data_end 00000020 g F .exceptions 00000000 alt_exception -00005f14 g F .text 000000fc alt_avalon_i2c_master_config_speed_set -000061a8 g F .text 000000ec alt_avalon_i2c_cmd_write -00002d1c g F .text 00000060 .hidden __fixunssfsi -00001418 g F .text 0000006c set_gamma_enable -00008bb0 g F .text 00000038 _exit -00002cbc g F .text 00000060 .hidden __muldi3 -00004bdc g F .text 0000001c strlen -00002a48 g F .text 00000128 rintf -000081f4 g F .text 00000158 open -00008578 g F .text 00000030 alt_putchar -00007ce0 g F .text 00000034 alt_icache_flush_all -000099e8 g O .rwdata 00000004 alt_priority_mask -00007d64 g F .text 00000094 alt_ic_irq_enable -00005150 g F .text 00000018 __vfprintf_internal -000099c0 g O .rwdata 00000008 alt_alarm_list -00007b88 g F .text 00000064 _do_ctors -0000799c g F .text 000000d0 close -000034c0 g F .text 0000046c .hidden __addsf3 -00007404 g F .text 0000004c alt_avalon_i2c_tfr_cmd_fifo_threshold_get -000053b8 g F .text 00000084 alt_load -000066a4 g F .text 0000013c alt_avalon_i2c_master_rx -00001088 g F .text 00000138 run_gamma_submenu +00007ff8 g F .text 000000fc alt_avalon_i2c_master_config_speed_set +0000828c g F .text 000000ec alt_avalon_i2c_cmd_write +0000687c g F .text 00000054 .hidden __unorddf2 +00001554 g F .text 00000098 set_gamma_enable +0000ac94 g F .text 00000038 _exit +00003cec g F .text 00000060 .hidden __muldi3 +00006cc0 g F .text 0000001c strlen +0000a2d8 g F .text 00000158 open +00005784 g F .text 000000e8 .hidden __gedf2 +0000a65c g F .text 00000030 alt_putchar +00009dc4 g F .text 00000034 alt_icache_flush_all +0000be80 g O .rwdata 00000004 alt_priority_mask +00009e48 g F .text 00000094 alt_ic_irq_enable +00007234 g F .text 00000018 __vfprintf_internal +00005fc8 g F .text 000008b4 .hidden __subdf3 +0000be58 g O .rwdata 00000008 alt_alarm_list +00009c6c g F .text 00000064 _do_ctors +00009a80 g F .text 000000d0 close +000094e8 g F .text 0000004c alt_avalon_i2c_tfr_cmd_fifo_threshold_get +0000749c g F .text 00000084 alt_load +00008788 g F .text 0000013c alt_avalon_i2c_master_rx +00001128 g F .text 00000138 run_gamma_submenu @@ -477,12 +485,12 @@ Disassembly of section .exceptions: 140: 100690fa slli r3,r2,3 144: 00800074 movhi r2,1 148: 1885883a add r2,r3,r2 - 14c: 10eb5817 ldw r3,-21152(r2) + 14c: 10f47817 ldw r3,-11808(r2) 150: e0bffd17 ldw r2,-12(fp) 154: 100890fa slli r4,r2,3 158: 00800074 movhi r2,1 15c: 2085883a add r2,r4,r2 - 160: 10ab5917 ldw r2,-21148(r2) + 160: 10b47917 ldw r2,-11804(r2) 164: 1009883a mov r4,r2 168: 183ee83a callr r3 16c: 0001883a nop @@ -522,9 +530,9 @@ Disassembly of section .exceptions: 1ec: e0bfff15 stw r2,-4(fp) 1f0: 0005333a rdctl r2,badaddr 1f4: e0bffe15 stw r2,-8(fp) - 1f8: d0a0e617 ldw r2,-31848(gp) + 1f8: d0a0e317 ldw r2,-31860(gp) 1fc: 10000726 beq r2,zero,21c - 200: d0a0e617 ldw r2,-31848(gp) + 200: d0a0e317 ldw r2,-31860(gp) 204: e0ffff17 ldw r3,-4(fp) 208: e1bffe17 ldw r6,-8(fp) 20c: e17ffd17 ldw r5,-12(fp) @@ -549,9108 +557,11223 @@ Disassembly of section .text: 248: 06c00074 movhi sp,1 24c: dee1a814 ori sp,sp,34464 250: 06800074 movhi gp,1 - 254: d6866b14 ori gp,gp,6572 + 254: d68f9314 ori gp,gp,15948 258: 00800034 movhi r2,0 - 25c: 10a74714 ori r2,r2,40220 + 25c: 10b06b14 ori r2,r2,49580 260: 00c00034 movhi r3,0 - 264: 18eb9814 ori r3,r3,44640 + 264: 18f4b814 ori r3,r3,53984 268: 10c00326 beq r2,r3,278 <_start+0x40> 26c: 10000015 stw zero,0(r2) 270: 10800104 addi r2,r2,4 274: 10fffd36 bltu r2,r3,26c <_start+0x34> - 278: 00053b80 call 53b8 - 27c: 000543c0 call 543c + 278: 000749c0 call 749c + 27c: 00075200 call 7520 00000280 : 280: 003fff06 br 280 00000284 : - 284: deffe304 addi sp,sp,-116 - 288: dfc01c15 stw ra,112(sp) - 28c: df001b15 stw fp,108(sp) - 290: dcc01a15 stw r19,104(sp) - 294: dc801915 stw r18,100(sp) - 298: dc401815 stw r17,96(sp) - 29c: dc001715 stw r16,92(sp) - 2a0: df001b04 addi fp,sp,108 + 284: deffe204 addi sp,sp,-120 + 288: dfc01d15 stw ra,116(sp) + 28c: df001c15 stw fp,112(sp) + 290: dcc01b15 stw r19,108(sp) + 294: dc801a15 stw r18,104(sp) + 298: dc401915 stw r17,100(sp) + 29c: dc001815 stw r16,96(sp) + 2a0: df001c04 addi fp,sp,112 2a4: e13fe515 stw r4,-108(fp) - 2a8: 01000074 movhi r4,1 - 2ac: 2122fa04 addi r4,r4,-29720 - 2b0: 0004bcc0 call 4bcc - 2b4: 00800074 movhi r2,1 - 2b8: 10a75804 addi r2,r2,-25248 - 2bc: e0bff315 stw r2,-52(fp) - 2c0: 00a20034 movhi r2,34816 - 2c4: e0bff215 stw r2,-56(fp) - 2c8: e0fff317 ldw r3,-52(fp) - 2cc: 00a00034 movhi r2,32768 - 2d0: 10bfffc4 addi r2,r2,-1 - 2d4: 1884703a and r2,r3,r2 - 2d8: e0bff115 stw r2,-60(fp) - 2dc: e03ffb15 stw zero,-20(fp) - 2e0: 00001106 br 328 - 2e4: e0fffb17 ldw r3,-20(fp) - 2e8: 00844474 movhi r2,4369 - 2ec: 1889883a add r4,r3,r2 - 2f0: e0bffb17 ldw r2,-20(fp) - 2f4: 100490ba slli r2,r2,2 - 2f8: e0fff317 ldw r3,-52(fp) - 2fc: 1885883a add r2,r3,r2 - 300: 2007883a mov r3,r4 - 304: 10c00015 stw r3,0(r2) - 308: e0bffb17 ldw r2,-20(fp) - 30c: 100490ba slli r2,r2,2 - 310: e0fff217 ldw r3,-56(fp) - 314: 1885883a add r2,r3,r2 - 318: 10000015 stw zero,0(r2) - 31c: e0bffb17 ldw r2,-20(fp) - 320: 10800044 addi r2,r2,1 - 324: e0bffb15 stw r2,-20(fp) - 328: e0bffb17 ldw r2,-20(fp) - 32c: 10810010 cmplti r2,r2,1024 - 330: 103fec1e bne r2,zero,2e4 - 334: 00053040 call 5304 - 338: 01000074 movhi r4,1 - 33c: 21230704 addi r4,r4,-29668 - 340: 0004ae40 call 4ae4 - 344: 0000c040 call c04 - 348: e0bfef15 stw r2,-68(fp) - 34c: e0fff015 stw r3,-64(fp) - 350: e03ffa15 stw zero,-24(fp) - 354: 00001506 br 3ac - 358: e03ff915 stw zero,-28(fp) - 35c: 00000d06 br 394 - 360: e0bff917 ldw r2,-28(fp) - 364: 100490ba slli r2,r2,2 - 368: e0fff317 ldw r3,-52(fp) - 36c: 1887883a add r3,r3,r2 - 370: e0bff917 ldw r2,-28(fp) - 374: 100490ba slli r2,r2,2 - 378: e13ff217 ldw r4,-56(fp) - 37c: 2085883a add r2,r4,r2 - 380: 18c00017 ldw r3,0(r3) - 384: 10c00015 stw r3,0(r2) - 388: e0bff917 ldw r2,-28(fp) - 38c: 10800044 addi r2,r2,1 - 390: e0bff915 stw r2,-28(fp) - 394: e0bff917 ldw r2,-28(fp) - 398: 10810010 cmplti r2,r2,1024 - 39c: 103ff01e bne r2,zero,360 - 3a0: e0bffa17 ldw r2,-24(fp) - 3a4: 10800044 addi r2,r2,1 - 3a8: e0bffa15 stw r2,-24(fp) - 3ac: e0bffa17 ldw r2,-24(fp) - 3b0: 10801910 cmplti r2,r2,100 - 3b4: 103fe81e bne r2,zero,358 - 3b8: 0000c040 call c04 - 3bc: e0bfed15 stw r2,-76(fp) - 3c0: e0ffee15 stw r3,-72(fp) - 3c4: e0ffed17 ldw r3,-76(fp) - 3c8: e0bfef17 ldw r2,-68(fp) - 3cc: 1885c83a sub r2,r3,r2 - 3d0: e0bff815 stw r2,-32(fp) - 3d4: e0bff817 ldw r2,-32(fp) - 3d8: 1000021e bne r2,zero,3e4 - 3dc: 00800044 movi r2,1 - 3e0: e0bff815 stw r2,-32(fp) - 3e4: e0bff817 ldw r2,-32(fp) - 3e8: 1025883a mov r18,r2 - 3ec: 0027883a mov r19,zero - 3f0: 900d883a mov r6,r18 - 3f4: 980f883a mov r7,r19 - 3f8: 0102e934 movhi r4,2980 - 3fc: 210edd04 addi r4,r4,15220 - 400: 000b883a mov r5,zero - 404: 0002d7c0 call 2d7c <__udivdi3> - 408: 1009883a mov r4,r2 - 40c: 180b883a mov r5,r3 - 410: 2005883a mov r2,r4 - 414: 2807883a mov r3,r5 - 418: e0bfec15 stw r2,-80(fp) - 41c: e0bfec17 ldw r2,-80(fp) - 420: 01400284 movi r5,10 - 424: 1009883a mov r4,r2 - 428: 00034000 call 3400 <__udivsi3> - 42c: 1025883a mov r18,r2 - 430: e0bfec17 ldw r2,-80(fp) - 434: 01400284 movi r5,10 - 438: 1009883a mov r4,r2 - 43c: 00034640 call 3464 <__umodsi3> - 440: 100f883a mov r7,r2 - 444: 900d883a mov r6,r18 - 448: e17ff817 ldw r5,-32(fp) - 44c: 01000074 movhi r4,1 - 450: 21231004 addi r4,r4,-29632 - 454: 0004ae40 call 4ae4 - 458: 00053040 call 5304 - 45c: 01000074 movhi r4,1 - 460: 21231804 addi r4,r4,-29600 - 464: 0004ae40 call 4ae4 - 468: 0000c040 call c04 - 46c: e0bfea15 stw r2,-88(fp) - 470: e0ffeb15 stw r3,-84(fp) - 474: 00880034 movhi r2,8192 - 478: e0bfe915 stw r2,-92(fp) - 47c: e03ff715 stw zero,-36(fp) - 480: 00002a06 br 52c - 484: e0bfe517 ldw r2,-108(fp) - 488: 10800204 addi r2,r2,8 - 48c: 1007883a mov r3,r2 - 490: e0bff117 ldw r2,-60(fp) - 494: 18800035 stwio r2,0(r3) - 498: e0bfe517 ldw r2,-108(fp) - 49c: 10800304 addi r2,r2,12 - 4a0: 1007883a mov r3,r2 - 4a4: e0bfe917 ldw r2,-92(fp) - 4a8: 18800035 stwio r2,0(r3) - 4ac: e0bfe517 ldw r2,-108(fp) - 4b0: 10800404 addi r2,r2,16 - 4b4: 1007883a mov r3,r2 - 4b8: 00840004 movi r2,4096 - 4bc: 18800035 stwio r2,0(r3) - 4c0: e0bfe517 ldw r2,-108(fp) - 4c4: 10800504 addi r2,r2,20 - 4c8: 1007883a mov r3,r2 - 4cc: 00800804 movi r2,32 - 4d0: 18800035 stwio r2,0(r3) - 4d4: e0bfe517 ldw r2,-108(fp) - 4d8: 10800604 addi r2,r2,24 - 4dc: 1007883a mov r3,r2 - 4e0: 00800804 movi r2,32 - 4e4: 18800035 stwio r2,0(r3) - 4e8: e0bfe517 ldw r2,-108(fp) - 4ec: 00c00044 movi r3,1 - 4f0: 10c00035 stwio r3,0(r2) - 4f4: 0001883a nop - 4f8: e0bfe517 ldw r2,-108(fp) - 4fc: 10800104 addi r2,r2,4 - 500: 10800037 ldwio r2,0(r2) - 504: 1080004c andi r2,r2,1 - 508: 103ffb26 beq r2,zero,4f8 - 50c: e0bfe517 ldw r2,-108(fp) - 510: 10800104 addi r2,r2,4 - 514: 1007883a mov r3,r2 - 518: 00800044 movi r2,1 - 51c: 18800035 stwio r2,0(r3) - 520: e0bff717 ldw r2,-36(fp) - 524: 10800044 addi r2,r2,1 - 528: e0bff715 stw r2,-36(fp) - 52c: e0bff717 ldw r2,-36(fp) - 530: 10801910 cmplti r2,r2,100 - 534: 103fd31e bne r2,zero,484 - 538: 0000c040 call c04 - 53c: e0bfe715 stw r2,-100(fp) - 540: e0ffe815 stw r3,-96(fp) - 544: e0ffe717 ldw r3,-100(fp) - 548: e0bfea17 ldw r2,-88(fp) - 54c: 1885c83a sub r2,r3,r2 - 550: e0bff615 stw r2,-40(fp) - 554: e0bff617 ldw r2,-40(fp) - 558: 1000021e bne r2,zero,564 - 55c: 00800044 movi r2,1 - 560: e0bff615 stw r2,-40(fp) - 564: e0bff617 ldw r2,-40(fp) - 568: 1021883a mov r16,r2 - 56c: 0023883a mov r17,zero - 570: 800d883a mov r6,r16 - 574: 880f883a mov r7,r17 - 578: 0102e934 movhi r4,2980 - 57c: 210edd04 addi r4,r4,15220 - 580: 000b883a mov r5,zero - 584: 0002d7c0 call 2d7c <__udivdi3> - 588: 1009883a mov r4,r2 - 58c: 180b883a mov r5,r3 - 590: 2005883a mov r2,r4 - 594: 2807883a mov r3,r5 - 598: e0bfe615 stw r2,-104(fp) - 59c: e0bfe617 ldw r2,-104(fp) - 5a0: 01400284 movi r5,10 - 5a4: 1009883a mov r4,r2 - 5a8: 00034000 call 3400 <__udivsi3> - 5ac: 1021883a mov r16,r2 - 5b0: e0bfe617 ldw r2,-104(fp) - 5b4: 01400284 movi r5,10 - 5b8: 1009883a mov r4,r2 - 5bc: 00034640 call 3464 <__umodsi3> - 5c0: 100f883a mov r7,r2 - 5c4: 800d883a mov r6,r16 - 5c8: e17ff617 ldw r5,-40(fp) - 5cc: 01000074 movhi r4,1 - 5d0: 21231004 addi r4,r4,-29632 - 5d4: 0004ae40 call 4ae4 - 5d8: e17ff617 ldw r5,-40(fp) - 5dc: e13ff817 ldw r4,-32(fp) - 5e0: 00034000 call 3400 <__udivsi3> - 5e4: 100b883a mov r5,r2 - 5e8: 01000074 movhi r4,1 - 5ec: 21232004 addi r4,r4,-29568 - 5f0: 0004ae40 call 4ae4 - 5f4: 00053040 call 5304 - 5f8: e03ff515 stw zero,-44(fp) - 5fc: e03ff415 stw zero,-48(fp) - 600: 00000f06 br 640 - 604: e0bff417 ldw r2,-48(fp) - 608: 100490ba slli r2,r2,2 - 60c: e0fff217 ldw r3,-56(fp) - 610: 1885883a add r2,r3,r2 - 614: 10800017 ldw r2,0(r2) - 618: e13ff417 ldw r4,-48(fp) - 61c: 00c44474 movhi r3,4369 - 620: 20c7883a add r3,r4,r3 - 624: 10c00326 beq r2,r3,634 - 628: e0bff517 ldw r2,-44(fp) - 62c: 10800044 addi r2,r2,1 - 630: e0bff515 stw r2,-44(fp) - 634: e0bff417 ldw r2,-48(fp) - 638: 10800044 addi r2,r2,1 - 63c: e0bff415 stw r2,-48(fp) - 640: e0bff417 ldw r2,-48(fp) - 644: 10810010 cmplti r2,r2,1024 - 648: 103fee1e bne r2,zero,604 - 64c: e0bff517 ldw r2,-44(fp) - 650: 1000041e bne r2,zero,664 - 654: 01000074 movhi r4,1 - 658: 21232404 addi r4,r4,-29552 - 65c: 0004bcc0 call 4bcc - 660: 00000406 br 674 - 664: e17ff517 ldw r5,-44(fp) - 668: 01000074 movhi r4,1 - 66c: 21232c04 addi r4,r4,-29520 - 670: 0004ae40 call 4ae4 - 674: 0001883a nop - 678: e6fffc04 addi sp,fp,-16 - 67c: dfc00517 ldw ra,20(sp) - 680: df000417 ldw fp,16(sp) - 684: dcc00317 ldw r19,12(sp) - 688: dc800217 ldw r18,8(sp) - 68c: dc400117 ldw r17,4(sp) - 690: dc000017 ldw r16,0(sp) - 694: dec00604 addi sp,sp,24 - 698: f800283a ret - -0000069c : - 69c: deffdc04 addi sp,sp,-144 - 6a0: dfc02315 stw ra,140(sp) - 6a4: df002215 stw fp,136(sp) - 6a8: ddc02115 stw r23,132(sp) - 6ac: dd802015 stw r22,128(sp) - 6b0: dd401f15 stw r21,124(sp) - 6b4: dd001e15 stw r20,120(sp) - 6b8: dcc01d15 stw r19,116(sp) - 6bc: dc801c15 stw r18,112(sp) - 6c0: dc401b15 stw r17,108(sp) - 6c4: dc001a15 stw r16,104(sp) - 6c8: df002204 addi fp,sp,136 - 6cc: e13fde15 stw r4,-136(fp) - 6d0: 01000074 movhi r4,1 - 6d4: 21233504 addi r4,r4,-29484 - 6d8: 0004bcc0 call 4bcc - 6dc: 01000074 movhi r4,1 - 6e0: 21234204 addi r4,r4,-29432 - 6e4: 0004bcc0 call 4bcc - 6e8: 00804034 movhi r2,256 - 6ec: e0bff115 stw r2,-60(fp) - 6f0: 00808034 movhi r2,512 - 6f4: e0bff015 stw r2,-64(fp) - 6f8: 0080c034 movhi r2,768 - 6fc: e0bfef15 stw r2,-68(fp) - 700: e0fff117 ldw r3,-60(fp) - 704: 00a20034 movhi r2,34816 - 708: 1885883a add r2,r3,r2 - 70c: e0bfee15 stw r2,-72(fp) - 710: e0fff017 ldw r3,-64(fp) - 714: 00a20034 movhi r2,34816 - 718: 1885883a add r2,r3,r2 - 71c: e0bfed15 stw r2,-76(fp) - 720: e0ffef17 ldw r3,-68(fp) - 724: 00a20034 movhi r2,34816 - 728: 1885883a add r2,r3,r2 - 72c: e0bfec15 stw r2,-80(fp) - 730: e03ff715 stw zero,-36(fp) - 734: 00001506 br 78c - 738: e0bff717 ldw r2,-36(fp) - 73c: 1100ffc4 addi r4,r2,1023 + 2a8: e17fe415 stw r5,-112(fp) + 2ac: 01000074 movhi r4,1 + 2b0: 212b3304 addi r4,r4,-21300 + 2b4: 0006cb00 call 6cb0 + 2b8: 00800074 movhi r2,1 + 2bc: 10b07804 addi r2,r2,-15904 + 2c0: e0bff315 stw r2,-52(fp) + 2c4: 00a20034 movhi r2,34816 + 2c8: e0bff215 stw r2,-56(fp) + 2cc: e0fff317 ldw r3,-52(fp) + 2d0: 00a00034 movhi r2,32768 + 2d4: 10bfffc4 addi r2,r2,-1 + 2d8: 1884703a and r2,r3,r2 + 2dc: e0bff115 stw r2,-60(fp) + 2e0: e03ffb15 stw zero,-20(fp) + 2e4: 00001106 br 32c + 2e8: e0fffb17 ldw r3,-20(fp) + 2ec: 00844474 movhi r2,4369 + 2f0: 1889883a add r4,r3,r2 + 2f4: e0bffb17 ldw r2,-20(fp) + 2f8: 100490ba slli r2,r2,2 + 2fc: e0fff317 ldw r3,-52(fp) + 300: 1885883a add r2,r3,r2 + 304: 2007883a mov r3,r4 + 308: 10c00015 stw r3,0(r2) + 30c: e0bffb17 ldw r2,-20(fp) + 310: 100490ba slli r2,r2,2 + 314: e0fff217 ldw r3,-56(fp) + 318: 1885883a add r2,r3,r2 + 31c: 10000015 stw zero,0(r2) + 320: e0bffb17 ldw r2,-20(fp) + 324: 10800044 addi r2,r2,1 + 328: e0bffb15 stw r2,-20(fp) + 32c: e0bffb17 ldw r2,-20(fp) + 330: 10810010 cmplti r2,r2,1024 + 334: 103fec1e bne r2,zero,2e8 + 338: 00073e80 call 73e8 + 33c: 01000074 movhi r4,1 + 340: 212b4004 addi r4,r4,-21248 + 344: 0006bc80 call 6bc8 + 348: 0000c0c0 call c0c + 34c: e0bfef15 stw r2,-68(fp) + 350: e0fff015 stw r3,-64(fp) + 354: e03ffa15 stw zero,-24(fp) + 358: 00001506 br 3b0 + 35c: e03ff915 stw zero,-28(fp) + 360: 00000d06 br 398 + 364: e0bff917 ldw r2,-28(fp) + 368: 100490ba slli r2,r2,2 + 36c: e0fff317 ldw r3,-52(fp) + 370: 1887883a add r3,r3,r2 + 374: e0bff917 ldw r2,-28(fp) + 378: 100490ba slli r2,r2,2 + 37c: e13ff217 ldw r4,-56(fp) + 380: 2085883a add r2,r4,r2 + 384: 18c00017 ldw r3,0(r3) + 388: 10c00015 stw r3,0(r2) + 38c: e0bff917 ldw r2,-28(fp) + 390: 10800044 addi r2,r2,1 + 394: e0bff915 stw r2,-28(fp) + 398: e0bff917 ldw r2,-28(fp) + 39c: 10810010 cmplti r2,r2,1024 + 3a0: 103ff01e bne r2,zero,364 + 3a4: e0bffa17 ldw r2,-24(fp) + 3a8: 10800044 addi r2,r2,1 + 3ac: e0bffa15 stw r2,-24(fp) + 3b0: e0bffa17 ldw r2,-24(fp) + 3b4: 10801910 cmplti r2,r2,100 + 3b8: 103fe81e bne r2,zero,35c + 3bc: 0000c0c0 call c0c + 3c0: e0bfed15 stw r2,-76(fp) + 3c4: e0ffee15 stw r3,-72(fp) + 3c8: e0ffed17 ldw r3,-76(fp) + 3cc: e0bfef17 ldw r2,-68(fp) + 3d0: 1885c83a sub r2,r3,r2 + 3d4: e0bff815 stw r2,-32(fp) + 3d8: e0bff817 ldw r2,-32(fp) + 3dc: 1000021e bne r2,zero,3e8 + 3e0: 00800044 movi r2,1 + 3e4: e0bff815 stw r2,-32(fp) + 3e8: e0bff817 ldw r2,-32(fp) + 3ec: 1025883a mov r18,r2 + 3f0: 0027883a mov r19,zero + 3f4: 900d883a mov r6,r18 + 3f8: 980f883a mov r7,r19 + 3fc: 0102e934 movhi r4,2980 + 400: 210edd04 addi r4,r4,15220 + 404: 000b883a mov r5,zero + 408: 0003dc00 call 3dc0 <__udivdi3> + 40c: 1009883a mov r4,r2 + 410: 180b883a mov r5,r3 + 414: 2005883a mov r2,r4 + 418: 2807883a mov r3,r5 + 41c: e0bfec15 stw r2,-80(fp) + 420: e0bfec17 ldw r2,-80(fp) + 424: 01400284 movi r5,10 + 428: 1009883a mov r4,r2 + 42c: 00044440 call 4444 <__udivsi3> + 430: 1025883a mov r18,r2 + 434: e0bfec17 ldw r2,-80(fp) + 438: 01400284 movi r5,10 + 43c: 1009883a mov r4,r2 + 440: 00044a80 call 44a8 <__umodsi3> + 444: 100f883a mov r7,r2 + 448: 900d883a mov r6,r18 + 44c: e17ff817 ldw r5,-32(fp) + 450: 01000074 movhi r4,1 + 454: 212b4904 addi r4,r4,-21212 + 458: 0006bc80 call 6bc8 + 45c: 00073e80 call 73e8 + 460: 01000074 movhi r4,1 + 464: 212b5104 addi r4,r4,-21180 + 468: 0006bc80 call 6bc8 + 46c: 0000c0c0 call c0c + 470: e0bfea15 stw r2,-88(fp) + 474: e0ffeb15 stw r3,-84(fp) + 478: 008c0034 movhi r2,12288 + 47c: e0bfe915 stw r2,-92(fp) + 480: e03ff715 stw zero,-36(fp) + 484: 00002a06 br 530 + 488: e0bfe517 ldw r2,-108(fp) + 48c: 10800204 addi r2,r2,8 + 490: 1007883a mov r3,r2 + 494: e0bff117 ldw r2,-60(fp) + 498: 18800035 stwio r2,0(r3) + 49c: e0bfe517 ldw r2,-108(fp) + 4a0: 10800304 addi r2,r2,12 + 4a4: 1007883a mov r3,r2 + 4a8: e0bfe917 ldw r2,-92(fp) + 4ac: 18800035 stwio r2,0(r3) + 4b0: e0bfe517 ldw r2,-108(fp) + 4b4: 10800404 addi r2,r2,16 + 4b8: 1007883a mov r3,r2 + 4bc: 00840004 movi r2,4096 + 4c0: 18800035 stwio r2,0(r3) + 4c4: e0bfe517 ldw r2,-108(fp) + 4c8: 10800504 addi r2,r2,20 + 4cc: 1007883a mov r3,r2 + 4d0: 00800804 movi r2,32 + 4d4: 18800035 stwio r2,0(r3) + 4d8: e0bfe517 ldw r2,-108(fp) + 4dc: 10800604 addi r2,r2,24 + 4e0: 1007883a mov r3,r2 + 4e4: 00800804 movi r2,32 + 4e8: 18800035 stwio r2,0(r3) + 4ec: e0bfe517 ldw r2,-108(fp) + 4f0: 00c00044 movi r3,1 + 4f4: 10c00035 stwio r3,0(r2) + 4f8: 0001883a nop + 4fc: e0bfe517 ldw r2,-108(fp) + 500: 10800104 addi r2,r2,4 + 504: 10800037 ldwio r2,0(r2) + 508: 1080004c andi r2,r2,1 + 50c: 103ffb26 beq r2,zero,4fc + 510: e0bfe517 ldw r2,-108(fp) + 514: 10800104 addi r2,r2,4 + 518: 1007883a mov r3,r2 + 51c: 00800044 movi r2,1 + 520: 18800035 stwio r2,0(r3) + 524: e0bff717 ldw r2,-36(fp) + 528: 10800044 addi r2,r2,1 + 52c: e0bff715 stw r2,-36(fp) + 530: e0bff717 ldw r2,-36(fp) + 534: 10801910 cmplti r2,r2,100 + 538: 103fd31e bne r2,zero,488 + 53c: 0000c0c0 call c0c + 540: e0bfe715 stw r2,-100(fp) + 544: e0ffe815 stw r3,-96(fp) + 548: e0ffe717 ldw r3,-100(fp) + 54c: e0bfea17 ldw r2,-88(fp) + 550: 1885c83a sub r2,r3,r2 + 554: e0bff615 stw r2,-40(fp) + 558: e0bff617 ldw r2,-40(fp) + 55c: 1000021e bne r2,zero,568 + 560: 00800044 movi r2,1 + 564: e0bff615 stw r2,-40(fp) + 568: e0bff617 ldw r2,-40(fp) + 56c: 1021883a mov r16,r2 + 570: 0023883a mov r17,zero + 574: 800d883a mov r6,r16 + 578: 880f883a mov r7,r17 + 57c: 0102e934 movhi r4,2980 + 580: 210edd04 addi r4,r4,15220 + 584: 000b883a mov r5,zero + 588: 0003dc00 call 3dc0 <__udivdi3> + 58c: 1009883a mov r4,r2 + 590: 180b883a mov r5,r3 + 594: 2005883a mov r2,r4 + 598: 2807883a mov r3,r5 + 59c: e0bfe615 stw r2,-104(fp) + 5a0: e0bfe617 ldw r2,-104(fp) + 5a4: 01400284 movi r5,10 + 5a8: 1009883a mov r4,r2 + 5ac: 00044440 call 4444 <__udivsi3> + 5b0: 1021883a mov r16,r2 + 5b4: e0bfe617 ldw r2,-104(fp) + 5b8: 01400284 movi r5,10 + 5bc: 1009883a mov r4,r2 + 5c0: 00044a80 call 44a8 <__umodsi3> + 5c4: 100f883a mov r7,r2 + 5c8: 800d883a mov r6,r16 + 5cc: e17ff617 ldw r5,-40(fp) + 5d0: 01000074 movhi r4,1 + 5d4: 212b4904 addi r4,r4,-21212 + 5d8: 0006bc80 call 6bc8 + 5dc: e17ff617 ldw r5,-40(fp) + 5e0: e13ff817 ldw r4,-32(fp) + 5e4: 00044440 call 4444 <__udivsi3> + 5e8: 100b883a mov r5,r2 + 5ec: 01000074 movhi r4,1 + 5f0: 212b5904 addi r4,r4,-21148 + 5f4: 0006bc80 call 6bc8 + 5f8: 00073e80 call 73e8 + 5fc: e03ff515 stw zero,-44(fp) + 600: e03ff415 stw zero,-48(fp) + 604: 00000f06 br 644 + 608: e0bff417 ldw r2,-48(fp) + 60c: 100490ba slli r2,r2,2 + 610: e0fff217 ldw r3,-56(fp) + 614: 1885883a add r2,r3,r2 + 618: 10800017 ldw r2,0(r2) + 61c: e13ff417 ldw r4,-48(fp) + 620: 00c44474 movhi r3,4369 + 624: 20c7883a add r3,r4,r3 + 628: 10c00326 beq r2,r3,638 + 62c: e0bff517 ldw r2,-44(fp) + 630: 10800044 addi r2,r2,1 + 634: e0bff515 stw r2,-44(fp) + 638: e0bff417 ldw r2,-48(fp) + 63c: 10800044 addi r2,r2,1 + 640: e0bff415 stw r2,-48(fp) + 644: e0bff417 ldw r2,-48(fp) + 648: 10810010 cmplti r2,r2,1024 + 64c: 103fee1e bne r2,zero,608 + 650: e0bff517 ldw r2,-44(fp) + 654: 1000041e bne r2,zero,668 + 658: 01000074 movhi r4,1 + 65c: 212b5d04 addi r4,r4,-21132 + 660: 0006cb00 call 6cb0 + 664: 00000406 br 678 + 668: e17ff517 ldw r5,-44(fp) + 66c: 01000074 movhi r4,1 + 670: 212b6504 addi r4,r4,-21100 + 674: 0006bc80 call 6bc8 + 678: 0001883a nop + 67c: e6fffc04 addi sp,fp,-16 + 680: dfc00517 ldw ra,20(sp) + 684: df000417 ldw fp,16(sp) + 688: dcc00317 ldw r19,12(sp) + 68c: dc800217 ldw r18,8(sp) + 690: dc400117 ldw r17,4(sp) + 694: dc000017 ldw r16,0(sp) + 698: dec00604 addi sp,sp,24 + 69c: f800283a ret + +000006a0 : + 6a0: deffdb04 addi sp,sp,-148 + 6a4: dfc02415 stw ra,144(sp) + 6a8: df002315 stw fp,140(sp) + 6ac: ddc02215 stw r23,136(sp) + 6b0: dd802115 stw r22,132(sp) + 6b4: dd402015 stw r21,128(sp) + 6b8: dd001f15 stw r20,124(sp) + 6bc: dcc01e15 stw r19,120(sp) + 6c0: dc801d15 stw r18,116(sp) + 6c4: dc401c15 stw r17,112(sp) + 6c8: dc001b15 stw r16,108(sp) + 6cc: df002304 addi fp,sp,140 + 6d0: e13fde15 stw r4,-136(fp) + 6d4: e17fdd15 stw r5,-140(fp) + 6d8: 01000074 movhi r4,1 + 6dc: 212b6e04 addi r4,r4,-21064 + 6e0: 0006cb00 call 6cb0 + 6e4: 01000074 movhi r4,1 + 6e8: 212b7b04 addi r4,r4,-21012 + 6ec: 0006cb00 call 6cb0 + 6f0: 00804034 movhi r2,256 + 6f4: e0bff115 stw r2,-60(fp) + 6f8: 00808034 movhi r2,512 + 6fc: e0bff015 stw r2,-64(fp) + 700: 0080c034 movhi r2,768 + 704: e0bfef15 stw r2,-68(fp) + 708: e0fff117 ldw r3,-60(fp) + 70c: 00a20034 movhi r2,34816 + 710: 1885883a add r2,r3,r2 + 714: e0bfee15 stw r2,-72(fp) + 718: e0fff017 ldw r3,-64(fp) + 71c: 00a20034 movhi r2,34816 + 720: 1885883a add r2,r3,r2 + 724: e0bfed15 stw r2,-76(fp) + 728: e0ffef17 ldw r3,-68(fp) + 72c: 00a20034 movhi r2,34816 + 730: 1885883a add r2,r3,r2 + 734: e0bfec15 stw r2,-80(fp) + 738: e03ff715 stw zero,-36(fp) + 73c: 00001506 br 794 740: e0bff717 ldw r2,-36(fp) - 744: 100490ba slli r2,r2,2 - 748: e0ffee17 ldw r3,-72(fp) - 74c: 1885883a add r2,r3,r2 - 750: 2007883a mov r3,r4 - 754: 10c00015 stw r3,0(r2) - 758: e0bff717 ldw r2,-36(fp) - 75c: 100490ba slli r2,r2,2 - 760: e0ffed17 ldw r3,-76(fp) - 764: 1885883a add r2,r3,r2 - 768: 10000015 stw zero,0(r2) - 76c: e0bff717 ldw r2,-36(fp) - 770: 100490ba slli r2,r2,2 - 774: e0ffec17 ldw r3,-80(fp) - 778: 1885883a add r2,r3,r2 - 77c: 10000015 stw zero,0(r2) - 780: e0bff717 ldw r2,-36(fp) - 784: 10800044 addi r2,r2,1 - 788: e0bff715 stw r2,-36(fp) - 78c: e0fff717 ldw r3,-36(fp) - 790: 00800134 movhi r2,4 - 794: 18bfe816 blt r3,r2,738 - 798: 00053040 call 5304 - 79c: 0080c804 movi r2,800 - 7a0: e0bfeb15 stw r2,-84(fp) - 7a4: 01000074 movhi r4,1 - 7a8: 21234704 addi r4,r4,-29412 - 7ac: 0004ae40 call 4ae4 - 7b0: 0000c040 call c04 - 7b4: e0bfe915 stw r2,-92(fp) - 7b8: e0ffea15 stw r3,-88(fp) - 7bc: e03ff615 stw zero,-40(fp) - 7c0: 00002406 br 854 - 7c4: e0bff617 ldw r2,-40(fp) - 7c8: 100490ba slli r2,r2,2 - 7cc: e0ffee17 ldw r3,-72(fp) - 7d0: 1885883a add r2,r3,r2 - 7d4: 10800017 ldw r2,0(r2) - 7d8: 1029883a mov r20,r2 - 7dc: 002b883a mov r21,zero - 7e0: e0bfeb17 ldw r2,-84(fp) - 7e4: 102d883a mov r22,r2 - 7e8: 002f883a mov r23,zero - 7ec: b00d883a mov r6,r22 - 7f0: b80f883a mov r7,r23 - 7f4: a009883a mov r4,r20 - 7f8: a80b883a mov r5,r21 - 7fc: 0002cbc0 call 2cbc <__muldi3> - 800: 1009883a mov r4,r2 - 804: 180b883a mov r5,r3 - 808: 2005883a mov r2,r4 - 80c: 2807883a mov r3,r5 - 810: 01806404 movi r6,400 - 814: 000f883a mov r7,zero - 818: 1009883a mov r4,r2 - 81c: 180b883a mov r5,r3 - 820: 0002d7c0 call 2d7c <__udivdi3> - 824: 1009883a mov r4,r2 - 828: 180b883a mov r5,r3 - 82c: 2005883a mov r2,r4 - 830: 2807883a mov r3,r5 - 834: e13ff617 ldw r4,-40(fp) - 838: 200890ba slli r4,r4,2 - 83c: e17fed17 ldw r5,-76(fp) - 840: 2909883a add r4,r5,r4 - 844: 20800015 stw r2,0(r4) - 848: e0bff617 ldw r2,-40(fp) - 84c: 10800044 addi r2,r2,1 - 850: e0bff615 stw r2,-40(fp) - 854: e0fff617 ldw r3,-40(fp) - 858: 00800134 movhi r2,4 - 85c: 18bfd916 blt r3,r2,7c4 - 860: 0000c040 call c04 - 864: e0bfe715 stw r2,-100(fp) - 868: e0ffe815 stw r3,-96(fp) - 86c: e0ffe717 ldw r3,-100(fp) - 870: e0bfe917 ldw r2,-92(fp) - 874: 1885c83a sub r2,r3,r2 - 878: e0bff515 stw r2,-44(fp) - 87c: e0bff517 ldw r2,-44(fp) - 880: 1000021e bne r2,zero,88c - 884: 00800044 movi r2,1 - 888: e0bff515 stw r2,-44(fp) - 88c: e0bff517 ldw r2,-44(fp) - 890: 1025883a mov r18,r2 - 894: 0027883a mov r19,zero - 898: 900d883a mov r6,r18 - 89c: 980f883a mov r7,r19 - 8a0: 01077374 movhi r4,7629 - 8a4: 21194004 addi r4,r4,25856 - 8a8: 000b883a mov r5,zero - 8ac: 0002d7c0 call 2d7c <__udivdi3> - 8b0: 1009883a mov r4,r2 - 8b4: 180b883a mov r5,r3 - 8b8: 2005883a mov r2,r4 - 8bc: 2807883a mov r3,r5 - 8c0: e0bfe615 stw r2,-104(fp) - 8c4: e0bfe617 ldw r2,-104(fp) - 8c8: 01400284 movi r5,10 - 8cc: 1009883a mov r4,r2 - 8d0: 00034000 call 3400 <__udivsi3> - 8d4: 1025883a mov r18,r2 - 8d8: e0bfe617 ldw r2,-104(fp) - 8dc: 01400284 movi r5,10 - 8e0: 1009883a mov r4,r2 - 8e4: 00034640 call 3464 <__umodsi3> - 8e8: 100f883a mov r7,r2 - 8ec: 900d883a mov r6,r18 - 8f0: e17ff517 ldw r5,-44(fp) - 8f4: 01000074 movhi r4,1 - 8f8: 21231004 addi r4,r4,-29632 - 8fc: 0004ae40 call 4ae4 - 900: 00053040 call 5304 - 904: e0bfde17 ldw r2,-136(fp) - 908: 10800504 addi r2,r2,20 - 90c: 1007883a mov r3,r2 - 910: 00804004 movi r2,256 - 914: 18800035 stwio r2,0(r3) - 918: e0bfde17 ldw r2,-136(fp) - 91c: 10800604 addi r2,r2,24 - 920: 1007883a mov r3,r2 - 924: 00804004 movi r2,256 - 928: 18800035 stwio r2,0(r3) - 92c: e0bfde17 ldw r2,-136(fp) - 930: 10800704 addi r2,r2,28 - 934: 1007883a mov r3,r2 - 938: e0bfeb17 ldw r2,-84(fp) - 93c: 18800035 stwio r2,0(r3) - 940: 01000074 movhi r4,1 - 944: 21234e04 addi r4,r4,-29384 - 948: 0004ae40 call 4ae4 - 94c: 0000c040 call c04 - 950: e0bfe415 stw r2,-112(fp) - 954: e0ffe515 stw r3,-108(fp) - 958: 00880034 movhi r2,8192 - 95c: e0bfe315 stw r2,-116(fp) - 960: e0bfde17 ldw r2,-136(fp) - 964: 10800204 addi r2,r2,8 - 968: 1009883a mov r4,r2 - 96c: e0ffe317 ldw r3,-116(fp) - 970: e0bff117 ldw r2,-60(fp) - 974: 1885883a add r2,r3,r2 - 978: 20800035 stwio r2,0(r4) - 97c: e0bfde17 ldw r2,-136(fp) - 980: 10800304 addi r2,r2,12 - 984: 1009883a mov r4,r2 - 988: e0ffe317 ldw r3,-116(fp) - 98c: e0bfef17 ldw r2,-68(fp) - 990: 1885883a add r2,r3,r2 - 994: 20800035 stwio r2,0(r4) - 998: e0bfde17 ldw r2,-136(fp) - 99c: 10800404 addi r2,r2,16 - 9a0: 1007883a mov r3,r2 - 9a4: 00800434 movhi r2,16 - 9a8: 18800035 stwio r2,0(r3) - 9ac: e0bfde17 ldw r2,-136(fp) - 9b0: 00c00044 movi r3,1 - 9b4: 10c00035 stwio r3,0(r2) - 9b8: 0001883a nop - 9bc: e0bfde17 ldw r2,-136(fp) - 9c0: 10800104 addi r2,r2,4 - 9c4: 10800037 ldwio r2,0(r2) - 9c8: 1080004c andi r2,r2,1 - 9cc: 103ffb26 beq r2,zero,9bc - 9d0: e0bfde17 ldw r2,-136(fp) - 9d4: 10800104 addi r2,r2,4 - 9d8: 1007883a mov r3,r2 - 9dc: 00800044 movi r2,1 - 9e0: 18800035 stwio r2,0(r3) - 9e4: 0000c040 call c04 - 9e8: e0bfe115 stw r2,-124(fp) - 9ec: e0ffe215 stw r3,-120(fp) - 9f0: e0ffe117 ldw r3,-124(fp) - 9f4: e0bfe417 ldw r2,-112(fp) - 9f8: 1885c83a sub r2,r3,r2 - 9fc: e0bff415 stw r2,-48(fp) - a00: e0bff417 ldw r2,-48(fp) - a04: 1000021e bne r2,zero,a10 - a08: 00800044 movi r2,1 - a0c: e0bff415 stw r2,-48(fp) - a10: e0bff417 ldw r2,-48(fp) - a14: 1021883a mov r16,r2 - a18: 0023883a mov r17,zero - a1c: 800d883a mov r6,r16 - a20: 880f883a mov r7,r17 - a24: 01077374 movhi r4,7629 - a28: 21194004 addi r4,r4,25856 - a2c: 000b883a mov r5,zero - a30: 0002d7c0 call 2d7c <__udivdi3> - a34: 1009883a mov r4,r2 - a38: 180b883a mov r5,r3 - a3c: 2005883a mov r2,r4 - a40: 2807883a mov r3,r5 - a44: e0bfe015 stw r2,-128(fp) - a48: e0bfe017 ldw r2,-128(fp) - a4c: 01400284 movi r5,10 - a50: 1009883a mov r4,r2 - a54: 00034000 call 3400 <__udivsi3> - a58: 1021883a mov r16,r2 - a5c: e0bfe017 ldw r2,-128(fp) - a60: 01400284 movi r5,10 - a64: 1009883a mov r4,r2 - a68: 00034640 call 3464 <__umodsi3> - a6c: 100f883a mov r7,r2 - a70: 800d883a mov r6,r16 - a74: e17ff417 ldw r5,-48(fp) - a78: 01000074 movhi r4,1 - a7c: 21231004 addi r4,r4,-29632 - a80: 0004ae40 call 4ae4 - a84: e17ff417 ldw r5,-48(fp) - a88: e13ff517 ldw r4,-44(fp) - a8c: 00034000 call 3400 <__udivsi3> - a90: 100b883a mov r5,r2 - a94: 01000074 movhi r4,1 - a98: 21232004 addi r4,r4,-29568 - a9c: 0004ae40 call 4ae4 - aa0: 01000074 movhi r4,1 - aa4: 21235504 addi r4,r4,-29356 - aa8: 0004bcc0 call 4bcc - aac: e03ff315 stw zero,-52(fp) - ab0: e03ff215 stw zero,-56(fp) - ab4: 00001906 br b1c - ab8: e0bff217 ldw r2,-56(fp) - abc: 100490ba slli r2,r2,2 - ac0: e0ffec17 ldw r3,-80(fp) - ac4: 1885883a add r2,r3,r2 - ac8: 10800017 ldw r2,0(r2) - acc: 1009883a mov r4,r2 - ad0: e0bff217 ldw r2,-56(fp) - ad4: 100490ba slli r2,r2,2 - ad8: e0ffed17 ldw r3,-76(fp) - adc: 1885883a add r2,r3,r2 - ae0: 10800017 ldw r2,0(r2) - ae4: 2085c83a sub r2,r4,r2 - ae8: e0bfdf15 stw r2,-132(fp) - aec: e0bfdf17 ldw r2,-132(fp) - af0: 10800088 cmpgei r2,r2,2 - af4: 1000031e bne r2,zero,b04 - af8: e0bfdf17 ldw r2,-132(fp) - afc: 10bfffc8 cmpgei r2,r2,-1 - b00: 1000031e bne r2,zero,b10 - b04: e0bff317 ldw r2,-52(fp) - b08: 10800044 addi r2,r2,1 - b0c: e0bff315 stw r2,-52(fp) - b10: e0bff217 ldw r2,-56(fp) - b14: 10800044 addi r2,r2,1 - b18: e0bff215 stw r2,-56(fp) - b1c: e0bff217 ldw r2,-56(fp) - b20: 10810010 cmplti r2,r2,1024 - b24: 103fe41e bne r2,zero,ab8 - b28: e0bff317 ldw r2,-52(fp) - b2c: 1000051e bne r2,zero,b44 - b30: e17feb17 ldw r5,-84(fp) - b34: 01000074 movhi r4,1 - b38: 21235b04 addi r4,r4,-29332 - b3c: 0004ae40 call 4ae4 - b40: 00000406 br b54 - b44: e17ff317 ldw r5,-52(fp) - b48: 01000074 movhi r4,1 - b4c: 21236604 addi r4,r4,-29288 - b50: 0004ae40 call 4ae4 - b54: 0001883a nop - b58: e6fff804 addi sp,fp,-32 - b5c: dfc00917 ldw ra,36(sp) - b60: df000817 ldw fp,32(sp) - b64: ddc00717 ldw r23,28(sp) - b68: dd800617 ldw r22,24(sp) - b6c: dd400517 ldw r21,20(sp) - b70: dd000417 ldw r20,16(sp) - b74: dcc00317 ldw r19,12(sp) - b78: dc800217 ldw r18,8(sp) - b7c: dc400117 ldw r17,4(sp) - b80: dc000017 ldw r16,0(sp) - b84: dec00a04 addi sp,sp,40 - b88: f800283a ret - -00000b8c : - b8c: defffe04 addi sp,sp,-8 - b90: df000115 stw fp,4(sp) - b94: df000104 addi fp,sp,4 - b98: 008000b4 movhi r2,2 - b9c: 10800037 ldwio r2,0(r2) - ba0: e0bfff15 stw r2,-4(fp) - ba4: e0bfff17 ldw r2,-4(fp) - ba8: 10a0000c andi r2,r2,32768 - bac: 103ffa26 beq r2,zero,b98 - bb0: e0bfff17 ldw r2,-4(fp) - bb4: e037883a mov sp,fp - bb8: df000017 ldw fp,0(sp) - bbc: dec00104 addi sp,sp,4 - bc0: f800283a ret - -00000bc4 : - bc4: defffe04 addi sp,sp,-8 - bc8: df000115 stw fp,4(sp) - bcc: df000104 addi fp,sp,4 - bd0: 008000b4 movhi r2,2 - bd4: 10800037 ldwio r2,0(r2) - bd8: e0bfff15 stw r2,-4(fp) - bdc: e0bfff17 ldw r2,-4(fp) - be0: 10a0000c andi r2,r2,32768 - be4: 10000226 beq r2,zero,bf0 - be8: e0bfff17 ldw r2,-4(fp) - bec: 00000106 br bf4 - bf0: 0005883a mov r2,zero - bf4: e037883a mov sp,fp - bf8: df000017 ldw fp,0(sp) - bfc: dec00104 addi sp,sp,4 - c00: f800283a ret - -00000c04 : - c04: defff504 addi sp,sp,-44 - c08: dfc00a15 stw ra,40(sp) - c0c: df000915 stw fp,36(sp) - c10: dc400815 stw r17,32(sp) - c14: dc000715 stw r16,28(sp) - c18: df000904 addi fp,sp,36 - c1c: 01000074 movhi r4,1 - c20: 21274f17 ldw r4,-25284(r4) - c24: e13ffd15 stw r4,-12(fp) - c28: 000b883a mov r5,zero - c2c: 010000b4 movhi r4,2 - c30: 21402435 stwio r5,144(r4) + 744: 1100ffc4 addi r4,r2,1023 + 748: e0bff717 ldw r2,-36(fp) + 74c: 100490ba slli r2,r2,2 + 750: e0ffee17 ldw r3,-72(fp) + 754: 1885883a add r2,r3,r2 + 758: 2007883a mov r3,r4 + 75c: 10c00015 stw r3,0(r2) + 760: e0bff717 ldw r2,-36(fp) + 764: 100490ba slli r2,r2,2 + 768: e0ffed17 ldw r3,-76(fp) + 76c: 1885883a add r2,r3,r2 + 770: 10000015 stw zero,0(r2) + 774: e0bff717 ldw r2,-36(fp) + 778: 100490ba slli r2,r2,2 + 77c: e0ffec17 ldw r3,-80(fp) + 780: 1885883a add r2,r3,r2 + 784: 10000015 stw zero,0(r2) + 788: e0bff717 ldw r2,-36(fp) + 78c: 10800044 addi r2,r2,1 + 790: e0bff715 stw r2,-36(fp) + 794: e0fff717 ldw r3,-36(fp) + 798: 00800134 movhi r2,4 + 79c: 18bfe816 blt r3,r2,740 + 7a0: 00073e80 call 73e8 + 7a4: 0080c804 movi r2,800 + 7a8: e0bfeb15 stw r2,-84(fp) + 7ac: 01000074 movhi r4,1 + 7b0: 212b8004 addi r4,r4,-20992 + 7b4: 0006bc80 call 6bc8 + 7b8: 0000c0c0 call c0c + 7bc: e0bfe915 stw r2,-92(fp) + 7c0: e0ffea15 stw r3,-88(fp) + 7c4: e03ff615 stw zero,-40(fp) + 7c8: 00002406 br 85c + 7cc: e0bff617 ldw r2,-40(fp) + 7d0: 100490ba slli r2,r2,2 + 7d4: e0ffee17 ldw r3,-72(fp) + 7d8: 1885883a add r2,r3,r2 + 7dc: 10800017 ldw r2,0(r2) + 7e0: 1029883a mov r20,r2 + 7e4: 002b883a mov r21,zero + 7e8: e0bfeb17 ldw r2,-84(fp) + 7ec: 102d883a mov r22,r2 + 7f0: 002f883a mov r23,zero + 7f4: b00d883a mov r6,r22 + 7f8: b80f883a mov r7,r23 + 7fc: a009883a mov r4,r20 + 800: a80b883a mov r5,r21 + 804: 0003cec0 call 3cec <__muldi3> + 808: 1009883a mov r4,r2 + 80c: 180b883a mov r5,r3 + 810: 2005883a mov r2,r4 + 814: 2807883a mov r3,r5 + 818: 01806404 movi r6,400 + 81c: 000f883a mov r7,zero + 820: 1009883a mov r4,r2 + 824: 180b883a mov r5,r3 + 828: 0003dc00 call 3dc0 <__udivdi3> + 82c: 1009883a mov r4,r2 + 830: 180b883a mov r5,r3 + 834: 2005883a mov r2,r4 + 838: 2807883a mov r3,r5 + 83c: e13ff617 ldw r4,-40(fp) + 840: 200890ba slli r4,r4,2 + 844: e17fed17 ldw r5,-76(fp) + 848: 2909883a add r4,r5,r4 + 84c: 20800015 stw r2,0(r4) + 850: e0bff617 ldw r2,-40(fp) + 854: 10800044 addi r2,r2,1 + 858: e0bff615 stw r2,-40(fp) + 85c: e0fff617 ldw r3,-40(fp) + 860: 00800134 movhi r2,4 + 864: 18bfd916 blt r3,r2,7cc + 868: 0000c0c0 call c0c + 86c: e0bfe715 stw r2,-100(fp) + 870: e0ffe815 stw r3,-96(fp) + 874: e0ffe717 ldw r3,-100(fp) + 878: e0bfe917 ldw r2,-92(fp) + 87c: 1885c83a sub r2,r3,r2 + 880: e0bff515 stw r2,-44(fp) + 884: e0bff517 ldw r2,-44(fp) + 888: 1000021e bne r2,zero,894 + 88c: 00800044 movi r2,1 + 890: e0bff515 stw r2,-44(fp) + 894: e0bff517 ldw r2,-44(fp) + 898: 1025883a mov r18,r2 + 89c: 0027883a mov r19,zero + 8a0: 900d883a mov r6,r18 + 8a4: 980f883a mov r7,r19 + 8a8: 01077374 movhi r4,7629 + 8ac: 21194004 addi r4,r4,25856 + 8b0: 000b883a mov r5,zero + 8b4: 0003dc00 call 3dc0 <__udivdi3> + 8b8: 1009883a mov r4,r2 + 8bc: 180b883a mov r5,r3 + 8c0: 2005883a mov r2,r4 + 8c4: 2807883a mov r3,r5 + 8c8: e0bfe615 stw r2,-104(fp) + 8cc: e0bfe617 ldw r2,-104(fp) + 8d0: 01400284 movi r5,10 + 8d4: 1009883a mov r4,r2 + 8d8: 00044440 call 4444 <__udivsi3> + 8dc: 1025883a mov r18,r2 + 8e0: e0bfe617 ldw r2,-104(fp) + 8e4: 01400284 movi r5,10 + 8e8: 1009883a mov r4,r2 + 8ec: 00044a80 call 44a8 <__umodsi3> + 8f0: 100f883a mov r7,r2 + 8f4: 900d883a mov r6,r18 + 8f8: e17ff517 ldw r5,-44(fp) + 8fc: 01000074 movhi r4,1 + 900: 212b4904 addi r4,r4,-21212 + 904: 0006bc80 call 6bc8 + 908: 00073e80 call 73e8 + 90c: e0bfde17 ldw r2,-136(fp) + 910: 10800504 addi r2,r2,20 + 914: 1007883a mov r3,r2 + 918: 00804004 movi r2,256 + 91c: 18800035 stwio r2,0(r3) + 920: e0bfde17 ldw r2,-136(fp) + 924: 10800604 addi r2,r2,24 + 928: 1007883a mov r3,r2 + 92c: 00804004 movi r2,256 + 930: 18800035 stwio r2,0(r3) + 934: e0bfde17 ldw r2,-136(fp) + 938: 10800704 addi r2,r2,28 + 93c: 1007883a mov r3,r2 + 940: e0bfeb17 ldw r2,-84(fp) + 944: 18800035 stwio r2,0(r3) + 948: 01000074 movhi r4,1 + 94c: 212b8704 addi r4,r4,-20964 + 950: 0006bc80 call 6bc8 + 954: 0000c0c0 call c0c + 958: e0bfe415 stw r2,-112(fp) + 95c: e0ffe515 stw r3,-108(fp) + 960: 008c0034 movhi r2,12288 + 964: e0bfe315 stw r2,-116(fp) + 968: e0bfde17 ldw r2,-136(fp) + 96c: 10800204 addi r2,r2,8 + 970: 1009883a mov r4,r2 + 974: e0ffe317 ldw r3,-116(fp) + 978: e0bff117 ldw r2,-60(fp) + 97c: 1885883a add r2,r3,r2 + 980: 20800035 stwio r2,0(r4) + 984: e0bfde17 ldw r2,-136(fp) + 988: 10800304 addi r2,r2,12 + 98c: 1009883a mov r4,r2 + 990: e0ffe317 ldw r3,-116(fp) + 994: e0bfef17 ldw r2,-68(fp) + 998: 1885883a add r2,r3,r2 + 99c: 20800035 stwio r2,0(r4) + 9a0: e0bfde17 ldw r2,-136(fp) + 9a4: 10800404 addi r2,r2,16 + 9a8: 1007883a mov r3,r2 + 9ac: 00800434 movhi r2,16 + 9b0: 18800035 stwio r2,0(r3) + 9b4: e0bfde17 ldw r2,-136(fp) + 9b8: 00c00044 movi r3,1 + 9bc: 10c00035 stwio r3,0(r2) + 9c0: 0001883a nop + 9c4: e0bfde17 ldw r2,-136(fp) + 9c8: 10800104 addi r2,r2,4 + 9cc: 10800037 ldwio r2,0(r2) + 9d0: 1080004c andi r2,r2,1 + 9d4: 103ffb26 beq r2,zero,9c4 + 9d8: e0bfde17 ldw r2,-136(fp) + 9dc: 10800104 addi r2,r2,4 + 9e0: 1007883a mov r3,r2 + 9e4: 00800044 movi r2,1 + 9e8: 18800035 stwio r2,0(r3) + 9ec: 0000c0c0 call c0c + 9f0: e0bfe115 stw r2,-124(fp) + 9f4: e0ffe215 stw r3,-120(fp) + 9f8: e0ffe117 ldw r3,-124(fp) + 9fc: e0bfe417 ldw r2,-112(fp) + a00: 1885c83a sub r2,r3,r2 + a04: e0bff415 stw r2,-48(fp) + a08: e0bff417 ldw r2,-48(fp) + a0c: 1000021e bne r2,zero,a18 + a10: 00800044 movi r2,1 + a14: e0bff415 stw r2,-48(fp) + a18: e0bff417 ldw r2,-48(fp) + a1c: 1021883a mov r16,r2 + a20: 0023883a mov r17,zero + a24: 800d883a mov r6,r16 + a28: 880f883a mov r7,r17 + a2c: 01077374 movhi r4,7629 + a30: 21194004 addi r4,r4,25856 + a34: 000b883a mov r5,zero + a38: 0003dc00 call 3dc0 <__udivdi3> + a3c: 1009883a mov r4,r2 + a40: 180b883a mov r5,r3 + a44: 2005883a mov r2,r4 + a48: 2807883a mov r3,r5 + a4c: e0bfe015 stw r2,-128(fp) + a50: e0bfe017 ldw r2,-128(fp) + a54: 01400284 movi r5,10 + a58: 1009883a mov r4,r2 + a5c: 00044440 call 4444 <__udivsi3> + a60: 1021883a mov r16,r2 + a64: e0bfe017 ldw r2,-128(fp) + a68: 01400284 movi r5,10 + a6c: 1009883a mov r4,r2 + a70: 00044a80 call 44a8 <__umodsi3> + a74: 100f883a mov r7,r2 + a78: 800d883a mov r6,r16 + a7c: e17ff417 ldw r5,-48(fp) + a80: 01000074 movhi r4,1 + a84: 212b4904 addi r4,r4,-21212 + a88: 0006bc80 call 6bc8 + a8c: e17ff417 ldw r5,-48(fp) + a90: e13ff517 ldw r4,-44(fp) + a94: 00044440 call 4444 <__udivsi3> + a98: 100b883a mov r5,r2 + a9c: 01000074 movhi r4,1 + aa0: 212b5904 addi r4,r4,-21148 + aa4: 0006bc80 call 6bc8 + aa8: 01000074 movhi r4,1 + aac: 212b8e04 addi r4,r4,-20936 + ab0: 0006cb00 call 6cb0 + ab4: e03ff315 stw zero,-52(fp) + ab8: e03ff215 stw zero,-56(fp) + abc: 00001906 br b24 + ac0: e0bff217 ldw r2,-56(fp) + ac4: 100490ba slli r2,r2,2 + ac8: e0ffec17 ldw r3,-80(fp) + acc: 1885883a add r2,r3,r2 + ad0: 10800017 ldw r2,0(r2) + ad4: 1009883a mov r4,r2 + ad8: e0bff217 ldw r2,-56(fp) + adc: 100490ba slli r2,r2,2 + ae0: e0ffed17 ldw r3,-76(fp) + ae4: 1885883a add r2,r3,r2 + ae8: 10800017 ldw r2,0(r2) + aec: 2085c83a sub r2,r4,r2 + af0: e0bfdf15 stw r2,-132(fp) + af4: e0bfdf17 ldw r2,-132(fp) + af8: 10800088 cmpgei r2,r2,2 + afc: 1000031e bne r2,zero,b0c + b00: e0bfdf17 ldw r2,-132(fp) + b04: 10bfffc8 cmpgei r2,r2,-1 + b08: 1000031e bne r2,zero,b18 + b0c: e0bff317 ldw r2,-52(fp) + b10: 10800044 addi r2,r2,1 + b14: e0bff315 stw r2,-52(fp) + b18: e0bff217 ldw r2,-56(fp) + b1c: 10800044 addi r2,r2,1 + b20: e0bff215 stw r2,-56(fp) + b24: e0bff217 ldw r2,-56(fp) + b28: 10810010 cmplti r2,r2,1024 + b2c: 103fe41e bne r2,zero,ac0 + b30: e0bff317 ldw r2,-52(fp) + b34: 1000051e bne r2,zero,b4c + b38: e17feb17 ldw r5,-84(fp) + b3c: 01000074 movhi r4,1 + b40: 212b9404 addi r4,r4,-20912 + b44: 0006bc80 call 6bc8 + b48: 00000406 br b5c + b4c: e17ff317 ldw r5,-52(fp) + b50: 01000074 movhi r4,1 + b54: 212b9f04 addi r4,r4,-20868 + b58: 0006bc80 call 6bc8 + b5c: 0001883a nop + b60: e6fff804 addi sp,fp,-32 + b64: dfc00917 ldw ra,36(sp) + b68: df000817 ldw fp,32(sp) + b6c: ddc00717 ldw r23,28(sp) + b70: dd800617 ldw r22,24(sp) + b74: dd400517 ldw r21,20(sp) + b78: dd000417 ldw r20,16(sp) + b7c: dcc00317 ldw r19,12(sp) + b80: dc800217 ldw r18,8(sp) + b84: dc400117 ldw r17,4(sp) + b88: dc000017 ldw r16,0(sp) + b8c: dec00a04 addi sp,sp,40 + b90: f800283a ret + +00000b94 : + b94: defffe04 addi sp,sp,-8 + b98: df000115 stw fp,4(sp) + b9c: df000104 addi fp,sp,4 + ba0: 008000b4 movhi r2,2 + ba4: 10800037 ldwio r2,0(r2) + ba8: e0bfff15 stw r2,-4(fp) + bac: e0bfff17 ldw r2,-4(fp) + bb0: 10a0000c andi r2,r2,32768 + bb4: 103ffa26 beq r2,zero,ba0 + bb8: e0bfff17 ldw r2,-4(fp) + bbc: e037883a mov sp,fp + bc0: df000017 ldw fp,0(sp) + bc4: dec00104 addi sp,sp,4 + bc8: f800283a ret + +00000bcc : + bcc: defffe04 addi sp,sp,-8 + bd0: df000115 stw fp,4(sp) + bd4: df000104 addi fp,sp,4 + bd8: 008000b4 movhi r2,2 + bdc: 10800037 ldwio r2,0(r2) + be0: e0bfff15 stw r2,-4(fp) + be4: e0bfff17 ldw r2,-4(fp) + be8: 10a0000c andi r2,r2,32768 + bec: 10000226 beq r2,zero,bf8 + bf0: e0bfff17 ldw r2,-4(fp) + bf4: 00000106 br bfc + bf8: 0005883a mov r2,zero + bfc: e037883a mov sp,fp + c00: df000017 ldw fp,0(sp) + c04: dec00104 addi sp,sp,4 + c08: f800283a ret + +00000c0c : + c0c: defff504 addi sp,sp,-44 + c10: dfc00a15 stw ra,40(sp) + c14: df000915 stw fp,36(sp) + c18: dc400815 stw r17,32(sp) + c1c: dc000715 stw r16,28(sp) + c20: df000904 addi fp,sp,36 + c24: 01000074 movhi r4,1 + c28: 21307417 ldw r4,-15920(r4) + c2c: e13ffd15 stw r4,-12(fp) + c30: 000b883a mov r5,zero c34: 010000b4 movhi r4,2 - c38: 21002437 ldwio r4,144(r4) - c3c: e13ffc15 stw r4,-16(fp) - c40: 010000b4 movhi r4,2 - c44: 21002537 ldwio r4,148(r4) - c48: e13ffb15 stw r4,-20(fp) - c4c: e13ffb17 ldw r4,-20(fp) - c50: 2008943a slli r4,r4,16 - c54: e17ffc17 ldw r5,-16(fp) - c58: 2908b03a or r4,r5,r4 - c5c: e13ffa15 stw r4,-24(fp) - c60: 01000074 movhi r4,1 - c64: 21274f17 ldw r4,-25284(r4) - c68: e13ff915 stw r4,-28(fp) - c6c: e17ffd17 ldw r5,-12(fp) - c70: e13ff917 ldw r4,-28(fp) - c74: 293fe91e bne r5,r4,c1c - c78: e13ffd17 ldw r4,-12(fp) - c7c: 2005883a mov r2,r4 - c80: 0007883a mov r3,zero - c84: 01b0d414 movui r6,50000 - c88: 000f883a mov r7,zero - c8c: 1009883a mov r4,r2 - c90: 180b883a mov r5,r3 - c94: 0002cbc0 call 2cbc <__muldi3> - c98: 1009883a mov r4,r2 - c9c: 180b883a mov r5,r3 - ca0: e13ff715 stw r4,-36(fp) - ca4: e17ff815 stw r5,-32(fp) - ca8: 00f0d3d4 movui r3,49999 - cac: e0bffa17 ldw r2,-24(fp) - cb0: 1885c83a sub r2,r3,r2 - cb4: 1021883a mov r16,r2 - cb8: 0023883a mov r17,zero - cbc: e13ff717 ldw r4,-36(fp) - cc0: e17ff817 ldw r5,-32(fp) - cc4: 2405883a add r2,r4,r16 - cc8: 110d803a cmpltu r6,r2,r4 - ccc: 2c47883a add r3,r5,r17 - cd0: 30c9883a add r4,r6,r3 - cd4: 2007883a mov r3,r4 - cd8: e0bff715 stw r2,-36(fp) - cdc: e0fff815 stw r3,-32(fp) - ce0: e0bff717 ldw r2,-36(fp) - ce4: e0fff817 ldw r3,-32(fp) - ce8: 1009883a mov r4,r2 - cec: 180b883a mov r5,r3 - cf0: 2005883a mov r2,r4 - cf4: 2807883a mov r3,r5 - cf8: e6fffe04 addi sp,fp,-8 - cfc: dfc00317 ldw ra,12(sp) - d00: df000217 ldw fp,8(sp) - d04: dc400117 ldw r17,4(sp) - d08: dc000017 ldw r16,0(sp) - d0c: dec00404 addi sp,sp,16 - d10: f800283a ret - -00000d14 : - d14: defffb04 addi sp,sp,-20 - d18: dfc00415 stw ra,16(sp) - d1c: df000315 stw fp,12(sp) - d20: df000304 addi fp,sp,12 - d24: 2005883a mov r2,r4 - d28: 2807883a mov r3,r5 - d2c: e0bffe05 stb r2,-8(fp) - d30: 1805883a mov r2,r3 - d34: e0bffd05 stb r2,-12(fp) - d38: e0bffe03 ldbu r2,-8(fp) - d3c: e0bfff85 stb r2,-2(fp) - d40: e0bffd03 ldbu r2,-12(fp) - d44: e0bfffc5 stb r2,-1(fp) - d48: d0a0dc17 ldw r2,-31888(gp) - d4c: 01400e44 movi r5,57 - d50: 1009883a mov r4,r2 - d54: 00063bc0 call 63bc - d58: d0a0dc17 ldw r2,-31888(gp) - d5c: e0ffff84 addi r3,fp,-2 - d60: 000f883a mov r7,zero - d64: 01800084 movi r6,2 - d68: 180b883a mov r5,r3 - d6c: 1009883a mov r4,r2 - d70: 00065bc0 call 65bc - d74: 0001883a nop - d78: e037883a mov sp,fp - d7c: dfc00117 ldw ra,4(sp) - d80: df000017 ldw fp,0(sp) - d84: dec00204 addi sp,sp,8 - d88: f800283a ret - -00000d8c : - d8c: defff904 addi sp,sp,-28 - d90: dfc00615 stw ra,24(sp) - d94: df000515 stw fp,20(sp) - d98: df000504 addi fp,sp,20 - d9c: 0080fa04 movi r2,1000 - da0: e0bfff15 stw r2,-4(fp) - da4: 01000074 movhi r4,1 - da8: 21236f04 addi r4,r4,-29252 - dac: 0004bcc0 call 4bcc - db0: 00000c06 br de4 - db4: 0100fa04 movi r4,1000 - db8: 00056640 call 5664 - dbc: e0bfff17 ldw r2,-4(fp) - dc0: 10bfffc4 addi r2,r2,-1 - dc4: e0bfff15 stw r2,-4(fp) - dc8: e0bfff17 ldw r2,-4(fp) - dcc: 1000051e bne r2,zero,de4 - dd0: 01000074 movhi r4,1 - dd4: 21237804 addi r4,r4,-29216 - dd8: 0004bcc0 call 4bcc - ddc: 00bfffc4 movi r2,-1 - de0: 00004c06 br f14 - de4: 008000b4 movhi r2,2 - de8: 10800437 ldwio r2,16(r2) - dec: 103ff126 beq r2,zero,db4 - df0: 01000074 movhi r4,1 - df4: 21238404 addi r4,r4,-29168 - df8: 0004bcc0 call 4bcc - dfc: 01000074 movhi r4,1 - e00: 21239204 addi r4,r4,-29112 - e04: 0005be00 call 5be0 - e08: d0a0dc15 stw r2,-31888(gp) - e0c: d0a0dc17 ldw r2,-31888(gp) - e10: 1000071e bne r2,zero,e30 - e14: 01400074 movhi r5,1 - e18: 29639204 addi r5,r5,-29112 - e1c: 01000074 movhi r4,1 - e20: 21239604 addi r4,r4,-29096 - e24: 0004ae40 call 4ae4 - e28: 00bfff84 movi r2,-2 - e2c: 00003906 br f14 - e30: d0a0dc17 ldw r2,-31888(gp) - e34: e0fffb04 addi r3,fp,-20 - e38: 180b883a mov r5,r3 - e3c: 1009883a mov r4,r2 - e40: 0005d040 call 5d04 - e44: d0a0dc17 ldw r2,-31888(gp) - e48: e0fffb04 addi r3,fp,-20 - e4c: 018000b4 movhi r6,2 - e50: 31a1a804 addi r6,r6,-31072 - e54: 180b883a mov r5,r3 - e58: 1009883a mov r4,r2 - e5c: 0005f140 call 5f14 - e60: d0a0dc17 ldw r2,-31888(gp) - e64: e0fffb04 addi r3,fp,-20 - e68: 180b883a mov r5,r3 - e6c: 1009883a mov r4,r2 - e70: 0005db40 call 5db4 - e74: 01400404 movi r5,16 - e78: 01001044 movi r4,65 - e7c: 0000d140 call d14 - e80: 000b883a mov r5,zero - e84: 01000584 movi r4,22 - e88: 0000d140 call d14 - e8c: 01400184 movi r5,6 - e90: 01002bc4 movi r4,175 - e94: 0000d140 call d14 - e98: 01400604 movi r5,24 - e9c: 01000f04 movi r4,60 - ea0: 0000d140 call d14 - ea4: 014000c4 movi r5,3 - ea8: 01002604 movi r4,152 - eac: 0000d140 call d14 - eb0: 01403804 movi r5,224 - eb4: 01002684 movi r4,154 - eb8: 0000d140 call d14 - ebc: 01400c04 movi r5,48 - ec0: 01002704 movi r4,156 - ec4: 0000d140 call d14 - ec8: 01401844 movi r5,97 - ecc: 01002744 movi r4,157 - ed0: 0000d140 call d14 - ed4: 01402904 movi r5,164 - ed8: 01002884 movi r4,162 - edc: 0000d140 call d14 - ee0: 01402904 movi r5,164 - ee4: 010028c4 movi r4,163 - ee8: 0000d140 call d14 - eec: 01403404 movi r5,208 - ef0: 01003804 movi r4,224 - ef4: 0000d140 call d14 - ef8: 000b883a mov r5,zero - efc: 01003e44 movi r4,249 - f00: 0000d140 call d14 - f04: 01000074 movhi r4,1 - f08: 2123a004 addi r4,r4,-29056 - f0c: 0004bcc0 call 4bcc - f10: 0005883a mov r2,zero - f14: e037883a mov sp,fp - f18: dfc00117 ldw ra,4(sp) - f1c: df000017 ldw fp,0(sp) - f20: dec00204 addi sp,sp,8 - f24: f800283a ret - -00000f28 : - f28: deffef04 addi sp,sp,-68 - f2c: dfc01015 stw ra,64(sp) - f30: df000f15 stw fp,60(sp) - f34: df000f04 addi fp,sp,60 - f38: 01000074 movhi r4,1 - f3c: 2123ac04 addi r4,r4,-29008 - f40: 0004ae40 call 4ae4 - f44: 00a20034 movhi r2,34816 - f48: e0bffc15 stw r2,-16(fp) - f4c: 00814004 movi r2,1280 - f50: e0bffb15 stw r2,-20(fp) - f54: 0080b404 movi r2,720 - f58: e0bffa15 stw r2,-24(fp) - f5c: e0bffb17 ldw r2,-20(fp) - f60: 1000010e bge r2,zero,f68 - f64: 108001c4 addi r2,r2,7 - f68: 1005d0fa srai r2,r2,3 - f6c: e0bff915 stw r2,-28(fp) - f70: 00804034 movhi r2,256 - f74: 10bfffc4 addi r2,r2,-1 - f78: e0bff115 stw r2,-60(fp) - f7c: 00804034 movhi r2,256 - f80: 10bfc004 addi r2,r2,-256 - f84: e0bff215 stw r2,-56(fp) - f88: 00bfffd4 movui r2,65535 - f8c: e0bff315 stw r2,-52(fp) - f90: 00bfc014 movui r2,65280 - f94: e0bff415 stw r2,-48(fp) - f98: 00803ff4 movhi r2,255 - f9c: 10803fc4 addi r2,r2,255 - fa0: e0bff515 stw r2,-44(fp) - fa4: 00803ff4 movhi r2,255 - fa8: e0bff615 stw r2,-40(fp) - fac: 00803fc4 movi r2,255 - fb0: e0bff715 stw r2,-36(fp) - fb4: e03ff815 stw zero,-32(fp) - fb8: e03fff15 stw zero,-4(fp) - fbc: 00002106 br 1044 - fc0: e03ffe15 stw zero,-8(fp) - fc4: 00001906 br 102c - fc8: e17ff917 ldw r5,-28(fp) - fcc: e13ffe17 ldw r4,-8(fp) - fd0: 000330c0 call 330c <__divsi3> - fd4: e0bffd15 stw r2,-12(fp) - fd8: e0bffd17 ldw r2,-12(fp) - fdc: 10800210 cmplti r2,r2,8 - fe0: 1000021e bne r2,zero,fec - fe4: 008001c4 movi r2,7 - fe8: e0bffd15 stw r2,-12(fp) - fec: e0ffff17 ldw r3,-4(fp) - ff0: e0bffb17 ldw r2,-20(fp) - ff4: 1887383a mul r3,r3,r2 - ff8: e0bffe17 ldw r2,-8(fp) - ffc: 1885883a add r2,r3,r2 - 1000: 100490ba slli r2,r2,2 - 1004: e0fffc17 ldw r3,-16(fp) - 1008: 1885883a add r2,r3,r2 - 100c: e0fffd17 ldw r3,-12(fp) - 1010: 180690ba slli r3,r3,2 - 1014: e0c7883a add r3,fp,r3 - 1018: 18fff117 ldw r3,-60(r3) - 101c: 10c00015 stw r3,0(r2) - 1020: e0bffe17 ldw r2,-8(fp) - 1024: 10800044 addi r2,r2,1 - 1028: e0bffe15 stw r2,-8(fp) - 102c: e0fffe17 ldw r3,-8(fp) - 1030: e0bffb17 ldw r2,-20(fp) - 1034: 18bfe416 blt r3,r2,fc8 - 1038: e0bfff17 ldw r2,-4(fp) - 103c: 10800044 addi r2,r2,1 - 1040: e0bfff15 stw r2,-4(fp) - 1044: e0ffff17 ldw r3,-4(fp) - 1048: e0bffa17 ldw r2,-24(fp) - 104c: 18bfdc16 blt r3,r2,fc0 - 1050: 00053040 call 5304 - 1054: e0fffb17 ldw r3,-20(fp) - 1058: e0bffa17 ldw r2,-24(fp) - 105c: 1885383a mul r2,r3,r2 - 1060: 100b883a mov r5,r2 - 1064: 01000074 movhi r4,1 - 1068: 2123b804 addi r4,r4,-28960 - 106c: 0004ae40 call 4ae4 - 1070: 0001883a nop - 1074: e037883a mov sp,fp - 1078: dfc00117 ldw ra,4(sp) - 107c: df000017 ldw fp,0(sp) - 1080: dec00204 addi sp,sp,8 - 1084: f800283a ret - -00001088 : - 1088: defffd04 addi sp,sp,-12 - 108c: dfc00215 stw ra,8(sp) - 1090: df000115 stw fp,4(sp) - 1094: df000104 addi fp,sp,4 - 1098: 01000074 movhi r4,1 - 109c: 2123c104 addi r4,r4,-28924 - 10a0: 0004bcc0 call 4bcc - 10a4: d0a0dd17 ldw r2,-31884(gp) - 10a8: 10000326 beq r2,zero,10b8 - 10ac: 00800074 movhi r2,1 - 10b0: 10a3ca04 addi r2,r2,-28888 - 10b4: 00000206 br 10c0 - 10b8: 00800074 movhi r2,1 - 10bc: 10a3cb04 addi r2,r2,-28884 - 10c0: 100b883a mov r5,r2 - 10c4: 01000074 movhi r4,1 - 10c8: 2123cc04 addi r4,r4,-28880 - 10cc: 0004ae40 call 4ae4 - 10d0: 01000074 movhi r4,1 - 10d4: 2123d504 addi r4,r4,-28844 - 10d8: 0004bcc0 call 4bcc - 10dc: 01000074 movhi r4,1 - 10e0: 2123dd04 addi r4,r4,-28812 - 10e4: 0004bcc0 call 4bcc - 10e8: 01000074 movhi r4,1 - 10ec: 2123e504 addi r4,r4,-28780 - 10f0: 0004bcc0 call 4bcc - 10f4: 01000074 movhi r4,1 - 10f8: 2123f104 addi r4,r4,-28732 - 10fc: 0004bcc0 call 4bcc - 1100: 01000074 movhi r4,1 - 1104: 2123f704 addi r4,r4,-28708 - 1108: 0004ae40 call 4ae4 - 110c: 0000b8c0 call b8c - 1110: e0bfffc5 stb r2,-1(fp) - 1114: e0bfffc7 ldb r2,-1(fp) - 1118: 100b883a mov r5,r2 - 111c: 01000074 movhi r4,1 - 1120: 2123fb04 addi r4,r4,-28692 - 1124: 0004ae40 call 4ae4 - 1128: e0bfffc7 ldb r2,-1(fp) - 112c: 10801898 cmpnei r2,r2,98 - 1130: 10001c26 beq r2,zero,11a4 - 1134: e0bfffc7 ldb r2,-1(fp) - 1138: 10800c58 cmpnei r2,r2,49 - 113c: 1000081e bne r2,zero,1160 - 1140: d0a0dd17 ldw r2,-31884(gp) - 1144: 1005003a cmpeq r2,r2,zero - 1148: 10803fcc andi r2,r2,255 - 114c: d0a0dd15 stw r2,-31884(gp) - 1150: d0a0dd17 ldw r2,-31884(gp) - 1154: 1009883a mov r4,r2 - 1158: 00014180 call 1418 - 115c: 003fce06 br 1098 - 1160: e0bfffc7 ldb r2,-1(fp) - 1164: 10800c98 cmpnei r2,r2,50 - 1168: 1000041e bne r2,zero,117c - 116c: 01100374 movhi r4,16397 - 1170: 21333344 addi r4,r4,-13107 - 1174: 00012e00 call 12e0 - 1178: 003fc706 br 1098 - 117c: e0bfffc7 ldb r2,-1(fp) - 1180: 10800cd8 cmpnei r2,r2,51 - 1184: 1000021e bne r2,zero,1190 - 1188: 00014840 call 1484 - 118c: 003fc206 br 1098 - 1190: e0bfffc7 ldb r2,-1(fp) - 1194: 10800d18 cmpnei r2,r2,52 - 1198: 103fbf1e bne r2,zero,1098 - 119c: 00015f00 call 15f0 - 11a0: 003fbd06 br 1098 - 11a4: 0001883a nop - 11a8: 0001883a nop - 11ac: e037883a mov sp,fp - 11b0: dfc00117 ldw ra,4(sp) - 11b4: df000017 ldw fp,0(sp) - 11b8: dec00204 addi sp,sp,8 - 11bc: f800283a ret - -000011c0 : - 11c0: defffc04 addi sp,sp,-16 - 11c4: dfc00315 stw ra,12(sp) - 11c8: df000215 stw fp,8(sp) - 11cc: df000204 addi fp,sp,8 - 11d0: 01000074 movhi r4,1 - 11d4: 2123fc04 addi r4,r4,-28688 - 11d8: 0004bcc0 call 4bcc - 11dc: 01000074 movhi r4,1 - 11e0: 21240304 addi r4,r4,-28660 - 11e4: 0004bcc0 call 4bcc - 11e8: 01000074 movhi r4,1 - 11ec: 21240704 addi r4,r4,-28644 - 11f0: 0004bcc0 call 4bcc - 11f4: 01000074 movhi r4,1 - 11f8: 21240c04 addi r4,r4,-28624 - 11fc: 0004bcc0 call 4bcc - 1200: 01000074 movhi r4,1 - 1204: 21241004 addi r4,r4,-28608 - 1208: 0004bcc0 call 4bcc - 120c: 01000074 movhi r4,1 - 1210: 21241504 addi r4,r4,-28588 - 1214: 0004bcc0 call 4bcc - 1218: 01000074 movhi r4,1 - 121c: 21241a04 addi r4,r4,-28568 - 1220: 0004bcc0 call 4bcc - 1224: 01000074 movhi r4,1 - 1228: 21241f04 addi r4,r4,-28548 - 122c: 0004bcc0 call 4bcc - 1230: 01000074 movhi r4,1 - 1234: 21242504 addi r4,r4,-28524 - 1238: 0004bcc0 call 4bcc - 123c: 01000074 movhi r4,1 - 1240: 2123f104 addi r4,r4,-28732 - 1244: 0004bcc0 call 4bcc - 1248: 01000074 movhi r4,1 - 124c: 2123f704 addi r4,r4,-28708 - 1250: 0004ae40 call 4ae4 - 1254: 0000b8c0 call b8c - 1258: e0bfffc5 stb r2,-1(fp) - 125c: e0bfffc7 ldb r2,-1(fp) - 1260: 100b883a mov r5,r2 - 1264: 01000074 movhi r4,1 - 1268: 2123fb04 addi r4,r4,-28692 - 126c: 0004ae40 call 4ae4 - 1270: e0bfffc7 ldb r2,-1(fp) - 1274: 10801898 cmpnei r2,r2,98 - 1278: 10001226 beq r2,zero,12c4 - 127c: e0bfffc7 ldb r2,-1(fp) - 1280: 10bff404 addi r2,r2,-48 - 1284: e0bffe15 stw r2,-8(fp) - 1288: e0bffe17 ldw r2,-8(fp) - 128c: 10800228 cmpgeui r2,r2,8 - 1290: 1000081e bne r2,zero,12b4 - 1294: e0fffe17 ldw r3,-8(fp) - 1298: 00a000b4 movhi r2,32770 - 129c: 10c00835 stwio r3,32(r2) - 12a0: e17ffe17 ldw r5,-8(fp) - 12a4: 01000074 movhi r4,1 - 12a8: 21242e04 addi r4,r4,-28488 - 12ac: 0004ae40 call 4ae4 - 12b0: 003fc706 br 11d0 - 12b4: 01000074 movhi r4,1 - 12b8: 21243404 addi r4,r4,-28464 - 12bc: 0004bcc0 call 4bcc - 12c0: 003fc306 br 11d0 - 12c4: 0001883a nop - 12c8: 0001883a nop - 12cc: e037883a mov sp,fp - 12d0: dfc00117 ldw ra,4(sp) - 12d4: df000017 ldw fp,0(sp) - 12d8: dec00204 addi sp,sp,8 - 12dc: f800283a ret - -000012e0 : - 12e0: defff804 addi sp,sp,-32 - 12e4: dfc00715 stw ra,28(sp) - 12e8: df000615 stw fp,24(sp) - 12ec: df000604 addi fp,sp,24 - 12f0: e13ffa15 stw r4,-24(fp) - 12f4: e13ffa17 ldw r4,-24(fp) - 12f8: 00049240 call 4924 <__extendsfdf2> - 12fc: 100d883a mov r6,r2 - 1300: 180f883a mov r7,r3 - 1304: 300b883a mov r5,r6 - 1308: 380d883a mov r6,r7 - 130c: 01000074 movhi r4,1 - 1310: 21244104 addi r4,r4,-28412 - 1314: 0004ae40 call 4ae4 - 1318: e17ffa17 ldw r5,-24(fp) - 131c: 010fe034 movhi r4,16256 - 1320: 000392c0 call 392c <__divsf3> - 1324: 1007883a mov r3,r2 - 1328: e0fffe15 stw r3,-8(fp) - 132c: e03fff15 stw zero,-4(fp) - 1330: 00002d06 br 13e8 - 1334: e13fff17 ldw r4,-4(fp) - 1338: 00048000 call 4800 <__floatsisf> - 133c: 1007883a mov r3,r2 - 1340: 0150dff4 movhi r5,17279 - 1344: 1809883a mov r4,r3 - 1348: 000392c0 call 392c <__divsf3> - 134c: 1007883a mov r3,r2 - 1350: e0fffd15 stw r3,-12(fp) - 1354: e17ffe17 ldw r5,-8(fp) - 1358: e13ffd17 ldw r4,-12(fp) - 135c: 0001b600 call 1b60 - 1360: e0bffc15 stw r2,-16(fp) - 1364: 0150dff4 movhi r5,17279 - 1368: e13ffc17 ldw r4,-16(fp) - 136c: 0003efc0 call 3efc <__mulsf3> - 1370: 1007883a mov r3,r2 - 1374: 1805883a mov r2,r3 - 1378: 014fc034 movhi r5,16128 - 137c: 1009883a mov r4,r2 - 1380: 00034c00 call 34c0 <__addsf3> - 1384: 1007883a mov r3,r2 - 1388: 1805883a mov r2,r3 - 138c: 1009883a mov r4,r2 - 1390: 0002d1c0 call 2d1c <__fixunssfsi> - 1394: e0bffbc5 stb r2,-17(fp) - 1398: e0ffff17 ldw r3,-4(fp) - 139c: 00a000b4 movhi r2,32770 - 13a0: 10c00a35 stwio r3,40(r2) - 13a4: e0fffbc3 ldbu r3,-17(fp) - 13a8: 00a000b4 movhi r2,32770 - 13ac: 10c00b35 stwio r3,44(r2) - 13b0: e0bffbc3 ldbu r2,-17(fp) - 13b4: 100b883a mov r5,r2 - 13b8: 01000074 movhi r4,1 - 13bc: 21244f04 addi r4,r4,-28356 - 13c0: 0004ae40 call 4ae4 - 13c4: e0bfff17 ldw r2,-4(fp) - 13c8: 10800044 addi r2,r2,1 - 13cc: 108003cc andi r2,r2,15 - 13d0: 1000021e bne r2,zero,13dc - 13d4: 01000284 movi r4,10 - 13d8: 0004b340 call 4b34 - 13dc: e0bfff17 ldw r2,-4(fp) - 13e0: 10800044 addi r2,r2,1 - 13e4: e0bfff15 stw r2,-4(fp) - 13e8: e0bfff17 ldw r2,-4(fp) - 13ec: 10804010 cmplti r2,r2,256 - 13f0: 103fd01e bne r2,zero,1334 - 13f4: 01000074 movhi r4,1 - 13f8: 21245104 addi r4,r4,-28348 - 13fc: 0004bcc0 call 4bcc - 1400: 0001883a nop - 1404: e037883a mov sp,fp - 1408: dfc00117 ldw ra,4(sp) - 140c: df000017 ldw fp,0(sp) - 1410: dec00204 addi sp,sp,8 - 1414: f800283a ret - -00001418 : - 1418: defffd04 addi sp,sp,-12 - 141c: dfc00215 stw ra,8(sp) - 1420: df000115 stw fp,4(sp) - 1424: df000104 addi fp,sp,4 - 1428: e13fff15 stw r4,-4(fp) - 142c: e0bfff17 ldw r2,-4(fp) - 1430: 1004c03a cmpne r2,r2,zero - 1434: 10c03fcc andi r3,r2,255 - 1438: 00a000b4 movhi r2,32770 - 143c: 10c00935 stwio r3,36(r2) - 1440: e0bfff17 ldw r2,-4(fp) - 1444: 10000326 beq r2,zero,1454 - 1448: 00800074 movhi r2,1 - 144c: 10a45304 addi r2,r2,-28340 - 1450: 00000206 br 145c - 1454: 00800074 movhi r2,1 - 1458: 10a45504 addi r2,r2,-28332 - 145c: 100b883a mov r5,r2 - 1460: 01000074 movhi r4,1 - 1464: 21245804 addi r4,r4,-28320 - 1468: 0004ae40 call 4ae4 - 146c: 0001883a nop - 1470: e037883a mov sp,fp - 1474: dfc00117 ldw ra,4(sp) - 1478: df000017 ldw fp,0(sp) - 147c: dec00204 addi sp,sp,8 - 1480: f800283a ret - -00001484 : - 1484: defffa04 addi sp,sp,-24 - 1488: dfc00515 stw ra,20(sp) - 148c: df000415 stw fp,16(sp) - 1490: df000404 addi fp,sp,16 - 1494: 01000074 movhi r4,1 - 1498: 21245e04 addi r4,r4,-28296 - 149c: 0004bcc0 call 4bcc - 14a0: e03fff15 stw zero,-4(fp) - 14a4: 00004606 br 15c0 - 14a8: e13fff17 ldw r4,-4(fp) - 14ac: 00048000 call 4800 <__floatsisf> - 14b0: 1007883a mov r3,r2 - 14b4: 0150dff4 movhi r5,17279 - 14b8: 1809883a mov r4,r3 - 14bc: 000392c0 call 392c <__divsf3> - 14c0: 1007883a mov r3,r2 - 14c4: e0fffd15 stw r3,-12(fp) - 14c8: 014ed374 movhi r5,15181 - 14cc: 294b8704 addi r5,r5,11804 - 14d0: e13ffd17 ldw r4,-12(fp) - 14d4: 0003e480 call 3e48 <__lesf2> - 14d8: 00800716 blt zero,r2,14f8 - 14dc: 015053f4 movhi r5,16719 - 14e0: 296e1484 addi r5,r5,-18350 - 14e4: e13ffd17 ldw r4,-12(fp) - 14e8: 0003efc0 call 3efc <__mulsf3> - 14ec: 1007883a mov r3,r2 - 14f0: e0fffe15 stw r3,-8(fp) - 14f4: 00001106 br 153c - 14f8: 014fb574 movhi r5,16085 - 14fc: 29555544 addi r5,r5,21845 - 1500: e13ffd17 ldw r4,-12(fp) - 1504: 0001b600 call 1b60 - 1508: 1007883a mov r3,r2 - 150c: 014fe1f4 movhi r5,16263 - 1510: 29428f44 addi r5,r5,2621 - 1514: 1809883a mov r4,r3 - 1518: 0003efc0 call 3efc <__mulsf3> - 151c: 1007883a mov r3,r2 - 1520: 1805883a mov r2,r3 - 1524: 014f5874 movhi r5,15713 - 1528: 2951eb84 addi r5,r5,18350 - 152c: 1009883a mov r4,r2 - 1530: 00042b00 call 42b0 <__subsf3> - 1534: 1007883a mov r3,r2 - 1538: e0fffe15 stw r3,-8(fp) - 153c: 0150dff4 movhi r5,17279 - 1540: e13ffe17 ldw r4,-8(fp) - 1544: 0003efc0 call 3efc <__mulsf3> - 1548: 1007883a mov r3,r2 - 154c: 1805883a mov r2,r3 - 1550: 014fc034 movhi r5,16128 - 1554: 1009883a mov r4,r2 - 1558: 00034c00 call 34c0 <__addsf3> - 155c: 1007883a mov r3,r2 - 1560: 1805883a mov r2,r3 - 1564: 1009883a mov r4,r2 - 1568: 0002d1c0 call 2d1c <__fixunssfsi> - 156c: e0bffcc5 stb r2,-13(fp) - 1570: e0ffff17 ldw r3,-4(fp) - 1574: 00a000b4 movhi r2,32770 - 1578: 10c00a35 stwio r3,40(r2) - 157c: e0fffcc3 ldbu r3,-13(fp) - 1580: 00a000b4 movhi r2,32770 - 1584: 10c00b35 stwio r3,44(r2) - 1588: e0bffcc3 ldbu r2,-13(fp) - 158c: 100b883a mov r5,r2 - 1590: 01000074 movhi r4,1 - 1594: 21244f04 addi r4,r4,-28356 - 1598: 0004ae40 call 4ae4 - 159c: e0bfff17 ldw r2,-4(fp) - 15a0: 10800044 addi r2,r2,1 - 15a4: 108003cc andi r2,r2,15 - 15a8: 1000021e bne r2,zero,15b4 - 15ac: 01000284 movi r4,10 - 15b0: 0004b340 call 4b34 - 15b4: e0bfff17 ldw r2,-4(fp) - 15b8: 10800044 addi r2,r2,1 - 15bc: e0bfff15 stw r2,-4(fp) - 15c0: e0bfff17 ldw r2,-4(fp) - 15c4: 10804010 cmplti r2,r2,256 - 15c8: 103fb71e bne r2,zero,14a8 - 15cc: 01000074 movhi r4,1 - 15d0: 21246904 addi r4,r4,-28252 - 15d4: 0004bcc0 call 4bcc - 15d8: 0001883a nop - 15dc: e037883a mov sp,fp - 15e0: dfc00117 ldw ra,4(sp) - 15e4: df000017 ldw fp,0(sp) - 15e8: dec00204 addi sp,sp,8 - 15ec: f800283a ret - -000015f0 : - 15f0: defffa04 addi sp,sp,-24 - 15f4: dfc00515 stw ra,20(sp) - 15f8: df000415 stw fp,16(sp) - 15fc: df000404 addi fp,sp,16 - 1600: 01000074 movhi r4,1 - 1604: 21246e04 addi r4,r4,-28232 - 1608: 0004bcc0 call 4bcc - 160c: e03fff15 stw zero,-4(fp) - 1610: 00002306 br 16a0 - 1614: e13fff17 ldw r4,-4(fp) - 1618: 00048000 call 4800 <__floatsisf> - 161c: 1007883a mov r3,r2 - 1620: 0150dff4 movhi r5,17279 - 1624: 1809883a mov r4,r3 - 1628: 000392c0 call 392c <__divsf3> - 162c: 1007883a mov r3,r2 - 1630: e0fffe15 stw r3,-8(fp) - 1634: 01500374 movhi r5,16397 - 1638: 29733344 addi r5,r5,-13107 - 163c: e13ffe17 ldw r4,-8(fp) - 1640: 0001b600 call 1b60 - 1644: e0bffd15 stw r2,-12(fp) - 1648: 0150dff4 movhi r5,17279 - 164c: e13ffd17 ldw r4,-12(fp) - 1650: 0003efc0 call 3efc <__mulsf3> - 1654: 1007883a mov r3,r2 - 1658: 1805883a mov r2,r3 - 165c: 014fc034 movhi r5,16128 - 1660: 1009883a mov r4,r2 - 1664: 00034c00 call 34c0 <__addsf3> - 1668: 1007883a mov r3,r2 - 166c: 1805883a mov r2,r3 - 1670: 1009883a mov r4,r2 - 1674: 0002d1c0 call 2d1c <__fixunssfsi> - 1678: e0bffcc5 stb r2,-13(fp) - 167c: e0ffff17 ldw r3,-4(fp) - 1680: 00a000b4 movhi r2,32770 - 1684: 10c00a35 stwio r3,40(r2) - 1688: e0fffcc3 ldbu r3,-13(fp) - 168c: 00a000b4 movhi r2,32770 - 1690: 10c00b35 stwio r3,44(r2) - 1694: e0bfff17 ldw r2,-4(fp) - 1698: 10800044 addi r2,r2,1 - 169c: e0bfff15 stw r2,-4(fp) - 16a0: e0bfff17 ldw r2,-4(fp) - 16a4: 10804010 cmplti r2,r2,256 - 16a8: 103fda1e bne r2,zero,1614 - 16ac: 01000074 movhi r4,1 - 16b0: 21248104 addi r4,r4,-28156 - 16b4: 0004bcc0 call 4bcc - 16b8: 0001883a nop - 16bc: e037883a mov sp,fp - 16c0: dfc00117 ldw ra,4(sp) - 16c4: df000017 ldw fp,0(sp) - 16c8: dec00204 addi sp,sp,8 - 16cc: f800283a ret - -000016d0 : - 16d0: defff504 addi sp,sp,-44 - 16d4: dfc00a15 stw ra,40(sp) - 16d8: df000915 stw fp,36(sp) - 16dc: df000904 addi fp,sp,36 - 16e0: 01000074 movhi r4,1 - 16e4: 21248704 addi r4,r4,-28132 - 16e8: 0004ae40 call 4ae4 - 16ec: e0fff704 addi r3,fp,-36 - 16f0: 00800074 movhi r2,1 - 16f4: 10a49004 addi r2,r2,-28096 - 16f8: 01000804 movi r4,32 - 16fc: 200d883a mov r6,r4 - 1700: 100b883a mov r5,r2 - 1704: 1809883a mov r4,r3 - 1708: 0004a800 call 4a80 - 170c: e03fff15 stw zero,-4(fp) - 1710: 00000d06 br 1748 - 1714: e0ffff17 ldw r3,-4(fp) - 1718: 00a000b4 movhi r2,32770 - 171c: 10c00c35 stwio r3,48(r2) - 1720: e0bfff17 ldw r2,-4(fp) - 1724: 1085883a add r2,r2,r2 - 1728: e085883a add r2,fp,r2 - 172c: 10bff70b ldhu r2,-36(r2) - 1730: 10ffffcc andi r3,r2,65535 - 1734: 00a000b4 movhi r2,32770 - 1738: 10c00d35 stwio r3,52(r2) - 173c: e0bfff17 ldw r2,-4(fp) - 1740: 10800044 addi r2,r2,1 - 1744: e0bfff15 stw r2,-4(fp) - 1748: e0bfff17 ldw r2,-4(fp) - 174c: 10800410 cmplti r2,r2,16 - 1750: 103ff01e bne r2,zero,1714 - 1754: 01000074 movhi r4,1 - 1758: 21245104 addi r4,r4,-28348 - 175c: 0004bcc0 call 4bcc - 1760: 0001883a nop - 1764: e037883a mov sp,fp - 1768: dfc00117 ldw ra,4(sp) - 176c: df000017 ldw fp,0(sp) - 1770: dec00204 addi sp,sp,8 - 1774: f800283a ret - -00001778 : - 1778: defffe04 addi sp,sp,-8 - 177c: dfc00115 stw ra,4(sp) - 1780: df000015 stw fp,0(sp) - 1784: d839883a mov fp,sp - 1788: 01000074 movhi r4,1 - 178c: 21249804 addi r4,r4,-28064 - 1790: 0004bcc0 call 4bcc - 1794: 01000074 movhi r4,1 - 1798: 2124a504 addi r4,r4,-28012 - 179c: 0004bcc0 call 4bcc + c38: 21402435 stwio r5,144(r4) + c3c: 010000b4 movhi r4,2 + c40: 21002437 ldwio r4,144(r4) + c44: e13ffc15 stw r4,-16(fp) + c48: 010000b4 movhi r4,2 + c4c: 21002537 ldwio r4,148(r4) + c50: e13ffb15 stw r4,-20(fp) + c54: e13ffb17 ldw r4,-20(fp) + c58: 2008943a slli r4,r4,16 + c5c: e17ffc17 ldw r5,-16(fp) + c60: 2908b03a or r4,r5,r4 + c64: e13ffa15 stw r4,-24(fp) + c68: 01000074 movhi r4,1 + c6c: 21307417 ldw r4,-15920(r4) + c70: e13ff915 stw r4,-28(fp) + c74: e17ffd17 ldw r5,-12(fp) + c78: e13ff917 ldw r4,-28(fp) + c7c: 293fe91e bne r5,r4,c24 + c80: e13ffd17 ldw r4,-12(fp) + c84: 2005883a mov r2,r4 + c88: 0007883a mov r3,zero + c8c: 01b0d414 movui r6,50000 + c90: 000f883a mov r7,zero + c94: 1009883a mov r4,r2 + c98: 180b883a mov r5,r3 + c9c: 0003cec0 call 3cec <__muldi3> + ca0: 1009883a mov r4,r2 + ca4: 180b883a mov r5,r3 + ca8: e13ff715 stw r4,-36(fp) + cac: e17ff815 stw r5,-32(fp) + cb0: 00f0d3d4 movui r3,49999 + cb4: e0bffa17 ldw r2,-24(fp) + cb8: 1885c83a sub r2,r3,r2 + cbc: 1021883a mov r16,r2 + cc0: 0023883a mov r17,zero + cc4: e13ff717 ldw r4,-36(fp) + cc8: e17ff817 ldw r5,-32(fp) + ccc: 2405883a add r2,r4,r16 + cd0: 110d803a cmpltu r6,r2,r4 + cd4: 2c47883a add r3,r5,r17 + cd8: 30c9883a add r4,r6,r3 + cdc: 2007883a mov r3,r4 + ce0: e0bff715 stw r2,-36(fp) + ce4: e0fff815 stw r3,-32(fp) + ce8: e0bff717 ldw r2,-36(fp) + cec: e0fff817 ldw r3,-32(fp) + cf0: 1009883a mov r4,r2 + cf4: 180b883a mov r5,r3 + cf8: 2005883a mov r2,r4 + cfc: 2807883a mov r3,r5 + d00: e6fffe04 addi sp,fp,-8 + d04: dfc00317 ldw ra,12(sp) + d08: df000217 ldw fp,8(sp) + d0c: dc400117 ldw r17,4(sp) + d10: dc000017 ldw r16,0(sp) + d14: dec00404 addi sp,sp,16 + d18: f800283a ret + +00000d1c : + d1c: defffb04 addi sp,sp,-20 + d20: dfc00415 stw ra,16(sp) + d24: df000315 stw fp,12(sp) + d28: df000304 addi fp,sp,12 + d2c: 2005883a mov r2,r4 + d30: 2807883a mov r3,r5 + d34: e0bffe05 stb r2,-8(fp) + d38: 1805883a mov r2,r3 + d3c: e0bffd05 stb r2,-12(fp) + d40: e0bffe03 ldbu r2,-8(fp) + d44: e0bfff85 stb r2,-2(fp) + d48: e0bffd03 ldbu r2,-12(fp) + d4c: e0bfffc5 stb r2,-1(fp) + d50: d0a0d817 ldw r2,-31904(gp) + d54: 01400e44 movi r5,57 + d58: 1009883a mov r4,r2 + d5c: 00084a00 call 84a0 + d60: d0a0d817 ldw r2,-31904(gp) + d64: e0ffff84 addi r3,fp,-2 + d68: 000f883a mov r7,zero + d6c: 01800084 movi r6,2 + d70: 180b883a mov r5,r3 + d74: 1009883a mov r4,r2 + d78: 00086a00 call 86a0 + d7c: 0001883a nop + d80: e037883a mov sp,fp + d84: dfc00117 ldw ra,4(sp) + d88: df000017 ldw fp,0(sp) + d8c: dec00204 addi sp,sp,8 + d90: f800283a ret + +00000d94 : + d94: defff904 addi sp,sp,-28 + d98: dfc00615 stw ra,24(sp) + d9c: df000515 stw fp,20(sp) + da0: df000504 addi fp,sp,20 + da4: 0080fa04 movi r2,1000 + da8: e0bfff15 stw r2,-4(fp) + dac: 01000074 movhi r4,1 + db0: 212ba804 addi r4,r4,-20832 + db4: 0006cb00 call 6cb0 + db8: 00000c06 br dec + dbc: 0100fa04 movi r4,1000 + dc0: 00077480 call 7748 + dc4: e0bfff17 ldw r2,-4(fp) + dc8: 10bfffc4 addi r2,r2,-1 + dcc: e0bfff15 stw r2,-4(fp) + dd0: e0bfff17 ldw r2,-4(fp) + dd4: 1000051e bne r2,zero,dec + dd8: 01000074 movhi r4,1 + ddc: 212bb104 addi r4,r4,-20796 + de0: 0006cb00 call 6cb0 + de4: 00bfffc4 movi r2,-1 + de8: 00004c06 br f1c + dec: 008000b4 movhi r2,2 + df0: 10800437 ldwio r2,16(r2) + df4: 103ff126 beq r2,zero,dbc + df8: 01000074 movhi r4,1 + dfc: 212bbd04 addi r4,r4,-20748 + e00: 0006cb00 call 6cb0 + e04: 01000074 movhi r4,1 + e08: 212bcb04 addi r4,r4,-20692 + e0c: 0007cc40 call 7cc4 + e10: d0a0d815 stw r2,-31904(gp) + e14: d0a0d817 ldw r2,-31904(gp) + e18: 1000071e bne r2,zero,e38 + e1c: 01400074 movhi r5,1 + e20: 296bcb04 addi r5,r5,-20692 + e24: 01000074 movhi r4,1 + e28: 212bcf04 addi r4,r4,-20676 + e2c: 0006bc80 call 6bc8 + e30: 00bfff84 movi r2,-2 + e34: 00003906 br f1c + e38: d0a0d817 ldw r2,-31904(gp) + e3c: e0fffb04 addi r3,fp,-20 + e40: 180b883a mov r5,r3 + e44: 1009883a mov r4,r2 + e48: 0007de80 call 7de8 + e4c: d0a0d817 ldw r2,-31904(gp) + e50: e0fffb04 addi r3,fp,-20 + e54: 018000b4 movhi r6,2 + e58: 31a1a804 addi r6,r6,-31072 + e5c: 180b883a mov r5,r3 + e60: 1009883a mov r4,r2 + e64: 0007ff80 call 7ff8 + e68: d0a0d817 ldw r2,-31904(gp) + e6c: e0fffb04 addi r3,fp,-20 + e70: 180b883a mov r5,r3 + e74: 1009883a mov r4,r2 + e78: 0007e980 call 7e98 + e7c: 01400404 movi r5,16 + e80: 01001044 movi r4,65 + e84: 0000d1c0 call d1c + e88: 000b883a mov r5,zero + e8c: 01000584 movi r4,22 + e90: 0000d1c0 call d1c + e94: 01400184 movi r5,6 + e98: 01002bc4 movi r4,175 + e9c: 0000d1c0 call d1c + ea0: 01400604 movi r5,24 + ea4: 01000f04 movi r4,60 + ea8: 0000d1c0 call d1c + eac: 014000c4 movi r5,3 + eb0: 01002604 movi r4,152 + eb4: 0000d1c0 call d1c + eb8: 01403804 movi r5,224 + ebc: 01002684 movi r4,154 + ec0: 0000d1c0 call d1c + ec4: 01400c04 movi r5,48 + ec8: 01002704 movi r4,156 + ecc: 0000d1c0 call d1c + ed0: 01401844 movi r5,97 + ed4: 01002744 movi r4,157 + ed8: 0000d1c0 call d1c + edc: 01402904 movi r5,164 + ee0: 01002884 movi r4,162 + ee4: 0000d1c0 call d1c + ee8: 01402904 movi r5,164 + eec: 010028c4 movi r4,163 + ef0: 0000d1c0 call d1c + ef4: 01403404 movi r5,208 + ef8: 01003804 movi r4,224 + efc: 0000d1c0 call d1c + f00: 000b883a mov r5,zero + f04: 01003e44 movi r4,249 + f08: 0000d1c0 call d1c + f0c: 01000074 movhi r4,1 + f10: 212bd904 addi r4,r4,-20636 + f14: 0006cb00 call 6cb0 + f18: 0005883a mov r2,zero + f1c: e037883a mov sp,fp + f20: dfc00117 ldw ra,4(sp) + f24: df000017 ldw fp,0(sp) + f28: dec00204 addi sp,sp,8 + f2c: f800283a ret + +00000f30 : + f30: deffee04 addi sp,sp,-72 + f34: dfc01115 stw ra,68(sp) + f38: df001015 stw fp,64(sp) + f3c: df001004 addi fp,sp,64 + f40: 01000074 movhi r4,1 + f44: 212be504 addi r4,r4,-20588 + f48: 0006bc80 call 6bc8 + f4c: 00a20034 movhi r2,34816 + f50: e0bffc15 stw r2,-16(fp) + f54: e0bffc17 ldw r2,-16(fp) + f58: 100b883a mov r5,r2 + f5c: 01000074 movhi r4,1 + f60: 212bf104 addi r4,r4,-20540 + f64: 0006bc80 call 6bc8 + f68: 0080f004 movi r2,960 + f6c: e0bffb15 stw r2,-20(fp) + f70: 00808704 movi r2,540 + f74: e0bffa15 stw r2,-24(fp) + f78: e0bffb17 ldw r2,-20(fp) + f7c: 1000010e bge r2,zero,f84 + f80: 108001c4 addi r2,r2,7 + f84: 1005d0fa srai r2,r2,3 + f88: e0bff915 stw r2,-28(fp) + f8c: 00804034 movhi r2,256 + f90: 10bfffc4 addi r2,r2,-1 + f94: e0bff015 stw r2,-64(fp) + f98: 00804034 movhi r2,256 + f9c: 10bfc004 addi r2,r2,-256 + fa0: e0bff115 stw r2,-60(fp) + fa4: 00bfffd4 movui r2,65535 + fa8: e0bff215 stw r2,-56(fp) + fac: 00bfc014 movui r2,65280 + fb0: e0bff315 stw r2,-52(fp) + fb4: 00803ff4 movhi r2,255 + fb8: 10803fc4 addi r2,r2,255 + fbc: e0bff415 stw r2,-48(fp) + fc0: 00803ff4 movhi r2,255 + fc4: e0bff515 stw r2,-44(fp) + fc8: 00803fc4 movi r2,255 + fcc: e0bff615 stw r2,-40(fp) + fd0: e03ff715 stw zero,-36(fp) + fd4: e03fff15 stw zero,-4(fp) + fd8: 00002106 br 1060 + fdc: e03ffe15 stw zero,-8(fp) + fe0: 00001906 br 1048 + fe4: e17ff917 ldw r5,-28(fp) + fe8: e13ffe17 ldw r4,-8(fp) + fec: 00043500 call 4350 <__divsi3> + ff0: e0bffd15 stw r2,-12(fp) + ff4: e0bffd17 ldw r2,-12(fp) + ff8: 10800210 cmplti r2,r2,8 + ffc: 1000021e bne r2,zero,1008 + 1000: 008001c4 movi r2,7 + 1004: e0bffd15 stw r2,-12(fp) + 1008: e0ffff17 ldw r3,-4(fp) + 100c: e0bffb17 ldw r2,-20(fp) + 1010: 1887383a mul r3,r3,r2 + 1014: e0bffe17 ldw r2,-8(fp) + 1018: 1885883a add r2,r3,r2 + 101c: 100490ba slli r2,r2,2 + 1020: e0fffc17 ldw r3,-16(fp) + 1024: 1885883a add r2,r3,r2 + 1028: e0fffd17 ldw r3,-12(fp) + 102c: 180690ba slli r3,r3,2 + 1030: e0c7883a add r3,fp,r3 + 1034: 18fff017 ldw r3,-64(r3) + 1038: 10c00015 stw r3,0(r2) + 103c: e0bffe17 ldw r2,-8(fp) + 1040: 10800044 addi r2,r2,1 + 1044: e0bffe15 stw r2,-8(fp) + 1048: e0fffe17 ldw r3,-8(fp) + 104c: e0bffb17 ldw r2,-20(fp) + 1050: 18bfe416 blt r3,r2,fe4 + 1054: e0bfff17 ldw r2,-4(fp) + 1058: 10800044 addi r2,r2,1 + 105c: e0bfff15 stw r2,-4(fp) + 1060: e0ffff17 ldw r3,-4(fp) + 1064: e0bffa17 ldw r2,-24(fp) + 1068: 18bfdc16 blt r3,r2,fdc + 106c: 00073e80 call 73e8 + 1070: e0fffb17 ldw r3,-20(fp) + 1074: e0bffa17 ldw r2,-24(fp) + 1078: 1885383a mul r2,r3,r2 + 107c: 100b883a mov r5,r2 + 1080: 01000074 movhi r4,1 + 1084: 212c0004 addi r4,r4,-20480 + 1088: 0006bc80 call 6bc8 + 108c: e0bffc17 ldw r2,-16(fp) + 1090: e0bff815 stw r2,-32(fp) + 1094: e0fffc17 ldw r3,-16(fp) + 1098: e0bff817 ldw r2,-32(fp) + 109c: 10800017 ldw r2,0(r2) + 10a0: 100f883a mov r7,r2 + 10a4: 01804034 movhi r6,256 + 10a8: 31bfffc4 addi r6,r6,-1 + 10ac: 180b883a mov r5,r3 + 10b0: 01000074 movhi r4,1 + 10b4: 212c0904 addi r4,r4,-20444 + 10b8: 0006bc80 call 6bc8 + 10bc: e0bffb17 ldw r2,-20(fp) + 10c0: 1000010e bge r2,zero,10c8 + 10c4: 108001c4 addi r2,r2,7 + 10c8: 1005d0fa srai r2,r2,3 + 10cc: 100490ba slli r2,r2,2 + 10d0: e0fffc17 ldw r3,-16(fp) + 10d4: 1885883a add r2,r3,r2 + 10d8: 1009883a mov r4,r2 + 10dc: e0bffb17 ldw r2,-20(fp) + 10e0: 1000010e bge r2,zero,10e8 + 10e4: 108001c4 addi r2,r2,7 + 10e8: 1005d0fa srai r2,r2,3 + 10ec: 100490ba slli r2,r2,2 + 10f0: e0fff817 ldw r3,-32(fp) + 10f4: 1885883a add r2,r3,r2 + 10f8: 10800017 ldw r2,0(r2) + 10fc: 100d883a mov r6,r2 + 1100: 200b883a mov r5,r4 + 1104: 01000074 movhi r4,1 + 1108: 212c1604 addi r4,r4,-20392 + 110c: 0006bc80 call 6bc8 + 1110: 0001883a nop + 1114: e037883a mov sp,fp + 1118: dfc00117 ldw ra,4(sp) + 111c: df000017 ldw fp,0(sp) + 1120: dec00204 addi sp,sp,8 + 1124: f800283a ret + +00001128 : + 1128: defffd04 addi sp,sp,-12 + 112c: dfc00215 stw ra,8(sp) + 1130: df000115 stw fp,4(sp) + 1134: df000104 addi fp,sp,4 + 1138: 01000074 movhi r4,1 + 113c: 212c2404 addi r4,r4,-20336 + 1140: 0006cb00 call 6cb0 + 1144: d0a0d917 ldw r2,-31900(gp) + 1148: 10000326 beq r2,zero,1158 + 114c: 00800074 movhi r2,1 + 1150: 10ac2d04 addi r2,r2,-20300 + 1154: 00000206 br 1160 + 1158: 00800074 movhi r2,1 + 115c: 10ac2e04 addi r2,r2,-20296 + 1160: 100b883a mov r5,r2 + 1164: 01000074 movhi r4,1 + 1168: 212c2f04 addi r4,r4,-20292 + 116c: 0006bc80 call 6bc8 + 1170: 01000074 movhi r4,1 + 1174: 212c3804 addi r4,r4,-20256 + 1178: 0006cb00 call 6cb0 + 117c: 01000074 movhi r4,1 + 1180: 212c4004 addi r4,r4,-20224 + 1184: 0006cb00 call 6cb0 + 1188: 01000074 movhi r4,1 + 118c: 212c4804 addi r4,r4,-20192 + 1190: 0006cb00 call 6cb0 + 1194: 01000074 movhi r4,1 + 1198: 212c5404 addi r4,r4,-20144 + 119c: 0006cb00 call 6cb0 + 11a0: 01000074 movhi r4,1 + 11a4: 212c5a04 addi r4,r4,-20120 + 11a8: 0006bc80 call 6bc8 + 11ac: 0000b940 call b94 + 11b0: e0bfffc5 stb r2,-1(fp) + 11b4: e0bfffc7 ldb r2,-1(fp) + 11b8: 100b883a mov r5,r2 + 11bc: 01000074 movhi r4,1 + 11c0: 212c5e04 addi r4,r4,-20104 + 11c4: 0006bc80 call 6bc8 + 11c8: e0bfffc7 ldb r2,-1(fp) + 11cc: 10801898 cmpnei r2,r2,98 + 11d0: 10001c26 beq r2,zero,1244 + 11d4: e0bfffc7 ldb r2,-1(fp) + 11d8: 10800c58 cmpnei r2,r2,49 + 11dc: 1000081e bne r2,zero,1200 + 11e0: d0a0d917 ldw r2,-31900(gp) + 11e4: 1005003a cmpeq r2,r2,zero + 11e8: 10803fcc andi r2,r2,255 + 11ec: d0a0d915 stw r2,-31900(gp) + 11f0: d0a0d917 ldw r2,-31900(gp) + 11f4: 1009883a mov r4,r2 + 11f8: 00015540 call 1554 + 11fc: 003fce06 br 1138 + 1200: e0bfffc7 ldb r2,-1(fp) + 1204: 10800c98 cmpnei r2,r2,50 + 1208: 1000041e bne r2,zero,121c + 120c: 01100374 movhi r4,16397 + 1210: 21333344 addi r4,r4,-13107 + 1214: 00013800 call 1380 + 1218: 003fc706 br 1138 + 121c: e0bfffc7 ldb r2,-1(fp) + 1220: 10800cd8 cmpnei r2,r2,51 + 1224: 1000021e bne r2,zero,1230 + 1228: 00015ec0 call 15ec + 122c: 003fc206 br 1138 + 1230: e0bfffc7 ldb r2,-1(fp) + 1234: 10800d18 cmpnei r2,r2,52 + 1238: 103fbf1e bne r2,zero,1138 + 123c: 00018000 call 1800 + 1240: 003fbd06 br 1138 + 1244: 0001883a nop + 1248: 0001883a nop + 124c: e037883a mov sp,fp + 1250: dfc00117 ldw ra,4(sp) + 1254: df000017 ldw fp,0(sp) + 1258: dec00204 addi sp,sp,8 + 125c: f800283a ret + +00001260 : + 1260: defffc04 addi sp,sp,-16 + 1264: dfc00315 stw ra,12(sp) + 1268: df000215 stw fp,8(sp) + 126c: df000204 addi fp,sp,8 + 1270: 01000074 movhi r4,1 + 1274: 212c5f04 addi r4,r4,-20100 + 1278: 0006cb00 call 6cb0 + 127c: 01000074 movhi r4,1 + 1280: 212c6604 addi r4,r4,-20072 + 1284: 0006cb00 call 6cb0 + 1288: 01000074 movhi r4,1 + 128c: 212c6a04 addi r4,r4,-20056 + 1290: 0006cb00 call 6cb0 + 1294: 01000074 movhi r4,1 + 1298: 212c6f04 addi r4,r4,-20036 + 129c: 0006cb00 call 6cb0 + 12a0: 01000074 movhi r4,1 + 12a4: 212c7304 addi r4,r4,-20020 + 12a8: 0006cb00 call 6cb0 + 12ac: 01000074 movhi r4,1 + 12b0: 212c7804 addi r4,r4,-20000 + 12b4: 0006cb00 call 6cb0 + 12b8: 01000074 movhi r4,1 + 12bc: 212c7d04 addi r4,r4,-19980 + 12c0: 0006cb00 call 6cb0 + 12c4: 01000074 movhi r4,1 + 12c8: 212c8204 addi r4,r4,-19960 + 12cc: 0006cb00 call 6cb0 + 12d0: 01000074 movhi r4,1 + 12d4: 212c8804 addi r4,r4,-19936 + 12d8: 0006cb00 call 6cb0 + 12dc: 01000074 movhi r4,1 + 12e0: 212c5404 addi r4,r4,-20144 + 12e4: 0006cb00 call 6cb0 + 12e8: 01000074 movhi r4,1 + 12ec: 212c5a04 addi r4,r4,-20120 + 12f0: 0006bc80 call 6bc8 + 12f4: 0000b940 call b94 + 12f8: e0bfffc5 stb r2,-1(fp) + 12fc: e0bfffc7 ldb r2,-1(fp) + 1300: 100b883a mov r5,r2 + 1304: 01000074 movhi r4,1 + 1308: 212c5e04 addi r4,r4,-20104 + 130c: 0006bc80 call 6bc8 + 1310: e0bfffc7 ldb r2,-1(fp) + 1314: 10801898 cmpnei r2,r2,98 + 1318: 10001226 beq r2,zero,1364 + 131c: e0bfffc7 ldb r2,-1(fp) + 1320: 10bff404 addi r2,r2,-48 + 1324: e0bffe15 stw r2,-8(fp) + 1328: e0bffe17 ldw r2,-8(fp) + 132c: 10800228 cmpgeui r2,r2,8 + 1330: 1000081e bne r2,zero,1354 + 1334: e0fffe17 ldw r3,-8(fp) + 1338: 00a000b4 movhi r2,32770 + 133c: 10c00835 stwio r3,32(r2) + 1340: e17ffe17 ldw r5,-8(fp) + 1344: 01000074 movhi r4,1 + 1348: 212c9104 addi r4,r4,-19900 + 134c: 0006bc80 call 6bc8 + 1350: 003fc706 br 1270 + 1354: 01000074 movhi r4,1 + 1358: 212c9704 addi r4,r4,-19876 + 135c: 0006cb00 call 6cb0 + 1360: 003fc306 br 1270 + 1364: 0001883a nop + 1368: 0001883a nop + 136c: e037883a mov sp,fp + 1370: dfc00117 ldw ra,4(sp) + 1374: df000017 ldw fp,0(sp) + 1378: dec00204 addi sp,sp,8 + 137c: f800283a ret + +00001380 : + 1380: defff504 addi sp,sp,-44 + 1384: dfc00a15 stw ra,40(sp) + 1388: df000915 stw fp,36(sp) + 138c: df000904 addi fp,sp,36 + 1390: e13ff715 stw r4,-36(fp) + 1394: e13ff717 ldw r4,-36(fp) + 1398: 0006a080 call 6a08 <__extendsfdf2> + 139c: 100d883a mov r6,r2 + 13a0: 180f883a mov r7,r3 + 13a4: 300b883a mov r5,r6 + 13a8: 380d883a mov r6,r7 + 13ac: 01000074 movhi r4,1 + 13b0: 212ca404 addi r4,r4,-19824 + 13b4: 0006bc80 call 6bc8 + 13b8: 014f7374 movhi r5,15821 + 13bc: 29733344 addi r5,r5,-13107 + 13c0: e13ff717 ldw r4,-36(fp) + 13c4: 00045040 call 4504 <__lesf2> + 13c8: 00800316 blt zero,r2,13d8 + 13cc: 00900374 movhi r2,16397 + 13d0: 10b33344 addi r2,r2,-13107 + 13d4: e0bff715 stw r2,-36(fp) + 13d8: e13ff717 ldw r4,-36(fp) + 13dc: 0006a080 call 6a08 <__extendsfdf2> + 13e0: 1009883a mov r4,r2 + 13e4: 180b883a mov r5,r3 + 13e8: 200d883a mov r6,r4 + 13ec: 280f883a mov r7,r5 + 13f0: 0009883a mov r4,zero + 13f4: 014ffc34 movhi r5,16368 + 13f8: 0004ea80 call 4ea8 <__divdf3> + 13fc: 1009883a mov r4,r2 + 1400: 180b883a mov r5,r3 + 1404: e13ffd15 stw r4,-12(fp) + 1408: e17ffe15 stw r5,-8(fp) + 140c: e03fff15 stw zero,-4(fp) + 1410: 00004406 br 1524 + 1414: e13fff17 ldw r4,-4(fp) + 1418: 00069500 call 6950 <__floatsidf> + 141c: 1011883a mov r8,r2 + 1420: 1813883a mov r9,r3 + 1424: 000d883a mov r6,zero + 1428: 01d01c34 movhi r7,16496 + 142c: 39f80004 addi r7,r7,-8192 + 1430: 4009883a mov r4,r8 + 1434: 480b883a mov r5,r9 + 1438: 0004ea80 call 4ea8 <__divdf3> + 143c: 1009883a mov r4,r2 + 1440: 180b883a mov r5,r3 + 1444: e13ffb15 stw r4,-20(fp) + 1448: e17ffc15 stw r5,-16(fp) + 144c: e1bffd17 ldw r6,-12(fp) + 1450: e1fffe17 ldw r7,-8(fp) + 1454: e13ffb17 ldw r4,-20(fp) + 1458: e17ffc17 ldw r5,-16(fp) + 145c: 000228c0 call 228c + 1460: e0bff915 stw r2,-28(fp) + 1464: e0fffa15 stw r3,-24(fp) + 1468: 000d883a mov r6,zero + 146c: 01d01c34 movhi r7,16496 + 1470: 39f80004 addi r7,r7,-8192 + 1474: e13ff917 ldw r4,-28(fp) + 1478: e17ffa17 ldw r5,-24(fp) + 147c: 00059540 call 5954 <__muldf3> + 1480: 1009883a mov r4,r2 + 1484: 180b883a mov r5,r3 + 1488: 2005883a mov r2,r4 + 148c: 2807883a mov r3,r5 + 1490: 000d883a mov r6,zero + 1494: 01cff834 movhi r7,16352 + 1498: 1009883a mov r4,r2 + 149c: 180b883a mov r5,r3 + 14a0: 00045b80 call 45b8 <__adddf3> + 14a4: 1009883a mov r4,r2 + 14a8: 180b883a mov r5,r3 + 14ac: 2005883a mov r2,r4 + 14b0: 2807883a mov r3,r5 + 14b4: 1009883a mov r4,r2 + 14b8: 180b883a mov r5,r3 + 14bc: 0003d4c0 call 3d4c <__fixunsdfsi> + 14c0: e0bff8c5 stb r2,-29(fp) + 14c4: e0ffff17 ldw r3,-4(fp) + 14c8: 00a000b4 movhi r2,32770 + 14cc: 10c00a35 stwio r3,40(r2) + 14d0: 01000284 movi r4,10 + 14d4: 00077480 call 7748 + 14d8: e0fff8c3 ldbu r3,-29(fp) + 14dc: 00a000b4 movhi r2,32770 + 14e0: 10c00b35 stwio r3,44(r2) + 14e4: 01000284 movi r4,10 + 14e8: 00077480 call 7748 + 14ec: e0bff8c3 ldbu r2,-29(fp) + 14f0: 100b883a mov r5,r2 + 14f4: 01000074 movhi r4,1 + 14f8: 212cb204 addi r4,r4,-19768 + 14fc: 0006bc80 call 6bc8 + 1500: e0bfff17 ldw r2,-4(fp) + 1504: 10800044 addi r2,r2,1 + 1508: 108003cc andi r2,r2,15 + 150c: 1000021e bne r2,zero,1518 + 1510: 01000284 movi r4,10 + 1514: 0006c180 call 6c18 + 1518: e0bfff17 ldw r2,-4(fp) + 151c: 10800044 addi r2,r2,1 + 1520: e0bfff15 stw r2,-4(fp) + 1524: e0bfff17 ldw r2,-4(fp) + 1528: 10804010 cmplti r2,r2,256 + 152c: 103fb91e bne r2,zero,1414 + 1530: 01000074 movhi r4,1 + 1534: 212cb404 addi r4,r4,-19760 + 1538: 0006cb00 call 6cb0 + 153c: 0001883a nop + 1540: e037883a mov sp,fp + 1544: dfc00117 ldw ra,4(sp) + 1548: df000017 ldw fp,0(sp) + 154c: dec00204 addi sp,sp,8 + 1550: f800283a ret + +00001554 : + 1554: defffc04 addi sp,sp,-16 + 1558: dfc00315 stw ra,12(sp) + 155c: df000215 stw fp,8(sp) + 1560: df000204 addi fp,sp,8 + 1564: e13ffe15 stw r4,-8(fp) + 1568: 00a000b4 movhi r2,32770 + 156c: 10800937 ldwio r2,36(r2) + 1570: e0bfff15 stw r2,-4(fp) + 1574: e0bffe17 ldw r2,-8(fp) + 1578: 10000426 beq r2,zero,158c + 157c: e0bfff17 ldw r2,-4(fp) + 1580: 10800054 ori r2,r2,1 + 1584: e0bfff15 stw r2,-4(fp) + 1588: 00000406 br 159c + 158c: e0ffff17 ldw r3,-4(fp) + 1590: 00bfff84 movi r2,-2 + 1594: 1884703a and r2,r3,r2 + 1598: e0bfff15 stw r2,-4(fp) + 159c: e0ffff17 ldw r3,-4(fp) + 15a0: 00a000b4 movhi r2,32770 + 15a4: 10c00935 stwio r3,36(r2) + 15a8: e0bffe17 ldw r2,-8(fp) + 15ac: 10000326 beq r2,zero,15bc + 15b0: 00800074 movhi r2,1 + 15b4: 10acb604 addi r2,r2,-19752 + 15b8: 00000206 br 15c4 + 15bc: 00800074 movhi r2,1 + 15c0: 10acb804 addi r2,r2,-19744 + 15c4: 100b883a mov r5,r2 + 15c8: 01000074 movhi r4,1 + 15cc: 212cbb04 addi r4,r4,-19732 + 15d0: 0006bc80 call 6bc8 + 15d4: 0001883a nop + 15d8: e037883a mov sp,fp + 15dc: dfc00117 ldw ra,4(sp) + 15e0: df000017 ldw fp,0(sp) + 15e4: dec00204 addi sp,sp,8 + 15e8: f800283a ret + +000015ec : + 15ec: defff804 addi sp,sp,-32 + 15f0: dfc00715 stw ra,28(sp) + 15f4: df000615 stw fp,24(sp) + 15f8: df000604 addi fp,sp,24 + 15fc: 01000074 movhi r4,1 + 1600: 212cc104 addi r4,r4,-19708 + 1604: 0006cb00 call 6cb0 + 1608: e03fff15 stw zero,-4(fp) + 160c: 00007006 br 17d0 + 1610: e13fff17 ldw r4,-4(fp) + 1614: 00069500 call 6950 <__floatsidf> + 1618: 1011883a mov r8,r2 + 161c: 1813883a mov r9,r3 + 1620: 000d883a mov r6,zero + 1624: 01d01c34 movhi r7,16496 + 1628: 39f80004 addi r7,r7,-8192 + 162c: 4009883a mov r4,r8 + 1630: 480b883a mov r5,r9 + 1634: 0004ea80 call 4ea8 <__divdf3> + 1638: 1009883a mov r4,r2 + 163c: 180b883a mov r5,r3 + 1640: e13ffb15 stw r4,-20(fp) + 1644: e17ffc15 stw r5,-16(fp) + 1648: 019ce234 movhi r6,29576 + 164c: 31adc644 addi r6,r6,-18663 + 1650: 01cfdab4 movhi r7,16234 + 1654: 39e970c4 addi r7,r7,-23101 + 1658: e13ffb17 ldw r4,-20(fp) + 165c: e17ffc17 ldw r5,-16(fp) + 1660: 000586c0 call 586c <__ledf2> + 1664: 00800c16 blt zero,r2,1698 + 1668: 018f5c74 movhi r6,15729 + 166c: 31a8f5c4 addi r6,r6,-23593 + 1670: 01d00ab4 movhi r7,16426 + 1674: 39f5c284 addi r7,r7,-10486 + 1678: e13ffb17 ldw r4,-20(fp) + 167c: e17ffc17 ldw r5,-16(fp) + 1680: 00059540 call 5954 <__muldf3> + 1684: 1009883a mov r4,r2 + 1688: 180b883a mov r5,r3 + 168c: e13ffd15 stw r4,-12(fp) + 1690: e17ffe15 stw r5,-8(fp) + 1694: 00001f06 br 1714 + 1698: 01aaaaf4 movhi r6,43691 + 169c: 31aaaac4 addi r6,r6,-21845 + 16a0: 01cff6f4 movhi r7,16347 + 16a4: 39eaaa84 addi r7,r7,-21846 + 16a8: e13ffb17 ldw r4,-20(fp) + 16ac: e17ffc17 ldw r5,-16(fp) + 16b0: 000228c0 call 228c + 16b4: 1011883a mov r8,r2 + 16b8: 1813883a mov r9,r3 + 16bc: 01ab8534 movhi r6,44564 + 16c0: 319eb844 addi r6,r6,31457 + 16c4: 01cffc74 movhi r7,16369 + 16c8: 39f851c4 addi r7,r7,-7865 + 16cc: 4009883a mov r4,r8 + 16d0: 480b883a mov r5,r9 + 16d4: 00059540 call 5954 <__muldf3> + 16d8: 1009883a mov r4,r2 + 16dc: 180b883a mov r5,r3 + 16e0: 2005883a mov r2,r4 + 16e4: 2807883a mov r3,r5 + 16e8: 01b0a3f4 movhi r6,49807 + 16ec: 31970a44 addi r6,r6,23593 + 16f0: 01cfeb34 movhi r7,16300 + 16f4: 39ca3d44 addi r7,r7,10485 + 16f8: 1009883a mov r4,r2 + 16fc: 180b883a mov r5,r3 + 1700: 0005fc80 call 5fc8 <__subdf3> + 1704: 1009883a mov r4,r2 + 1708: 180b883a mov r5,r3 + 170c: e13ffd15 stw r4,-12(fp) + 1710: e17ffe15 stw r5,-8(fp) + 1714: 000d883a mov r6,zero + 1718: 01d01c34 movhi r7,16496 + 171c: 39f80004 addi r7,r7,-8192 + 1720: e13ffd17 ldw r4,-12(fp) + 1724: e17ffe17 ldw r5,-8(fp) + 1728: 00059540 call 5954 <__muldf3> + 172c: 1009883a mov r4,r2 + 1730: 180b883a mov r5,r3 + 1734: 2005883a mov r2,r4 + 1738: 2807883a mov r3,r5 + 173c: 000d883a mov r6,zero + 1740: 01cff834 movhi r7,16352 + 1744: 1009883a mov r4,r2 + 1748: 180b883a mov r5,r3 + 174c: 00045b80 call 45b8 <__adddf3> + 1750: 1009883a mov r4,r2 + 1754: 180b883a mov r5,r3 + 1758: 2005883a mov r2,r4 + 175c: 2807883a mov r3,r5 + 1760: 1009883a mov r4,r2 + 1764: 180b883a mov r5,r3 + 1768: 0003d4c0 call 3d4c <__fixunsdfsi> + 176c: e0bffac5 stb r2,-21(fp) + 1770: e0ffff17 ldw r3,-4(fp) + 1774: 00a000b4 movhi r2,32770 + 1778: 10c00a35 stwio r3,40(r2) + 177c: 01000284 movi r4,10 + 1780: 00077480 call 7748 + 1784: e0fffac3 ldbu r3,-21(fp) + 1788: 00a000b4 movhi r2,32770 + 178c: 10c00b35 stwio r3,44(r2) + 1790: 01000284 movi r4,10 + 1794: 00077480 call 7748 + 1798: e0bffac3 ldbu r2,-21(fp) + 179c: 100b883a mov r5,r2 17a0: 01000074 movhi r4,1 - 17a4: 2124af04 addi r4,r4,-27972 - 17a8: 0004bcc0 call 4bcc - 17ac: 01000074 movhi r4,1 - 17b0: 2124bb04 addi r4,r4,-27924 - 17b4: 0004bcc0 call 4bcc - 17b8: 01000074 movhi r4,1 - 17bc: 2124c504 addi r4,r4,-27884 - 17c0: 0004bcc0 call 4bcc - 17c4: 01000074 movhi r4,1 - 17c8: 2124d104 addi r4,r4,-27836 - 17cc: 0004bcc0 call 4bcc - 17d0: 01000074 movhi r4,1 - 17d4: 2124df04 addi r4,r4,-27780 - 17d8: 0004bcc0 call 4bcc + 17a4: 212cb204 addi r4,r4,-19768 + 17a8: 0006bc80 call 6bc8 + 17ac: e0bfff17 ldw r2,-4(fp) + 17b0: 10800044 addi r2,r2,1 + 17b4: 108003cc andi r2,r2,15 + 17b8: 1000021e bne r2,zero,17c4 + 17bc: 01000284 movi r4,10 + 17c0: 0006c180 call 6c18 + 17c4: e0bfff17 ldw r2,-4(fp) + 17c8: 10800044 addi r2,r2,1 + 17cc: e0bfff15 stw r2,-4(fp) + 17d0: e0bfff17 ldw r2,-4(fp) + 17d4: 10804010 cmplti r2,r2,256 + 17d8: 103f8d1e bne r2,zero,1610 17dc: 01000074 movhi r4,1 - 17e0: 2124ee04 addi r4,r4,-27720 - 17e4: 0004bcc0 call 4bcc - 17e8: 01000074 movhi r4,1 - 17ec: 2124f704 addi r4,r4,-27684 - 17f0: 0004bcc0 call 4bcc - 17f4: 01000074 movhi r4,1 - 17f8: 21250004 addi r4,r4,-27648 - 17fc: 0004bcc0 call 4bcc - 1800: 01000074 movhi r4,1 - 1804: 21250304 addi r4,r4,-27636 - 1808: 0004bcc0 call 4bcc - 180c: 01000074 movhi r4,1 - 1810: 21251004 addi r4,r4,-27584 - 1814: 0004ae40 call 4ae4 - 1818: 0001883a nop - 181c: e037883a mov sp,fp - 1820: dfc00117 ldw ra,4(sp) - 1824: df000017 ldw fp,0(sp) - 1828: dec00204 addi sp,sp,8 - 182c: f800283a ret - -00001830 : - 1830: defffd04 addi sp,sp,-12 - 1834: dfc00215 stw ra,8(sp) - 1838: df000115 stw fp,4(sp) - 183c: df000104 addi fp,sp,4 - 1840: 00017780 call 1778 - 1844: e03fffc5 stb zero,-1(fp) - 1848: 00000206 br 1854 - 184c: 0000b8c0 call b8c - 1850: e0bfffc5 stb r2,-1(fp) - 1854: e0bfffc7 ldb r2,-1(fp) - 1858: 10800810 cmplti r2,r2,32 - 185c: 103ffb1e bne r2,zero,184c - 1860: e0bfffc7 ldb r2,-1(fp) - 1864: 100b883a mov r5,r2 - 1868: 01000074 movhi r4,1 - 186c: 21251504 addi r4,r4,-27564 - 1870: 0004ae40 call 4ae4 - 1874: e0bfffc7 ldb r2,-1(fp) - 1878: 10bff3c4 addi r2,r2,-49 - 187c: 10c010a8 cmpgeui r3,r2,66 - 1880: 1800641e bne r3,zero,1a14 - 1884: 100690ba slli r3,r2,2 - 1888: 00800034 movhi r2,0 - 188c: 1885883a add r2,r3,r2 - 1890: 10862617 ldw r2,6296(r2) - 1894: 1000683a jmp r2 - 1898: 000019a0 cmpeqi zero,zero,102 - 189c: 000019b0 cmpltui zero,zero,102 - 18a0: 000019c0 call 19c - 18a4: 000019c8 cmpgei zero,zero,103 - 18a8: 000019d0 cmplti zero,zero,103 - 18ac: 000019d8 cmpnei zero,zero,103 - 18b0: 00001a14 movui zero,104 - 18b4: 00001a14 movui zero,104 - 18b8: 00001a14 movui zero,104 - 18bc: 00001a14 movui zero,104 - 18c0: 00001a14 movui zero,104 - 18c4: 00001a14 movui zero,104 - 18c8: 00001a14 movui zero,104 - 18cc: 00001a14 movui zero,104 - 18d0: 00001a14 movui zero,104 - 18d4: 00001a14 movui zero,104 - 18d8: 00001a14 movui zero,104 - 18dc: 00001a14 movui zero,104 - 18e0: 000019e0 cmpeqi zero,zero,103 - 18e4: 00001a14 movui zero,104 - 18e8: 00001a14 movui zero,104 - 18ec: 00001a14 movui zero,104 - 18f0: 00001a14 movui zero,104 - 18f4: 00001a14 movui zero,104 - 18f8: 00001a14 movui zero,104 - 18fc: 00001a14 movui zero,104 - 1900: 00001a14 movui zero,104 - 1904: 00001a14 movui zero,104 - 1908: 00001a14 movui zero,104 - 190c: 00001a14 movui zero,104 - 1910: 00001a14 movui zero,104 - 1914: 00001a14 movui zero,104 - 1918: 00001a14 movui zero,104 - 191c: 00001a14 movui zero,104 - 1920: 00001a14 movui zero,104 - 1924: 00001a14 movui zero,104 - 1928: 00001a14 movui zero,104 - 192c: 00001a14 movui zero,104 - 1930: 00001a14 movui zero,104 - 1934: 00001a14 movui zero,104 - 1938: 00001a14 movui zero,104 - 193c: 00001a14 movui zero,104 - 1940: 00001a14 movui zero,104 - 1944: 00001a14 movui zero,104 - 1948: 00001a14 movui zero,104 - 194c: 00001a14 movui zero,104 - 1950: 00001a14 movui zero,104 - 1954: 00001a14 movui zero,104 - 1958: 00001a14 movui zero,104 - 195c: 00001a14 movui zero,104 - 1960: 000019e0 cmpeqi zero,zero,103 - 1964: 00001a14 movui zero,104 - 1968: 00001a14 movui zero,104 - 196c: 00001a14 movui zero,104 - 1970: 00001a14 movui zero,104 - 1974: 00001a14 movui zero,104 - 1978: 00001a14 movui zero,104 - 197c: 00001a14 movui zero,104 - 1980: 00001a14 movui zero,104 - 1984: 00001a14 movui zero,104 - 1988: 00001a14 movui zero,104 - 198c: 00001a14 movui zero,104 - 1990: 00001a14 movui zero,104 - 1994: 00001a14 movui zero,104 - 1998: 00001a04 movi zero,104 - 199c: 000019e8 cmpgeui zero,zero,103 - 19a0: 012000b4 movhi r4,32770 - 19a4: 21002804 addi r4,r4,160 - 19a8: 00002840 call 284 - 19ac: 00001d06 br 1a24 - 19b0: 012000b4 movhi r4,32770 - 19b4: 21003004 addi r4,r4,192 - 19b8: 000069c0 call 69c - 19bc: 00001906 br 1a24 - 19c0: 0000d8c0 call d8c - 19c4: 00001706 br 1a24 - 19c8: 0000f280 call f28 - 19cc: 00001506 br 1a24 - 19d0: 00011c00 call 11c0 - 19d4: 00001306 br 1a24 - 19d8: 00010880 call 1088 - 19dc: 00001106 br 1a24 - 19e0: 00016d00 call 16d0 - 19e4: 00000f06 br 1a24 - 19e8: 0007883a mov r3,zero - 19ec: 00a000b4 movhi r2,32770 - 19f0: 10c00835 stwio r3,32(r2) - 19f4: 01000074 movhi r4,1 - 19f8: 21251604 addi r4,r4,-27560 - 19fc: 0004bcc0 call 4bcc - 1a00: 00000806 br 1a24 - 1a04: 01000074 movhi r4,1 - 1a08: 21251e04 addi r4,r4,-27528 - 1a0c: 0004bcc0 call 4bcc - 1a10: 00000506 br 1a28 - 1a14: 01000074 movhi r4,1 - 1a18: 21252304 addi r4,r4,-27508 - 1a1c: 0004bcc0 call 4bcc - 1a20: 0001883a nop - 1a24: 003f8606 br 1840 + 17e0: 212ccc04 addi r4,r4,-19664 + 17e4: 0006cb00 call 6cb0 + 17e8: 0001883a nop + 17ec: e037883a mov sp,fp + 17f0: dfc00117 ldw ra,4(sp) + 17f4: df000017 ldw fp,0(sp) + 17f8: dec00204 addi sp,sp,8 + 17fc: f800283a ret + +00001800 : + 1800: defff804 addi sp,sp,-32 + 1804: dfc00715 stw ra,28(sp) + 1808: df000615 stw fp,24(sp) + 180c: df000604 addi fp,sp,24 + 1810: 01000074 movhi r4,1 + 1814: 212cd104 addi r4,r4,-19644 + 1818: 0006cb00 call 6cb0 + 181c: e03fff15 stw zero,-4(fp) + 1820: 00003b06 br 1910 + 1824: e13fff17 ldw r4,-4(fp) + 1828: 00069500 call 6950 <__floatsidf> + 182c: 1011883a mov r8,r2 + 1830: 1813883a mov r9,r3 + 1834: 000d883a mov r6,zero + 1838: 01d01c34 movhi r7,16496 + 183c: 39f80004 addi r7,r7,-8192 + 1840: 4009883a mov r4,r8 + 1844: 480b883a mov r5,r9 + 1848: 0004ea80 call 4ea8 <__divdf3> + 184c: 1009883a mov r4,r2 + 1850: 180b883a mov r5,r3 + 1854: e13ffd15 stw r4,-12(fp) + 1858: e17ffe15 stw r5,-8(fp) + 185c: 01a666b4 movhi r6,39322 + 1860: 31a66684 addi r6,r6,-26214 + 1864: 01d000b4 movhi r7,16386 + 1868: 39e66644 addi r7,r7,-26215 + 186c: e13ffd17 ldw r4,-12(fp) + 1870: e17ffe17 ldw r5,-8(fp) + 1874: 000228c0 call 228c + 1878: e0bffb15 stw r2,-20(fp) + 187c: e0fffc15 stw r3,-16(fp) + 1880: 000d883a mov r6,zero + 1884: 01d01c34 movhi r7,16496 + 1888: 39f80004 addi r7,r7,-8192 + 188c: e13ffb17 ldw r4,-20(fp) + 1890: e17ffc17 ldw r5,-16(fp) + 1894: 00059540 call 5954 <__muldf3> + 1898: 1009883a mov r4,r2 + 189c: 180b883a mov r5,r3 + 18a0: 2005883a mov r2,r4 + 18a4: 2807883a mov r3,r5 + 18a8: 000d883a mov r6,zero + 18ac: 01cff834 movhi r7,16352 + 18b0: 1009883a mov r4,r2 + 18b4: 180b883a mov r5,r3 + 18b8: 00045b80 call 45b8 <__adddf3> + 18bc: 1009883a mov r4,r2 + 18c0: 180b883a mov r5,r3 + 18c4: 2005883a mov r2,r4 + 18c8: 2807883a mov r3,r5 + 18cc: 1009883a mov r4,r2 + 18d0: 180b883a mov r5,r3 + 18d4: 0003d4c0 call 3d4c <__fixunsdfsi> + 18d8: e0bffac5 stb r2,-21(fp) + 18dc: e0ffff17 ldw r3,-4(fp) + 18e0: 00a000b4 movhi r2,32770 + 18e4: 10c00a35 stwio r3,40(r2) + 18e8: 01000284 movi r4,10 + 18ec: 00077480 call 7748 + 18f0: e0fffac3 ldbu r3,-21(fp) + 18f4: 00a000b4 movhi r2,32770 + 18f8: 10c00b35 stwio r3,44(r2) + 18fc: 01000284 movi r4,10 + 1900: 00077480 call 7748 + 1904: e0bfff17 ldw r2,-4(fp) + 1908: 10800044 addi r2,r2,1 + 190c: e0bfff15 stw r2,-4(fp) + 1910: e0bfff17 ldw r2,-4(fp) + 1914: 10804010 cmplti r2,r2,256 + 1918: 103fc21e bne r2,zero,1824 + 191c: 01000074 movhi r4,1 + 1920: 212ce404 addi r4,r4,-19568 + 1924: 0006cb00 call 6cb0 + 1928: 0001883a nop + 192c: e037883a mov sp,fp + 1930: dfc00117 ldw ra,4(sp) + 1934: df000017 ldw fp,0(sp) + 1938: dec00204 addi sp,sp,8 + 193c: f800283a ret + +00001940 : + 1940: defff504 addi sp,sp,-44 + 1944: dfc00a15 stw ra,40(sp) + 1948: df000915 stw fp,36(sp) + 194c: df000904 addi fp,sp,36 + 1950: 01000074 movhi r4,1 + 1954: 212cea04 addi r4,r4,-19544 + 1958: 0006bc80 call 6bc8 + 195c: e0fff704 addi r3,fp,-36 + 1960: 00800074 movhi r2,1 + 1964: 10acf304 addi r2,r2,-19508 + 1968: 01000804 movi r4,32 + 196c: 200d883a mov r6,r4 + 1970: 100b883a mov r5,r2 + 1974: 1809883a mov r4,r3 + 1978: 0006b640 call 6b64 + 197c: e03fff15 stw zero,-4(fp) + 1980: 00000d06 br 19b8 + 1984: e0ffff17 ldw r3,-4(fp) + 1988: 00a000b4 movhi r2,32770 + 198c: 10c00c35 stwio r3,48(r2) + 1990: e0bfff17 ldw r2,-4(fp) + 1994: 1085883a add r2,r2,r2 + 1998: e085883a add r2,fp,r2 + 199c: 10bff70b ldhu r2,-36(r2) + 19a0: 10ffffcc andi r3,r2,65535 + 19a4: 00a000b4 movhi r2,32770 + 19a8: 10c00d35 stwio r3,52(r2) + 19ac: e0bfff17 ldw r2,-4(fp) + 19b0: 10800044 addi r2,r2,1 + 19b4: e0bfff15 stw r2,-4(fp) + 19b8: e0bfff17 ldw r2,-4(fp) + 19bc: 10800410 cmplti r2,r2,16 + 19c0: 103ff01e bne r2,zero,1984 + 19c4: 01000074 movhi r4,1 + 19c8: 212cb404 addi r4,r4,-19760 + 19cc: 0006cb00 call 6cb0 + 19d0: 0001883a nop + 19d4: e037883a mov sp,fp + 19d8: dfc00117 ldw ra,4(sp) + 19dc: df000017 ldw fp,0(sp) + 19e0: dec00204 addi sp,sp,8 + 19e4: f800283a ret + +000019e8 : + 19e8: defffd04 addi sp,sp,-12 + 19ec: dfc00215 stw ra,8(sp) + 19f0: df000115 stw fp,4(sp) + 19f4: df000104 addi fp,sp,4 + 19f8: 00a000b4 movhi r2,32770 + 19fc: 10800937 ldwio r2,36(r2) + 1a00: e0bfff15 stw r2,-4(fp) + 1a04: e0bfff17 ldw r2,-4(fp) + 1a08: 10800114 ori r2,r2,4 + 1a0c: 1007883a mov r3,r2 + 1a10: 00a000b4 movhi r2,32770 + 1a14: 10c00935 stwio r3,36(r2) + 1a18: 01000074 movhi r4,1 + 1a1c: 212cfb04 addi r4,r4,-19476 + 1a20: 0006cb00 call 6cb0 + 1a24: 0001883a nop 1a28: e037883a mov sp,fp 1a2c: dfc00117 ldw ra,4(sp) 1a30: df000017 ldw fp,0(sp) 1a34: dec00204 addi sp,sp,8 1a38: f800283a ret -00001a3c
: - 1a3c: defff804 addi sp,sp,-32 - 1a40: dfc00715 stw ra,28(sp) - 1a44: df000615 stw fp,24(sp) - 1a48: df000604 addi fp,sp,24 - 1a4c: 01000074 movhi r4,1 - 1a50: 21252c04 addi r4,r4,-27472 - 1a54: 0004bcc0 call 4bcc - 1a58: 00800044 movi r2,1 - 1a5c: 1001703a wrctl status,r2 - 1a60: 00c001c4 movi r3,7 - 1a64: 008000b4 movhi r2,2 - 1a68: 10c02135 stwio r3,132(r2) - 1a6c: 01000074 movhi r4,1 - 1a70: 21253904 addi r4,r4,-27420 - 1a74: 0004ae40 call 4ae4 - 1a78: 0000c040 call c04 - 1a7c: e0bffe15 stw r2,-8(fp) - 1a80: e0ffff15 stw r3,-4(fp) - 1a84: e03ffa15 stw zero,-24(fp) - 1a88: 00000306 br 1a98 - 1a8c: e0bffa17 ldw r2,-24(fp) - 1a90: 10800044 addi r2,r2,1 - 1a94: e0bffa15 stw r2,-24(fp) - 1a98: e0bffa17 ldw r2,-24(fp) - 1a9c: 1089c410 cmplti r2,r2,10000 - 1aa0: 103ffa1e bne r2,zero,1a8c - 1aa4: 0000c040 call c04 - 1aa8: e0bffc15 stw r2,-16(fp) - 1aac: e0fffd15 stw r3,-12(fp) - 1ab0: e0bffd17 ldw r2,-12(fp) - 1ab4: e0ffff17 ldw r3,-4(fp) - 1ab8: 18800636 bltu r3,r2,1ad4 - 1abc: e0fffd17 ldw r3,-12(fp) - 1ac0: e0bfff17 ldw r2,-4(fp) - 1ac4: 18800b1e bne r3,r2,1af4 - 1ac8: e0bffc17 ldw r2,-16(fp) - 1acc: e0fffe17 ldw r3,-8(fp) - 1ad0: 1880082e bgeu r3,r2,1af4 - 1ad4: e0fffc17 ldw r3,-16(fp) - 1ad8: e0bffe17 ldw r2,-8(fp) - 1adc: 1885c83a sub r2,r3,r2 - 1ae0: 100b883a mov r5,r2 - 1ae4: 01000074 movhi r4,1 - 1ae8: 21253e04 addi r4,r4,-27400 - 1aec: 0004ae40 call 4ae4 - 1af0: 00000506 br 1b08 - 1af4: e0bffe17 ldw r2,-8(fp) - 1af8: 100b883a mov r5,r2 - 1afc: 01000074 movhi r4,1 - 1b00: 21254404 addi r4,r4,-27376 - 1b04: 0004ae40 call 4ae4 - 1b08: 00880034 movhi r2,8192 - 1b0c: e0bffb15 stw r2,-20(fp) - 1b10: e17ffb17 ldw r5,-20(fp) - 1b14: 01000074 movhi r4,1 - 1b18: 21254a04 addi r4,r4,-27352 - 1b1c: 0004ae40 call 4ae4 - 1b20: e0fffb17 ldw r3,-20(fp) - 1b24: 008000b4 movhi r2,2 - 1b28: 10c00235 stwio r3,8(r2) - 1b2c: 0007883a mov r3,zero - 1b30: 008000b4 movhi r2,2 - 1b34: 10c00335 stwio r3,12(r2) +00001a3c : + 1a3c: defffc04 addi sp,sp,-16 + 1a40: dfc00315 stw ra,12(sp) + 1a44: df000215 stw fp,8(sp) + 1a48: df000204 addi fp,sp,8 + 1a4c: e13ffe15 stw r4,-8(fp) + 1a50: 00a000b4 movhi r2,32770 + 1a54: 10800937 ldwio r2,36(r2) + 1a58: e0bfff15 stw r2,-4(fp) + 1a5c: e0bffe17 ldw r2,-8(fp) + 1a60: 10000926 beq r2,zero,1a88 + 1a64: e0bfff17 ldw r2,-4(fp) + 1a68: 10800094 ori r2,r2,2 + 1a6c: 1007883a mov r3,r2 + 1a70: 00a000b4 movhi r2,32770 + 1a74: 10c00935 stwio r3,36(r2) + 1a78: 01000074 movhi r4,1 + 1a7c: 212d0404 addi r4,r4,-19440 + 1a80: 0006cb00 call 6cb0 + 1a84: 00000806 br 1aa8 + 1a88: e0ffff17 ldw r3,-4(fp) + 1a8c: 00bfff44 movi r2,-3 + 1a90: 1886703a and r3,r3,r2 + 1a94: 00a000b4 movhi r2,32770 + 1a98: 10c00935 stwio r3,36(r2) + 1a9c: 01000074 movhi r4,1 + 1aa0: 212d0c04 addi r4,r4,-19408 + 1aa4: 0006cb00 call 6cb0 + 1aa8: 0001883a nop + 1aac: e037883a mov sp,fp + 1ab0: dfc00117 ldw ra,4(sp) + 1ab4: df000017 ldw fp,0(sp) + 1ab8: dec00204 addi sp,sp,8 + 1abc: f800283a ret + +00001ac0 : + 1ac0: defffd04 addi sp,sp,-12 + 1ac4: dfc00215 stw ra,8(sp) + 1ac8: df000115 stw fp,4(sp) + 1acc: df000104 addi fp,sp,4 + 1ad0: 00a000b4 movhi r2,32770 + 1ad4: 10800937 ldwio r2,36(r2) + 1ad8: e0bfff15 stw r2,-4(fp) + 1adc: 01000074 movhi r4,1 + 1ae0: 212d1404 addi r4,r4,-19376 + 1ae4: 0006cb00 call 6cb0 + 1ae8: e0bfff17 ldw r2,-4(fp) + 1aec: 1000030e bge r2,zero,1afc + 1af0: 00800074 movhi r2,1 + 1af4: 10ad1904 addi r2,r2,-19356 + 1af8: 00000206 br 1b04 + 1afc: 00800074 movhi r2,1 + 1b00: 10ad1a04 addi r2,r2,-19352 + 1b04: 100b883a mov r5,r2 + 1b08: 01000074 movhi r4,1 + 1b0c: 212d1b04 addi r4,r4,-19348 + 1b10: 0006bc80 call 6bc8 + 1b14: e0bfff17 ldw r2,-4(fp) + 1b18: 1090002c andhi r2,r2,16384 + 1b1c: 10000326 beq r2,zero,1b2c + 1b20: 00800074 movhi r2,1 + 1b24: 10ad1e04 addi r2,r2,-19336 + 1b28: 00000206 br 1b34 + 1b2c: 00800074 movhi r2,1 + 1b30: 10ad1a04 addi r2,r2,-19352 + 1b34: 100b883a mov r5,r2 1b38: 01000074 movhi r4,1 - 1b3c: 21255504 addi r4,r4,-27308 - 1b40: 0004bcc0 call 4bcc - 1b44: 00018300 call 1830 - 1b48: 0005883a mov r2,zero - 1b4c: e037883a mov sp,fp - 1b50: dfc00117 ldw ra,4(sp) - 1b54: df000017 ldw fp,0(sp) - 1b58: dec00204 addi sp,sp,8 - 1b5c: f800283a ret - -00001b60 : - 1b60: defffa04 addi sp,sp,-24 - 1b64: dc800215 stw r18,8(sp) - 1b68: dc400115 stw r17,4(sp) - 1b6c: dc000015 stw r16,0(sp) - 1b70: dfc00515 stw ra,20(sp) - 1b74: dd000415 stw r20,16(sp) - 1b78: dcc00315 stw r19,12(sp) - 1b7c: 2021883a mov r16,r4 - 1b80: 2823883a mov r17,r5 - 1b84: 0001df80 call 1df8 <__ieee754_powf> - 1b88: 1025883a mov r18,r2 - 1b8c: 00800074 movhi r2,1 - 1b90: 10a66b17 ldw r2,-26196(r2) - 1b94: 10bfffe0 cmpeqi r2,r2,-1 - 1b98: 1000211e bne r2,zero,1c20 - 1b9c: 880b883a mov r5,r17 - 1ba0: 8809883a mov r4,r17 - 1ba4: 00047440 call 4744 <__unordsf2> - 1ba8: 10001d1e bne r2,zero,1c20 - 1bac: 800b883a mov r5,r16 - 1bb0: 8009883a mov r4,r16 - 1bb4: 00047440 call 4744 <__unordsf2> - 1bb8: 000b883a mov r5,zero - 1bbc: 10007a1e bne r2,zero,1da8 - 1bc0: 8009883a mov r4,r16 - 1bc4: 0003d200 call 3d20 <__eqsf2> - 1bc8: 10001e1e bne r2,zero,1c44 - 1bcc: 000b883a mov r5,zero - 1bd0: 8809883a mov r4,r17 - 1bd4: 0003d200 call 3d20 <__eqsf2> - 1bd8: 10007626 beq r2,zero,1db4 - 1bdc: 01200034 movhi r4,32768 - 1be0: 213fffc4 addi r4,r4,-1 - 1be4: 8920703a and r16,r17,r4 - 1be8: 015fe034 movhi r5,32640 - 1bec: 297fffc4 addi r5,r5,-1 - 1bf0: 8009883a mov r4,r16 - 1bf4: 00047440 call 4744 <__unordsf2> - 1bf8: 1000091e bne r2,zero,1c20 - 1bfc: 015fe034 movhi r5,32640 - 1c00: 297fffc4 addi r5,r5,-1 - 1c04: 8009883a mov r4,r16 - 1c08: 0003d900 call 3d90 <__gesf2> - 1c0c: 00800416 blt zero,r2,1c20 - 1c10: 000b883a mov r5,zero - 1c14: 8809883a mov r4,r17 - 1c18: 0003e480 call 3e48 <__lesf2> - 1c1c: 10006716 blt r2,zero,1dbc - 1c20: 9005883a mov r2,r18 - 1c24: dfc00517 ldw ra,20(sp) - 1c28: dd000417 ldw r20,16(sp) - 1c2c: dcc00317 ldw r19,12(sp) - 1c30: dc800217 ldw r18,8(sp) - 1c34: dc400117 ldw r17,4(sp) - 1c38: dc000017 ldw r16,0(sp) - 1c3c: dec00604 addi sp,sp,24 - 1c40: f800283a ret - 1c44: 01200034 movhi r4,32768 - 1c48: 213fffc4 addi r4,r4,-1 - 1c4c: 9126703a and r19,r18,r4 - 1c50: 015fe034 movhi r5,32640 - 1c54: 297fffc4 addi r5,r5,-1 - 1c58: 9809883a mov r4,r19 - 1c5c: 00047440 call 4744 <__unordsf2> - 1c60: 1000261e bne r2,zero,1cfc - 1c64: 015fe034 movhi r5,32640 - 1c68: 297fffc4 addi r5,r5,-1 - 1c6c: 9809883a mov r4,r19 - 1c70: 0003d900 call 3d90 <__gesf2> - 1c74: 00802116 blt zero,r2,1cfc - 1c78: 000b883a mov r5,zero - 1c7c: 9009883a mov r4,r18 - 1c80: 0003d200 call 3d20 <__eqsf2> - 1c84: 103fe61e bne r2,zero,1c20 - 1c88: 04e00034 movhi r19,32768 - 1c8c: 9cffffc4 addi r19,r19,-1 - 1c90: 84e0703a and r16,r16,r19 - 1c94: 015fe034 movhi r5,32640 - 1c98: 297fffc4 addi r5,r5,-1 - 1c9c: 8009883a mov r4,r16 - 1ca0: 00047440 call 4744 <__unordsf2> - 1ca4: 103fde1e bne r2,zero,1c20 - 1ca8: 015fe034 movhi r5,32640 - 1cac: 297fffc4 addi r5,r5,-1 - 1cb0: 8009883a mov r4,r16 - 1cb4: 0003d900 call 3d90 <__gesf2> - 1cb8: 00bfd916 blt zero,r2,1c20 - 1cbc: 8ce2703a and r17,r17,r19 - 1cc0: 015fe034 movhi r5,32640 - 1cc4: 297fffc4 addi r5,r5,-1 - 1cc8: 8809883a mov r4,r17 - 1ccc: 00047440 call 4744 <__unordsf2> - 1cd0: 103fd31e bne r2,zero,1c20 - 1cd4: 015fe034 movhi r5,32640 - 1cd8: 297fffc4 addi r5,r5,-1 - 1cdc: 8809883a mov r4,r17 - 1ce0: 0003d900 call 3d90 <__gesf2> - 1ce4: 00bfce16 blt zero,r2,1c20 - 1ce8: 0004a740 call 4a74 <__errno> - 1cec: 00c00884 movi r3,34 - 1cf0: 10c00015 stw r3,0(r2) - 1cf4: 0025883a mov r18,zero - 1cf8: 003fc906 br 1c20 - 1cfc: 04e00034 movhi r19,32768 - 1d00: 9cffffc4 addi r19,r19,-1 - 1d04: 84e8703a and r20,r16,r19 - 1d08: 015fe034 movhi r5,32640 - 1d0c: 297fffc4 addi r5,r5,-1 - 1d10: a009883a mov r4,r20 - 1d14: 00047440 call 4744 <__unordsf2> - 1d18: 103fc11e bne r2,zero,1c20 - 1d1c: 015fe034 movhi r5,32640 - 1d20: 297fffc4 addi r5,r5,-1 - 1d24: a009883a mov r4,r20 - 1d28: 0003d900 call 3d90 <__gesf2> - 1d2c: 00bfbc16 blt zero,r2,1c20 - 1d30: 8ce6703a and r19,r17,r19 - 1d34: 015fe034 movhi r5,32640 - 1d38: 297fffc4 addi r5,r5,-1 - 1d3c: 9809883a mov r4,r19 - 1d40: 00047440 call 4744 <__unordsf2> - 1d44: 103fcc1e bne r2,zero,1c78 - 1d48: 015fe034 movhi r5,32640 - 1d4c: 297fffc4 addi r5,r5,-1 - 1d50: 9809883a mov r4,r19 - 1d54: 0003d900 call 3d90 <__gesf2> - 1d58: 00bfc716 blt zero,r2,1c78 - 1d5c: 900b883a mov r5,r18 - 1d60: 9009883a mov r4,r18 - 1d64: 00047440 call 4744 <__unordsf2> - 1d68: 10001b1e bne r2,zero,1dd8 - 1d6c: 0004a740 call 4a74 <__errno> - 1d70: 00c00884 movi r3,34 - 1d74: 10c00015 stw r3,0(r2) - 1d78: 000b883a mov r5,zero - 1d7c: 8009883a mov r4,r16 - 1d80: 0003e480 call 3e48 <__lesf2> - 1d84: 1000120e bge r2,zero,1dd0 - 1d88: 8809883a mov r4,r17 - 1d8c: 0002a480 call 2a48 - 1d90: 880b883a mov r5,r17 - 1d94: 1009883a mov r4,r2 - 1d98: 0003d200 call 3d20 <__eqsf2> - 1d9c: 10000c26 beq r2,zero,1dd0 - 1da0: 04bfe034 movhi r18,65408 - 1da4: 003f9e06 br 1c20 - 1da8: 8809883a mov r4,r17 - 1dac: 0003d200 call 3d20 <__eqsf2> - 1db0: 103f9b1e bne r2,zero,1c20 - 1db4: 048fe034 movhi r18,16256 - 1db8: 003f9906 br 1c20 - 1dbc: 0004a740 call 4a74 <__errno> - 1dc0: 00c00844 movi r3,33 - 1dc4: 10c00015 stw r3,0(r2) - 1dc8: 04bfe034 movhi r18,65408 - 1dcc: 003f9406 br 1c20 - 1dd0: 049fe034 movhi r18,32640 - 1dd4: 003f9206 br 1c20 - 1dd8: 0004a740 call 4a74 <__errno> - 1ddc: 00c00844 movi r3,33 - 1de0: 10c00015 stw r3,0(r2) - 1de4: 000b883a mov r5,zero - 1de8: 0009883a mov r4,zero - 1dec: 000392c0 call 392c <__divsf3> - 1df0: 1025883a mov r18,r2 - 1df4: 003f8a06 br 1c20 - -00001df8 <__ieee754_powf>: - 1df8: 00a00034 movhi r2,32768 - 1dfc: 10bfffc4 addi r2,r2,-1 - 1e00: 1146703a and r3,r2,r5 - 1e04: 18010926 beq r3,zero,222c <__ieee754_powf+0x434> - 1e08: defff004 addi sp,sp,-64 - 1e0c: dc800815 stw r18,32(sp) - 1e10: dc000615 stw r16,24(sp) - 1e14: dfc00f15 stw ra,60(sp) - 1e18: 1120703a and r16,r2,r4 - 1e1c: df000e15 stw fp,56(sp) - 1e20: ddc00d15 stw r23,52(sp) - 1e24: dd800c15 stw r22,48(sp) - 1e28: dd400b15 stw r21,44(sp) - 1e2c: dd000a15 stw r20,40(sp) - 1e30: dcc00915 stw r19,36(sp) - 1e34: dc400715 stw r17,28(sp) - 1e38: 009fe034 movhi r2,32640 - 1e3c: 2025883a mov r18,r4 - 1e40: 14000d0e bge r2,r16,1e78 <__ieee754_powf+0x80> - 1e44: 009ff034 movhi r2,32704 - 1e48: dfc00f17 ldw ra,60(sp) - 1e4c: df000e17 ldw fp,56(sp) - 1e50: ddc00d17 ldw r23,52(sp) - 1e54: dd800c17 ldw r22,48(sp) - 1e58: dd400b17 ldw r21,44(sp) - 1e5c: dd000a17 ldw r20,40(sp) - 1e60: dcc00917 ldw r19,36(sp) - 1e64: dc800817 ldw r18,32(sp) - 1e68: dc400717 ldw r17,28(sp) - 1e6c: dc000617 ldw r16,24(sp) - 1e70: dec01004 addi sp,sp,64 - 1e74: f800283a ret - 1e78: 10c0ee16 blt r2,r3,2234 <__ieee754_powf+0x43c> - 1e7c: 2823883a mov r17,r5 - 1e80: 2000ef16 blt r4,zero,2240 <__ieee754_powf+0x448> - 1e84: 0027883a mov r19,zero - 1e88: 009fe034 movhi r2,32640 - 1e8c: 1880f826 beq r3,r2,2270 <__ieee754_powf+0x478> - 1e90: 008fe034 movhi r2,16256 - 1e94: 18811326 beq r3,r2,22e4 <__ieee754_powf+0x4ec> - 1e98: 00900034 movhi r2,16384 - 1e9c: 28812126 beq r5,r2,2324 <__ieee754_powf+0x52c> - 1ea0: 008fc034 movhi r2,16128 - 1ea4: 2880fa26 beq r5,r2,2290 <__ieee754_powf+0x498> - 1ea8: 00a00034 movhi r2,32768 - 1eac: 10bfffc4 addi r2,r2,-1 - 1eb0: 019fe034 movhi r6,32640 - 1eb4: 2084703a and r2,r4,r2 - 1eb8: 81810d26 beq r16,r6,22f0 <__ieee754_powf+0x4f8> - 1ebc: 80010c26 beq r16,zero,22f0 <__ieee754_powf+0x4f8> - 1ec0: 018fe034 movhi r6,16256 - 1ec4: 81810a26 beq r16,r6,22f0 <__ieee754_powf+0x4f8> - 1ec8: 2024d7fa srli r18,r4,31 - 1ecc: 94bfffc4 addi r18,r18,-1 - 1ed0: 9c8cb03a or r6,r19,r18 - 1ed4: 30011926 beq r6,zero,233c <__ieee754_powf+0x544> - 1ed8: 01934034 movhi r6,19712 - 1edc: 30c11d0e bge r6,r3,2354 <__ieee754_powf+0x55c> - 1ee0: 00cfe034 movhi r3,16256 - 1ee4: 18fffdc4 addi r3,r3,-9 - 1ee8: 1c02670e bge r3,r16,2888 <__ieee754_powf+0xa90> - 1eec: 00cfe034 movhi r3,16256 - 1ef0: 18c001c4 addi r3,r3,7 - 1ef4: 1c010e16 blt r3,r16,2330 <__ieee754_powf+0x538> - 1ef8: 014fe034 movhi r5,16256 - 1efc: 1009883a mov r4,r2 - 1f00: 00042b00 call 42b0 <__subsf3> - 1f04: 014fee74 movhi r5,16313 - 1f08: 296a8004 addi r5,r5,-22016 - 1f0c: 1009883a mov r4,r2 - 1f10: 1021883a mov r16,r2 - 1f14: 0003efc0 call 3efc <__mulsf3> - 1f18: 014dbb74 movhi r5,14061 - 1f1c: 8009883a mov r4,r16 - 1f20: 29695c04 addi r5,r5,-23184 - 1f24: 102b883a mov r21,r2 - 1f28: 0003efc0 call 3efc <__mulsf3> - 1f2c: 8009883a mov r4,r16 - 1f30: 014fa034 movhi r5,16000 - 1f34: 1029883a mov r20,r2 - 1f38: 0003efc0 call 3efc <__mulsf3> - 1f3c: 010faaf4 movhi r4,16043 - 1f40: 100b883a mov r5,r2 - 1f44: 212aaac4 addi r4,r4,-21845 - 1f48: 00042b00 call 42b0 <__subsf3> - 1f4c: 800b883a mov r5,r16 - 1f50: 1009883a mov r4,r2 - 1f54: 0003efc0 call 3efc <__mulsf3> - 1f58: 100b883a mov r5,r2 - 1f5c: 010fc034 movhi r4,16128 - 1f60: 00042b00 call 42b0 <__subsf3> - 1f64: 800b883a mov r5,r16 - 1f68: 8009883a mov r4,r16 - 1f6c: 102d883a mov r22,r2 - 1f70: 0003efc0 call 3efc <__mulsf3> - 1f74: 100b883a mov r5,r2 - 1f78: b009883a mov r4,r22 - 1f7c: 0003efc0 call 3efc <__mulsf3> - 1f80: 014fee74 movhi r5,16313 - 1f84: 296a8ec4 addi r5,r5,-21957 - 1f88: 1009883a mov r4,r2 - 1f8c: 0003efc0 call 3efc <__mulsf3> - 1f90: a009883a mov r4,r20 - 1f94: 100b883a mov r5,r2 - 1f98: 00042b00 call 42b0 <__subsf3> - 1f9c: 100b883a mov r5,r2 - 1fa0: a809883a mov r4,r21 - 1fa4: 1029883a mov r20,r2 - 1fa8: 00034c00 call 34c0 <__addsf3> - 1fac: 013c0004 movi r4,-4096 - 1fb0: 1108703a and r4,r2,r4 - 1fb4: a80b883a mov r5,r21 - 1fb8: 2021883a mov r16,r4 - 1fbc: 00042b00 call 42b0 <__subsf3> - 1fc0: a009883a mov r4,r20 - 1fc4: 100b883a mov r5,r2 - 1fc8: 00042b00 call 42b0 <__subsf3> - 1fcc: 1029883a mov r20,r2 - 1fd0: 9cffffc4 addi r19,r19,-1 - 1fd4: 9ca4b03a or r18,r19,r18 - 1fd8: 9001e61e bne r18,zero,2774 <__ieee754_powf+0x97c> - 1fdc: 04afe034 movhi r18,49024 - 1fe0: 04fc0004 movi r19,-4096 - 1fe4: 9c66703a and r19,r19,r17 - 1fe8: 980b883a mov r5,r19 - 1fec: 8809883a mov r4,r17 - 1ff0: 00042b00 call 42b0 <__subsf3> - 1ff4: 800b883a mov r5,r16 - 1ff8: 1009883a mov r4,r2 - 1ffc: 0003efc0 call 3efc <__mulsf3> - 2000: 880b883a mov r5,r17 - 2004: a009883a mov r4,r20 - 2008: 102b883a mov r21,r2 - 200c: 0003efc0 call 3efc <__mulsf3> - 2010: a809883a mov r4,r21 - 2014: 100b883a mov r5,r2 - 2018: 00034c00 call 34c0 <__addsf3> - 201c: 980b883a mov r5,r19 - 2020: 8009883a mov r4,r16 - 2024: 1023883a mov r17,r2 - 2028: 0003efc0 call 3efc <__mulsf3> - 202c: 100b883a mov r5,r2 - 2030: 8809883a mov r4,r17 - 2034: 1029883a mov r20,r2 - 2038: 00034c00 call 34c0 <__addsf3> - 203c: 1027883a mov r19,r2 - 2040: 00a00034 movhi r2,32768 - 2044: 10bfffc4 addi r2,r2,-1 - 2048: 9807883a mov r3,r19 - 204c: a02b883a mov r21,r20 - 2050: 982d883a mov r22,r19 - 2054: 14e0703a and r16,r2,r19 - 2058: 04c1c80e bge zero,r19,277c <__ieee754_powf+0x984> - 205c: 0090c034 movhi r2,17152 - 2060: 14020016 blt r2,r16,2864 <__ieee754_powf+0xa6c> - 2064: 8081f326 beq r16,r2,2834 <__ieee754_powf+0xa3c> - 2068: 008fc034 movhi r2,16128 - 206c: 1401cd16 blt r2,r16,27a4 <__ieee754_powf+0x9ac> - 2070: 0029883a mov r20,zero - 2074: 0027883a mov r19,zero - 2078: 043c0004 movi r16,-4096 - 207c: 1c20703a and r16,r3,r16 - 2080: 014fcc74 movhi r5,16177 - 2084: 8009883a mov r4,r16 - 2088: 295c8004 addi r5,r5,29184 - 208c: 0003efc0 call 3efc <__mulsf3> - 2090: a80b883a mov r5,r21 - 2094: 8009883a mov r4,r16 - 2098: 102d883a mov r22,r2 - 209c: 00042b00 call 42b0 <__subsf3> - 20a0: 8809883a mov r4,r17 - 20a4: 100b883a mov r5,r2 - 20a8: 00042b00 call 42b0 <__subsf3> - 20ac: 014fcc74 movhi r5,16177 - 20b0: 295c8604 addi r5,r5,29208 - 20b4: 1009883a mov r4,r2 - 20b8: 0003efc0 call 3efc <__mulsf3> - 20bc: 014d7034 movhi r5,13760 - 20c0: 8009883a mov r4,r16 - 20c4: 296fa304 addi r5,r5,-16756 - 20c8: 1023883a mov r17,r2 - 20cc: 0003efc0 call 3efc <__mulsf3> - 20d0: 8809883a mov r4,r17 - 20d4: 100b883a mov r5,r2 - 20d8: 00034c00 call 34c0 <__addsf3> - 20dc: b009883a mov r4,r22 - 20e0: 100b883a mov r5,r2 - 20e4: 1023883a mov r17,r2 - 20e8: 00034c00 call 34c0 <__addsf3> - 20ec: b00b883a mov r5,r22 - 20f0: 1009883a mov r4,r2 - 20f4: 1021883a mov r16,r2 - 20f8: 00042b00 call 42b0 <__subsf3> - 20fc: 8809883a mov r4,r17 - 2100: 100b883a mov r5,r2 - 2104: 00042b00 call 42b0 <__subsf3> - 2108: 800b883a mov r5,r16 - 210c: 8009883a mov r4,r16 - 2110: 102b883a mov r21,r2 - 2114: 0003efc0 call 3efc <__mulsf3> - 2118: 014cccb4 movhi r5,13106 - 211c: 296ed304 addi r5,r5,-17588 - 2120: 1009883a mov r4,r2 - 2124: 1023883a mov r17,r2 - 2128: 0003efc0 call 3efc <__mulsf3> - 212c: 014d77b4 movhi r5,13790 - 2130: 297a8384 addi r5,r5,-5618 - 2134: 1009883a mov r4,r2 - 2138: 00042b00 call 42b0 <__subsf3> - 213c: 880b883a mov r5,r17 - 2140: 1009883a mov r4,r2 - 2144: 0003efc0 call 3efc <__mulsf3> - 2148: 014e22f4 movhi r5,14475 - 214c: 296cd544 addi r5,r5,-19627 - 2150: 1009883a mov r4,r2 - 2154: 00034c00 call 34c0 <__addsf3> - 2158: 880b883a mov r5,r17 - 215c: 1009883a mov r4,r2 - 2160: 0003efc0 call 3efc <__mulsf3> - 2164: 014ecdb4 movhi r5,15158 - 2168: 2942d844 addi r5,r5,2913 - 216c: 1009883a mov r4,r2 - 2170: 00042b00 call 42b0 <__subsf3> - 2174: 880b883a mov r5,r17 - 2178: 1009883a mov r4,r2 - 217c: 0003efc0 call 3efc <__mulsf3> - 2180: 014f8af4 movhi r5,15915 - 2184: 296aaac4 addi r5,r5,-21845 - 2188: 1009883a mov r4,r2 - 218c: 00034c00 call 34c0 <__addsf3> - 2190: 880b883a mov r5,r17 - 2194: 1009883a mov r4,r2 - 2198: 0003efc0 call 3efc <__mulsf3> - 219c: 100b883a mov r5,r2 - 21a0: 8009883a mov r4,r16 - 21a4: 00042b00 call 42b0 <__subsf3> - 21a8: 100b883a mov r5,r2 - 21ac: 8009883a mov r4,r16 - 21b0: 1023883a mov r17,r2 - 21b4: 0003efc0 call 3efc <__mulsf3> - 21b8: 8809883a mov r4,r17 - 21bc: 01500034 movhi r5,16384 - 21c0: 102d883a mov r22,r2 - 21c4: 00042b00 call 42b0 <__subsf3> - 21c8: 100b883a mov r5,r2 - 21cc: b009883a mov r4,r22 - 21d0: 000392c0 call 392c <__divsf3> - 21d4: a80b883a mov r5,r21 - 21d8: 8009883a mov r4,r16 - 21dc: 1023883a mov r17,r2 - 21e0: 0003efc0 call 3efc <__mulsf3> - 21e4: a80b883a mov r5,r21 - 21e8: 1009883a mov r4,r2 - 21ec: 00034c00 call 34c0 <__addsf3> - 21f0: 100b883a mov r5,r2 - 21f4: 8809883a mov r4,r17 - 21f8: 00042b00 call 42b0 <__subsf3> - 21fc: 800b883a mov r5,r16 - 2200: 1009883a mov r4,r2 - 2204: 00042b00 call 42b0 <__subsf3> - 2208: 010fe034 movhi r4,16256 - 220c: 100b883a mov r5,r2 - 2210: 00042b00 call 42b0 <__subsf3> - 2214: a089883a add r4,r20,r2 - 2218: 2007d5fa srai r3,r4,23 - 221c: 00c1b10e bge zero,r3,28e4 <__ieee754_powf+0xaec> - 2220: 900b883a mov r5,r18 - 2224: 0003efc0 call 3efc <__mulsf3> - 2228: 003f0706 br 1e48 <__ieee754_powf+0x50> - 222c: 008fe034 movhi r2,16256 - 2230: f800283a ret - 2234: 008fe034 movhi r2,16256 - 2238: 80bf0326 beq r16,r2,1e48 <__ieee754_powf+0x50> - 223c: 003f0106 br 1e44 <__ieee754_powf+0x4c> - 2240: 0092e034 movhi r2,19328 - 2244: 1880100e bge r3,r2,2288 <__ieee754_powf+0x490> - 2248: 008fe034 movhi r2,16256 - 224c: 18800616 blt r3,r2,2268 <__ieee754_powf+0x470> - 2250: 1805d5fa srai r2,r3,23 - 2254: 01802584 movi r6,150 - 2258: 3085c83a sub r2,r6,r2 - 225c: 188dd83a sra r6,r3,r2 - 2260: 3084983a sll r2,r6,r2 - 2264: 10c13326 beq r2,r3,2734 <__ieee754_powf+0x93c> - 2268: 0027883a mov r19,zero - 226c: 003f0806 br 1e90 <__ieee754_powf+0x98> - 2270: 008fe034 movhi r2,16256 - 2274: 80801926 beq r16,r2,22dc <__ieee754_powf+0x4e4> - 2278: 1400220e bge r2,r16,2304 <__ieee754_powf+0x50c> - 227c: 28002d16 blt r5,zero,2334 <__ieee754_powf+0x53c> - 2280: 8805883a mov r2,r17 - 2284: 003ef006 br 1e48 <__ieee754_powf+0x50> - 2288: 04c00084 movi r19,2 - 228c: 003efe06 br 1e88 <__ieee754_powf+0x90> - 2290: 90012c0e bge r18,zero,2744 <__ieee754_powf+0x94c> - 2294: 00a00034 movhi r2,32768 - 2298: 10bfffc4 addi r2,r2,-1 - 229c: 019fe034 movhi r6,32640 - 22a0: 2084703a and r2,r4,r2 - 22a4: 81800226 beq r16,r6,22b0 <__ieee754_powf+0x4b8> - 22a8: 803f051e bne r16,zero,1ec0 <__ieee754_powf+0xc8> - 22ac: 903ee60e bge r18,zero,1e48 <__ieee754_powf+0x50> - 22b0: 00f02034 movhi r3,49280 - 22b4: 80c7883a add r3,r16,r3 - 22b8: 1cc6b03a or r3,r3,r19 - 22bc: 1801191e bne r3,zero,2724 <__ieee754_powf+0x92c> - 22c0: 100b883a mov r5,r2 - 22c4: 1009883a mov r4,r2 - 22c8: 00042b00 call 42b0 <__subsf3> - 22cc: 100b883a mov r5,r2 - 22d0: 1009883a mov r4,r2 - 22d4: 000392c0 call 392c <__divsf3> - 22d8: 003edb06 br 1e48 <__ieee754_powf+0x50> - 22dc: 008fe034 movhi r2,16256 - 22e0: 003ed906 br 1e48 <__ieee754_powf+0x50> - 22e4: 28000b16 blt r5,zero,2314 <__ieee754_powf+0x51c> - 22e8: 2005883a mov r2,r4 - 22ec: 003ed606 br 1e48 <__ieee754_powf+0x50> - 22f0: 283fee0e bge r5,zero,22ac <__ieee754_powf+0x4b4> - 22f4: 100b883a mov r5,r2 - 22f8: 010fe034 movhi r4,16256 - 22fc: 000392c0 call 392c <__divsf3> - 2300: 003fea06 br 22ac <__ieee754_powf+0x4b4> - 2304: 280bd7fa srai r5,r5,31 - 2308: 88a0003c xorhi r2,r17,32768 - 230c: 1144703a and r2,r2,r5 - 2310: 003ecd06 br 1e48 <__ieee754_powf+0x50> - 2314: 200b883a mov r5,r4 - 2318: 010fe034 movhi r4,16256 - 231c: 000392c0 call 392c <__divsf3> - 2320: 003ec906 br 1e48 <__ieee754_powf+0x50> - 2324: 200b883a mov r5,r4 - 2328: 0003efc0 call 3efc <__mulsf3> - 232c: 003ec606 br 1e48 <__ieee754_powf+0x50> - 2330: 01415616 blt zero,r5,288c <__ieee754_powf+0xa94> - 2334: 0005883a mov r2,zero - 2338: 003ec306 br 1e48 <__ieee754_powf+0x50> - 233c: 200b883a mov r5,r4 - 2340: 00042b00 call 42b0 <__subsf3> - 2344: 100b883a mov r5,r2 - 2348: 1009883a mov r4,r2 - 234c: 000392c0 call 392c <__divsf3> - 2350: 003ebd06 br 1e48 <__ieee754_powf+0x50> - 2354: 211fe02c andhi r4,r4,32640 - 2358: 2001341e bne r4,zero,282c <__ieee754_powf+0xa34> - 235c: 0152e034 movhi r5,19328 - 2360: 1009883a mov r4,r2 - 2364: 0003efc0 call 3efc <__mulsf3> - 2368: 1021883a mov r16,r2 - 236c: 00fffa04 movi r3,-24 - 2370: 802fd5fa srai r23,r16,23 - 2374: 00802034 movhi r2,128 - 2378: 10bfffc4 addi r2,r2,-1 - 237c: 01000774 movhi r4,29 - 2380: bdffe044 addi r23,r23,-127 - 2384: 8084703a and r2,r16,r2 - 2388: 21311c44 addi r4,r4,-15247 - 238c: b8cd883a add r6,r23,r3 - 2390: 15cfe034 orhi r23,r2,16256 - 2394: 2081200e bge r4,r2,2818 <__ieee754_powf+0xa20> - 2398: 010017b4 movhi r4,94 - 239c: 212cf584 addi r4,r4,-19498 - 23a0: 20813f0e bge r4,r2,28a0 <__ieee754_powf+0xaa8> - 23a4: 00bfe034 movhi r2,65408 - 23a8: 31800044 addi r6,r6,1 - 23ac: b8af883a add r23,r23,r2 - 23b0: 0015883a mov r10,zero - 23b4: 000f883a mov r7,zero - 23b8: d8000215 stw zero,8(sp) - 23bc: 020fe034 movhi r8,16256 - 23c0: 400b883a mov r5,r8 - 23c4: b809883a mov r4,r23 - 23c8: da800515 stw r10,20(sp) - 23cc: d9c00415 stw r7,16(sp) - 23d0: d9800315 stw r6,12(sp) - 23d4: da000015 stw r8,0(sp) - 23d8: 00042b00 call 42b0 <__subsf3> - 23dc: da000017 ldw r8,0(sp) - 23e0: b809883a mov r4,r23 - 23e4: 102d883a mov r22,r2 - 23e8: 400b883a mov r5,r8 - 23ec: da000115 stw r8,4(sp) - 23f0: 00034c00 call 34c0 <__addsf3> - 23f4: 100b883a mov r5,r2 - 23f8: 010fe034 movhi r4,16256 - 23fc: 000392c0 call 392c <__divsf3> - 2400: b821d07a srai r16,r23,1 - 2404: b009883a mov r4,r22 - 2408: 100b883a mov r5,r2 - 240c: d8800015 stw r2,0(sp) - 2410: 0003efc0 call 3efc <__mulsf3> - 2414: 1039883a mov fp,r2 - 2418: 84080034 orhi r16,r16,8192 - 241c: 00800134 movhi r2,4 - 2420: 80a1883a add r16,r16,r2 - 2424: d8800217 ldw r2,8(sp) - 2428: 053c0004 movi r20,-4096 - 242c: a72a703a and r21,r20,fp - 2430: 80a1883a add r16,r16,r2 - 2434: 800b883a mov r5,r16 - 2438: a809883a mov r4,r21 - 243c: 0003efc0 call 3efc <__mulsf3> - 2440: b009883a mov r4,r22 - 2444: 100b883a mov r5,r2 - 2448: 00042b00 call 42b0 <__subsf3> - 244c: da000117 ldw r8,4(sp) - 2450: 8009883a mov r4,r16 - 2454: 102d883a mov r22,r2 - 2458: 400b883a mov r5,r8 - 245c: 00042b00 call 42b0 <__subsf3> - 2460: 100b883a mov r5,r2 - 2464: b809883a mov r4,r23 - 2468: 00042b00 call 42b0 <__subsf3> - 246c: a80b883a mov r5,r21 - 2470: 1009883a mov r4,r2 - 2474: 0003efc0 call 3efc <__mulsf3> - 2478: b009883a mov r4,r22 - 247c: 100b883a mov r5,r2 - 2480: 00042b00 call 42b0 <__subsf3> - 2484: da400017 ldw r9,0(sp) - 2488: 1009883a mov r4,r2 - 248c: 480b883a mov r5,r9 - 2490: 0003efc0 call 3efc <__mulsf3> - 2494: e00b883a mov r5,fp - 2498: e009883a mov r4,fp - 249c: 102d883a mov r22,r2 - 24a0: 0003efc0 call 3efc <__mulsf3> - 24a4: 014f9534 movhi r5,15956 - 24a8: 297c5084 addi r5,r5,-3774 - 24ac: 1009883a mov r4,r2 - 24b0: 1021883a mov r16,r2 - 24b4: 0003efc0 call 3efc <__mulsf3> - 24b8: 014f9b34 movhi r5,15980 - 24bc: 294c9544 addi r5,r5,12885 - 24c0: 1009883a mov r4,r2 - 24c4: 00034c00 call 34c0 <__addsf3> - 24c8: 800b883a mov r5,r16 - 24cc: 1009883a mov r4,r2 - 24d0: 0003efc0 call 3efc <__mulsf3> - 24d4: 014fa334 movhi r5,16012 - 24d8: 2968c144 addi r5,r5,-23803 - 24dc: 1009883a mov r4,r2 - 24e0: 00034c00 call 34c0 <__addsf3> - 24e4: 800b883a mov r5,r16 - 24e8: 1009883a mov r4,r2 - 24ec: 0003efc0 call 3efc <__mulsf3> - 24f0: 014faaf4 movhi r5,16043 - 24f4: 296aaac4 addi r5,r5,-21845 - 24f8: 1009883a mov r4,r2 - 24fc: 00034c00 call 34c0 <__addsf3> - 2500: 800b883a mov r5,r16 - 2504: 1009883a mov r4,r2 - 2508: 0003efc0 call 3efc <__mulsf3> - 250c: 014fb6f4 movhi r5,16091 - 2510: 295b6dc4 addi r5,r5,28087 - 2514: 1009883a mov r4,r2 - 2518: 00034c00 call 34c0 <__addsf3> - 251c: 800b883a mov r5,r16 - 2520: 1009883a mov r4,r2 - 2524: 0003efc0 call 3efc <__mulsf3> - 2528: 014fc6b4 movhi r5,16154 - 252c: 29666684 addi r5,r5,-26214 - 2530: 1009883a mov r4,r2 - 2534: 00034c00 call 34c0 <__addsf3> - 2538: 800b883a mov r5,r16 - 253c: 8009883a mov r4,r16 - 2540: d8800015 stw r2,0(sp) - 2544: 0003efc0 call 3efc <__mulsf3> - 2548: d8c00017 ldw r3,0(sp) - 254c: 100b883a mov r5,r2 - 2550: 1809883a mov r4,r3 - 2554: 0003efc0 call 3efc <__mulsf3> - 2558: a80b883a mov r5,r21 - 255c: e009883a mov r4,fp - 2560: 1021883a mov r16,r2 - 2564: 00034c00 call 34c0 <__addsf3> - 2568: b00b883a mov r5,r22 - 256c: 1009883a mov r4,r2 - 2570: 0003efc0 call 3efc <__mulsf3> - 2574: 800b883a mov r5,r16 - 2578: 1009883a mov r4,r2 - 257c: 00034c00 call 34c0 <__addsf3> - 2580: a80b883a mov r5,r21 - 2584: a809883a mov r4,r21 - 2588: d8800015 stw r2,0(sp) - 258c: 0003efc0 call 3efc <__mulsf3> - 2590: 01501034 movhi r5,16448 + 1b3c: 212d2304 addi r4,r4,-19316 + 1b40: 0006bc80 call 6bc8 + 1b44: e0bfff17 ldw r2,-4(fp) + 1b48: 1080008c andi r2,r2,2 + 1b4c: 10000326 beq r2,zero,1b5c + 1b50: 00800074 movhi r2,1 + 1b54: 10ac2d04 addi r2,r2,-20300 + 1b58: 00000206 br 1b64 + 1b5c: 00800074 movhi r2,1 + 1b60: 10ac2e04 addi r2,r2,-20296 + 1b64: 100b883a mov r5,r2 + 1b68: 01000074 movhi r4,1 + 1b6c: 212d2604 addi r4,r4,-19304 + 1b70: 0006bc80 call 6bc8 + 1b74: 0001883a nop + 1b78: e037883a mov sp,fp + 1b7c: dfc00117 ldw ra,4(sp) + 1b80: df000017 ldw fp,0(sp) + 1b84: dec00204 addi sp,sp,8 + 1b88: f800283a ret + +00001b8c : + 1b8c: defffb04 addi sp,sp,-20 + 1b90: dfc00415 stw ra,16(sp) + 1b94: df000315 stw fp,12(sp) + 1b98: df000304 addi fp,sp,12 + 1b9c: 00a000b4 movhi r2,32770 + 1ba0: 10800937 ldwio r2,36(r2) + 1ba4: e0bfff15 stw r2,-4(fp) + 1ba8: 00a000b4 movhi r2,32770 + 1bac: 10800837 ldwio r2,32(r2) + 1bb0: e0bffe15 stw r2,-8(fp) + 1bb4: e0bffe17 ldw r2,-8(fp) + 1bb8: 10800220 cmpeqi r2,r2,8 + 1bbc: 10803fcc andi r2,r2,255 + 1bc0: d0a0da15 stw r2,-31896(gp) + 1bc4: e0bfff17 ldw r2,-4(fp) + 1bc8: 1004d07a srli r2,r2,1 + 1bcc: 1080004c andi r2,r2,1 + 1bd0: d0a0db15 stw r2,-31892(gp) + 1bd4: 01000074 movhi r4,1 + 1bd8: 212d2904 addi r4,r4,-19292 + 1bdc: 0006cb00 call 6cb0 + 1be0: d0a0da17 ldw r2,-31896(gp) + 1be4: 10000326 beq r2,zero,1bf4 + 1be8: 00800074 movhi r2,1 + 1bec: 10ad3204 addi r2,r2,-19256 + 1bf0: 00000206 br 1bfc + 1bf4: 00800074 movhi r2,1 + 1bf8: 10ad3504 addi r2,r2,-19244 + 1bfc: 100b883a mov r5,r2 + 1c00: 01000074 movhi r4,1 + 1c04: 212d3904 addi r4,r4,-19228 + 1c08: 0006bc80 call 6bc8 + 1c0c: d0a0db17 ldw r2,-31892(gp) + 1c10: 10000326 beq r2,zero,1c20 + 1c14: 00800074 movhi r2,1 + 1c18: 10ad4104 addi r2,r2,-19196 + 1c1c: 00000206 br 1c28 + 1c20: 00800074 movhi r2,1 + 1c24: 10ad4304 addi r2,r2,-19188 + 1c28: 100b883a mov r5,r2 + 1c2c: 01000074 movhi r4,1 + 1c30: 212d4604 addi r4,r4,-19176 + 1c34: 0006bc80 call 6bc8 + 1c38: 01000074 movhi r4,1 + 1c3c: 212d4e04 addi r4,r4,-19144 + 1c40: 0006cb00 call 6cb0 + 1c44: e0bfff17 ldw r2,-4(fp) + 1c48: 1000030e bge r2,zero,1c58 + 1c4c: 00800074 movhi r2,1 + 1c50: 10ad5804 addi r2,r2,-19104 + 1c54: 00000206 br 1c60 + 1c58: 00800074 movhi r2,1 + 1c5c: 10ad5904 addi r2,r2,-19100 + 1c60: e0ffff17 ldw r3,-4(fp) + 1c64: 18d0002c andhi r3,r3,16384 + 1c68: 18000326 beq r3,zero,1c78 + 1c6c: 00c00074 movhi r3,1 + 1c70: 18ed5804 addi r3,r3,-19104 + 1c74: 00000206 br 1c80 + 1c78: 00c00074 movhi r3,1 + 1c7c: 18ed5904 addi r3,r3,-19100 + 1c80: 180d883a mov r6,r3 + 1c84: 100b883a mov r5,r2 + 1c88: 01000074 movhi r4,1 + 1c8c: 212d5a04 addi r4,r4,-19096 + 1c90: 0006bc80 call 6bc8 + 1c94: 01000074 movhi r4,1 + 1c98: 212c5404 addi r4,r4,-20144 + 1c9c: 0006cb00 call 6cb0 + 1ca0: 01000074 movhi r4,1 + 1ca4: 212d6504 addi r4,r4,-19052 + 1ca8: 0006cb00 call 6cb0 + 1cac: 01000074 movhi r4,1 + 1cb0: 212d6e04 addi r4,r4,-19016 + 1cb4: 0006bc80 call 6bc8 + 1cb8: 0000b940 call b94 + 1cbc: e0bffdc5 stb r2,-9(fp) + 1cc0: e0bffdc7 ldb r2,-9(fp) + 1cc4: 100b883a mov r5,r2 + 1cc8: 01000074 movhi r4,1 + 1ccc: 212c5e04 addi r4,r4,-20104 + 1cd0: 0006bc80 call 6bc8 + 1cd4: e0bffdc7 ldb r2,-9(fp) + 1cd8: 10801898 cmpnei r2,r2,98 + 1cdc: 10003626 beq r2,zero,1db8 + 1ce0: e0bffdc7 ldb r2,-9(fp) + 1ce4: 10c00d20 cmpeqi r3,r2,52 + 1ce8: 18002c1e bne r3,zero,1d9c + 1cec: 10c00d48 cmpgei r3,r2,53 + 1cf0: 18002c1e bne r3,zero,1da4 + 1cf4: 10c00ce0 cmpeqi r3,r2,51 + 1cf8: 1800261e bne r3,zero,1d94 + 1cfc: 10c00d08 cmpgei r3,r2,52 + 1d00: 1800281e bne r3,zero,1da4 + 1d04: 10c00c60 cmpeqi r3,r2,49 + 1d08: 1800031e bne r3,zero,1d18 + 1d0c: 10800ca0 cmpeqi r2,r2,50 + 1d10: 1000181e bne r2,zero,1d74 + 1d14: 00002306 br 1da4 + 1d18: d0a0da17 ldw r2,-31896(gp) + 1d1c: 1005003a cmpeq r2,r2,zero + 1d20: 10803fcc andi r2,r2,255 + 1d24: d0a0da15 stw r2,-31896(gp) + 1d28: d0a0da17 ldw r2,-31896(gp) + 1d2c: 10000226 beq r2,zero,1d38 + 1d30: 00800204 movi r2,8 + 1d34: 00000106 br 1d3c + 1d38: 0005883a mov r2,zero + 1d3c: 00e000b4 movhi r3,32770 + 1d40: 18800835 stwio r2,32(r3) + 1d44: d0a0da17 ldw r2,-31896(gp) + 1d48: 10000326 beq r2,zero,1d58 + 1d4c: 00800074 movhi r2,1 + 1d50: 10ad7204 addi r2,r2,-19000 + 1d54: 00000206 br 1d60 + 1d58: 00800074 movhi r2,1 + 1d5c: 10ad7304 addi r2,r2,-18996 + 1d60: 100b883a mov r5,r2 + 1d64: 01000074 movhi r4,1 + 1d68: 212d7604 addi r4,r4,-18984 + 1d6c: 0006bc80 call 6bc8 + 1d70: 00001006 br 1db4 + 1d74: d0a0db17 ldw r2,-31892(gp) + 1d78: 1005003a cmpeq r2,r2,zero + 1d7c: 10803fcc andi r2,r2,255 + 1d80: d0a0db15 stw r2,-31892(gp) + 1d84: d0a0db17 ldw r2,-31892(gp) + 1d88: 1009883a mov r4,r2 + 1d8c: 0001a3c0 call 1a3c + 1d90: 00000806 br 1db4 + 1d94: 00019e80 call 19e8 + 1d98: 00000606 br 1db4 + 1d9c: 0001ac00 call 1ac0 + 1da0: 00000406 br 1db4 + 1da4: 01000074 movhi r4,1 + 1da8: 212d7c04 addi r4,r4,-18960 + 1dac: 0006cb00 call 6cb0 + 1db0: 0001883a nop + 1db4: 003f7906 br 1b9c + 1db8: 0001883a nop + 1dbc: 0001883a nop + 1dc0: e037883a mov sp,fp + 1dc4: dfc00117 ldw ra,4(sp) + 1dc8: df000017 ldw fp,0(sp) + 1dcc: dec00204 addi sp,sp,8 + 1dd0: f800283a ret + +00001dd4 : + 1dd4: defffe04 addi sp,sp,-8 + 1dd8: dfc00115 stw ra,4(sp) + 1ddc: df000015 stw fp,0(sp) + 1de0: d839883a mov fp,sp + 1de4: 01000074 movhi r4,1 + 1de8: 212d8004 addi r4,r4,-18944 + 1dec: 0006cb00 call 6cb0 + 1df0: 01000074 movhi r4,1 + 1df4: 212d8d04 addi r4,r4,-18892 + 1df8: 0006cb00 call 6cb0 + 1dfc: 01000074 movhi r4,1 + 1e00: 212d9704 addi r4,r4,-18852 + 1e04: 0006cb00 call 6cb0 + 1e08: 01000074 movhi r4,1 + 1e0c: 212da304 addi r4,r4,-18804 + 1e10: 0006cb00 call 6cb0 + 1e14: 01000074 movhi r4,1 + 1e18: 212dad04 addi r4,r4,-18764 + 1e1c: 0006cb00 call 6cb0 + 1e20: 01000074 movhi r4,1 + 1e24: 212db904 addi r4,r4,-18716 + 1e28: 0006cb00 call 6cb0 + 1e2c: 01000074 movhi r4,1 + 1e30: 212dc704 addi r4,r4,-18660 + 1e34: 0006cb00 call 6cb0 + 1e38: 01000074 movhi r4,1 + 1e3c: 212dd604 addi r4,r4,-18600 + 1e40: 0006cb00 call 6cb0 + 1e44: 01000074 movhi r4,1 + 1e48: 212de004 addi r4,r4,-18560 + 1e4c: 0006cb00 call 6cb0 + 1e50: 01000074 movhi r4,1 + 1e54: 212de904 addi r4,r4,-18524 + 1e58: 0006cb00 call 6cb0 + 1e5c: 01000074 movhi r4,1 + 1e60: 212df204 addi r4,r4,-18488 + 1e64: 0006cb00 call 6cb0 + 1e68: 01000074 movhi r4,1 + 1e6c: 212df504 addi r4,r4,-18476 + 1e70: 0006cb00 call 6cb0 + 1e74: 01000074 movhi r4,1 + 1e78: 212e0204 addi r4,r4,-18424 + 1e7c: 0006bc80 call 6bc8 + 1e80: 0001883a nop + 1e84: e037883a mov sp,fp + 1e88: dfc00117 ldw ra,4(sp) + 1e8c: df000017 ldw fp,0(sp) + 1e90: dec00204 addi sp,sp,8 + 1e94: f800283a ret + +00001e98 : + 1e98: defffd04 addi sp,sp,-12 + 1e9c: dfc00215 stw ra,8(sp) + 1ea0: df000115 stw fp,4(sp) + 1ea4: df000104 addi fp,sp,4 + 1ea8: 0001dd40 call 1dd4 + 1eac: e03fffc5 stb zero,-1(fp) + 1eb0: 00000206 br 1ebc + 1eb4: 0000b940 call b94 + 1eb8: e0bfffc5 stb r2,-1(fp) + 1ebc: e0bfffc7 ldb r2,-1(fp) + 1ec0: 10800810 cmplti r2,r2,32 + 1ec4: 103ffb1e bne r2,zero,1eb4 + 1ec8: e0bfffc7 ldb r2,-1(fp) + 1ecc: 100b883a mov r5,r2 + 1ed0: 01000074 movhi r4,1 + 1ed4: 212e0704 addi r4,r4,-18404 + 1ed8: 0006bc80 call 6bc8 + 1edc: e0bfffc7 ldb r2,-1(fp) + 1ee0: 10bff3c4 addi r2,r2,-49 + 1ee4: 10c010a8 cmpgeui r3,r2,66 + 1ee8: 1800801e bne r3,zero,20ec + 1eec: 100690ba slli r3,r2,2 + 1ef0: 00800034 movhi r2,0 + 1ef4: 1885883a add r2,r3,r2 + 1ef8: 1087c017 ldw r2,7936(r2) + 1efc: 1000683a jmp r2 + 1f00: 00002008 cmpgei zero,zero,128 + 1f04: 0000204c andi zero,zero,129 + 1f08: 00002090 cmplti zero,zero,130 + 1f0c: 00002098 cmpnei zero,zero,130 + 1f10: 000020a0 cmpeqi zero,zero,130 + 1f14: 000020b0 cmpltui zero,zero,130 + 1f18: 000020ec andhi zero,zero,131 + 1f1c: 000020a8 cmpgeui zero,zero,130 + 1f20: 000020ec andhi zero,zero,131 + 1f24: 000020ec andhi zero,zero,131 + 1f28: 000020ec andhi zero,zero,131 + 1f2c: 000020ec andhi zero,zero,131 + 1f30: 000020ec andhi zero,zero,131 + 1f34: 000020ec andhi zero,zero,131 + 1f38: 000020ec andhi zero,zero,131 + 1f3c: 000020ec andhi zero,zero,131 + 1f40: 000020ec andhi zero,zero,131 + 1f44: 000020ec andhi zero,zero,131 + 1f48: 000020b8 rdprs zero,zero,130 + 1f4c: 000020ec andhi zero,zero,131 + 1f50: 000020ec andhi zero,zero,131 + 1f54: 000020ec andhi zero,zero,131 + 1f58: 000020ec andhi zero,zero,131 + 1f5c: 000020ec andhi zero,zero,131 + 1f60: 000020ec andhi zero,zero,131 + 1f64: 000020ec andhi zero,zero,131 + 1f68: 000020ec andhi zero,zero,131 + 1f6c: 000020ec andhi zero,zero,131 + 1f70: 000020ec andhi zero,zero,131 + 1f74: 000020ec andhi zero,zero,131 + 1f78: 000020ec andhi zero,zero,131 + 1f7c: 000020ec andhi zero,zero,131 + 1f80: 000020ec andhi zero,zero,131 + 1f84: 000020ec andhi zero,zero,131 + 1f88: 000020ec andhi zero,zero,131 + 1f8c: 000020ec andhi zero,zero,131 + 1f90: 000020ec andhi zero,zero,131 + 1f94: 000020ec andhi zero,zero,131 + 1f98: 000020ec andhi zero,zero,131 + 1f9c: 000020ec andhi zero,zero,131 + 1fa0: 000020ec andhi zero,zero,131 + 1fa4: 000020ec andhi zero,zero,131 + 1fa8: 000020ec andhi zero,zero,131 + 1fac: 000020ec andhi zero,zero,131 + 1fb0: 000020ec andhi zero,zero,131 + 1fb4: 000020ec andhi zero,zero,131 + 1fb8: 000020ec andhi zero,zero,131 + 1fbc: 000020ec andhi zero,zero,131 + 1fc0: 000020ec andhi zero,zero,131 + 1fc4: 000020ec andhi zero,zero,131 + 1fc8: 000020b8 rdprs zero,zero,130 + 1fcc: 000020ec andhi zero,zero,131 + 1fd0: 000020ec andhi zero,zero,131 + 1fd4: 000020ec andhi zero,zero,131 + 1fd8: 000020ec andhi zero,zero,131 + 1fdc: 000020ec andhi zero,zero,131 + 1fe0: 000020ec andhi zero,zero,131 + 1fe4: 000020ec andhi zero,zero,131 + 1fe8: 000020ec andhi zero,zero,131 + 1fec: 000020ec andhi zero,zero,131 + 1ff0: 000020ec andhi zero,zero,131 + 1ff4: 000020ec andhi zero,zero,131 + 1ff8: 000020ec andhi zero,zero,131 + 1ffc: 000020ec andhi zero,zero,131 + 2000: 000020dc xori zero,zero,131 + 2004: 000020c0 call 20c + 2008: 00c80034 movhi r3,8192 + 200c: 008000b4 movhi r2,2 + 2010: 10c00235 stwio r3,8(r2) + 2014: 01000074 movhi r4,1 + 2018: 212e0804 addi r4,r4,-18400 + 201c: 0006cb00 call 6cb0 + 2020: 01480034 movhi r5,8192 + 2024: 012000b4 movhi r4,32770 + 2028: 21002804 addi r4,r4,160 + 202c: 00002840 call 284 + 2030: 00cc0034 movhi r3,12288 + 2034: 008000b4 movhi r2,2 + 2038: 10c00235 stwio r3,8(r2) + 203c: 01000074 movhi r4,1 + 2040: 212e1504 addi r4,r4,-18348 + 2044: 0006cb00 call 6cb0 + 2048: 00002c06 br 20fc + 204c: 00c80034 movhi r3,8192 + 2050: 008000b4 movhi r2,2 + 2054: 10c00235 stwio r3,8(r2) + 2058: 01000074 movhi r4,1 + 205c: 212e0804 addi r4,r4,-18400 + 2060: 0006cb00 call 6cb0 + 2064: 01480034 movhi r5,8192 + 2068: 012000b4 movhi r4,32770 + 206c: 21003004 addi r4,r4,192 + 2070: 00006a00 call 6a0 + 2074: 00cc0034 movhi r3,12288 + 2078: 008000b4 movhi r2,2 + 207c: 10c00235 stwio r3,8(r2) + 2080: 01000074 movhi r4,1 + 2084: 212e1504 addi r4,r4,-18348 + 2088: 0006cb00 call 6cb0 + 208c: 00001b06 br 20fc + 2090: 0000d940 call d94 + 2094: 00001906 br 20fc + 2098: 0000f300 call f30 + 209c: 00001706 br 20fc + 20a0: 00012600 call 1260 + 20a4: 00001506 br 20fc + 20a8: 0001b8c0 call 1b8c + 20ac: 00001306 br 20fc + 20b0: 00011280 call 1128 + 20b4: 00001106 br 20fc + 20b8: 00019400 call 1940 + 20bc: 00000f06 br 20fc + 20c0: 0007883a mov r3,zero + 20c4: 00a000b4 movhi r2,32770 + 20c8: 10c00835 stwio r3,32(r2) + 20cc: 01000074 movhi r4,1 + 20d0: 212e2104 addi r4,r4,-18300 + 20d4: 0006cb00 call 6cb0 + 20d8: 00000806 br 20fc + 20dc: 01000074 movhi r4,1 + 20e0: 212e2904 addi r4,r4,-18268 + 20e4: 0006cb00 call 6cb0 + 20e8: 00000506 br 2100 + 20ec: 01000074 movhi r4,1 + 20f0: 212e2e04 addi r4,r4,-18248 + 20f4: 0006cb00 call 6cb0 + 20f8: 0001883a nop + 20fc: 003f6a06 br 1ea8 + 2100: e037883a mov sp,fp + 2104: dfc00117 ldw ra,4(sp) + 2108: df000017 ldw fp,0(sp) + 210c: dec00204 addi sp,sp,8 + 2110: f800283a ret + +00002114
: + 2114: defff704 addi sp,sp,-36 + 2118: dfc00815 stw ra,32(sp) + 211c: df000715 stw fp,28(sp) + 2120: df000704 addi fp,sp,28 + 2124: 01000074 movhi r4,1 + 2128: 212e3704 addi r4,r4,-18212 + 212c: 0006cb00 call 6cb0 + 2130: 00800044 movi r2,1 + 2134: 1001703a wrctl status,r2 + 2138: 00c001c4 movi r3,7 + 213c: 008000b4 movhi r2,2 + 2140: 10c02135 stwio r3,132(r2) + 2144: 01000074 movhi r4,1 + 2148: 212e4404 addi r4,r4,-18160 + 214c: 0006bc80 call 6bc8 + 2150: 0000c0c0 call c0c + 2154: e0bffe15 stw r2,-8(fp) + 2158: e0ffff15 stw r3,-4(fp) + 215c: e03ff915 stw zero,-28(fp) + 2160: 00000306 br 2170 + 2164: e0bff917 ldw r2,-28(fp) + 2168: 10800044 addi r2,r2,1 + 216c: e0bff915 stw r2,-28(fp) + 2170: e0bff917 ldw r2,-28(fp) + 2174: 1089c410 cmplti r2,r2,10000 + 2178: 103ffa1e bne r2,zero,2164 + 217c: 0000c0c0 call c0c + 2180: e0bffc15 stw r2,-16(fp) + 2184: e0fffd15 stw r3,-12(fp) + 2188: e0bffd17 ldw r2,-12(fp) + 218c: e0ffff17 ldw r3,-4(fp) + 2190: 18800636 bltu r3,r2,21ac + 2194: e0fffd17 ldw r3,-12(fp) + 2198: e0bfff17 ldw r2,-4(fp) + 219c: 18800b1e bne r3,r2,21cc + 21a0: e0bffc17 ldw r2,-16(fp) + 21a4: e0fffe17 ldw r3,-8(fp) + 21a8: 1880082e bgeu r3,r2,21cc + 21ac: e0fffc17 ldw r3,-16(fp) + 21b0: e0bffe17 ldw r2,-8(fp) + 21b4: 1885c83a sub r2,r3,r2 + 21b8: 100b883a mov r5,r2 + 21bc: 01000074 movhi r4,1 + 21c0: 212e4904 addi r4,r4,-18140 + 21c4: 0006bc80 call 6bc8 + 21c8: 00000506 br 21e0 + 21cc: e0bffe17 ldw r2,-8(fp) + 21d0: 100b883a mov r5,r2 + 21d4: 01000074 movhi r4,1 + 21d8: 212e4f04 addi r4,r4,-18116 + 21dc: 0006bc80 call 6bc8 + 21e0: 008c0034 movhi r2,12288 + 21e4: e0bffb15 stw r2,-20(fp) + 21e8: e17ffb17 ldw r5,-20(fp) + 21ec: 01000074 movhi r4,1 + 21f0: 212e5504 addi r4,r4,-18092 + 21f4: 0006bc80 call 6bc8 + 21f8: e0fffb17 ldw r3,-20(fp) + 21fc: 008000b4 movhi r2,2 + 2200: 10c00235 stwio r3,8(r2) + 2204: 0007883a mov r3,zero + 2208: 008000b4 movhi r2,2 + 220c: 10c00335 stwio r3,12(r2) + 2210: 01000074 movhi r4,1 + 2214: 212e6004 addi r4,r4,-18048 + 2218: 0006cb00 call 6cb0 + 221c: 01000074 movhi r4,1 + 2220: 212e6204 addi r4,r4,-18040 + 2224: 0006bc80 call 6bc8 + 2228: 008000b4 movhi r2,2 + 222c: 10800437 ldwio r2,16(r2) + 2230: e0bffa15 stw r2,-24(fp) + 2234: e0bffa17 ldw r2,-24(fp) + 2238: 1080004c andi r2,r2,1 + 223c: 10000526 beq r2,zero,2254 + 2240: e17ffa17 ldw r5,-24(fp) + 2244: 01000074 movhi r4,1 + 2248: 212e6a04 addi r4,r4,-18008 + 224c: 0006bc80 call 6bc8 + 2250: 00000706 br 2270 + 2254: e17ffa17 ldw r5,-24(fp) + 2258: 01000074 movhi r4,1 + 225c: 212e6e04 addi r4,r4,-17992 + 2260: 0006bc80 call 6bc8 + 2264: 01000074 movhi r4,1 + 2268: 212e7204 addi r4,r4,-17976 + 226c: 0006cb00 call 6cb0 + 2270: 0001e980 call 1e98 + 2274: 0005883a mov r2,zero + 2278: e037883a mov sp,fp + 227c: dfc00117 ldw ra,4(sp) + 2280: df000017 ldw fp,0(sp) + 2284: dec00204 addi sp,sp,8 + 2288: f800283a ret + +0000228c : + 228c: defff704 addi sp,sp,-36 + 2290: dd400515 stw r21,20(sp) + 2294: dd000415 stw r20,16(sp) + 2298: dcc00315 stw r19,12(sp) + 229c: dc800215 stw r18,8(sp) + 22a0: dc400115 stw r17,4(sp) + 22a4: dc000015 stw r16,0(sp) + 22a8: 202b883a mov r21,r4 + 22ac: dfc00815 stw ra,32(sp) + 22b0: ddc00715 stw r23,28(sp) + 22b4: dd800615 stw r22,24(sp) + 22b8: 2823883a mov r17,r5 + 22bc: 3021883a mov r16,r6 + 22c0: 3825883a mov r18,r7 + 22c4: 00026240 call 2624 <__ieee754_pow> + 22c8: 01000074 movhi r4,1 + 22cc: 222f9317 ldw r8,-16820(r4) + 22d0: 1029883a mov r20,r2 + 22d4: 1827883a mov r19,r3 + 22d8: 423fffe0 cmpeqi r8,r8,-1 + 22dc: 40002f1e bne r8,zero,239c + 22e0: 800d883a mov r6,r16 + 22e4: 900f883a mov r7,r18 + 22e8: 8009883a mov r4,r16 + 22ec: 900b883a mov r5,r18 + 22f0: 000687c0 call 687c <__unorddf2> + 22f4: 1000291e bne r2,zero,239c + 22f8: a80d883a mov r6,r21 + 22fc: 880f883a mov r7,r17 + 2300: a809883a mov r4,r21 + 2304: 880b883a mov r5,r17 + 2308: 000687c0 call 687c <__unorddf2> + 230c: 000d883a mov r6,zero + 2310: 000f883a mov r7,zero + 2314: 1000a61e bne r2,zero,25b0 + 2318: a809883a mov r4,r21 + 231c: 880b883a mov r5,r17 + 2320: 00057040 call 5704 <__eqdf2> + 2324: 10002a1e bne r2,zero,23d0 + 2328: 000d883a mov r6,zero + 232c: 000f883a mov r7,zero + 2330: 8009883a mov r4,r16 + 2334: 900b883a mov r5,r18 + 2338: 00057040 call 5704 <__eqdf2> + 233c: 1000a026 beq r2,zero,25c0 + 2340: 01600034 movhi r5,32768 + 2344: 297fffc4 addi r5,r5,-1 + 2348: 9162703a and r17,r18,r5 + 234c: 01dffc34 movhi r7,32752 + 2350: 01bfffc4 movi r6,-1 + 2354: 39ffffc4 addi r7,r7,-1 + 2358: 8009883a mov r4,r16 + 235c: 880b883a mov r5,r17 + 2360: 000687c0 call 687c <__unorddf2> + 2364: 10000d1e bne r2,zero,239c + 2368: 01dffc34 movhi r7,32752 + 236c: 01bfffc4 movi r6,-1 + 2370: 39ffffc4 addi r7,r7,-1 + 2374: 8009883a mov r4,r16 + 2378: 880b883a mov r5,r17 + 237c: 00057840 call 5784 <__gedf2> + 2380: 00800616 blt zero,r2,239c + 2384: 000d883a mov r6,zero + 2388: 000f883a mov r7,zero + 238c: 8009883a mov r4,r16 + 2390: 900b883a mov r5,r18 + 2394: 000586c0 call 586c <__ledf2> + 2398: 10008c16 blt r2,zero,25cc + 239c: a005883a mov r2,r20 + 23a0: 9807883a mov r3,r19 + 23a4: dfc00817 ldw ra,32(sp) + 23a8: ddc00717 ldw r23,28(sp) + 23ac: dd800617 ldw r22,24(sp) + 23b0: dd400517 ldw r21,20(sp) + 23b4: dd000417 ldw r20,16(sp) + 23b8: dcc00317 ldw r19,12(sp) + 23bc: dc800217 ldw r18,8(sp) + 23c0: dc400117 ldw r17,4(sp) + 23c4: dc000017 ldw r16,0(sp) + 23c8: dec00904 addi sp,sp,36 + 23cc: f800283a ret + 23d0: 01600034 movhi r5,32768 + 23d4: 297fffc4 addi r5,r5,-1 + 23d8: 996c703a and r22,r19,r5 + 23dc: 01dffc34 movhi r7,32752 + 23e0: 01bfffc4 movi r6,-1 + 23e4: 39ffffc4 addi r7,r7,-1 + 23e8: a009883a mov r4,r20 + 23ec: b00b883a mov r5,r22 + 23f0: 000687c0 call 687c <__unorddf2> + 23f4: 1000331e bne r2,zero,24c4 + 23f8: 01dffc34 movhi r7,32752 + 23fc: 01bfffc4 movi r6,-1 + 2400: 39ffffc4 addi r7,r7,-1 + 2404: a009883a mov r4,r20 + 2408: b00b883a mov r5,r22 + 240c: 00057840 call 5784 <__gedf2> + 2410: 00802c16 blt zero,r2,24c4 + 2414: 000d883a mov r6,zero + 2418: 000f883a mov r7,zero + 241c: a009883a mov r4,r20 + 2420: 980b883a mov r5,r19 + 2424: 00057040 call 5704 <__eqdf2> + 2428: 103fdc1e bne r2,zero,239c + 242c: 05a00034 movhi r22,32768 + 2430: b5bfffc4 addi r22,r22,-1 + 2434: 8da2703a and r17,r17,r22 + 2438: 01dffc34 movhi r7,32752 + 243c: 01bfffc4 movi r6,-1 + 2440: 39ffffc4 addi r7,r7,-1 + 2444: a809883a mov r4,r21 + 2448: 880b883a mov r5,r17 + 244c: 000687c0 call 687c <__unorddf2> + 2450: 103fd21e bne r2,zero,239c + 2454: 01dffc34 movhi r7,32752 + 2458: 01bfffc4 movi r6,-1 + 245c: 39ffffc4 addi r7,r7,-1 + 2460: a809883a mov r4,r21 + 2464: 880b883a mov r5,r17 + 2468: 00057840 call 5784 <__gedf2> + 246c: 00bfcb16 blt zero,r2,239c + 2470: 95a4703a and r18,r18,r22 + 2474: 01dffc34 movhi r7,32752 + 2478: 01bfffc4 movi r6,-1 + 247c: 39ffffc4 addi r7,r7,-1 + 2480: 8009883a mov r4,r16 + 2484: 900b883a mov r5,r18 + 2488: 000687c0 call 687c <__unorddf2> + 248c: 103fc31e bne r2,zero,239c + 2490: 01dffc34 movhi r7,32752 + 2494: 01bfffc4 movi r6,-1 + 2498: 39ffffc4 addi r7,r7,-1 + 249c: 8009883a mov r4,r16 + 24a0: 900b883a mov r5,r18 + 24a4: 00057840 call 5784 <__gedf2> + 24a8: 00bfbc16 blt zero,r2,239c + 24ac: 0006b580 call 6b58 <__errno> + 24b0: 00c00884 movi r3,34 + 24b4: 10c00015 stw r3,0(r2) + 24b8: 0029883a mov r20,zero + 24bc: 0027883a mov r19,zero + 24c0: 003fb606 br 239c + 24c4: 05a00034 movhi r22,32768 + 24c8: b5bfffc4 addi r22,r22,-1 + 24cc: 8dae703a and r23,r17,r22 + 24d0: 01dffc34 movhi r7,32752 + 24d4: 01bfffc4 movi r6,-1 + 24d8: 39ffffc4 addi r7,r7,-1 + 24dc: a809883a mov r4,r21 + 24e0: b80b883a mov r5,r23 + 24e4: 000687c0 call 687c <__unorddf2> + 24e8: 103fac1e bne r2,zero,239c + 24ec: 01dffc34 movhi r7,32752 + 24f0: 01bfffc4 movi r6,-1 + 24f4: 39ffffc4 addi r7,r7,-1 + 24f8: a809883a mov r4,r21 + 24fc: b80b883a mov r5,r23 + 2500: 00057840 call 5784 <__gedf2> + 2504: 00bfa516 blt zero,r2,239c + 2508: 95ac703a and r22,r18,r22 + 250c: 01dffc34 movhi r7,32752 + 2510: 01bfffc4 movi r6,-1 + 2514: 39ffffc4 addi r7,r7,-1 + 2518: 8009883a mov r4,r16 + 251c: b00b883a mov r5,r22 + 2520: 000687c0 call 687c <__unorddf2> + 2524: 103fbb1e bne r2,zero,2414 + 2528: 01dffc34 movhi r7,32752 + 252c: 01bfffc4 movi r6,-1 + 2530: 39ffffc4 addi r7,r7,-1 + 2534: 8009883a mov r4,r16 + 2538: b00b883a mov r5,r22 + 253c: 00057840 call 5784 <__gedf2> + 2540: 00bfb416 blt zero,r2,2414 + 2544: a00d883a mov r6,r20 + 2548: 980f883a mov r7,r19 + 254c: a009883a mov r4,r20 + 2550: 980b883a mov r5,r19 + 2554: 000687c0 call 687c <__unorddf2> + 2558: 1000271e bne r2,zero,25f8 + 255c: 0006b580 call 6b58 <__errno> + 2560: 00c00884 movi r3,34 + 2564: 10c00015 stw r3,0(r2) + 2568: 000d883a mov r6,zero + 256c: 000f883a mov r7,zero + 2570: a809883a mov r4,r21 + 2574: 880b883a mov r5,r17 + 2578: 000586c0 call 586c <__ledf2> + 257c: 1000190e bge r2,zero,25e4 + 2580: 8009883a mov r4,r16 + 2584: 900b883a mov r5,r18 + 2588: 00039500 call 3950 + 258c: 800d883a mov r6,r16 + 2590: 900f883a mov r7,r18 2594: 1009883a mov r4,r2 - 2598: d8800215 stw r2,8(sp) - 259c: 00034c00 call 34c0 <__addsf3> - 25a0: da000017 ldw r8,0(sp) - 25a4: 1009883a mov r4,r2 - 25a8: 400b883a mov r5,r8 - 25ac: da000115 stw r8,4(sp) - 25b0: 00034c00 call 34c0 <__addsf3> - 25b4: 1520703a and r16,r2,r20 - 25b8: 800b883a mov r5,r16 - 25bc: a809883a mov r4,r21 - 25c0: 0003efc0 call 3efc <__mulsf3> - 25c4: 8009883a mov r4,r16 - 25c8: 01501034 movhi r5,16448 - 25cc: d8800015 stw r2,0(sp) - 25d0: 00042b00 call 42b0 <__subsf3> - 25d4: da400217 ldw r9,8(sp) - 25d8: 1009883a mov r4,r2 - 25dc: 480b883a mov r5,r9 - 25e0: 00042b00 call 42b0 <__subsf3> - 25e4: da000117 ldw r8,4(sp) - 25e8: 100b883a mov r5,r2 - 25ec: 4009883a mov r4,r8 - 25f0: 00042b00 call 42b0 <__subsf3> - 25f4: e00b883a mov r5,fp - 25f8: 1009883a mov r4,r2 - 25fc: 0003efc0 call 3efc <__mulsf3> - 2600: 800b883a mov r5,r16 - 2604: b009883a mov r4,r22 - 2608: 102b883a mov r21,r2 - 260c: 0003efc0 call 3efc <__mulsf3> - 2610: a809883a mov r4,r21 - 2614: 100b883a mov r5,r2 - 2618: 00034c00 call 34c0 <__addsf3> - 261c: d8c00017 ldw r3,0(sp) - 2620: 100b883a mov r5,r2 - 2624: 102b883a mov r21,r2 - 2628: 1809883a mov r4,r3 - 262c: 00034c00 call 34c0 <__addsf3> - 2630: 1520703a and r16,r2,r20 - 2634: 014fddb4 movhi r5,16246 - 2638: 8009883a mov r4,r16 - 263c: 294e0004 addi r5,r5,14336 - 2640: 0003efc0 call 3efc <__mulsf3> - 2644: d8c00017 ldw r3,0(sp) - 2648: 8009883a mov r4,r16 - 264c: 102d883a mov r22,r2 - 2650: 180b883a mov r5,r3 - 2654: 00042b00 call 42b0 <__subsf3> - 2658: a809883a mov r4,r21 - 265c: 100b883a mov r5,r2 - 2660: 00042b00 call 42b0 <__subsf3> - 2664: 014fddb4 movhi r5,16246 - 2668: 294e13c4 addi r5,r5,14415 - 266c: 1009883a mov r4,r2 - 2670: 0003efc0 call 3efc <__mulsf3> - 2674: 014da7b4 movhi r5,13982 - 2678: 8009883a mov r4,r16 - 267c: 2970e804 addi r5,r5,-15456 - 2680: 102b883a mov r21,r2 - 2684: 0003efc0 call 3efc <__mulsf3> - 2688: a809883a mov r4,r21 - 268c: 100b883a mov r5,r2 - 2690: 00034c00 call 34c0 <__addsf3> - 2694: d9c00417 ldw r7,16(sp) - 2698: 1009883a mov r4,r2 - 269c: 380b883a mov r5,r7 - 26a0: 00034c00 call 34c0 <__addsf3> - 26a4: d9800317 ldw r6,12(sp) - 26a8: 102b883a mov r21,r2 - 26ac: 3009883a mov r4,r6 - 26b0: 00048000 call 4800 <__floatsisf> - 26b4: a80b883a mov r5,r21 - 26b8: b009883a mov r4,r22 - 26bc: 1021883a mov r16,r2 - 26c0: 00034c00 call 34c0 <__addsf3> - 26c4: da800517 ldw r10,20(sp) - 26c8: 1009883a mov r4,r2 - 26cc: 500b883a mov r5,r10 - 26d0: da800015 stw r10,0(sp) - 26d4: 00034c00 call 34c0 <__addsf3> - 26d8: 800b883a mov r5,r16 - 26dc: 1009883a mov r4,r2 - 26e0: 00034c00 call 34c0 <__addsf3> - 26e4: 1508703a and r4,r2,r20 - 26e8: 800b883a mov r5,r16 - 26ec: 2021883a mov r16,r4 - 26f0: 00042b00 call 42b0 <__subsf3> - 26f4: da800017 ldw r10,0(sp) - 26f8: 1009883a mov r4,r2 - 26fc: 500b883a mov r5,r10 - 2700: 00042b00 call 42b0 <__subsf3> - 2704: b00b883a mov r5,r22 - 2708: 1009883a mov r4,r2 - 270c: 00042b00 call 42b0 <__subsf3> - 2710: 100b883a mov r5,r2 - 2714: a809883a mov r4,r21 - 2718: 00042b00 call 42b0 <__subsf3> - 271c: 1029883a mov r20,r2 - 2720: 003e2b06 br 1fd0 <__ieee754_powf+0x1d8> - 2724: 9cc00058 cmpnei r19,r19,1 - 2728: 983dc71e bne r19,zero,1e48 <__ieee754_powf+0x50> - 272c: 10a0003c xorhi r2,r2,32768 - 2730: 003dc506 br 1e48 <__ieee754_powf+0x50> - 2734: 3180004c andi r6,r6,1 - 2738: 04c00084 movi r19,2 - 273c: 99a7c83a sub r19,r19,r6 - 2740: 003dd306 br 1e90 <__ieee754_powf+0x98> - 2744: dfc00f17 ldw ra,60(sp) - 2748: df000e17 ldw fp,56(sp) - 274c: ddc00d17 ldw r23,52(sp) - 2750: dd800c17 ldw r22,48(sp) - 2754: dd400b17 ldw r21,44(sp) - 2758: dd000a17 ldw r20,40(sp) - 275c: dcc00917 ldw r19,36(sp) - 2760: dc800817 ldw r18,32(sp) - 2764: dc400717 ldw r17,28(sp) - 2768: dc000617 ldw r16,24(sp) - 276c: dec01004 addi sp,sp,64 - 2770: 00028f81 jmpi 28f8 <__ieee754_sqrtf> - 2774: 048fe034 movhi r18,16256 - 2778: 003e1906 br 1fe0 <__ieee754_powf+0x1e8> - 277c: 0090c5b4 movhi r2,17174 - 2780: 14004f16 blt r2,r16,28c0 <__ieee754_powf+0xac8> - 2784: 80be381e bne r16,r2,2068 <__ieee754_powf+0x270> - 2788: a00b883a mov r5,r20 - 278c: 9809883a mov r4,r19 - 2790: 00042b00 call 42b0 <__subsf3> - 2794: 880b883a mov r5,r17 - 2798: 1009883a mov r4,r2 - 279c: 0003d900 call 3d90 <__gesf2> - 27a0: 1000470e bge r2,zero,28c0 <__ieee754_powf+0xac8> - 27a4: 8005d5fa srai r2,r16,23 - 27a8: 00c02034 movhi r3,128 - 27ac: 10bfe084 addi r2,r2,-126 - 27b0: 1887d83a sra r3,r3,r2 - 27b4: 00802034 movhi r2,128 - 27b8: 10bfffc4 addi r2,r2,-1 - 27bc: 1cc7883a add r3,r3,r19 - 27c0: 1809d5fa srai r4,r3,23 - 27c4: 18a6703a and r19,r3,r2 - 27c8: 9cc02034 orhi r19,r19,128 - 27cc: 21003fcc andi r4,r4,255 - 27d0: 213fe044 addi r4,r4,-127 - 27d4: 110bd83a sra r5,r2,r4 - 27d8: 008005c4 movi r2,23 - 27dc: 1109c83a sub r4,r2,r4 - 27e0: 014a303a nor r5,zero,r5 - 27e4: 9927d83a sra r19,r19,r4 - 27e8: 28ca703a and r5,r5,r3 - 27ec: b000010e bge r22,zero,27f4 <__ieee754_powf+0x9fc> - 27f0: 04e7c83a sub r19,zero,r19 - 27f4: a009883a mov r4,r20 - 27f8: 00042b00 call 42b0 <__subsf3> - 27fc: 100b883a mov r5,r2 - 2800: 8809883a mov r4,r17 - 2804: 102b883a mov r21,r2 - 2808: 00034c00 call 34c0 <__addsf3> - 280c: 982895fa slli r20,r19,23 - 2810: 1007883a mov r3,r2 - 2814: 003e1806 br 2078 <__ieee754_powf+0x280> - 2818: 0015883a mov r10,zero - 281c: 000f883a mov r7,zero - 2820: d8000215 stw zero,8(sp) - 2824: 020fe034 movhi r8,16256 - 2828: 003ee506 br 23c0 <__ieee754_powf+0x5c8> - 282c: 0007883a mov r3,zero - 2830: 003ecf06 br 2370 <__ieee754_powf+0x578> - 2834: 014cce74 movhi r5,13113 - 2838: 296a8f04 addi r5,r5,-21956 - 283c: 8809883a mov r4,r17 - 2840: 00034c00 call 34c0 <__addsf3> - 2844: a00b883a mov r5,r20 - 2848: 9809883a mov r4,r19 - 284c: 102b883a mov r21,r2 - 2850: 00042b00 call 42b0 <__subsf3> - 2854: 100b883a mov r5,r2 - 2858: a809883a mov r4,r21 - 285c: 0003d900 call 3d90 <__gesf2> - 2860: 00bfd00e bge zero,r2,27a4 <__ieee754_powf+0x9ac> - 2864: 015c52b4 movhi r5,29002 - 2868: 9009883a mov r4,r18 - 286c: 297cb284 addi r5,r5,-3382 - 2870: 0003efc0 call 3efc <__mulsf3> - 2874: 015c52b4 movhi r5,29002 - 2878: 297cb284 addi r5,r5,-3382 - 287c: 1009883a mov r4,r2 - 2880: 0003efc0 call 3efc <__mulsf3> - 2884: 003d7006 br 1e48 <__ieee754_powf+0x50> - 2888: 283eaa0e bge r5,zero,2334 <__ieee754_powf+0x53c> - 288c: 015c52b4 movhi r5,29002 - 2890: 297cb284 addi r5,r5,-3382 - 2894: 2809883a mov r4,r5 - 2898: 0003efc0 call 3efc <__mulsf3> - 289c: 003d6a06 br 1e48 <__ieee754_powf+0x50> - 28a0: 028fc5b4 movhi r10,16150 - 28a4: 01cd74b4 movhi r7,13778 - 28a8: 00800834 movhi r2,32 - 28ac: 52b00004 addi r10,r10,-16384 - 28b0: 39f3f704 addi r7,r7,-12324 - 28b4: d8800215 stw r2,8(sp) - 28b8: 020ff034 movhi r8,16320 - 28bc: 003ec006 br 23c0 <__ieee754_powf+0x5c8> - 28c0: 014368b4 movhi r5,3490 - 28c4: 9009883a mov r4,r18 - 28c8: 29509804 addi r5,r5,16992 - 28cc: 0003efc0 call 3efc <__mulsf3> - 28d0: 014368b4 movhi r5,3490 - 28d4: 29509804 addi r5,r5,16992 - 28d8: 1009883a mov r4,r2 - 28dc: 0003efc0 call 3efc <__mulsf3> - 28e0: 003d5906 br 1e48 <__ieee754_powf+0x50> - 28e4: 1009883a mov r4,r2 - 28e8: 980b883a mov r5,r19 - 28ec: 0002b700 call 2b70 - 28f0: 1009883a mov r4,r2 - 28f4: 003e4a06 br 2220 <__ieee754_powf+0x428> - -000028f8 <__ieee754_sqrtf>: - 28f8: 00a00034 movhi r2,32768 - 28fc: defffe04 addi sp,sp,-8 - 2900: 10bfffc4 addi r2,r2,-1 - 2904: dc000015 stw r16,0(sp) - 2908: dfc00115 stw ra,4(sp) - 290c: 1104703a and r2,r2,r4 - 2910: 00dfe034 movhi r3,32640 - 2914: 2021883a mov r16,r4 - 2918: 200b883a mov r5,r4 - 291c: 10c0362e bgeu r2,r3,29f8 <__ieee754_sqrtf+0x100> - 2920: 10003026 beq r2,zero,29e4 <__ieee754_sqrtf+0xec> - 2924: 2005883a mov r2,r4 - 2928: 20003d16 blt r4,zero,2a20 <__ieee754_sqrtf+0x128> - 292c: 211fe02c andhi r4,r4,32640 - 2930: 8007d5fa srai r3,r16,23 - 2934: 2000081e bne r4,zero,2958 <__ieee754_sqrtf+0x60> - 2938: 8400202c andhi r16,r16,128 - 293c: 8000401e bne r16,zero,2a40 <__ieee754_sqrtf+0x148> - 2940: 1085883a add r2,r2,r2 - 2944: 1100202c andhi r4,r2,128 - 2948: 800b883a mov r5,r16 - 294c: 84000044 addi r16,r16,1 - 2950: 203ffb26 beq r4,zero,2940 <__ieee754_sqrtf+0x48> - 2954: 1947c83a sub r3,r3,r5 - 2958: 01002034 movhi r4,128 - 295c: 213fffc4 addi r4,r4,-1 - 2960: 1104703a and r2,r2,r4 - 2964: 18ffe044 addi r3,r3,-127 - 2968: 11002034 orhi r4,r2,128 - 296c: 1940004c andi r5,r3,1 - 2970: 2105883a add r2,r4,r4 - 2974: 2800281e bne r5,zero,2a18 <__ieee754_sqrtf+0x120> - 2978: 1821d07a srai r16,r3,1 - 297c: 01000644 movi r4,25 - 2980: 000f883a mov r7,zero - 2984: 000d883a mov r6,zero - 2988: 00c04034 movhi r3,256 - 298c: 30cb883a add r5,r6,r3 - 2990: 213fffc4 addi r4,r4,-1 - 2994: 11400316 blt r2,r5,29a4 <__ieee754_sqrtf+0xac> - 2998: 28cd883a add r6,r5,r3 - 299c: 1145c83a sub r2,r2,r5 - 29a0: 38cf883a add r7,r7,r3 - 29a4: 1806d07a srli r3,r3,1 - 29a8: 1085883a add r2,r2,r2 - 29ac: 203ff71e bne r4,zero,298c <__ieee754_sqrtf+0x94> - 29b0: 10000326 beq r2,zero,29c0 <__ieee754_sqrtf+0xc8> - 29b4: 39c00044 addi r7,r7,1 - 29b8: 00bfff84 movi r2,-2 - 29bc: 388e703a and r7,r7,r2 - 29c0: 380fd07a srai r7,r7,1 - 29c4: 800495fa slli r2,r16,23 - 29c8: 040fc034 movhi r16,16128 - 29cc: 3c21883a add r16,r7,r16 - 29d0: 1405883a add r2,r2,r16 - 29d4: dfc00117 ldw ra,4(sp) - 29d8: dc000017 ldw r16,0(sp) - 29dc: dec00204 addi sp,sp,8 - 29e0: f800283a ret - 29e4: 2005883a mov r2,r4 - 29e8: dfc00117 ldw ra,4(sp) - 29ec: dc000017 ldw r16,0(sp) - 29f0: dec00204 addi sp,sp,8 - 29f4: f800283a ret - 29f8: 0003efc0 call 3efc <__mulsf3> - 29fc: 800b883a mov r5,r16 - 2a00: 1009883a mov r4,r2 - 2a04: 00034c00 call 34c0 <__addsf3> - 2a08: dfc00117 ldw ra,4(sp) - 2a0c: dc000017 ldw r16,0(sp) - 2a10: dec00204 addi sp,sp,8 - 2a14: f800283a ret - 2a18: 200490ba slli r2,r4,2 - 2a1c: 003fd606 br 2978 <__ieee754_sqrtf+0x80> - 2a20: 00042b00 call 42b0 <__subsf3> - 2a24: 100b883a mov r5,r2 - 2a28: 1009883a mov r4,r2 - 2a2c: 000392c0 call 392c <__divsf3> - 2a30: dfc00117 ldw ra,4(sp) - 2a34: dc000017 ldw r16,0(sp) - 2a38: dec00204 addi sp,sp,8 - 2a3c: f800283a ret - 2a40: 017fffc4 movi r5,-1 - 2a44: 003fc306 br 2954 <__ieee754_sqrtf+0x5c> - -00002a48 : - 2a48: defffb04 addi sp,sp,-20 - 2a4c: dc000115 stw r16,4(sp) - 2a50: 04200034 movhi r16,32768 - 2a54: 843fffc4 addi r16,r16,-1 - 2a58: 8106703a and r3,r16,r4 - 2a5c: 180ad5fa srli r5,r3,23 - 2a60: dfc00415 stw ra,16(sp) - 2a64: dc800315 stw r18,12(sp) - 2a68: 297fe044 addi r5,r5,-127 - 2a6c: dc400215 stw r17,8(sp) - 2a70: 298005c8 cmpgei r6,r5,23 - 2a74: 2005883a mov r2,r4 - 2a78: 3000221e bne r6,zero,2b04 - 2a7c: 18001b26 beq r3,zero,2aec - 2a80: 2023883a mov r17,r4 - 2a84: 2008d7fa srli r4,r4,31 - 2a88: 28002316 blt r5,zero,2b18 - 2a8c: 00c02034 movhi r3,128 - 2a90: 18ffffc4 addi r3,r3,-1 - 2a94: 1947d83a sra r3,r3,r5 - 2a98: 10cc703a and r6,r2,r3 - 2a9c: 30001326 beq r6,zero,2aec - 2aa0: 1806d07a srli r3,r3,1 - 2aa4: 10cc703a and r6,r2,r3 - 2aa8: 30000526 beq r6,zero,2ac0 - 2aac: 00800834 movhi r2,32 - 2ab0: 1145d83a sra r2,r2,r5 - 2ab4: 00c6303a nor r3,zero,r3 - 2ab8: 1c46703a and r3,r3,r17 - 2abc: 1884b03a or r2,r3,r2 - 2ac0: 200890ba slli r4,r4,2 - 2ac4: 00c00074 movhi r3,1 - 2ac8: 100b883a mov r5,r2 - 2acc: 20c7883a add r3,r4,r3 - 2ad0: 1c266c17 ldw r16,-26192(r3) - 2ad4: 8009883a mov r4,r16 - 2ad8: 00034c00 call 34c0 <__addsf3> - 2adc: d8800015 stw r2,0(sp) - 2ae0: d9000017 ldw r4,0(sp) - 2ae4: 800b883a mov r5,r16 - 2ae8: 00042b00 call 42b0 <__subsf3> - 2aec: dfc00417 ldw ra,16(sp) - 2af0: dc800317 ldw r18,12(sp) - 2af4: dc400217 ldw r17,8(sp) - 2af8: dc000117 ldw r16,4(sp) - 2afc: dec00504 addi sp,sp,20 - 2b00: f800283a ret - 2b04: 015fe034 movhi r5,32640 - 2b08: 197ff836 bltu r3,r5,2aec - 2b0c: 200b883a mov r5,r4 - 2b10: 00034c00 call 34c0 <__addsf3> - 2b14: 003ff506 br 2aec - 2b18: 00802034 movhi r2,128 - 2b1c: 200890ba slli r4,r4,2 - 2b20: 10bfffc4 addi r2,r2,-1 - 2b24: 8884703a and r2,r17,r2 - 2b28: 0085c83a sub r2,zero,r2 - 2b2c: 00c00074 movhi r3,1 - 2b30: 20c7883a add r3,r4,r3 - 2b34: 1004d27a srli r2,r2,9 - 2b38: 1ca66c17 ldw r18,-26192(r3) - 2b3c: 897ffc2c andhi r5,r17,65520 - 2b40: 1080102c andhi r2,r2,64 - 2b44: 114ab03a or r5,r2,r5 - 2b48: 9009883a mov r4,r18 - 2b4c: 00034c00 call 34c0 <__addsf3> - 2b50: d8800015 stw r2,0(sp) - 2b54: d9000017 ldw r4,0(sp) - 2b58: 900b883a mov r5,r18 - 2b5c: 00042b00 call 42b0 <__subsf3> - 2b60: 1404703a and r2,r2,r16 - 2b64: 88e0002c andhi r3,r17,32768 - 2b68: 10c4b03a or r2,r2,r3 - 2b6c: 003fdf06 br 2aec - -00002b70 : - 2b70: 00e00034 movhi r3,32768 - 2b74: 18ffffc4 addi r3,r3,-1 - 2b78: 1906703a and r3,r3,r4 - 2b7c: 2005883a mov r2,r4 - 2b80: 18002626 beq r3,zero,2c1c - 2b84: defffe04 addi sp,sp,-8 - 2b88: dc000015 stw r16,0(sp) - 2b8c: dfc00115 stw ra,4(sp) - 2b90: 019fe034 movhi r6,32640 - 2b94: 2821883a mov r16,r5 - 2b98: 200b883a mov r5,r4 - 2b9c: 19801a2e bgeu r3,r6,2c08 - 2ba0: 215fe02c andhi r5,r4,32640 - 2ba4: 28001e1e bne r5,zero,2c20 - 2ba8: 01530034 movhi r5,19456 - 2bac: 0003efc0 call 3efc <__mulsf3> - 2bb0: 00fffff4 movhi r3,65535 - 2bb4: 18cf2c04 addi r3,r3,15536 - 2bb8: 1009883a mov r4,r2 - 2bbc: 80c02616 blt r16,r3,2c58 - 2bc0: 1007d5fa srai r3,r2,23 - 2bc4: 18c03fcc andi r3,r3,255 - 2bc8: 18fff9c4 addi r3,r3,-25 - 2bcc: 1c07883a add r3,r3,r16 - 2bd0: 19403fd0 cmplti r5,r3,255 - 2bd4: 2800161e bne r5,zero,2c30 - 2bd8: 011c52b4 movhi r4,29002 - 2bdc: 213cb284 addi r4,r4,-3382 - 2be0: 1000020e bge r2,zero,2bec - 2be4: 013c52b4 movhi r4,61770 - 2be8: 213cb284 addi r4,r4,-3382 - 2bec: 015c52b4 movhi r5,29002 - 2bf0: 297cb284 addi r5,r5,-3382 - 2bf4: 0003efc0 call 3efc <__mulsf3> - 2bf8: dfc00117 ldw ra,4(sp) - 2bfc: dc000017 ldw r16,0(sp) - 2c00: dec00204 addi sp,sp,8 - 2c04: f800283a ret - 2c08: 00034c00 call 34c0 <__addsf3> - 2c0c: dfc00117 ldw ra,4(sp) - 2c10: dc000017 ldw r16,0(sp) - 2c14: dec00204 addi sp,sp,8 - 2c18: f800283a ret - 2c1c: f800283a ret - 2c20: 1806d5fa srli r3,r3,23 - 2c24: 1c07883a add r3,r3,r16 - 2c28: 19403fd0 cmplti r5,r3,255 - 2c2c: 283fea26 beq r5,zero,2bd8 - 2c30: 00c01016 blt zero,r3,2c74 - 2c34: 197ffa88 cmpgei r5,r3,-22 - 2c38: 2800171e bne r5,zero,2c98 - 2c3c: 00f0d414 movui r3,50000 - 2c40: 1c3fe516 blt r3,r16,2bd8 - 2c44: 010368b4 movhi r4,3490 - 2c48: 21109804 addi r4,r4,16992 - 2c4c: 1000020e bge r2,zero,2c58 - 2c50: 012368b4 movhi r4,36258 - 2c54: 21109804 addi r4,r4,16992 - 2c58: 014368b4 movhi r5,3490 - 2c5c: 29509804 addi r5,r5,16992 - 2c60: 0003efc0 call 3efc <__mulsf3> - 2c64: dfc00117 ldw ra,4(sp) - 2c68: dc000017 ldw r16,0(sp) - 2c6c: dec00204 addi sp,sp,8 - 2c70: f800283a ret - 2c74: 180695fa slli r3,r3,23 - 2c78: 00a02034 movhi r2,32896 - 2c7c: 10bfffc4 addi r2,r2,-1 - 2c80: 2084703a and r2,r4,r2 - 2c84: 10c4b03a or r2,r2,r3 - 2c88: dfc00117 ldw ra,4(sp) - 2c8c: dc000017 ldw r16,0(sp) - 2c90: dec00204 addi sp,sp,8 - 2c94: f800283a ret - 2c98: 18c00644 addi r3,r3,25 - 2c9c: 180695fa slli r3,r3,23 - 2ca0: 00a02034 movhi r2,32896 - 2ca4: 10bfffc4 addi r2,r2,-1 - 2ca8: 2088703a and r4,r4,r2 - 2cac: 014cc034 movhi r5,13056 - 2cb0: 1908b03a or r4,r3,r4 - 2cb4: 0003efc0 call 3efc <__mulsf3> - 2cb8: 003fd406 br 2c0c - -00002cbc <__muldi3>: - 2cbc: 20bfffcc andi r2,r4,65535 - 2cc0: 2010d43a srli r8,r4,16 - 2cc4: 3016d43a srli r11,r6,16 - 2cc8: 327fffcc andi r9,r6,65535 - 2ccc: 1255383a mul r10,r2,r9 - 2cd0: 12c7383a mul r3,r2,r11 - 2cd4: 4253383a mul r9,r8,r9 - 2cd8: 5004d43a srli r2,r10,16 - 2cdc: 42d1383a mul r8,r8,r11 - 2ce0: 1a47883a add r3,r3,r9 - 2ce4: 10c5883a add r2,r2,r3 - 2ce8: 1240022e bgeu r2,r9,2cf4 <__muldi3+0x38> - 2cec: 00c00074 movhi r3,1 - 2cf0: 40d1883a add r8,r8,r3 - 2cf4: 1006d43a srli r3,r2,16 - 2cf8: 21c9383a mul r4,r4,r7 - 2cfc: 314d383a mul r6,r6,r5 - 2d00: 1004943a slli r2,r2,16 - 2d04: 1a11883a add r8,r3,r8 - 2d08: 52bfffcc andi r10,r10,65535 - 2d0c: 2209883a add r4,r4,r8 - 2d10: 1285883a add r2,r2,r10 - 2d14: 2187883a add r3,r4,r6 - 2d18: f800283a ret - -00002d1c <__fixunssfsi>: - 2d1c: defffe04 addi sp,sp,-8 - 2d20: 0153c034 movhi r5,20224 - 2d24: dc000015 stw r16,0(sp) - 2d28: dfc00115 stw ra,4(sp) - 2d2c: 2021883a mov r16,r4 - 2d30: 0003d900 call 3d90 <__gesf2> - 2d34: 1000060e bge r2,zero,2d50 <__fixunssfsi+0x34> - 2d38: 8009883a mov r4,r16 - 2d3c: 00047900 call 4790 <__fixsfsi> - 2d40: dfc00117 ldw ra,4(sp) - 2d44: dc000017 ldw r16,0(sp) - 2d48: dec00204 addi sp,sp,8 - 2d4c: f800283a ret - 2d50: 0153c034 movhi r5,20224 - 2d54: 8009883a mov r4,r16 - 2d58: 00042b00 call 42b0 <__subsf3> - 2d5c: 1009883a mov r4,r2 - 2d60: 00047900 call 4790 <__fixsfsi> - 2d64: 00e00034 movhi r3,32768 - 2d68: 10c5883a add r2,r2,r3 - 2d6c: dfc00117 ldw ra,4(sp) - 2d70: dc000017 ldw r16,0(sp) - 2d74: dec00204 addi sp,sp,8 - 2d78: f800283a ret - -00002d7c <__udivdi3>: - 2d7c: defff504 addi sp,sp,-44 - 2d80: dcc00415 stw r19,16(sp) - 2d84: dc000115 stw r16,4(sp) - 2d88: dfc00a15 stw ra,40(sp) - 2d8c: df000915 stw fp,36(sp) - 2d90: ddc00815 stw r23,32(sp) - 2d94: dd800715 stw r22,28(sp) - 2d98: dd400615 stw r21,24(sp) - 2d9c: dd000515 stw r20,20(sp) - 2da0: dc800315 stw r18,12(sp) - 2da4: dc400215 stw r17,8(sp) - 2da8: 2027883a mov r19,r4 - 2dac: 2821883a mov r16,r5 - 2db0: 3800411e bne r7,zero,2eb8 <__udivdi3+0x13c> - 2db4: 3829883a mov r20,r7 - 2db8: 3023883a mov r17,r6 - 2dbc: 2025883a mov r18,r4 - 2dc0: 29805d2e bgeu r5,r6,2f38 <__udivdi3+0x1bc> - 2dc4: 00bfffd4 movui r2,65535 - 2dc8: 282b883a mov r21,r5 - 2dcc: 1180a02e bgeu r2,r6,3050 <__udivdi3+0x2d4> - 2dd0: 00804034 movhi r2,256 - 2dd4: 30813636 bltu r6,r2,32b0 <__udivdi3+0x534> - 2dd8: 3006d63a srli r3,r6,24 - 2ddc: 05000604 movi r20,24 - 2de0: 00800074 movhi r2,1 - 2de4: 1885883a add r2,r3,r2 - 2de8: 10a55703 ldbu r2,-27300(r2) - 2dec: 00c00804 movi r3,32 - 2df0: 1505883a add r2,r2,r20 - 2df4: 1889c83a sub r4,r3,r2 - 2df8: 18800526 beq r3,r2,2e10 <__udivdi3+0x94> - 2dfc: 8120983a sll r16,r16,r4 - 2e00: 9884d83a srl r2,r19,r2 - 2e04: 3122983a sll r17,r6,r4 - 2e08: 9924983a sll r18,r19,r4 - 2e0c: 142ab03a or r21,r2,r16 - 2e10: 882cd43a srli r22,r17,16 - 2e14: a809883a mov r4,r21 - 2e18: 8d3fffcc andi r20,r17,65535 - 2e1c: b00b883a mov r5,r22 - 2e20: 00034640 call 3464 <__umodsi3> - 2e24: a809883a mov r4,r21 - 2e28: b00b883a mov r5,r22 - 2e2c: 1027883a mov r19,r2 - 2e30: 00034000 call 3400 <__udivsi3> - 2e34: 9826943a slli r19,r19,16 - 2e38: 9008d43a srli r4,r18,16 - 2e3c: 1021883a mov r16,r2 - 2e40: a085383a mul r2,r20,r2 - 2e44: 9908b03a or r4,r19,r4 - 2e48: 2080052e bgeu r4,r2,2e60 <__udivdi3+0xe4> - 2e4c: 2449883a add r4,r4,r17 - 2e50: 80ffffc4 addi r3,r16,-1 - 2e54: 24400136 bltu r4,r17,2e5c <__udivdi3+0xe0> - 2e58: 20812636 bltu r4,r2,32f4 <__udivdi3+0x578> - 2e5c: 1821883a mov r16,r3 - 2e60: 20a7c83a sub r19,r4,r2 - 2e64: 9809883a mov r4,r19 - 2e68: b00b883a mov r5,r22 - 2e6c: 00034640 call 3464 <__umodsi3> - 2e70: 9809883a mov r4,r19 - 2e74: b00b883a mov r5,r22 - 2e78: 1027883a mov r19,r2 - 2e7c: 9826943a slli r19,r19,16 - 2e80: 00034000 call 3400 <__udivsi3> - 2e84: a0a9383a mul r20,r20,r2 - 2e88: 94bfffcc andi r18,r18,65535 - 2e8c: 9ca4b03a or r18,r19,r18 - 2e90: 9500052e bgeu r18,r20,2ea8 <__udivdi3+0x12c> - 2e94: 8ca5883a add r18,r17,r18 - 2e98: 10ffffc4 addi r3,r2,-1 - 2e9c: 94400136 bltu r18,r17,2ea4 <__udivdi3+0x128> - 2ea0: 95011236 bltu r18,r20,32ec <__udivdi3+0x570> - 2ea4: 1805883a mov r2,r3 - 2ea8: 8020943a slli r16,r16,16 - 2eac: 0007883a mov r3,zero - 2eb0: 8084b03a or r2,r16,r2 - 2eb4: 00000306 br 2ec4 <__udivdi3+0x148> - 2eb8: 29c00e2e bgeu r5,r7,2ef4 <__udivdi3+0x178> - 2ebc: 0007883a mov r3,zero - 2ec0: 0005883a mov r2,zero - 2ec4: dfc00a17 ldw ra,40(sp) - 2ec8: df000917 ldw fp,36(sp) - 2ecc: ddc00817 ldw r23,32(sp) - 2ed0: dd800717 ldw r22,28(sp) - 2ed4: dd400617 ldw r21,24(sp) - 2ed8: dd000517 ldw r20,20(sp) - 2edc: dcc00417 ldw r19,16(sp) - 2ee0: dc800317 ldw r18,12(sp) - 2ee4: dc400217 ldw r17,8(sp) - 2ee8: dc000117 ldw r16,4(sp) - 2eec: dec00b04 addi sp,sp,44 - 2ef0: f800283a ret - 2ef4: 00bfffd4 movui r2,65535 - 2ef8: 11c05a2e bgeu r2,r7,3064 <__udivdi3+0x2e8> - 2efc: 00804034 movhi r2,256 - 2f00: 3880dd36 bltu r7,r2,3278 <__udivdi3+0x4fc> - 2f04: 3804d63a srli r2,r7,24 - 2f08: 01000604 movi r4,24 - 2f0c: 00c00074 movhi r3,1 - 2f10: 10c7883a add r3,r2,r3 - 2f14: 18a55703 ldbu r2,-27300(r3) - 2f18: 00c00804 movi r3,32 - 2f1c: 1105883a add r2,r2,r4 - 2f20: 18abc83a sub r21,r3,r2 - 2f24: 1880861e bne r3,r2,3140 <__udivdi3+0x3c4> - 2f28: 3c00d836 bltu r7,r16,328c <__udivdi3+0x510> - 2f2c: 9985403a cmpgeu r2,r19,r6 - 2f30: 0007883a mov r3,zero - 2f34: 003fe306 br 2ec4 <__udivdi3+0x148> - 2f38: 3000041e bne r6,zero,2f4c <__udivdi3+0x1d0> - 2f3c: 000b883a mov r5,zero - 2f40: 01000044 movi r4,1 - 2f44: 00034000 call 3400 <__udivsi3> - 2f48: 1023883a mov r17,r2 - 2f4c: 00bfffd4 movui r2,65535 - 2f50: 14403a2e bgeu r2,r17,303c <__udivdi3+0x2c0> - 2f54: 00804034 movhi r2,256 - 2f58: 8880d236 bltu r17,r2,32a4 <__udivdi3+0x528> - 2f5c: 8806d63a srli r3,r17,24 - 2f60: 05000604 movi r20,24 - 2f64: 00800074 movhi r2,1 - 2f68: 1885883a add r2,r3,r2 - 2f6c: 10a55703 ldbu r2,-27300(r2) - 2f70: 00c00804 movi r3,32 - 2f74: 1505883a add r2,r2,r20 - 2f78: 188dc83a sub r6,r3,r2 - 2f7c: 18803e1e bne r3,r2,3078 <__udivdi3+0x2fc> - 2f80: 882ad43a srli r21,r17,16 - 2f84: 8461c83a sub r16,r16,r17 - 2f88: 8cffffcc andi r19,r17,65535 - 2f8c: 00c00044 movi r3,1 - 2f90: 8009883a mov r4,r16 - 2f94: a80b883a mov r5,r21 - 2f98: d8c00015 stw r3,0(sp) - 2f9c: 00034640 call 3464 <__umodsi3> - 2fa0: 8009883a mov r4,r16 - 2fa4: a80b883a mov r5,r21 - 2fa8: 1021883a mov r16,r2 - 2fac: 00034000 call 3400 <__udivsi3> - 2fb0: 8020943a slli r16,r16,16 - 2fb4: 9008d43a srli r4,r18,16 - 2fb8: 1029883a mov r20,r2 - 2fbc: 14c5383a mul r2,r2,r19 - 2fc0: 8108b03a or r4,r16,r4 - 2fc4: d8c00017 ldw r3,0(sp) - 2fc8: 2080052e bgeu r4,r2,2fe0 <__udivdi3+0x264> - 2fcc: 2449883a add r4,r4,r17 - 2fd0: a17fffc4 addi r5,r20,-1 - 2fd4: 24400136 bltu r4,r17,2fdc <__udivdi3+0x260> - 2fd8: 2080c936 bltu r4,r2,3300 <__udivdi3+0x584> - 2fdc: 2829883a mov r20,r5 - 2fe0: 20a1c83a sub r16,r4,r2 - 2fe4: 8009883a mov r4,r16 - 2fe8: a80b883a mov r5,r21 - 2fec: d8c00015 stw r3,0(sp) - 2ff0: 00034640 call 3464 <__umodsi3> - 2ff4: 8009883a mov r4,r16 - 2ff8: a80b883a mov r5,r21 - 2ffc: 1021883a mov r16,r2 - 3000: 8020943a slli r16,r16,16 - 3004: 00034000 call 3400 <__udivsi3> - 3008: 14e7383a mul r19,r2,r19 - 300c: 94bfffcc andi r18,r18,65535 - 3010: 84a4b03a or r18,r16,r18 - 3014: d8c00017 ldw r3,0(sp) - 3018: 94c0052e bgeu r18,r19,3030 <__udivdi3+0x2b4> - 301c: 8ca5883a add r18,r17,r18 - 3020: 113fffc4 addi r4,r2,-1 - 3024: 94400136 bltu r18,r17,302c <__udivdi3+0x2b0> - 3028: 94c0ae36 bltu r18,r19,32e4 <__udivdi3+0x568> - 302c: 2005883a mov r2,r4 - 3030: a00c943a slli r6,r20,16 - 3034: 3084b03a or r2,r6,r2 - 3038: 003fa206 br 2ec4 <__udivdi3+0x148> - 303c: 88804030 cmpltui r2,r17,256 - 3040: 10009e1e bne r2,zero,32bc <__udivdi3+0x540> - 3044: 8806d23a srli r3,r17,8 - 3048: 05000204 movi r20,8 - 304c: 003fc506 br 2f64 <__udivdi3+0x1e8> - 3050: 30804030 cmpltui r2,r6,256 - 3054: 10008b1e bne r2,zero,3284 <__udivdi3+0x508> - 3058: 3006d23a srli r3,r6,8 - 305c: 05000204 movi r20,8 - 3060: 003f5f06 br 2de0 <__udivdi3+0x64> - 3064: 38804030 cmpltui r2,r7,256 - 3068: 10008b1e bne r2,zero,3298 <__udivdi3+0x51c> - 306c: 3804d23a srli r2,r7,8 - 3070: 01000204 movi r4,8 - 3074: 003fa506 br 2f0c <__udivdi3+0x190> - 3078: 89a2983a sll r17,r17,r6 - 307c: 80acd83a srl r22,r16,r2 - 3080: 81a0983a sll r16,r16,r6 - 3084: 882ad43a srli r21,r17,16 - 3088: 9884d83a srl r2,r19,r2 - 308c: b009883a mov r4,r22 - 3090: a80b883a mov r5,r21 - 3094: 99a4983a sll r18,r19,r6 - 3098: 1428b03a or r20,r2,r16 - 309c: 00034640 call 3464 <__umodsi3> - 30a0: b009883a mov r4,r22 - 30a4: a80b883a mov r5,r21 - 30a8: 1021883a mov r16,r2 - 30ac: 00034000 call 3400 <__udivsi3> - 30b0: 8008943a slli r4,r16,16 - 30b4: a00ad43a srli r5,r20,16 - 30b8: 8cffffcc andi r19,r17,65535 - 30bc: 98a1383a mul r16,r19,r2 - 30c0: 2148b03a or r4,r4,r5 - 30c4: 102d883a mov r22,r2 - 30c8: 2400062e bgeu r4,r16,30e4 <__udivdi3+0x368> - 30cc: 2449883a add r4,r4,r17 - 30d0: 10bfffc4 addi r2,r2,-1 - 30d4: 24408136 bltu r4,r17,32dc <__udivdi3+0x560> - 30d8: 2400802e bgeu r4,r16,32dc <__udivdi3+0x560> - 30dc: b5bfff84 addi r22,r22,-2 - 30e0: 2449883a add r4,r4,r17 - 30e4: 2421c83a sub r16,r4,r16 - 30e8: 8009883a mov r4,r16 - 30ec: a80b883a mov r5,r21 - 30f0: 00034640 call 3464 <__umodsi3> - 30f4: 8009883a mov r4,r16 - 30f8: a80b883a mov r5,r21 - 30fc: 1021883a mov r16,r2 - 3100: 8020943a slli r16,r16,16 - 3104: 00034000 call 3400 <__udivsi3> - 3108: 9889383a mul r4,r19,r2 - 310c: a53fffcc andi r20,r20,65535 - 3110: 8520b03a or r16,r16,r20 - 3114: 8100062e bgeu r16,r4,3130 <__udivdi3+0x3b4> - 3118: 8461883a add r16,r16,r17 - 311c: 10ffffc4 addi r3,r2,-1 - 3120: 84406a36 bltu r16,r17,32cc <__udivdi3+0x550> - 3124: 8100692e bgeu r16,r4,32cc <__udivdi3+0x550> - 3128: 10bfff84 addi r2,r2,-2 - 312c: 8461883a add r16,r16,r17 - 3130: b006943a slli r3,r22,16 - 3134: 8121c83a sub r16,r16,r4 - 3138: 1886b03a or r3,r3,r2 - 313c: 003f9406 br 2f90 <__udivdi3+0x214> - 3140: 30acd83a srl r22,r6,r2 - 3144: 3d4e983a sll r7,r7,r21 - 3148: 80a4d83a srl r18,r16,r2 - 314c: 8546983a sll r3,r16,r21 - 3150: b1ecb03a or r22,r22,r7 - 3154: b038d43a srli fp,r22,16 - 3158: 9884d83a srl r2,r19,r2 - 315c: 9009883a mov r4,r18 - 3160: e00b883a mov r5,fp - 3164: 10e2b03a or r17,r2,r3 - 3168: 3568983a sll r20,r6,r21 - 316c: 00034640 call 3464 <__umodsi3> - 3170: 9009883a mov r4,r18 - 3174: e00b883a mov r5,fp - 3178: 1025883a mov r18,r2 - 317c: 00034000 call 3400 <__udivsi3> - 3180: 9008943a slli r4,r18,16 - 3184: 8806d43a srli r3,r17,16 - 3188: b5ffffcc andi r23,r22,65535 - 318c: b8a5383a mul r18,r23,r2 - 3190: 20c8b03a or r4,r4,r3 - 3194: 1021883a mov r16,r2 - 3198: 2480062e bgeu r4,r18,31b4 <__udivdi3+0x438> - 319c: 2589883a add r4,r4,r22 - 31a0: 10bfffc4 addi r2,r2,-1 - 31a4: 25804b36 bltu r4,r22,32d4 <__udivdi3+0x558> - 31a8: 24804a2e bgeu r4,r18,32d4 <__udivdi3+0x558> - 31ac: 843fff84 addi r16,r16,-2 - 31b0: 2589883a add r4,r4,r22 - 31b4: 24a5c83a sub r18,r4,r18 - 31b8: 9009883a mov r4,r18 - 31bc: e00b883a mov r5,fp - 31c0: 00034640 call 3464 <__umodsi3> - 31c4: 9009883a mov r4,r18 - 31c8: e00b883a mov r5,fp - 31cc: 1025883a mov r18,r2 - 31d0: 9024943a slli r18,r18,16 - 31d4: 00034000 call 3400 <__udivsi3> - 31d8: b8af383a mul r23,r23,r2 - 31dc: 8c7fffcc andi r17,r17,65535 - 31e0: 9462b03a or r17,r18,r17 - 31e4: 8dc0062e bgeu r17,r23,3200 <__udivdi3+0x484> - 31e8: 8da3883a add r17,r17,r22 - 31ec: 10ffffc4 addi r3,r2,-1 - 31f0: 8d803436 bltu r17,r22,32c4 <__udivdi3+0x548> - 31f4: 8dc0332e bgeu r17,r23,32c4 <__udivdi3+0x548> - 31f8: 10bfff84 addi r2,r2,-2 - 31fc: 8da3883a add r17,r17,r22 - 3200: 8020943a slli r16,r16,16 - 3204: 10ffffcc andi r3,r2,65535 - 3208: a00ed43a srli r7,r20,16 - 320c: 8084b03a or r2,r16,r2 - 3210: 1008d43a srli r4,r2,16 - 3214: a1bfffcc andi r6,r20,65535 - 3218: 1991383a mul r8,r3,r6 - 321c: 218d383a mul r6,r4,r6 - 3220: 19c7383a mul r3,r3,r7 - 3224: 400ad43a srli r5,r8,16 - 3228: 21c9383a mul r4,r4,r7 - 322c: 1987883a add r3,r3,r6 - 3230: 28c7883a add r3,r5,r3 - 3234: 8de3c83a sub r17,r17,r23 - 3238: 1980022e bgeu r3,r6,3244 <__udivdi3+0x4c8> - 323c: 01400074 movhi r5,1 - 3240: 2149883a add r4,r4,r5 - 3244: 180ad43a srli r5,r3,16 - 3248: 2909883a add r4,r5,r4 - 324c: 89000836 bltu r17,r4,3270 <__udivdi3+0x4f4> - 3250: 89000226 beq r17,r4,325c <__udivdi3+0x4e0> - 3254: 0007883a mov r3,zero - 3258: 003f1a06 br 2ec4 <__udivdi3+0x148> - 325c: 1806943a slli r3,r3,16 - 3260: 9d4c983a sll r6,r19,r21 - 3264: 423fffcc andi r8,r8,65535 - 3268: 1a07883a add r3,r3,r8 - 326c: 30fff92e bgeu r6,r3,3254 <__udivdi3+0x4d8> - 3270: 10bfffc4 addi r2,r2,-1 - 3274: 003ff706 br 3254 <__udivdi3+0x4d8> - 3278: 3804d43a srli r2,r7,16 - 327c: 01000404 movi r4,16 - 3280: 003f2206 br 2f0c <__udivdi3+0x190> - 3284: 3007883a mov r3,r6 - 3288: 003ed506 br 2de0 <__udivdi3+0x64> - 328c: 0007883a mov r3,zero - 3290: 00800044 movi r2,1 - 3294: 003f0b06 br 2ec4 <__udivdi3+0x148> - 3298: 3805883a mov r2,r7 - 329c: 0009883a mov r4,zero - 32a0: 003f1a06 br 2f0c <__udivdi3+0x190> - 32a4: 8806d43a srli r3,r17,16 - 32a8: 05000404 movi r20,16 - 32ac: 003f2d06 br 2f64 <__udivdi3+0x1e8> - 32b0: 3006d43a srli r3,r6,16 - 32b4: 05000404 movi r20,16 - 32b8: 003ec906 br 2de0 <__udivdi3+0x64> - 32bc: 8807883a mov r3,r17 - 32c0: 003f2806 br 2f64 <__udivdi3+0x1e8> - 32c4: 1805883a mov r2,r3 - 32c8: 003fcd06 br 3200 <__udivdi3+0x484> - 32cc: 1805883a mov r2,r3 - 32d0: 003f9706 br 3130 <__udivdi3+0x3b4> - 32d4: 1021883a mov r16,r2 - 32d8: 003fb606 br 31b4 <__udivdi3+0x438> - 32dc: 102d883a mov r22,r2 - 32e0: 003f8006 br 30e4 <__udivdi3+0x368> - 32e4: 10bfff84 addi r2,r2,-2 - 32e8: 003f5106 br 3030 <__udivdi3+0x2b4> - 32ec: 10bfff84 addi r2,r2,-2 - 32f0: 003eed06 br 2ea8 <__udivdi3+0x12c> - 32f4: 843fff84 addi r16,r16,-2 - 32f8: 2449883a add r4,r4,r17 - 32fc: 003ed806 br 2e60 <__udivdi3+0xe4> - 3300: a53fff84 addi r20,r20,-2 - 3304: 2449883a add r4,r4,r17 - 3308: 003f3506 br 2fe0 <__udivdi3+0x264> - -0000330c <__divsi3>: - 330c: 20001a16 blt r4,zero,3378 <__divsi3+0x6c> - 3310: 000f883a mov r7,zero - 3314: 2800020e bge r5,zero,3320 <__divsi3+0x14> - 3318: 014bc83a sub r5,zero,r5 - 331c: 39c0005c xori r7,r7,1 - 3320: 200d883a mov r6,r4 - 3324: 00c00044 movi r3,1 - 3328: 2900092e bgeu r5,r4,3350 <__divsi3+0x44> - 332c: 00800804 movi r2,32 - 3330: 00c00044 movi r3,1 - 3334: 00000106 br 333c <__divsi3+0x30> - 3338: 10001226 beq r2,zero,3384 <__divsi3+0x78> - 333c: 294b883a add r5,r5,r5 - 3340: 10bfffc4 addi r2,r2,-1 - 3344: 18c7883a add r3,r3,r3 - 3348: 293ffb36 bltu r5,r4,3338 <__divsi3+0x2c> - 334c: 18000d26 beq r3,zero,3384 <__divsi3+0x78> - 3350: 0005883a mov r2,zero - 3354: 31400236 bltu r6,r5,3360 <__divsi3+0x54> - 3358: 314dc83a sub r6,r6,r5 - 335c: 10c4b03a or r2,r2,r3 - 3360: 1806d07a srli r3,r3,1 - 3364: 280ad07a srli r5,r5,1 - 3368: 183ffa1e bne r3,zero,3354 <__divsi3+0x48> - 336c: 38000126 beq r7,zero,3374 <__divsi3+0x68> - 3370: 0085c83a sub r2,zero,r2 - 3374: f800283a ret - 3378: 0109c83a sub r4,zero,r4 - 337c: 01c00044 movi r7,1 - 3380: 003fe406 br 3314 <__divsi3+0x8> - 3384: 0005883a mov r2,zero - 3388: 003ff806 br 336c <__divsi3+0x60> - -0000338c <__modsi3>: - 338c: 20001916 blt r4,zero,33f4 <__modsi3+0x68> - 3390: 000f883a mov r7,zero - 3394: 2005883a mov r2,r4 - 3398: 2800010e bge r5,zero,33a0 <__modsi3+0x14> - 339c: 014bc83a sub r5,zero,r5 - 33a0: 00c00044 movi r3,1 - 33a4: 2900092e bgeu r5,r4,33cc <__modsi3+0x40> - 33a8: 01800804 movi r6,32 - 33ac: 00c00044 movi r3,1 - 33b0: 00000106 br 33b8 <__modsi3+0x2c> - 33b4: 30000d26 beq r6,zero,33ec <__modsi3+0x60> - 33b8: 294b883a add r5,r5,r5 - 33bc: 31bfffc4 addi r6,r6,-1 - 33c0: 18c7883a add r3,r3,r3 - 33c4: 293ffb36 bltu r5,r4,33b4 <__modsi3+0x28> - 33c8: 18000826 beq r3,zero,33ec <__modsi3+0x60> - 33cc: 1806d07a srli r3,r3,1 - 33d0: 11400136 bltu r2,r5,33d8 <__modsi3+0x4c> - 33d4: 1145c83a sub r2,r2,r5 - 33d8: 280ad07a srli r5,r5,1 - 33dc: 183ffb1e bne r3,zero,33cc <__modsi3+0x40> - 33e0: 38000126 beq r7,zero,33e8 <__modsi3+0x5c> - 33e4: 0085c83a sub r2,zero,r2 - 33e8: f800283a ret - 33ec: 2005883a mov r2,r4 - 33f0: 003ffb06 br 33e0 <__modsi3+0x54> - 33f4: 0109c83a sub r4,zero,r4 - 33f8: 01c00044 movi r7,1 - 33fc: 003fe506 br 3394 <__modsi3+0x8> - -00003400 <__udivsi3>: - 3400: 200d883a mov r6,r4 - 3404: 2900152e bgeu r5,r4,345c <__udivsi3+0x5c> - 3408: 28001416 blt r5,zero,345c <__udivsi3+0x5c> - 340c: 00800804 movi r2,32 - 3410: 00c00044 movi r3,1 - 3414: 00000206 br 3420 <__udivsi3+0x20> - 3418: 10000e26 beq r2,zero,3454 <__udivsi3+0x54> - 341c: 28000516 blt r5,zero,3434 <__udivsi3+0x34> - 3420: 294b883a add r5,r5,r5 - 3424: 10bfffc4 addi r2,r2,-1 - 3428: 18c7883a add r3,r3,r3 - 342c: 293ffa36 bltu r5,r4,3418 <__udivsi3+0x18> - 3430: 18000826 beq r3,zero,3454 <__udivsi3+0x54> - 3434: 0005883a mov r2,zero - 3438: 31400236 bltu r6,r5,3444 <__udivsi3+0x44> - 343c: 314dc83a sub r6,r6,r5 - 3440: 10c4b03a or r2,r2,r3 - 3444: 1806d07a srli r3,r3,1 - 3448: 280ad07a srli r5,r5,1 - 344c: 183ffa1e bne r3,zero,3438 <__udivsi3+0x38> - 3450: f800283a ret - 3454: 0005883a mov r2,zero - 3458: f800283a ret - 345c: 00c00044 movi r3,1 - 3460: 003ff406 br 3434 <__udivsi3+0x34> - -00003464 <__umodsi3>: - 3464: 2005883a mov r2,r4 - 3468: 2900132e bgeu r5,r4,34b8 <__umodsi3+0x54> - 346c: 28001216 blt r5,zero,34b8 <__umodsi3+0x54> - 3470: 01800804 movi r6,32 - 3474: 00c00044 movi r3,1 - 3478: 00000206 br 3484 <__umodsi3+0x20> - 347c: 30000c26 beq r6,zero,34b0 <__umodsi3+0x4c> - 3480: 28000516 blt r5,zero,3498 <__umodsi3+0x34> - 3484: 294b883a add r5,r5,r5 - 3488: 31bfffc4 addi r6,r6,-1 - 348c: 18c7883a add r3,r3,r3 - 3490: 293ffa36 bltu r5,r4,347c <__umodsi3+0x18> - 3494: 18000626 beq r3,zero,34b0 <__umodsi3+0x4c> - 3498: 1806d07a srli r3,r3,1 - 349c: 11400136 bltu r2,r5,34a4 <__umodsi3+0x40> - 34a0: 1145c83a sub r2,r2,r5 - 34a4: 280ad07a srli r5,r5,1 - 34a8: 183ffb1e bne r3,zero,3498 <__umodsi3+0x34> - 34ac: f800283a ret - 34b0: 2005883a mov r2,r4 - 34b4: f800283a ret - 34b8: 00c00044 movi r3,1 - 34bc: 003ff606 br 3498 <__umodsi3+0x34> - -000034c0 <__addsf3>: - 34c0: defffc04 addi sp,sp,-16 - 34c4: 2806d5fa srli r3,r5,23 - 34c8: dc000015 stw r16,0(sp) - 34cc: 2020d5fa srli r16,r4,23 - 34d0: 200cd7fa srli r6,r4,31 - 34d4: 00802034 movhi r2,128 - 34d8: 2812d7fa srli r9,r5,31 - 34dc: 10bfffc4 addi r2,r2,-1 - 34e0: 1114703a and r10,r2,r4 - 34e4: 1b003fcc andi r12,r3,255 - 34e8: dc400115 stw r17,4(sp) - 34ec: 84003fcc andi r16,r16,255 - 34f0: 115a703a and r13,r2,r5 - 34f4: dfc00315 stw ra,12(sp) - 34f8: dc800215 stw r18,8(sp) - 34fc: 500e90fa slli r7,r10,3 - 3500: 681090fa slli r8,r13,3 - 3504: 5007883a mov r3,r10 - 3508: 3023883a mov r17,r6 - 350c: 8317c83a sub r11,r16,r12 - 3510: 32403926 beq r6,r9,35f8 <__addsf3+0x138> - 3514: 02c02e0e bge zero,r11,35d0 <__addsf3+0x110> - 3518: 60004c26 beq r12,zero,364c <__addsf3+0x18c> - 351c: 80803fe0 cmpeqi r2,r16,255 - 3520: 1000801e bne r2,zero,3724 <__addsf3+0x264> - 3524: 42010034 orhi r8,r8,1024 - 3528: 58800710 cmplti r2,r11,28 - 352c: 10009e1e bne r2,zero,37a8 <__addsf3+0x2e8> - 3530: 01000044 movi r4,1 - 3534: 3909c83a sub r4,r7,r4 - 3538: 2081002c andhi r2,r4,1024 - 353c: 10006826 beq r2,zero,36e0 <__addsf3+0x220> - 3540: 04810034 movhi r18,1024 - 3544: 94bfffc4 addi r18,r18,-1 - 3548: 24a4703a and r18,r4,r18 - 354c: 9009883a mov r4,r18 - 3550: 0004a200 call 4a20 <__clzsi2> - 3554: 10bffec4 addi r2,r2,-5 - 3558: 9088983a sll r4,r18,r2 - 355c: 1400880e bge r2,r16,3780 <__addsf3+0x2c0> - 3560: 00ff0034 movhi r3,64512 - 3564: 18ffffc4 addi r3,r3,-1 - 3568: 80a1c83a sub r16,r16,r2 - 356c: 20c8703a and r4,r4,r3 - 3570: 208001cc andi r2,r4,7 - 3574: 10000426 beq r2,zero,3588 <__addsf3+0xc8> - 3578: 208003cc andi r2,r4,15 - 357c: 10800120 cmpeqi r2,r2,4 - 3580: 1000011e bne r2,zero,3588 <__addsf3+0xc8> - 3584: 21000104 addi r4,r4,4 - 3588: 2081002c andhi r2,r4,1024 - 358c: 10005626 beq r2,zero,36e8 <__addsf3+0x228> - 3590: 84000044 addi r16,r16,1 - 3594: 80803fe0 cmpeqi r2,r16,255 - 3598: 1000461e bne r2,zero,36b4 <__addsf3+0x1f4> - 359c: 200491ba slli r2,r4,6 - 35a0: 1006d27a srli r3,r2,9 - 35a4: 84003fcc andi r16,r16,255 - 35a8: 800495fa slli r2,r16,23 - 35ac: 882297fa slli r17,r17,31 - 35b0: 10c4b03a or r2,r2,r3 - 35b4: 1444b03a or r2,r2,r17 - 35b8: dfc00317 ldw ra,12(sp) - 35bc: dc800217 ldw r18,8(sp) - 35c0: dc400117 ldw r17,4(sp) - 35c4: dc000017 ldw r16,0(sp) - 35c8: dec00404 addi sp,sp,16 - 35cc: f800283a ret - 35d0: 58002526 beq r11,zero,3668 <__addsf3+0x1a8> - 35d4: 6417c83a sub r11,r12,r16 - 35d8: 8000821e bne r16,zero,37e4 <__addsf3+0x324> - 35dc: 38006426 beq r7,zero,3770 <__addsf3+0x2b0> - 35e0: 58bfffc4 addi r2,r11,-1 - 35e4: 1000c226 beq r2,zero,38f0 <__addsf3+0x430> - 35e8: 5ac03fe0 cmpeqi r11,r11,255 - 35ec: 58004b1e bne r11,zero,371c <__addsf3+0x25c> - 35f0: 1017883a mov r11,r2 - 35f4: 00007e06 br 37f0 <__addsf3+0x330> - 35f8: 02c0510e bge zero,r11,3740 <__addsf3+0x280> - 35fc: 60002626 beq r12,zero,3698 <__addsf3+0x1d8> - 3600: 80803fe0 cmpeqi r2,r16,255 - 3604: 1000471e bne r2,zero,3724 <__addsf3+0x264> - 3608: 42010034 orhi r8,r8,1024 - 360c: 58800710 cmplti r2,r11,28 - 3610: 10007e1e bne r2,zero,380c <__addsf3+0x34c> - 3614: 01000044 movi r4,1 - 3618: 21c9883a add r4,r4,r7 - 361c: 2081002c andhi r2,r4,1024 - 3620: 10002f26 beq r2,zero,36e0 <__addsf3+0x220> - 3624: 84000044 addi r16,r16,1 - 3628: 80803fe0 cmpeqi r2,r16,255 - 362c: 1000211e bne r2,zero,36b4 <__addsf3+0x1f4> - 3630: 2004d07a srli r2,r4,1 - 3634: 00df8034 movhi r3,32256 - 3638: 18ffffc4 addi r3,r3,-1 - 363c: 2100004c andi r4,r4,1 - 3640: 10c4703a and r2,r2,r3 - 3644: 1108b03a or r4,r2,r4 - 3648: 003fc906 br 3570 <__addsf3+0xb0> - 364c: 40004a26 beq r8,zero,3778 <__addsf3+0x2b8> - 3650: 58bfffc4 addi r2,r11,-1 - 3654: 10009326 beq r2,zero,38a4 <__addsf3+0x3e4> - 3658: 59003fe0 cmpeqi r4,r11,255 - 365c: 2000311e bne r4,zero,3724 <__addsf3+0x264> - 3660: 1017883a mov r11,r2 - 3664: 003fb006 br 3528 <__addsf3+0x68> - 3668: 81800044 addi r6,r16,1 - 366c: 31803f8c andi r6,r6,254 - 3670: 3000541e bne r6,zero,37c4 <__addsf3+0x304> - 3674: 80007e1e bne r16,zero,3870 <__addsf3+0x3b0> - 3678: 3800a326 beq r7,zero,3908 <__addsf3+0x448> - 367c: 40009326 beq r8,zero,38cc <__addsf3+0x40c> - 3680: 3a09c83a sub r4,r7,r8 - 3684: 2081002c andhi r2,r4,1024 - 3688: 1000a626 beq r2,zero,3924 <__addsf3+0x464> - 368c: 41c9c83a sub r4,r8,r7 - 3690: 4823883a mov r17,r9 - 3694: 003fb606 br 3570 <__addsf3+0xb0> - 3698: 40003726 beq r8,zero,3778 <__addsf3+0x2b8> - 369c: 58bfffc4 addi r2,r11,-1 - 36a0: 10007b26 beq r2,zero,3890 <__addsf3+0x3d0> - 36a4: 5ac03fe0 cmpeqi r11,r11,255 - 36a8: 58001e1e bne r11,zero,3724 <__addsf3+0x264> - 36ac: 1017883a mov r11,r2 - 36b0: 003fd606 br 360c <__addsf3+0x14c> - 36b4: 043fffc4 movi r16,-1 - 36b8: 0007883a mov r3,zero - 36bc: 003fb906 br 35a4 <__addsf3+0xe4> - 36c0: 80800044 addi r2,r16,1 - 36c4: 11803f8c andi r6,r2,254 - 36c8: 30005726 beq r6,zero,3828 <__addsf3+0x368> - 36cc: 10c03fe0 cmpeqi r3,r2,255 - 36d0: 183ff81e bne r3,zero,36b4 <__addsf3+0x1f4> - 36d4: 3a09883a add r4,r7,r8 - 36d8: 2008d07a srli r4,r4,1 - 36dc: 1021883a mov r16,r2 - 36e0: 208001cc andi r2,r4,7 - 36e4: 103fa41e bne r2,zero,3578 <__addsf3+0xb8> - 36e8: 2014d0fa srli r10,r4,3 - 36ec: 80803fe0 cmpeqi r2,r16,255 - 36f0: 10000c1e bne r2,zero,3724 <__addsf3+0x264> - 36f4: 00802034 movhi r2,128 - 36f8: 10bfffc4 addi r2,r2,-1 - 36fc: 5086703a and r3,r10,r2 - 3700: 003fa806 br 35a4 <__addsf3+0xe4> - 3704: 38000626 beq r7,zero,3720 <__addsf3+0x260> - 3708: 40000626 beq r8,zero,3724 <__addsf3+0x264> - 370c: 2080102c andhi r2,r4,64 - 3710: 10000426 beq r2,zero,3724 <__addsf3+0x264> - 3714: 2940102c andhi r5,r5,64 - 3718: 2800021e bne r5,zero,3724 <__addsf3+0x264> - 371c: 4823883a mov r17,r9 - 3720: 6815883a mov r10,r13 - 3724: 503fe326 beq r10,zero,36b4 <__addsf3+0x1f4> - 3728: 00802034 movhi r2,128 - 372c: 50c01034 orhi r3,r10,64 - 3730: 10bfffc4 addi r2,r2,-1 - 3734: 1886703a and r3,r3,r2 - 3738: 043fffc4 movi r16,-1 - 373c: 003f9906 br 35a4 <__addsf3+0xe4> - 3740: 583fdf26 beq r11,zero,36c0 <__addsf3+0x200> - 3744: 6417c83a sub r11,r12,r16 - 3748: 80004226 beq r16,zero,3854 <__addsf3+0x394> - 374c: 60803fe0 cmpeqi r2,r12,255 - 3750: 103ff31e bne r2,zero,3720 <__addsf3+0x260> - 3754: 39c10034 orhi r7,r7,1024 - 3758: 58800710 cmplti r2,r11,28 - 375c: 10005d1e bne r2,zero,38d4 <__addsf3+0x414> - 3760: 01000044 movi r4,1 - 3764: 2209883a add r4,r4,r8 - 3768: 6021883a mov r16,r12 - 376c: 003fab06 br 361c <__addsf3+0x15c> - 3770: 4823883a mov r17,r9 - 3774: 6815883a mov r10,r13 - 3778: 5821883a mov r16,r11 - 377c: 003fdb06 br 36ec <__addsf3+0x22c> - 3780: 1405c83a sub r2,r2,r16 - 3784: 14800044 addi r18,r2,1 - 3788: 00800804 movi r2,32 - 378c: 1485c83a sub r2,r2,r18 - 3790: 2084983a sll r2,r4,r2 - 3794: 2488d83a srl r4,r4,r18 - 3798: 0021883a mov r16,zero - 379c: 1004c03a cmpne r2,r2,zero - 37a0: 1108b03a or r4,r2,r4 - 37a4: 003f7206 br 3570 <__addsf3+0xb0> - 37a8: 01000804 movi r4,32 - 37ac: 22c9c83a sub r4,r4,r11 - 37b0: 4108983a sll r4,r8,r4 - 37b4: 42d0d83a srl r8,r8,r11 - 37b8: 2008c03a cmpne r4,r4,zero - 37bc: 2208b03a or r4,r4,r8 - 37c0: 003f5c06 br 3534 <__addsf3+0x74> - 37c4: 3a25c83a sub r18,r7,r8 - 37c8: 9081002c andhi r2,r18,1024 - 37cc: 10002d1e bne r2,zero,3884 <__addsf3+0x3c4> - 37d0: 903f5e1e bne r18,zero,354c <__addsf3+0x8c> - 37d4: 0023883a mov r17,zero - 37d8: 0021883a mov r16,zero - 37dc: 0007883a mov r3,zero - 37e0: 003f7006 br 35a4 <__addsf3+0xe4> - 37e4: 60803fe0 cmpeqi r2,r12,255 - 37e8: 103fcc1e bne r2,zero,371c <__addsf3+0x25c> - 37ec: 39c10034 orhi r7,r7,1024 - 37f0: 58800710 cmplti r2,r11,28 - 37f4: 10002e1e bne r2,zero,38b0 <__addsf3+0x3f0> - 37f8: 01000044 movi r4,1 - 37fc: 4109c83a sub r4,r8,r4 - 3800: 4823883a mov r17,r9 - 3804: 6021883a mov r16,r12 - 3808: 003f4b06 br 3538 <__addsf3+0x78> - 380c: 01000804 movi r4,32 - 3810: 22c9c83a sub r4,r4,r11 - 3814: 4108983a sll r4,r8,r4 - 3818: 42d0d83a srl r8,r8,r11 - 381c: 2008c03a cmpne r4,r4,zero - 3820: 2208b03a or r4,r4,r8 - 3824: 003f7c06 br 3618 <__addsf3+0x158> - 3828: 803fb61e bne r16,zero,3704 <__addsf3+0x244> - 382c: 38003a26 beq r7,zero,3918 <__addsf3+0x458> - 3830: 40002626 beq r8,zero,38cc <__addsf3+0x40c> - 3834: 3a09883a add r4,r7,r8 - 3838: 2081002c andhi r2,r4,1024 - 383c: 103fa826 beq r2,zero,36e0 <__addsf3+0x220> - 3840: 00bf0034 movhi r2,64512 - 3844: 10bfffc4 addi r2,r2,-1 - 3848: 2088703a and r4,r4,r2 - 384c: 04000044 movi r16,1 - 3850: 003fa306 br 36e0 <__addsf3+0x220> - 3854: 383fc726 beq r7,zero,3774 <__addsf3+0x2b4> - 3858: 58bfffc4 addi r2,r11,-1 - 385c: 10000c26 beq r2,zero,3890 <__addsf3+0x3d0> - 3860: 5ac03fe0 cmpeqi r11,r11,255 - 3864: 583fae1e bne r11,zero,3720 <__addsf3+0x260> - 3868: 1017883a mov r11,r2 - 386c: 003fba06 br 3758 <__addsf3+0x298> - 3870: 383fa51e bne r7,zero,3708 <__addsf3+0x248> - 3874: 403fa91e bne r8,zero,371c <__addsf3+0x25c> - 3878: 0023883a mov r17,zero - 387c: 1007883a mov r3,r2 - 3880: 003fad06 br 3738 <__addsf3+0x278> - 3884: 41e5c83a sub r18,r8,r7 - 3888: 4823883a mov r17,r9 - 388c: 003f2f06 br 354c <__addsf3+0x8c> - 3890: 3a09883a add r4,r7,r8 - 3894: 2081002c andhi r2,r4,1024 - 3898: 10001926 beq r2,zero,3900 <__addsf3+0x440> - 389c: 04000084 movi r16,2 - 38a0: 003f6306 br 3630 <__addsf3+0x170> - 38a4: 3a09c83a sub r4,r7,r8 - 38a8: 04000044 movi r16,1 - 38ac: 003f2206 br 3538 <__addsf3+0x78> - 38b0: 00800804 movi r2,32 - 38b4: 12c5c83a sub r2,r2,r11 - 38b8: 3884983a sll r2,r7,r2 - 38bc: 3aced83a srl r7,r7,r11 - 38c0: 1008c03a cmpne r4,r2,zero - 38c4: 21c8b03a or r4,r4,r7 - 38c8: 003fcc06 br 37fc <__addsf3+0x33c> - 38cc: 0021883a mov r16,zero - 38d0: 003f3406 br 35a4 <__addsf3+0xe4> - 38d4: 01000804 movi r4,32 - 38d8: 22c9c83a sub r4,r4,r11 - 38dc: 3908983a sll r4,r7,r4 - 38e0: 3aced83a srl r7,r7,r11 - 38e4: 2008c03a cmpne r4,r4,zero - 38e8: 21c8b03a or r4,r4,r7 - 38ec: 003f9d06 br 3764 <__addsf3+0x2a4> - 38f0: 41c9c83a sub r4,r8,r7 - 38f4: 4823883a mov r17,r9 - 38f8: 04000044 movi r16,1 - 38fc: 003f0e06 br 3538 <__addsf3+0x78> - 3900: 04000044 movi r16,1 - 3904: 003f7606 br 36e0 <__addsf3+0x220> - 3908: 403fb226 beq r8,zero,37d4 <__addsf3+0x314> - 390c: 4823883a mov r17,r9 - 3910: 6807883a mov r3,r13 - 3914: 003f2306 br 35a4 <__addsf3+0xe4> - 3918: 6807883a mov r3,r13 - 391c: 0021883a mov r16,zero - 3920: 003f2006 br 35a4 <__addsf3+0xe4> - 3924: 203fab26 beq r4,zero,37d4 <__addsf3+0x314> - 3928: 003f6d06 br 36e0 <__addsf3+0x220> - -0000392c <__divsf3>: - 392c: defff604 addi sp,sp,-40 - 3930: 2006d5fa srli r3,r4,23 - 3934: dd400615 stw r21,24(sp) - 3938: 202ad7fa srli r21,r4,31 - 393c: 00802034 movhi r2,128 - 3940: dc800315 stw r18,12(sp) - 3944: dc000115 stw r16,4(sp) - 3948: 10bfffc4 addi r2,r2,-1 - 394c: dfc00915 stw ra,36(sp) - 3950: ddc00815 stw r23,32(sp) - 3954: dd800715 stw r22,28(sp) - 3958: dd000515 stw r20,20(sp) - 395c: dcc00415 stw r19,16(sp) - 3960: dc400215 stw r17,8(sp) - 3964: 18c03fcc andi r3,r3,255 - 3968: 1120703a and r16,r2,r4 - 396c: a825883a mov r18,r21 - 3970: 18007b26 beq r3,zero,3b60 <__divsf3+0x234> - 3974: 18803fe0 cmpeqi r2,r3,255 - 3978: 10007e1e bne r2,zero,3b74 <__divsf3+0x248> - 397c: 800490fa slli r2,r16,3 - 3980: 1d3fe044 addi r20,r3,-127 - 3984: 0023883a mov r17,zero - 3988: 14010034 orhi r16,r2,1024 - 398c: 002d883a mov r22,zero - 3990: 2806d5fa srli r3,r5,23 - 3994: 01002034 movhi r4,128 + 2598: 180b883a mov r5,r3 + 259c: 00057040 call 5704 <__eqdf2> + 25a0: 0029883a mov r20,zero + 25a4: 10001226 beq r2,zero,25f0 + 25a8: 04fffc34 movhi r19,65520 + 25ac: 003f7b06 br 239c + 25b0: 8009883a mov r4,r16 + 25b4: 900b883a mov r5,r18 + 25b8: 00057040 call 5704 <__eqdf2> + 25bc: 103f771e bne r2,zero,239c + 25c0: 0029883a mov r20,zero + 25c4: 04cffc34 movhi r19,16368 + 25c8: 003f7406 br 239c + 25cc: 0006b580 call 6b58 <__errno> + 25d0: 00c00844 movi r3,33 + 25d4: 10c00015 stw r3,0(r2) + 25d8: 0029883a mov r20,zero + 25dc: 04fffc34 movhi r19,65520 + 25e0: 003f6e06 br 239c + 25e4: 0029883a mov r20,zero + 25e8: 04dffc34 movhi r19,32752 + 25ec: 003f6b06 br 239c + 25f0: 04dffc34 movhi r19,32752 + 25f4: 003f6906 br 239c + 25f8: 0006b580 call 6b58 <__errno> + 25fc: 00c00844 movi r3,33 + 2600: 10c00015 stw r3,0(r2) + 2604: 000d883a mov r6,zero + 2608: 000f883a mov r7,zero + 260c: 0009883a mov r4,zero + 2610: 000b883a mov r5,zero + 2614: 0004ea80 call 4ea8 <__divdf3> + 2618: 1029883a mov r20,r2 + 261c: 1827883a mov r19,r3 + 2620: 003f5e06 br 239c + +00002624 <__ieee754_pow>: + 2624: 00e00034 movhi r3,32768 + 2628: 18ffffc4 addi r3,r3,-1 + 262c: deffeb04 addi sp,sp,-84 + 2630: 38c4703a and r2,r7,r3 + 2634: dfc01415 stw ra,80(sp) + 2638: df001315 stw fp,76(sp) + 263c: ddc01215 stw r23,72(sp) + 2640: dd801115 stw r22,68(sp) + 2644: dd401015 stw r21,64(sp) + 2648: dd000f15 stw r20,60(sp) + 264c: dcc00e15 stw r19,56(sp) + 2650: dc800d15 stw r18,52(sp) + 2654: dc400c15 stw r17,48(sp) + 2658: dc000b15 stw r16,44(sp) + 265c: 1190b03a or r8,r2,r6 + 2660: 40003626 beq r8,zero,273c <__ieee754_pow+0x118> + 2664: 28e8703a and r20,r5,r3 + 2668: 00dffc34 movhi r3,32752 + 266c: 282b883a mov r21,r5 + 2670: 1d00130e bge r3,r20,26c0 <__ieee754_pow+0x9c> + 2674: 00f00434 movhi r3,49168 + 2678: a0c7883a add r3,r20,r3 + 267c: 1906b03a or r3,r3,r4 + 2680: 002d883a mov r22,zero + 2684: 1800321e bne r3,zero,2750 <__ieee754_pow+0x12c> + 2688: 00cffc34 movhi r3,16368 + 268c: b005883a mov r2,r22 + 2690: dfc01417 ldw ra,80(sp) + 2694: df001317 ldw fp,76(sp) + 2698: ddc01217 ldw r23,72(sp) + 269c: dd801117 ldw r22,68(sp) + 26a0: dd401017 ldw r21,64(sp) + 26a4: dd000f17 ldw r20,60(sp) + 26a8: dcc00e17 ldw r19,56(sp) + 26ac: dc800d17 ldw r18,52(sp) + 26b0: dc400c17 ldw r17,48(sp) + 26b4: dc000b17 ldw r16,44(sp) + 26b8: dec01504 addi sp,sp,84 + 26bc: f800283a ret + 26c0: 3823883a mov r17,r7 + 26c4: 3021883a mov r16,r6 + 26c8: a0c01e26 beq r20,r3,2744 <__ieee754_pow+0x120> + 26cc: 18bfe916 blt r3,r2,2674 <__ieee754_pow+0x50> + 26d0: 00dffc34 movhi r3,32752 + 26d4: 10c04226 beq r2,r3,27e0 <__ieee754_pow+0x1bc> + 26d8: a8001f16 blt r21,zero,2758 <__ieee754_pow+0x134> + 26dc: 0025883a mov r18,zero + 26e0: 80002c1e bne r16,zero,2794 <__ieee754_pow+0x170> + 26e4: 00dffc34 movhi r3,32752 + 26e8: 10c07426 beq r2,r3,28bc <__ieee754_pow+0x298> + 26ec: 00cffc34 movhi r3,16368 + 26f0: 10c32726 beq r2,r3,3390 <__ieee754_pow+0xd6c> + 26f4: 00d00034 movhi r3,16384 + 26f8: 88c3cb26 beq r17,r3,3628 <__ieee754_pow+0x1004> + 26fc: 00cff834 movhi r3,16352 + 2700: 88c0241e bne r17,r3,2794 <__ieee754_pow+0x170> + 2704: a8002316 blt r21,zero,2794 <__ieee754_pow+0x170> + 2708: a80b883a mov r5,r21 + 270c: dfc01417 ldw ra,80(sp) + 2710: df001317 ldw fp,76(sp) + 2714: ddc01217 ldw r23,72(sp) + 2718: dd801117 ldw r22,68(sp) + 271c: dd401017 ldw r21,64(sp) + 2720: dd000f17 ldw r20,60(sp) + 2724: dcc00e17 ldw r19,56(sp) + 2728: dc800d17 ldw r18,52(sp) + 272c: dc400c17 ldw r17,48(sp) + 2730: dc000b17 ldw r16,44(sp) + 2734: dec01504 addi sp,sp,84 + 2738: 00036e41 jmpi 36e4 <__ieee754_sqrt> + 273c: 002d883a mov r22,zero + 2740: 003fd106 br 2688 <__ieee754_pow+0x64> + 2744: 2000011e bne r4,zero,274c <__ieee754_pow+0x128> + 2748: a0bfe10e bge r20,r2,26d0 <__ieee754_pow+0xac> + 274c: 002d883a mov r22,zero + 2750: 00dffe34 movhi r3,32760 + 2754: 003fcd06 br 268c <__ieee754_pow+0x68> + 2758: 00d0d034 movhi r3,17216 + 275c: 10c0540e bge r2,r3,28b0 <__ieee754_pow+0x28c> + 2760: 00cffc34 movhi r3,16368 + 2764: 10c00916 blt r2,r3,278c <__ieee754_pow+0x168> + 2768: 1007d53a srai r3,r2,20 + 276c: 18ff0044 addi r3,r3,-1023 + 2770: 19400550 cmplti r5,r3,21 + 2774: 2803a41e bne r5,zero,3608 <__ieee754_pow+0xfe4> + 2778: 01400d04 movi r5,52 + 277c: 28c7c83a sub r3,r5,r3 + 2780: 80cad83a srl r5,r16,r3 + 2784: 28c6983a sll r3,r5,r3 + 2788: 1c03cb26 beq r3,r16,36b8 <__ieee754_pow+0x1094> + 278c: 0025883a mov r18,zero + 2790: 803fd626 beq r16,zero,26ec <__ieee754_pow+0xc8> + 2794: 00e00034 movhi r3,32768 + 2798: 18ffffc4 addi r3,r3,-1 + 279c: 202d883a mov r22,r4 + 27a0: a8c6703a and r3,r21,r3 + 27a4: 20001626 beq r4,zero,2800 <__ieee754_pow+0x1dc> + 27a8: a826d7fa srli r19,r21,31 + 27ac: 9cffffc4 addi r19,r19,-1 + 27b0: 94cab03a or r5,r18,r19 + 27b4: 28002126 beq r5,zero,283c <__ieee754_pow+0x218> + 27b8: 01507834 movhi r5,16864 + 27bc: 2880490e bge r5,r2,28e4 <__ieee754_pow+0x2c0> + 27c0: 0150fc34 movhi r5,17392 + 27c4: 28831e0e bge r5,r2,3440 <__ieee754_pow+0xe1c> + 27c8: 008ffc34 movhi r2,16368 + 27cc: a080270e bge r20,r2,286c <__ieee754_pow+0x248> + 27d0: 88002716 blt r17,zero,2870 <__ieee754_pow+0x24c> + 27d4: 002d883a mov r22,zero + 27d8: 0007883a mov r3,zero + 27dc: 003fab06 br 268c <__ieee754_pow+0x68> + 27e0: 803fbd26 beq r16,zero,26d8 <__ieee754_pow+0xb4> + 27e4: 003fa306 br 2674 <__ieee754_pow+0x50> + 27e8: 2000141e bne r4,zero,283c <__ieee754_pow+0x218> + 27ec: 00e00034 movhi r3,32768 + 27f0: 18ffffc4 addi r3,r3,-1 + 27f4: 002d883a mov r22,zero + 27f8: a8c6703a and r3,r21,r3 + 27fc: 0025883a mov r18,zero + 2800: a0000526 beq r20,zero,2818 <__ieee754_pow+0x1f4> + 2804: 01500034 movhi r5,16384 + 2808: 297fffc4 addi r5,r5,-1 + 280c: a94a703a and r5,r21,r5 + 2810: 018ffc34 movhi r6,16368 + 2814: 29bfe41e bne r5,r6,27a8 <__ieee754_pow+0x184> + 2818: 88001e16 blt r17,zero,2894 <__ieee754_pow+0x270> + 281c: a83f9b0e bge r21,zero,268c <__ieee754_pow+0x68> + 2820: 00b00434 movhi r2,49168 + 2824: a085883a add r2,r20,r2 + 2828: 1484b03a or r2,r2,r18 + 282c: 10038b1e bne r2,zero,365c <__ieee754_pow+0x1038> + 2830: b00d883a mov r6,r22 + 2834: 180f883a mov r7,r3 + 2838: 00000206 br 2844 <__ieee754_pow+0x220> + 283c: 200d883a mov r6,r4 + 2840: a80f883a mov r7,r21 + 2844: 3009883a mov r4,r6 + 2848: 380b883a mov r5,r7 + 284c: 0005fc80 call 5fc8 <__subdf3> + 2850: 100d883a mov r6,r2 + 2854: 180f883a mov r7,r3 + 2858: 1009883a mov r4,r2 + 285c: 180b883a mov r5,r3 + 2860: 0004ea80 call 4ea8 <__divdf3> + 2864: 102d883a mov r22,r2 + 2868: 003f8806 br 268c <__ieee754_pow+0x68> + 286c: 047fd90e bge zero,r17,27d4 <__ieee754_pow+0x1b0> + 2870: 01a20034 movhi r6,34816 + 2874: 01df8e34 movhi r7,32312 + 2878: 319d6704 addi r6,r6,30108 + 287c: 39f90f04 addi r7,r7,-7108 + 2880: 3009883a mov r4,r6 + 2884: 380b883a mov r5,r7 + 2888: 00059540 call 5954 <__muldf3> + 288c: 102d883a mov r22,r2 + 2890: 003f7e06 br 268c <__ieee754_pow+0x68> + 2894: 180f883a mov r7,r3 + 2898: 000d883a mov r6,zero + 289c: 0009883a mov r4,zero + 28a0: 014ffc34 movhi r5,16368 + 28a4: 0004ea80 call 4ea8 <__divdf3> + 28a8: 102d883a mov r22,r2 + 28ac: 003fdb06 br 281c <__ieee754_pow+0x1f8> + 28b0: 04800084 movi r18,2 + 28b4: 803fb71e bne r16,zero,2794 <__ieee754_pow+0x170> + 28b8: 003f8a06 br 26e4 <__ieee754_pow+0xc0> + 28bc: 00b00434 movhi r2,49168 + 28c0: a085883a add r2,r20,r2 + 28c4: 1108b03a or r4,r2,r4 + 28c8: 203f9c26 beq r4,zero,273c <__ieee754_pow+0x118> + 28cc: 008ffc34 movhi r2,16368 + 28d0: 002d883a mov r22,zero + 28d4: a0833416 blt r20,r2,35a8 <__ieee754_pow+0xf84> + 28d8: 883fbf16 blt r17,zero,27d8 <__ieee754_pow+0x1b4> + 28dc: 8807883a mov r3,r17 + 28e0: 003f6a06 br 268c <__ieee754_pow+0x68> + 28e4: a95ffc2c andhi r5,r21,32752 + 28e8: 000d883a mov r6,zero + 28ec: 2800061e bne r5,zero,2908 <__ieee754_pow+0x2e4> + 28f0: 01d0d034 movhi r7,17216 + 28f4: 180b883a mov r5,r3 + 28f8: 00059540 call 5954 <__muldf3> + 28fc: 102d883a mov r22,r2 + 2900: 1829883a mov r20,r3 + 2904: 01bff2c4 movi r6,-53 + 2908: a00bd53a srai r5,r20,20 + 290c: 00800434 movhi r2,16 + 2910: 10bfffc4 addi r2,r2,-1 + 2914: 01000134 movhi r4,4 + 2918: 297f0044 addi r5,r5,-1023 + 291c: a086703a and r3,r20,r2 + 2920: 21262384 addi r4,r4,-26482 + 2924: 2999883a add r12,r5,r6 + 2928: 1f0ffc34 orhi fp,r3,16368 + 292c: 20c0060e bge r4,r3,2948 <__ieee754_pow+0x324> + 2930: 00800334 movhi r2,12 + 2934: 10ad9e44 addi r2,r2,-18823 + 2938: 10c34c0e bge r2,r3,366c <__ieee754_pow+0x1048> + 293c: 00bffc34 movhi r2,65520 + 2940: 63000044 addi r12,r12,1 + 2944: e0b9883a add fp,fp,r2 + 2948: d8000015 stw zero,0(sp) + 294c: d8000115 stw zero,4(sp) + 2950: d8000a15 stw zero,40(sp) + 2954: 001f883a mov r15,zero + 2958: 002f883a mov r23,zero + 295c: 034ffc34 movhi r13,16368 + 2960: 680f883a mov r7,r13 + 2964: b009883a mov r4,r22 + 2968: e00b883a mov r5,fp + 296c: 000d883a mov r6,zero + 2970: dbc00915 stw r15,36(sp) + 2974: db000815 stw r12,32(sp) + 2978: db400215 stw r13,8(sp) + 297c: 0005fc80 call 5fc8 <__subdf3> + 2980: db400217 ldw r13,8(sp) + 2984: b009883a mov r4,r22 + 2988: e00b883a mov r5,fp + 298c: 680f883a mov r7,r13 + 2990: 000d883a mov r6,zero + 2994: db400615 stw r13,24(sp) + 2998: d8800315 stw r2,12(sp) + 299c: d8c00215 stw r3,8(sp) + 29a0: 00045b80 call 45b8 <__adddf3> + 29a4: 100d883a mov r6,r2 + 29a8: 180f883a mov r7,r3 + 29ac: 0009883a mov r4,zero + 29b0: 014ffc34 movhi r5,16368 + 29b4: 0004ea80 call 4ea8 <__divdf3> + 29b8: dac00217 ldw r11,8(sp) + 29bc: da400317 ldw r9,12(sp) + 29c0: 100d883a mov r6,r2 + 29c4: 580b883a mov r5,r11 + 29c8: 4809883a mov r4,r9 + 29cc: 180f883a mov r7,r3 + 29d0: d8800515 stw r2,20(sp) + 29d4: d8c00415 stw r3,16(sp) + 29d8: 00059540 call 5954 <__muldf3> + 29dc: e009d07a srai r4,fp,1 + 29e0: 01400234 movhi r5,8 + 29e4: 000d883a mov r6,zero + 29e8: 21080034 orhi r4,r4,8192 + 29ec: 2149883a add r4,r4,r5 + 29f0: 25ef883a add r23,r4,r23 + 29f4: b80f883a mov r7,r23 + 29f8: 0009883a mov r4,zero + 29fc: 180b883a mov r5,r3 + 2a00: 1829883a mov r20,r3 + 2a04: 102b883a mov r21,r2 + 2a08: 00059540 call 5954 <__muldf3> + 2a0c: da400317 ldw r9,12(sp) + 2a10: dac00217 ldw r11,8(sp) + 2a14: 100d883a mov r6,r2 + 2a18: 4809883a mov r4,r9 + 2a1c: 580b883a mov r5,r11 + 2a20: 180f883a mov r7,r3 + 2a24: 0005fc80 call 5fc8 <__subdf3> + 2a28: db400617 ldw r13,24(sp) + 2a2c: b80b883a mov r5,r23 + 2a30: 000d883a mov r6,zero + 2a34: 680f883a mov r7,r13 + 2a38: 0009883a mov r4,zero + 2a3c: 182f883a mov r23,r3 + 2a40: d8800215 stw r2,8(sp) + 2a44: 0005fc80 call 5fc8 <__subdf3> + 2a48: b009883a mov r4,r22 + 2a4c: e00b883a mov r5,fp + 2a50: 100d883a mov r6,r2 + 2a54: 180f883a mov r7,r3 + 2a58: 0005fc80 call 5fc8 <__subdf3> + 2a5c: a00f883a mov r7,r20 + 2a60: 000d883a mov r6,zero + 2a64: 1009883a mov r4,r2 + 2a68: 180b883a mov r5,r3 + 2a6c: 00059540 call 5954 <__muldf3> + 2a70: dac00217 ldw r11,8(sp) + 2a74: b80b883a mov r5,r23 + 2a78: 100d883a mov r6,r2 + 2a7c: 5809883a mov r4,r11 + 2a80: 180f883a mov r7,r3 + 2a84: 0005fc80 call 5fc8 <__subdf3> + 2a88: da000417 ldw r8,16(sp) + 2a8c: da800517 ldw r10,20(sp) + 2a90: 1009883a mov r4,r2 + 2a94: 400f883a mov r7,r8 + 2a98: 500d883a mov r6,r10 + 2a9c: 180b883a mov r5,r3 + 2aa0: 00059540 call 5954 <__muldf3> + 2aa4: a80d883a mov r6,r21 + 2aa8: a00f883a mov r7,r20 + 2aac: a809883a mov r4,r21 + 2ab0: a00b883a mov r5,r20 + 2ab4: d8800415 stw r2,16(sp) + 2ab8: d8c00315 stw r3,12(sp) + 2abc: 00059540 call 5954 <__muldf3> + 2ac0: 01929174 movhi r6,19013 + 2ac4: 01cff2b4 movhi r7,16330 + 2ac8: 3193bbc4 addi r6,r6,20207 + 2acc: 39df8a04 addi r7,r7,32296 + 2ad0: 1009883a mov r4,r2 + 2ad4: 180b883a mov r5,r3 + 2ad8: 102f883a mov r23,r2 + 2adc: 182d883a mov r22,r3 + 2ae0: 00059540 call 5954 <__muldf3> + 2ae4: 01a4f2b4 movhi r6,37834 + 2ae8: 01cff3b4 movhi r7,16334 + 2aec: 31b6d944 addi r6,r6,-9371 + 2af0: 39e19284 addi r7,r7,-31158 + 2af4: 1009883a mov r4,r2 + 2af8: 180b883a mov r5,r3 + 2afc: 00045b80 call 45b8 <__adddf3> + 2b00: b80d883a mov r6,r23 + 2b04: b00f883a mov r7,r22 + 2b08: 1009883a mov r4,r2 + 2b0c: 180b883a mov r5,r3 + 2b10: 00059540 call 5954 <__muldf3> + 2b14: 01aa4774 movhi r6,43293 + 2b18: 01cff474 movhi r7,16337 + 2b1c: 31904044 addi r6,r6,16641 + 2b20: 39dd1804 addi r7,r7,29792 + 2b24: 1009883a mov r4,r2 + 2b28: 180b883a mov r5,r3 + 2b2c: 00045b80 call 45b8 <__adddf3> + 2b30: b80d883a mov r6,r23 + 2b34: b00f883a mov r7,r22 + 2b38: 1009883a mov r4,r2 + 2b3c: 180b883a mov r5,r3 + 2b40: 00059540 call 5954 <__muldf3> + 2b44: 019463f4 movhi r6,20879 + 2b48: 01cff574 movhi r7,16341 + 2b4c: 31899344 addi r6,r6,9805 + 2b50: 39d55544 addi r7,r7,21845 + 2b54: 1009883a mov r4,r2 + 2b58: 180b883a mov r5,r3 + 2b5c: 00045b80 call 45b8 <__adddf3> + 2b60: b80d883a mov r6,r23 + 2b64: b00f883a mov r7,r22 + 2b68: 1009883a mov r4,r2 + 2b6c: 180b883a mov r5,r3 + 2b70: 00059540 call 5954 <__muldf3> + 2b74: 01b6dc34 movhi r6,56176 + 2b78: 01cff6f4 movhi r7,16347 + 2b7c: 31aaffc4 addi r6,r6,-21505 + 2b80: 39db6d84 addi r7,r7,28086 + 2b84: 1009883a mov r4,r2 + 2b88: 180b883a mov r5,r3 + 2b8c: 00045b80 call 45b8 <__adddf3> + 2b90: b80d883a mov r6,r23 + 2b94: b00f883a mov r7,r22 + 2b98: 1009883a mov r4,r2 + 2b9c: 180b883a mov r5,r3 + 2ba0: 00059540 call 5954 <__muldf3> + 2ba4: 018cccf4 movhi r6,13107 + 2ba8: 01cff8f4 movhi r7,16355 + 2bac: 318cc0c4 addi r6,r6,13059 + 2bb0: 39ccccc4 addi r7,r7,13107 + 2bb4: 1009883a mov r4,r2 + 2bb8: 180b883a mov r5,r3 + 2bbc: 00045b80 call 45b8 <__adddf3> + 2bc0: b80d883a mov r6,r23 + 2bc4: b00f883a mov r7,r22 + 2bc8: b809883a mov r4,r23 + 2bcc: b00b883a mov r5,r22 + 2bd0: 1839883a mov fp,r3 + 2bd4: d8800215 stw r2,8(sp) + 2bd8: 00059540 call 5954 <__muldf3> + 2bdc: dac00217 ldw r11,8(sp) + 2be0: e00b883a mov r5,fp + 2be4: 100d883a mov r6,r2 + 2be8: 5809883a mov r4,r11 + 2bec: 180f883a mov r7,r3 + 2bf0: 00059540 call 5954 <__muldf3> + 2bf4: a00f883a mov r7,r20 + 2bf8: a809883a mov r4,r21 + 2bfc: a00b883a mov r5,r20 + 2c00: 000d883a mov r6,zero + 2c04: 102f883a mov r23,r2 + 2c08: 182d883a mov r22,r3 + 2c0c: 00045b80 call 45b8 <__adddf3> + 2c10: da800417 ldw r10,16(sp) + 2c14: da400317 ldw r9,12(sp) + 2c18: 1009883a mov r4,r2 + 2c1c: 500d883a mov r6,r10 + 2c20: 480f883a mov r7,r9 + 2c24: 180b883a mov r5,r3 + 2c28: da800715 stw r10,28(sp) + 2c2c: da400615 stw r9,24(sp) + 2c30: 00059540 call 5954 <__muldf3> + 2c34: b80d883a mov r6,r23 + 2c38: b00f883a mov r7,r22 + 2c3c: 1009883a mov r4,r2 + 2c40: 180b883a mov r5,r3 + 2c44: 00045b80 call 45b8 <__adddf3> + 2c48: a00f883a mov r7,r20 + 2c4c: a00b883a mov r5,r20 + 2c50: 000d883a mov r6,zero + 2c54: 0009883a mov r4,zero + 2c58: d8800315 stw r2,12(sp) + 2c5c: d8c00215 stw r3,8(sp) + 2c60: 00059540 call 5954 <__muldf3> + 2c64: 000d883a mov r6,zero + 2c68: 01d00234 movhi r7,16392 + 2c6c: 1009883a mov r4,r2 + 2c70: 180b883a mov r5,r3 + 2c74: d8800515 stw r2,20(sp) + 2c78: d8c00415 stw r3,16(sp) + 2c7c: 00045b80 call 45b8 <__adddf3> + 2c80: da000317 ldw r8,12(sp) + 2c84: dac00217 ldw r11,8(sp) + 2c88: 1009883a mov r4,r2 + 2c8c: 400d883a mov r6,r8 + 2c90: 580f883a mov r7,r11 + 2c94: 180b883a mov r5,r3 + 2c98: 00045b80 call 45b8 <__adddf3> + 2c9c: a00b883a mov r5,r20 + 2ca0: 000d883a mov r6,zero + 2ca4: 180f883a mov r7,r3 + 2ca8: 0009883a mov r4,zero + 2cac: 182d883a mov r22,r3 + 2cb0: 00059540 call 5954 <__muldf3> + 2cb4: b00b883a mov r5,r22 + 2cb8: 000d883a mov r6,zero + 2cbc: 01d00234 movhi r7,16392 + 2cc0: 0009883a mov r4,zero + 2cc4: 1039883a mov fp,r2 + 2cc8: 182f883a mov r23,r3 + 2ccc: 0005fc80 call 5fc8 <__subdf3> + 2cd0: db800517 ldw r14,20(sp) + 2cd4: db400417 ldw r13,16(sp) + 2cd8: 1009883a mov r4,r2 + 2cdc: 700d883a mov r6,r14 + 2ce0: 680f883a mov r7,r13 + 2ce4: 180b883a mov r5,r3 + 2ce8: 0005fc80 call 5fc8 <__subdf3> + 2cec: da000317 ldw r8,12(sp) + 2cf0: dac00217 ldw r11,8(sp) + 2cf4: 100d883a mov r6,r2 + 2cf8: 4009883a mov r4,r8 + 2cfc: 580b883a mov r5,r11 + 2d00: 180f883a mov r7,r3 + 2d04: 0005fc80 call 5fc8 <__subdf3> + 2d08: a80d883a mov r6,r21 + 2d0c: a00f883a mov r7,r20 + 2d10: 1009883a mov r4,r2 + 2d14: 180b883a mov r5,r3 + 2d18: 00059540 call 5954 <__muldf3> + 2d1c: da800717 ldw r10,28(sp) + 2d20: da400617 ldw r9,24(sp) + 2d24: b00f883a mov r7,r22 + 2d28: 5009883a mov r4,r10 + 2d2c: 480b883a mov r5,r9 + 2d30: 000d883a mov r6,zero + 2d34: 102b883a mov r21,r2 + 2d38: 1829883a mov r20,r3 + 2d3c: 00059540 call 5954 <__muldf3> + 2d40: a809883a mov r4,r21 + 2d44: a00b883a mov r5,r20 + 2d48: 100d883a mov r6,r2 + 2d4c: 180f883a mov r7,r3 + 2d50: 00045b80 call 45b8 <__adddf3> + 2d54: e009883a mov r4,fp + 2d58: b80b883a mov r5,r23 + 2d5c: 100d883a mov r6,r2 + 2d60: 180f883a mov r7,r3 + 2d64: 102d883a mov r22,r2 + 2d68: 182b883a mov r21,r3 + 2d6c: 00045b80 call 45b8 <__adddf3> + 2d70: 01cffbf4 movhi r7,16367 + 2d74: 01b80034 movhi r6,57344 + 2d78: 39f1c244 addi r7,r7,-14583 + 2d7c: 0009883a mov r4,zero + 2d80: 180b883a mov r5,r3 + 2d84: 1829883a mov r20,r3 + 2d88: 00059540 call 5954 <__muldf3> + 2d8c: e00d883a mov r6,fp + 2d90: b80f883a mov r7,r23 + 2d94: a00b883a mov r5,r20 + 2d98: 0009883a mov r4,zero + 2d9c: 1039883a mov fp,r2 + 2da0: 182f883a mov r23,r3 + 2da4: 0005fc80 call 5fc8 <__subdf3> + 2da8: b009883a mov r4,r22 + 2dac: a80b883a mov r5,r21 + 2db0: 100d883a mov r6,r2 + 2db4: 180f883a mov r7,r3 + 2db8: 0005fc80 call 5fc8 <__subdf3> + 2dbc: 01b70eb4 movhi r6,56378 + 2dc0: 01cffbf4 movhi r7,16367 + 2dc4: 3180ff44 addi r6,r6,1021 + 2dc8: 39f1c244 addi r7,r7,-14583 + 2dcc: 1009883a mov r4,r2 + 2dd0: 180b883a mov r5,r3 + 2dd4: 00059540 call 5954 <__muldf3> + 2dd8: 018516f4 movhi r6,5211 + 2ddc: 01ef8fb4 movhi r7,48702 + 2de0: a00b883a mov r5,r20 + 2de4: 31807d44 addi r6,r6,501 + 2de8: 39cbf804 addi r7,r7,12256 + 2dec: 0009883a mov r4,zero + 2df0: 102d883a mov r22,r2 + 2df4: 182b883a mov r21,r3 + 2df8: 00059540 call 5954 <__muldf3> + 2dfc: b009883a mov r4,r22 + 2e00: a80b883a mov r5,r21 + 2e04: 100d883a mov r6,r2 + 2e08: 180f883a mov r7,r3 + 2e0c: 00045b80 call 45b8 <__adddf3> + 2e10: dbc00917 ldw r15,36(sp) + 2e14: d9800a17 ldw r6,40(sp) + 2e18: 180b883a mov r5,r3 + 2e1c: 780f883a mov r7,r15 + 2e20: 1009883a mov r4,r2 + 2e24: 00045b80 call 45b8 <__adddf3> + 2e28: db000817 ldw r12,32(sp) + 2e2c: 102d883a mov r22,r2 + 2e30: 182b883a mov r21,r3 + 2e34: 6009883a mov r4,r12 + 2e38: 00069500 call 6950 <__floatsidf> + 2e3c: b00d883a mov r6,r22 + 2e40: a80f883a mov r7,r21 + 2e44: e009883a mov r4,fp + 2e48: b80b883a mov r5,r23 + 2e4c: d8800315 stw r2,12(sp) + 2e50: d8c00215 stw r3,8(sp) + 2e54: 00045b80 call 45b8 <__adddf3> + 2e58: d9800017 ldw r6,0(sp) + 2e5c: d9c00117 ldw r7,4(sp) + 2e60: 1009883a mov r4,r2 + 2e64: 180b883a mov r5,r3 + 2e68: 00045b80 call 45b8 <__adddf3> + 2e6c: da800317 ldw r10,12(sp) + 2e70: da400217 ldw r9,8(sp) + 2e74: 1009883a mov r4,r2 + 2e78: 500d883a mov r6,r10 + 2e7c: 480f883a mov r7,r9 + 2e80: 180b883a mov r5,r3 + 2e84: 00045b80 call 45b8 <__adddf3> + 2e88: da800317 ldw r10,12(sp) + 2e8c: da400217 ldw r9,8(sp) + 2e90: 0009883a mov r4,zero + 2e94: 500d883a mov r6,r10 + 2e98: 480f883a mov r7,r9 + 2e9c: 180b883a mov r5,r3 + 2ea0: 1829883a mov r20,r3 + 2ea4: 0005fc80 call 5fc8 <__subdf3> + 2ea8: d9800017 ldw r6,0(sp) + 2eac: d9c00117 ldw r7,4(sp) + 2eb0: 1009883a mov r4,r2 + 2eb4: 180b883a mov r5,r3 + 2eb8: 0005fc80 call 5fc8 <__subdf3> + 2ebc: e00d883a mov r6,fp + 2ec0: b80f883a mov r7,r23 + 2ec4: 1009883a mov r4,r2 + 2ec8: 180b883a mov r5,r3 + 2ecc: 0005fc80 call 5fc8 <__subdf3> + 2ed0: b009883a mov r4,r22 + 2ed4: 100d883a mov r6,r2 + 2ed8: 180f883a mov r7,r3 + 2edc: a80b883a mov r5,r21 + 2ee0: 94bfffc4 addi r18,r18,-1 + 2ee4: 0005fc80 call 5fc8 <__subdf3> + 2ee8: 94e6b03a or r19,r18,r19 + 2eec: 102f883a mov r23,r2 + 2ef0: 182d883a mov r22,r3 + 2ef4: 9801501e bne r19,zero,3438 <__ieee754_pow+0xe14> + 2ef8: 04effc34 movhi r19,49136 + 2efc: 880f883a mov r7,r17 + 2f00: 8009883a mov r4,r16 + 2f04: 880b883a mov r5,r17 + 2f08: 000d883a mov r6,zero + 2f0c: 0005fc80 call 5fc8 <__subdf3> + 2f10: a00f883a mov r7,r20 + 2f14: 000d883a mov r6,zero + 2f18: 1009883a mov r4,r2 + 2f1c: 180b883a mov r5,r3 + 2f20: 00059540 call 5954 <__muldf3> + 2f24: 800d883a mov r6,r16 + 2f28: 880f883a mov r7,r17 + 2f2c: b809883a mov r4,r23 + 2f30: b00b883a mov r5,r22 + 2f34: 102b883a mov r21,r2 + 2f38: 1825883a mov r18,r3 + 2f3c: 00059540 call 5954 <__muldf3> + 2f40: a809883a mov r4,r21 + 2f44: 900b883a mov r5,r18 + 2f48: 100d883a mov r6,r2 + 2f4c: 180f883a mov r7,r3 + 2f50: 00045b80 call 45b8 <__adddf3> + 2f54: 880f883a mov r7,r17 + 2f58: a00b883a mov r5,r20 + 2f5c: 000d883a mov r6,zero + 2f60: 0009883a mov r4,zero + 2f64: 1029883a mov r20,r2 + 2f68: 182b883a mov r21,r3 + 2f6c: 00059540 call 5954 <__muldf3> + 2f70: a80b883a mov r5,r21 + 2f74: 100d883a mov r6,r2 + 2f78: 180f883a mov r7,r3 + 2f7c: a009883a mov r4,r20 + 2f80: 1023883a mov r17,r2 + 2f84: 1825883a mov r18,r3 + 2f88: 00045b80 call 45b8 <__adddf3> + 2f8c: 01502434 movhi r5,16528 + 2f90: 1821883a mov r16,r3 + 2f94: 8817883a mov r11,r17 + 2f98: 902f883a mov r23,r18 + 2f9c: 102d883a mov r22,r2 + 2fa0: 1839883a mov fp,r3 + 2fa4: 1940fe16 blt r3,r5,33a0 <__ieee754_pow+0xd7c> + 2fa8: 1947c83a sub r3,r3,r5 + 2fac: 1d86b03a or r3,r3,r22 + 2fb0: 1801851e bne r3,zero,35c8 <__ieee754_pow+0xfa4> + 2fb4: 01994b34 movhi r6,25900 + 2fb8: 01cf25f4 movhi r7,15511 + 2fbc: 31a0bf84 addi r6,r6,-32002 + 2fc0: 39c551c4 addi r7,r7,5447 + 2fc4: a009883a mov r4,r20 + 2fc8: a80b883a mov r5,r21 + 2fcc: 00045b80 call 45b8 <__adddf3> + 2fd0: 880d883a mov r6,r17 + 2fd4: 900f883a mov r7,r18 + 2fd8: b009883a mov r4,r22 + 2fdc: 800b883a mov r5,r16 + 2fe0: 1039883a mov fp,r2 + 2fe4: 182f883a mov r23,r3 + 2fe8: 0005fc80 call 5fc8 <__subdf3> + 2fec: 100d883a mov r6,r2 + 2ff0: 180f883a mov r7,r3 + 2ff4: e009883a mov r4,fp + 2ff8: b80b883a mov r5,r23 + 2ffc: 00057840 call 5784 <__gedf2> + 3000: 00817116 blt zero,r2,35c8 <__ieee754_pow+0xfa4> + 3004: 800bd53a srai r5,r16,20 + 3008: 2941ffcc andi r5,r5,2047 + 300c: 00c00434 movhi r3,16 + 3010: 297f0084 addi r5,r5,-1022 + 3014: 194bd83a sra r5,r3,r5 + 3018: 00800434 movhi r2,16 + 301c: 10bfffc4 addi r2,r2,-1 + 3020: 2c07883a add r3,r5,r16 + 3024: 1809d53a srai r4,r3,20 + 3028: 18ac703a and r22,r3,r2 + 302c: b5800434 orhi r22,r22,16 + 3030: 2101ffcc andi r4,r4,2047 + 3034: 213f0044 addi r4,r4,-1023 + 3038: 110fd83a sra r7,r2,r4 + 303c: 00800504 movi r2,20 + 3040: 1109c83a sub r4,r2,r4 + 3044: b105d83a sra r2,r22,r4 + 3048: 01ce303a nor r7,zero,r7 + 304c: 38ce703a and r7,r7,r3 + 3050: d8800315 stw r2,12(sp) + 3054: 8000020e bge r16,zero,3060 <__ieee754_pow+0xa3c> + 3058: 0085c83a sub r2,zero,r2 + 305c: d8800315 stw r2,12(sp) + 3060: 000d883a mov r6,zero + 3064: 8809883a mov r4,r17 + 3068: 900b883a mov r5,r18 + 306c: 0005fc80 call 5fc8 <__subdf3> + 3070: 100d883a mov r6,r2 + 3074: 180f883a mov r7,r3 + 3078: a009883a mov r4,r20 + 307c: a80b883a mov r5,r21 + 3080: 182f883a mov r23,r3 + 3084: d8800015 stw r2,0(sp) + 3088: 00045b80 call 45b8 <__adddf3> + 308c: d8800317 ldw r2,12(sp) + 3090: dac00017 ldw r11,0(sp) + 3094: 1839883a mov fp,r3 + 3098: 1014953a slli r10,r2,20 + 309c: 01cff9b4 movhi r7,16358 + 30a0: e00b883a mov r5,fp + 30a4: 000d883a mov r6,zero + 30a8: 39cb90c4 addi r7,r7,11843 + 30ac: 0009883a mov r4,zero + 30b0: da800215 stw r10,8(sp) + 30b4: dac00015 stw r11,0(sp) + 30b8: 00059540 call 5954 <__muldf3> + 30bc: dac00017 ldw r11,0(sp) + 30c0: b80f883a mov r7,r23 + 30c4: e00b883a mov r5,fp + 30c8: 580d883a mov r6,r11 + 30cc: 0009883a mov r4,zero + 30d0: 102d883a mov r22,r2 + 30d4: 182f883a mov r23,r3 + 30d8: 0005fc80 call 5fc8 <__subdf3> + 30dc: a009883a mov r4,r20 + 30e0: a80b883a mov r5,r21 + 30e4: 100d883a mov r6,r2 + 30e8: 180f883a mov r7,r3 + 30ec: 0005fc80 call 5fc8 <__subdf3> + 30f0: 01bfbeb4 movhi r6,65274 + 30f4: 01cff9b4 movhi r7,16358 + 30f8: 318e7bc4 addi r6,r6,14831 + 30fc: 39cb9084 addi r7,r7,11842 + 3100: 1009883a mov r4,r2 + 3104: 180b883a mov r5,r3 + 3108: 00059540 call 5954 <__muldf3> + 310c: 01832a34 movhi r6,3240 + 3110: 01ef8834 movhi r7,48672 + 3114: e00b883a mov r5,fp + 3118: 319b0e44 addi r6,r6,27705 + 311c: 39d71844 addi r7,r7,23649 + 3120: 0009883a mov r4,zero + 3124: 1023883a mov r17,r2 + 3128: 1821883a mov r16,r3 + 312c: 00059540 call 5954 <__muldf3> + 3130: 8809883a mov r4,r17 + 3134: 800b883a mov r5,r16 + 3138: 100d883a mov r6,r2 + 313c: 180f883a mov r7,r3 + 3140: 00045b80 call 45b8 <__adddf3> + 3144: 100d883a mov r6,r2 + 3148: 180f883a mov r7,r3 + 314c: b009883a mov r4,r22 + 3150: b80b883a mov r5,r23 + 3154: 1029883a mov r20,r2 + 3158: 1825883a mov r18,r3 + 315c: 00045b80 call 45b8 <__adddf3> + 3160: b00d883a mov r6,r22 + 3164: b80f883a mov r7,r23 + 3168: 1009883a mov r4,r2 + 316c: 180b883a mov r5,r3 + 3170: 1023883a mov r17,r2 + 3174: 1821883a mov r16,r3 + 3178: 0005fc80 call 5fc8 <__subdf3> + 317c: a009883a mov r4,r20 + 3180: 900b883a mov r5,r18 + 3184: 100d883a mov r6,r2 + 3188: 180f883a mov r7,r3 + 318c: 0005fc80 call 5fc8 <__subdf3> + 3190: 880d883a mov r6,r17 + 3194: 800f883a mov r7,r16 + 3198: 8809883a mov r4,r17 + 319c: 800b883a mov r5,r16 + 31a0: 1039883a mov fp,r2 + 31a4: 182b883a mov r21,r3 + 31a8: 00059540 call 5954 <__muldf3> + 31ac: 019caff4 movhi r6,29375 + 31b0: 01cf99b4 movhi r7,15974 + 31b4: 31a93404 addi r6,r6,-23344 + 31b8: 39cdda44 addi r7,r7,14185 + 31bc: 1009883a mov r4,r2 + 31c0: 180b883a mov r5,r3 + 31c4: 1029883a mov r20,r2 + 31c8: 1825883a mov r18,r3 + 31cc: 00059540 call 5954 <__muldf3> + 31d0: 01b174b4 movhi r6,50642 + 31d4: 01cfaf34 movhi r7,16060 + 31d8: 319afc44 addi r6,r6,27633 + 31dc: 39ef5044 addi r7,r7,-17087 + 31e0: 1009883a mov r4,r2 + 31e4: 180b883a mov r5,r3 + 31e8: 0005fc80 call 5fc8 <__subdf3> + 31ec: a00d883a mov r6,r20 + 31f0: 900f883a mov r7,r18 + 31f4: 1009883a mov r4,r2 + 31f8: 180b883a mov r5,r3 + 31fc: 00059540 call 5954 <__muldf3> + 3200: 01abc9b4 movhi r6,44838 + 3204: 01cfc474 movhi r7,16145 + 3208: 31b78b04 addi r6,r6,-8660 + 320c: 39d59a84 addi r7,r7,22122 + 3210: 1009883a mov r4,r2 + 3214: 180b883a mov r5,r3 + 3218: 00045b80 call 45b8 <__adddf3> + 321c: a00d883a mov r6,r20 + 3220: 900f883a mov r7,r18 + 3224: 1009883a mov r4,r2 + 3228: 180b883a mov r5,r3 + 322c: 00059540 call 5954 <__muldf3> + 3230: 0185aff4 movhi r6,5823 + 3234: 01cfd9f4 movhi r7,16231 + 3238: 31af64c4 addi r6,r6,-17005 + 323c: 39f05b04 addi r7,r7,-16020 + 3240: 1009883a mov r4,r2 + 3244: 180b883a mov r5,r3 + 3248: 0005fc80 call 5fc8 <__subdf3> + 324c: a00d883a mov r6,r20 + 3250: 900f883a mov r7,r18 + 3254: 1009883a mov r4,r2 + 3258: 180b883a mov r5,r3 + 325c: 00059540 call 5954 <__muldf3> + 3260: 01955574 movhi r6,21845 + 3264: 01cff174 movhi r7,16325 + 3268: 31954f84 addi r6,r6,21822 + 326c: 39d55544 addi r7,r7,21845 + 3270: 1009883a mov r4,r2 + 3274: 180b883a mov r5,r3 + 3278: 00045b80 call 45b8 <__adddf3> + 327c: a00d883a mov r6,r20 + 3280: 900f883a mov r7,r18 + 3284: 1009883a mov r4,r2 + 3288: 180b883a mov r5,r3 + 328c: 00059540 call 5954 <__muldf3> + 3290: 100d883a mov r6,r2 + 3294: 180f883a mov r7,r3 + 3298: 8809883a mov r4,r17 + 329c: 800b883a mov r5,r16 + 32a0: 0005fc80 call 5fc8 <__subdf3> + 32a4: 100d883a mov r6,r2 + 32a8: 180f883a mov r7,r3 + 32ac: 8809883a mov r4,r17 + 32b0: 800b883a mov r5,r16 + 32b4: 1029883a mov r20,r2 + 32b8: 1825883a mov r18,r3 + 32bc: 00059540 call 5954 <__muldf3> + 32c0: a009883a mov r4,r20 + 32c4: 900b883a mov r5,r18 + 32c8: 000d883a mov r6,zero + 32cc: 01d00034 movhi r7,16384 + 32d0: d8800115 stw r2,4(sp) + 32d4: d8c00015 stw r3,0(sp) + 32d8: 0005fc80 call 5fc8 <__subdf3> + 32dc: da400117 ldw r9,4(sp) + 32e0: da000017 ldw r8,0(sp) + 32e4: 100d883a mov r6,r2 + 32e8: 4809883a mov r4,r9 + 32ec: 400b883a mov r5,r8 + 32f0: 180f883a mov r7,r3 + 32f4: 0004ea80 call 4ea8 <__divdf3> + 32f8: e00d883a mov r6,fp + 32fc: a80f883a mov r7,r21 + 3300: 8809883a mov r4,r17 + 3304: 800b883a mov r5,r16 + 3308: 1029883a mov r20,r2 + 330c: 1825883a mov r18,r3 + 3310: 00059540 call 5954 <__muldf3> + 3314: e00d883a mov r6,fp + 3318: a80f883a mov r7,r21 + 331c: 1009883a mov r4,r2 + 3320: 180b883a mov r5,r3 + 3324: 00045b80 call 45b8 <__adddf3> + 3328: 100d883a mov r6,r2 + 332c: 180f883a mov r7,r3 + 3330: a009883a mov r4,r20 + 3334: 900b883a mov r5,r18 + 3338: 0005fc80 call 5fc8 <__subdf3> + 333c: 880d883a mov r6,r17 + 3340: 800f883a mov r7,r16 + 3344: 1009883a mov r4,r2 + 3348: 180b883a mov r5,r3 + 334c: 0005fc80 call 5fc8 <__subdf3> + 3350: 100d883a mov r6,r2 + 3354: 0009883a mov r4,zero + 3358: 014ffc34 movhi r5,16368 + 335c: 180f883a mov r7,r3 + 3360: 0005fc80 call 5fc8 <__subdf3> + 3364: da800217 ldw r10,8(sp) + 3368: 1009883a mov r4,r2 + 336c: 50cd883a add r6,r10,r3 + 3370: 300bd53a srai r5,r6,20 + 3374: 0140ca0e bge zero,r5,36a0 <__ieee754_pow+0x107c> + 3378: 300b883a mov r5,r6 + 337c: 000d883a mov r6,zero + 3380: 980f883a mov r7,r19 + 3384: 00059540 call 5954 <__muldf3> + 3388: 102d883a mov r22,r2 + 338c: 003cbf06 br 268c <__ieee754_pow+0x68> + 3390: 8800ab16 blt r17,zero,3640 <__ieee754_pow+0x101c> + 3394: 202d883a mov r22,r4 + 3398: a807883a mov r3,r21 + 339c: 003cbb06 br 268c <__ieee754_pow+0x68> + 33a0: 01600034 movhi r5,32768 + 33a4: 297fffc4 addi r5,r5,-1 + 33a8: 00902474 movhi r2,16529 + 33ac: 194a703a and r5,r3,r5 + 33b0: 10b2ffc4 addi r2,r2,-13313 + 33b4: 11407f0e bge r2,r5,35b4 <__ieee754_pow+0xf90> + 33b8: 008fdbf4 movhi r2,16239 + 33bc: 108d0004 addi r2,r2,13312 + 33c0: 1885883a add r2,r3,r2 + 33c4: 1584b03a or r2,r2,r22 + 33c8: 10000b1e bne r2,zero,33f8 <__ieee754_pow+0xdd4> + 33cc: 880d883a mov r6,r17 + 33d0: 900f883a mov r7,r18 + 33d4: b009883a mov r4,r22 + 33d8: 180b883a mov r5,r3 + 33dc: 0005fc80 call 5fc8 <__subdf3> + 33e0: a00d883a mov r6,r20 + 33e4: a80f883a mov r7,r21 + 33e8: 1009883a mov r4,r2 + 33ec: 180b883a mov r5,r3 + 33f0: 00057840 call 5784 <__gedf2> + 33f4: 103f0316 blt r2,zero,3004 <__ieee754_pow+0x9e0> + 33f8: 01b0be74 movhi r6,49913 + 33fc: 01c06974 movhi r7,421 + 3400: 31bcd644 addi r6,r6,-3239 + 3404: 39db87c4 addi r7,r7,28191 + 3408: 0009883a mov r4,zero + 340c: 980b883a mov r5,r19 + 3410: 00059540 call 5954 <__muldf3> + 3414: 01b0be74 movhi r6,49913 + 3418: 01c06974 movhi r7,421 + 341c: 31bcd644 addi r6,r6,-3239 + 3420: 39db87c4 addi r7,r7,28191 + 3424: 1009883a mov r4,r2 + 3428: 180b883a mov r5,r3 + 342c: 00059540 call 5954 <__muldf3> + 3430: 102d883a mov r22,r2 + 3434: 003c9506 br 268c <__ieee754_pow+0x68> + 3438: 04cffc34 movhi r19,16368 + 343c: 003eaf06 br 2efc <__ieee754_pow+0x8d8> + 3440: 008ffc34 movhi r2,16368 + 3444: 10bfff84 addi r2,r2,-2 + 3448: 153ce10e bge r2,r20,27d0 <__ieee754_pow+0x1ac> + 344c: 008ffc34 movhi r2,16368 + 3450: 153d0616 blt r2,r20,286c <__ieee754_pow+0x248> + 3454: 000d883a mov r6,zero + 3458: 01cffc34 movhi r7,16368 + 345c: 180b883a mov r5,r3 + 3460: 0005fc80 call 5fc8 <__subdf3> + 3464: 01cffdf4 movhi r7,16375 + 3468: 01980034 movhi r6,24576 + 346c: 39c551c4 addi r7,r7,5447 + 3470: 1009883a mov r4,r2 + 3474: 180b883a mov r5,r3 + 3478: 102b883a mov r21,r2 + 347c: 1829883a mov r20,r3 + 3480: 00059540 call 5954 <__muldf3> + 3484: 01be17b4 movhi r6,63582 + 3488: 01cf9574 movhi r7,15957 + 348c: a809883a mov r4,r21 + 3490: a00b883a mov r5,r20 + 3494: 31b7d104 addi r6,r6,-8380 + 3498: 39eb82c4 addi r7,r7,-20981 + 349c: 1039883a mov fp,r2 + 34a0: 182f883a mov r23,r3 + 34a4: 00059540 call 5954 <__muldf3> + 34a8: a809883a mov r4,r21 + 34ac: a00b883a mov r5,r20 + 34b0: 000d883a mov r6,zero + 34b4: 01cff434 movhi r7,16336 + 34b8: 182d883a mov r22,r3 + 34bc: d8800215 stw r2,8(sp) + 34c0: 00059540 call 5954 <__muldf3> + 34c4: 01155574 movhi r4,21845 + 34c8: 014ff574 movhi r5,16341 + 34cc: 100d883a mov r6,r2 + 34d0: 180f883a mov r7,r3 + 34d4: 21155544 addi r4,r4,21845 + 34d8: 29555544 addi r5,r5,21845 + 34dc: 0005fc80 call 5fc8 <__subdf3> + 34e0: a80d883a mov r6,r21 + 34e4: a00f883a mov r7,r20 + 34e8: 1009883a mov r4,r2 + 34ec: 180b883a mov r5,r3 + 34f0: 00059540 call 5954 <__muldf3> + 34f4: 100d883a mov r6,r2 + 34f8: 180f883a mov r7,r3 + 34fc: 0009883a mov r4,zero + 3500: 014ff834 movhi r5,16352 + 3504: 0005fc80 call 5fc8 <__subdf3> + 3508: a80d883a mov r6,r21 + 350c: a00f883a mov r7,r20 + 3510: a809883a mov r4,r21 + 3514: a00b883a mov r5,r20 + 3518: d8800115 stw r2,4(sp) + 351c: d8c00015 stw r3,0(sp) + 3520: 00059540 call 5954 <__muldf3> + 3524: da800117 ldw r10,4(sp) + 3528: da400017 ldw r9,0(sp) + 352c: 100d883a mov r6,r2 + 3530: 5009883a mov r4,r10 + 3534: 480b883a mov r5,r9 + 3538: 180f883a mov r7,r3 + 353c: 00059540 call 5954 <__muldf3> + 3540: 01994b34 movhi r6,25900 + 3544: 01cffdf4 movhi r7,16375 + 3548: 31a0bf84 addi r6,r6,-32002 + 354c: 39c551c4 addi r7,r7,5447 + 3550: 1009883a mov r4,r2 + 3554: 180b883a mov r5,r3 + 3558: 00059540 call 5954 <__muldf3> + 355c: da000217 ldw r8,8(sp) + 3560: b00b883a mov r5,r22 + 3564: 100d883a mov r6,r2 + 3568: 4009883a mov r4,r8 + 356c: 180f883a mov r7,r3 + 3570: 0005fc80 call 5fc8 <__subdf3> + 3574: 100d883a mov r6,r2 + 3578: 180f883a mov r7,r3 + 357c: e009883a mov r4,fp + 3580: b80b883a mov r5,r23 + 3584: 102d883a mov r22,r2 + 3588: 182b883a mov r21,r3 + 358c: 00045b80 call 45b8 <__adddf3> + 3590: 1829883a mov r20,r3 + 3594: e00d883a mov r6,fp + 3598: b80f883a mov r7,r23 + 359c: 0009883a mov r4,zero + 35a0: 180b883a mov r5,r3 + 35a4: 003e4906 br 2ecc <__ieee754_pow+0x8a8> + 35a8: 883c8b0e bge r17,zero,27d8 <__ieee754_pow+0x1b4> + 35ac: 88e0003c xorhi r3,r17,32768 + 35b0: 003c3606 br 268c <__ieee754_pow+0x68> + 35b4: 008ff834 movhi r2,16352 + 35b8: 11404816 blt r2,r5,36dc <__ieee754_pow+0x10b8> + 35bc: 0015883a mov r10,zero + 35c0: d8000315 stw zero,12(sp) + 35c4: 003eb506 br 309c <__ieee754_pow+0xa78> + 35c8: 01a20034 movhi r6,34816 + 35cc: 01df8e34 movhi r7,32312 + 35d0: 319d6704 addi r6,r6,30108 + 35d4: 39f90f04 addi r7,r7,-7108 + 35d8: 0009883a mov r4,zero + 35dc: 980b883a mov r5,r19 + 35e0: 00059540 call 5954 <__muldf3> + 35e4: 01a20034 movhi r6,34816 + 35e8: 01df8e34 movhi r7,32312 + 35ec: 319d6704 addi r6,r6,30108 + 35f0: 39f90f04 addi r7,r7,-7108 + 35f4: 1009883a mov r4,r2 + 35f8: 180b883a mov r5,r3 + 35fc: 00059540 call 5954 <__muldf3> + 3600: 102d883a mov r22,r2 + 3604: 003c2106 br 268c <__ieee754_pow+0x68> + 3608: 803c771e bne r16,zero,27e8 <__ieee754_pow+0x1c4> + 360c: 01400504 movi r5,20 + 3610: 28c7c83a sub r3,r5,r3 + 3614: 10cbd83a sra r5,r2,r3 + 3618: 28c6983a sll r3,r5,r3 + 361c: 18802b26 beq r3,r2,36cc <__ieee754_pow+0x10a8> + 3620: 0025883a mov r18,zero + 3624: 003c3106 br 26ec <__ieee754_pow+0xc8> + 3628: 200d883a mov r6,r4 + 362c: a80f883a mov r7,r21 + 3630: a80b883a mov r5,r21 + 3634: 00059540 call 5954 <__muldf3> + 3638: 102d883a mov r22,r2 + 363c: 003c1306 br 268c <__ieee754_pow+0x68> + 3640: 200d883a mov r6,r4 + 3644: a80f883a mov r7,r21 + 3648: 0009883a mov r4,zero + 364c: 014ffc34 movhi r5,16368 + 3650: 0004ea80 call 4ea8 <__divdf3> + 3654: 102d883a mov r22,r2 + 3658: 003c0c06 br 268c <__ieee754_pow+0x68> + 365c: 94800058 cmpnei r18,r18,1 + 3660: 903c0a1e bne r18,zero,268c <__ieee754_pow+0x68> + 3664: 18e0003c xorhi r3,r3,32768 + 3668: 003c0806 br 268c <__ieee754_pow+0x68> + 366c: 008ff8f4 movhi r2,16355 + 3670: 10ae00c4 addi r2,r2,-18429 + 3674: 00d0f434 movhi r3,17360 + 3678: 03cf9374 movhi r15,15949 + 367c: 01100034 movhi r4,16384 + 3680: d8800115 stw r2,4(sp) + 3684: 18b40184 addi r2,r3,-12282 + 3688: d9000015 stw r4,0(sp) + 368c: d8800a15 stw r2,40(sp) + 3690: 7bff7ac4 addi r15,r15,-533 + 3694: 05c00134 movhi r23,4 + 3698: 034ffe34 movhi r13,16376 + 369c: 003cb006 br 2960 <__ieee754_pow+0x33c> + 36a0: d9800317 ldw r6,12(sp) + 36a4: 180b883a mov r5,r3 + 36a8: 0003b2c0 call 3b2c + 36ac: 1009883a mov r4,r2 + 36b0: 180b883a mov r5,r3 + 36b4: 003f3106 br 337c <__ieee754_pow+0xd58> + 36b8: 2940004c andi r5,r5,1 + 36bc: 04800084 movi r18,2 + 36c0: 9165c83a sub r18,r18,r5 + 36c4: 803c331e bne r16,zero,2794 <__ieee754_pow+0x170> + 36c8: 003c0806 br 26ec <__ieee754_pow+0xc8> + 36cc: 2940004c andi r5,r5,1 + 36d0: 04800084 movi r18,2 + 36d4: 9165c83a sub r18,r18,r5 + 36d8: 003c0406 br 26ec <__ieee754_pow+0xc8> + 36dc: 280bd53a srai r5,r5,20 + 36e0: 003e4a06 br 300c <__ieee754_pow+0x9e8> + +000036e4 <__ieee754_sqrt>: + 36e4: defffd04 addi sp,sp,-12 + 36e8: dc400115 stw r17,4(sp) + 36ec: dc000015 stw r16,0(sp) + 36f0: dfc00215 stw ra,8(sp) + 36f4: 28dffc2c andhi r3,r5,32752 + 36f8: 009ffc34 movhi r2,32752 + 36fc: 2821883a mov r16,r5 + 3700: 2023883a mov r17,r4 + 3704: 18807726 beq r3,r2,38e4 <__ieee754_sqrt+0x200> + 3708: 2011883a mov r8,r4 + 370c: 01403a0e bge zero,r5,37f8 <__ieee754_sqrt+0x114> + 3710: 280bd53a srai r5,r5,20 + 3714: 28004626 beq r5,zero,3830 <__ieee754_sqrt+0x14c> + 3718: 00800434 movhi r2,16 + 371c: 10bfffc4 addi r2,r2,-1 + 3720: 4006d7fa srli r3,r8,31 + 3724: 8084703a and r2,r16,r2 + 3728: 297f0044 addi r5,r5,-1023 + 372c: 10800434 orhi r2,r2,16 + 3730: 1085883a add r2,r2,r2 + 3734: 2980004c andi r6,r5,1 + 3738: 10c7883a add r3,r2,r3 + 373c: 4209883a add r4,r8,r8 + 3740: 30000426 beq r6,zero,3754 <__ieee754_sqrt+0x70> + 3744: 2004d7fa srli r2,r4,31 + 3748: 400890ba slli r4,r8,2 + 374c: 18c7883a add r3,r3,r3 + 3750: 1887883a add r3,r3,r2 + 3754: 2815d07a srai r10,r5,1 + 3758: 01c00584 movi r7,22 + 375c: 0019883a mov r12,zero + 3760: 000b883a mov r5,zero + 3764: 00800834 movhi r2,32 + 3768: 288d883a add r6,r5,r2 + 376c: 2010d7fa srli r8,r4,31 + 3770: 39ffffc4 addi r7,r7,-1 + 3774: 19800316 blt r3,r6,3784 <__ieee754_sqrt+0xa0> + 3778: 1987c83a sub r3,r3,r6 + 377c: 308b883a add r5,r6,r2 + 3780: 6099883a add r12,r12,r2 + 3784: 18c7883a add r3,r3,r3 + 3788: 1004d07a srli r2,r2,1 + 378c: 40c7883a add r3,r8,r3 + 3790: 2109883a add r4,r4,r4 + 3794: 383ff41e bne r7,zero,3768 <__ieee754_sqrt+0x84> + 3798: 0013883a mov r9,zero + 379c: 00800804 movi r2,32 + 37a0: 01a00034 movhi r6,32768 + 37a4: 00000806 br 37c8 <__ieee754_sqrt+0xe4> + 37a8: 19403326 beq r3,r5,3878 <__ieee754_sqrt+0x194> + 37ac: 2010d7fa srli r8,r4,31 + 37b0: 18c7883a add r3,r3,r3 + 37b4: 10bfffc4 addi r2,r2,-1 + 37b8: 300cd07a srli r6,r6,1 + 37bc: 1a07883a add r3,r3,r8 + 37c0: 2109883a add r4,r4,r4 + 37c4: 10003226 beq r2,zero,3890 <__ieee754_sqrt+0x1ac> + 37c8: 31d1883a add r8,r6,r7 + 37cc: 28fff60e bge r5,r3,37a8 <__ieee754_sqrt+0xc4> + 37d0: 418f883a add r7,r8,r6 + 37d4: 40002516 blt r8,zero,386c <__ieee754_sqrt+0x188> + 37d8: 2817883a mov r11,r5 + 37dc: 1947c83a sub r3,r3,r5 + 37e0: 2200012e bgeu r4,r8,37e8 <__ieee754_sqrt+0x104> + 37e4: 18ffffc4 addi r3,r3,-1 + 37e8: 2209c83a sub r4,r4,r8 + 37ec: 4993883a add r9,r9,r6 + 37f0: 580b883a mov r5,r11 + 37f4: 003fed06 br 37ac <__ieee754_sqrt+0xc8> + 37f8: 00a00034 movhi r2,32768 + 37fc: 10bfffc4 addi r2,r2,-1 + 3800: 2884703a and r2,r5,r2 + 3804: 1104b03a or r2,r2,r4 + 3808: 10004826 beq r2,zero,392c <__ieee754_sqrt+0x248> + 380c: 28003e1e bne r5,zero,3908 <__ieee754_sqrt+0x224> + 3810: 000b883a mov r5,zero + 3814: 4004d2fa srli r2,r8,11 + 3818: 297ffac4 addi r5,r5,-21 + 381c: 4010957a slli r8,r8,21 + 3820: 1021883a mov r16,r2 + 3824: 103ffb26 beq r2,zero,3814 <__ieee754_sqrt+0x130> + 3828: 10c0042c andhi r3,r2,16 + 382c: 1800441e bne r3,zero,3940 <__ieee754_sqrt+0x25c> + 3830: 0005883a mov r2,zero + 3834: 8421883a add r16,r16,r16 + 3838: 8100042c andhi r4,r16,16 + 383c: 1007883a mov r3,r2 + 3840: 10800044 addi r2,r2,1 + 3844: 203ffb26 beq r4,zero,3834 <__ieee754_sqrt+0x150> + 3848: 01800804 movi r6,32 + 384c: 4009883a mov r4,r8 + 3850: 308dc83a sub r6,r6,r2 + 3854: 4090983a sll r8,r8,r2 + 3858: 8005883a mov r2,r16 + 385c: 218ed83a srl r7,r4,r6 + 3860: 28cbc83a sub r5,r5,r3 + 3864: 38a0b03a or r16,r7,r2 + 3868: 003fab06 br 3718 <__ieee754_sqrt+0x34> + 386c: 383fda16 blt r7,zero,37d8 <__ieee754_sqrt+0xf4> + 3870: 2ac00044 addi r11,r5,1 + 3874: 003fd906 br 37dc <__ieee754_sqrt+0xf8> + 3878: 223fcc36 bltu r4,r8,37ac <__ieee754_sqrt+0xc8> + 387c: 418f883a add r7,r8,r6 + 3880: 403ffa16 blt r8,zero,386c <__ieee754_sqrt+0x188> + 3884: 1817883a mov r11,r3 + 3888: 0007883a mov r3,zero + 388c: 003fd606 br 37e8 <__ieee754_sqrt+0x104> + 3890: 1906b03a or r3,r3,r4 + 3894: 18000e1e bne r3,zero,38d0 <__ieee754_sqrt+0x1ec> + 3898: 4804d07a srli r2,r9,1 + 389c: 6007d07a srai r3,r12,1 + 38a0: 01cff834 movhi r7,16352 + 38a4: 6300004c andi r12,r12,1 + 38a8: 19cf883a add r7,r3,r7 + 38ac: 60000126 beq r12,zero,38b4 <__ieee754_sqrt+0x1d0> + 38b0: 10a00034 orhi r2,r2,32768 + 38b4: 5006953a slli r3,r10,20 + 38b8: 19c7883a add r3,r3,r7 + 38bc: dfc00217 ldw ra,8(sp) + 38c0: dc400117 ldw r17,4(sp) + 38c4: dc000017 ldw r16,0(sp) + 38c8: dec00304 addi sp,sp,12 + 38cc: f800283a ret + 38d0: 48ffffd8 cmpnei r3,r9,-1 + 38d4: 18001826 beq r3,zero,3938 <__ieee754_sqrt+0x254> + 38d8: 48800044 addi r2,r9,1 + 38dc: 1004d07a srli r2,r2,1 + 38e0: 003fee06 br 389c <__ieee754_sqrt+0x1b8> + 38e4: 200d883a mov r6,r4 + 38e8: 280f883a mov r7,r5 + 38ec: 00059540 call 5954 <__muldf3> + 38f0: 880d883a mov r6,r17 + 38f4: 800f883a mov r7,r16 + 38f8: 1009883a mov r4,r2 + 38fc: 180b883a mov r5,r3 + 3900: 00045b80 call 45b8 <__adddf3> + 3904: 003fed06 br 38bc <__ieee754_sqrt+0x1d8> + 3908: 200d883a mov r6,r4 + 390c: 280f883a mov r7,r5 + 3910: 0005fc80 call 5fc8 <__subdf3> + 3914: 100d883a mov r6,r2 + 3918: 180f883a mov r7,r3 + 391c: 1009883a mov r4,r2 + 3920: 180b883a mov r5,r3 + 3924: 0004ea80 call 4ea8 <__divdf3> + 3928: 003fe406 br 38bc <__ieee754_sqrt+0x1d8> + 392c: 2005883a mov r2,r4 + 3930: 2807883a mov r3,r5 + 3934: 003fe106 br 38bc <__ieee754_sqrt+0x1d8> + 3938: 63000044 addi r12,r12,1 + 393c: 003fd706 br 389c <__ieee754_sqrt+0x1b8> + 3940: 4009883a mov r4,r8 + 3944: 01800804 movi r6,32 + 3948: 00ffffc4 movi r3,-1 + 394c: 003fc306 br 385c <__ieee754_sqrt+0x178> + +00003950 : + 3950: 2811d53a srai r8,r5,20 + 3954: defff904 addi sp,sp,-28 + 3958: dc000215 stw r16,8(sp) + 395c: 4201ffcc andi r8,r8,2047 + 3960: 427f0044 addi r9,r8,-1023 + 3964: dfc00615 stw ra,24(sp) + 3968: dcc00515 stw r19,20(sp) + 396c: dc800415 stw r18,16(sp) + 3970: dc400315 stw r17,12(sp) + 3974: 4a800508 cmpgei r10,r9,20 + 3978: 2816d7fa srli r11,r5,31 + 397c: 2821883a mov r16,r5 + 3980: 2005883a mov r2,r4 + 3984: 280f883a mov r7,r5 + 3988: 200d883a mov r6,r4 + 398c: 50002b1e bne r10,zero,3a3c + 3990: 48002316 blt r9,zero,3a20 + 3994: 01000434 movhi r4,16 3998: 213fffc4 addi r4,r4,-1 - 399c: 18c03fcc andi r3,r3,255 - 39a0: 282ed7fa srli r23,r5,31 - 39a4: 2166703a and r19,r4,r5 - 39a8: 18005326 beq r3,zero,3af8 <__divsf3+0x1cc> - 39ac: 18803fe0 cmpeqi r2,r3,255 - 39b0: 10004d1e bne r2,zero,3ae8 <__divsf3+0x1bc> - 39b4: 980a90fa slli r5,r19,3 - 39b8: 18ffe044 addi r3,r3,-127 - 39bc: a0e9c83a sub r20,r20,r3 - 39c0: 2cc10034 orhi r19,r5,1024 - 39c4: 0007883a mov r3,zero - 39c8: 1c62b03a or r17,r3,r17 - 39cc: 882290ba slli r17,r17,2 - 39d0: 00800034 movhi r2,0 - 39d4: bd6af03a xor r21,r23,r21 - 39d8: 8885883a add r2,r17,r2 - 39dc: 108e7a17 ldw r2,14824(r2) - 39e0: a809883a mov r4,r21 - 39e4: 1000683a jmp r2 - 39e8: 00003cac andhi zero,zero,242 - 39ec: 00003bec andhi zero,zero,239 - 39f0: 00003a9c xori zero,zero,234 - 39f4: 00003a2c andhi zero,zero,232 - 39f8: 00003a9c xori zero,zero,234 - 39fc: 00003c58 cmpnei zero,zero,241 - 3a00: 00003a9c xori zero,zero,234 - 3a04: 00003a2c andhi zero,zero,232 - 3a08: 00003bec andhi zero,zero,239 - 3a0c: 00003bec andhi zero,zero,239 - 3a10: 00003c58 cmpnei zero,zero,241 - 3a14: 00003a2c andhi zero,zero,232 - 3a18: 00003a38 rdprs zero,zero,232 - 3a1c: 00003a38 rdprs zero,zero,232 - 3a20: 00003a38 rdprs zero,zero,232 - 3a24: 00003c70 cmpltui zero,zero,241 - 3a28: 0027883a mov r19,zero - 3a2c: b825883a mov r18,r23 - 3a30: 9821883a mov r16,r19 - 3a34: 182d883a mov r22,r3 - 3a38: b08000a0 cmpeqi r2,r22,2 - 3a3c: 1000831e bne r2,zero,3c4c <__divsf3+0x320> - 3a40: b08000e0 cmpeqi r2,r22,3 - 3a44: 1000941e bne r2,zero,3c98 <__divsf3+0x36c> - 3a48: b5800060 cmpeqi r22,r22,1 - 3a4c: b000141e bne r22,zero,3aa0 <__divsf3+0x174> - 3a50: a0801fc4 addi r2,r20,127 - 3a54: 0080690e bge zero,r2,3bfc <__divsf3+0x2d0> - 3a58: 80c001cc andi r3,r16,7 - 3a5c: 18000426 beq r3,zero,3a70 <__divsf3+0x144> - 3a60: 80c003cc andi r3,r16,15 - 3a64: 18c00120 cmpeqi r3,r3,4 - 3a68: 1800011e bne r3,zero,3a70 <__divsf3+0x144> - 3a6c: 84000104 addi r16,r16,4 - 3a70: 80c2002c andhi r3,r16,2048 - 3a74: 18000426 beq r3,zero,3a88 <__divsf3+0x15c> - 3a78: 00be0034 movhi r2,63488 - 3a7c: 10bfffc4 addi r2,r2,-1 - 3a80: 80a0703a and r16,r16,r2 - 3a84: a0802004 addi r2,r20,128 - 3a88: 10c03fc8 cmpgei r3,r2,255 - 3a8c: 18006f1e bne r3,zero,3c4c <__divsf3+0x320> - 3a90: 802091ba slli r16,r16,6 - 3a94: 8020d27a srli r16,r16,9 - 3a98: 00000306 br 3aa8 <__divsf3+0x17c> - 3a9c: a825883a mov r18,r21 - 3aa0: 0005883a mov r2,zero - 3aa4: 0021883a mov r16,zero - 3aa8: 10803fcc andi r2,r2,255 - 3aac: 100495fa slli r2,r2,23 - 3ab0: 902497fa slli r18,r18,31 - 3ab4: 1404b03a or r2,r2,r16 - 3ab8: 1484b03a or r2,r2,r18 - 3abc: dfc00917 ldw ra,36(sp) - 3ac0: ddc00817 ldw r23,32(sp) - 3ac4: dd800717 ldw r22,28(sp) - 3ac8: dd400617 ldw r21,24(sp) - 3acc: dd000517 ldw r20,20(sp) - 3ad0: dcc00417 ldw r19,16(sp) - 3ad4: dc800317 ldw r18,12(sp) - 3ad8: dc400217 ldw r17,8(sp) - 3adc: dc000117 ldw r16,4(sp) - 3ae0: dec00a04 addi sp,sp,40 - 3ae4: f800283a ret - 3ae8: a53fc044 addi r20,r20,-255 - 3aec: 98003d1e bne r19,zero,3be4 <__divsf3+0x2b8> - 3af0: 00c00084 movi r3,2 - 3af4: 00000206 br 3b00 <__divsf3+0x1d4> - 3af8: 9800321e bne r19,zero,3bc4 <__divsf3+0x298> - 3afc: 00c00044 movi r3,1 - 3b00: 1c62b03a or r17,r3,r17 - 3b04: 882290ba slli r17,r17,2 - 3b08: 00800034 movhi r2,0 - 3b0c: bd6af03a xor r21,r23,r21 - 3b10: 8885883a add r2,r17,r2 - 3b14: 108ec817 ldw r2,15136(r2) - 3b18: a809883a mov r4,r21 - 3b1c: 1000683a jmp r2 - 3b20: 00003bec andhi zero,zero,239 - 3b24: 00003bec andhi zero,zero,239 - 3b28: 00003a9c xori zero,zero,234 - 3b2c: 00003a28 cmpgeui zero,zero,232 - 3b30: 00003a9c xori zero,zero,234 - 3b34: 00003c58 cmpnei zero,zero,241 - 3b38: 00003a9c xori zero,zero,234 - 3b3c: 00003a28 cmpgeui zero,zero,232 - 3b40: 00003bec andhi zero,zero,239 - 3b44: 00003bec andhi zero,zero,239 - 3b48: 00003c58 cmpnei zero,zero,241 - 3b4c: 00003a28 cmpgeui zero,zero,232 - 3b50: 00003a38 rdprs zero,zero,232 - 3b54: 00003a38 rdprs zero,zero,232 - 3b58: 00003a38 rdprs zero,zero,232 - 3b5c: 00003c6c andhi zero,zero,241 - 3b60: 80000d1e bne r16,zero,3b98 <__divsf3+0x26c> - 3b64: 04400104 movi r17,4 - 3b68: 0029883a mov r20,zero - 3b6c: 05800044 movi r22,1 - 3b70: 003f8706 br 3990 <__divsf3+0x64> - 3b74: 8000041e bne r16,zero,3b88 <__divsf3+0x25c> - 3b78: 04400204 movi r17,8 - 3b7c: 05003fc4 movi r20,255 - 3b80: 05800084 movi r22,2 - 3b84: 003f8206 br 3990 <__divsf3+0x64> - 3b88: 04400304 movi r17,12 - 3b8c: 05003fc4 movi r20,255 - 3b90: 058000c4 movi r22,3 - 3b94: 003f7e06 br 3990 <__divsf3+0x64> - 3b98: 8009883a mov r4,r16 - 3b9c: d9400015 stw r5,0(sp) - 3ba0: 0004a200 call 4a20 <__clzsi2> - 3ba4: 10fffec4 addi r3,r2,-5 - 3ba8: 80e0983a sll r16,r16,r3 - 3bac: 00ffe284 movi r3,-118 - 3bb0: d9400017 ldw r5,0(sp) - 3bb4: 18a9c83a sub r20,r3,r2 - 3bb8: 0023883a mov r17,zero - 3bbc: 002d883a mov r22,zero - 3bc0: 003f7306 br 3990 <__divsf3+0x64> - 3bc4: 9809883a mov r4,r19 - 3bc8: 0004a200 call 4a20 <__clzsi2> - 3bcc: a087883a add r3,r20,r2 - 3bd0: 113ffec4 addi r4,r2,-5 - 3bd4: 1d001d84 addi r20,r3,118 - 3bd8: 9926983a sll r19,r19,r4 - 3bdc: 0007883a mov r3,zero - 3be0: 003f7906 br 39c8 <__divsf3+0x9c> - 3be4: 00c000c4 movi r3,3 - 3be8: 003f7706 br 39c8 <__divsf3+0x9c> - 3bec: 2025883a mov r18,r4 - 3bf0: 00bfffc4 movi r2,-1 - 3bf4: 0021883a mov r16,zero - 3bf8: 003fab06 br 3aa8 <__divsf3+0x17c> - 3bfc: 00c00044 movi r3,1 - 3c00: 1885c83a sub r2,r3,r2 - 3c04: 10c00708 cmpgei r3,r2,28 - 3c08: 183fa51e bne r3,zero,3aa0 <__divsf3+0x174> - 3c0c: a0c02784 addi r3,r20,158 - 3c10: 80c6983a sll r3,r16,r3 - 3c14: 8084d83a srl r2,r16,r2 - 3c18: 1820c03a cmpne r16,r3,zero - 3c1c: 1404b03a or r2,r2,r16 - 3c20: 10c001cc andi r3,r2,7 - 3c24: 18000426 beq r3,zero,3c38 <__divsf3+0x30c> - 3c28: 10c003cc andi r3,r2,15 - 3c2c: 18c00120 cmpeqi r3,r3,4 - 3c30: 1800011e bne r3,zero,3c38 <__divsf3+0x30c> - 3c34: 10800104 addi r2,r2,4 - 3c38: 10c1002c andhi r3,r2,1024 - 3c3c: 18003426 beq r3,zero,3d10 <__divsf3+0x3e4> - 3c40: 00800044 movi r2,1 - 3c44: 0021883a mov r16,zero - 3c48: 003f9706 br 3aa8 <__divsf3+0x17c> - 3c4c: 00bfffc4 movi r2,-1 - 3c50: 0021883a mov r16,zero - 3c54: 003f9406 br 3aa8 <__divsf3+0x17c> - 3c58: 04002034 movhi r16,128 - 3c5c: 0025883a mov r18,zero - 3c60: 843fffc4 addi r16,r16,-1 - 3c64: 00bfffc4 movi r2,-1 - 3c68: 003f8f06 br 3aa8 <__divsf3+0x17c> - 3c6c: 0027883a mov r19,zero - 3c70: 8080102c andhi r2,r16,64 - 3c74: 10000826 beq r2,zero,3c98 <__divsf3+0x36c> - 3c78: 9880102c andhi r2,r19,64 - 3c7c: 1000061e bne r2,zero,3c98 <__divsf3+0x36c> - 3c80: 00802034 movhi r2,128 - 3c84: 9c001034 orhi r16,r19,64 - 3c88: 10bfffc4 addi r2,r2,-1 - 3c8c: 80a0703a and r16,r16,r2 - 3c90: b825883a mov r18,r23 - 3c94: 003ff306 br 3c64 <__divsf3+0x338> - 3c98: 00802034 movhi r2,128 - 3c9c: 84001034 orhi r16,r16,64 - 3ca0: 10bfffc4 addi r2,r2,-1 - 3ca4: 80a0703a and r16,r16,r2 - 3ca8: 003fee06 br 3c64 <__divsf3+0x338> - 3cac: 8004917a slli r2,r16,5 - 3cb0: 980a917a slli r5,r19,5 - 3cb4: 1140122e bgeu r2,r5,3d00 <__divsf3+0x3d4> - 3cb8: a53fffc4 addi r20,r20,-1 - 3cbc: 010006c4 movi r4,27 - 3cc0: 0021883a mov r16,zero - 3cc4: 1007883a mov r3,r2 - 3cc8: 213fffc4 addi r4,r4,-1 - 3ccc: 1085883a add r2,r2,r2 - 3cd0: 8421883a add r16,r16,r16 - 3cd4: 18000116 blt r3,zero,3cdc <__divsf3+0x3b0> - 3cd8: 11400236 bltu r2,r5,3ce4 <__divsf3+0x3b8> - 3cdc: 1145c83a sub r2,r2,r5 - 3ce0: 84000054 ori r16,r16,1 - 3ce4: 203ff71e bne r4,zero,3cc4 <__divsf3+0x398> - 3ce8: 1004c03a cmpne r2,r2,zero - 3cec: 1420b03a or r16,r2,r16 - 3cf0: a0801fc4 addi r2,r20,127 - 3cf4: a825883a mov r18,r21 - 3cf8: 00bf5716 blt zero,r2,3a58 <__divsf3+0x12c> - 3cfc: 003fbf06 br 3bfc <__divsf3+0x2d0> - 3d00: 1145c83a sub r2,r2,r5 - 3d04: 01000684 movi r4,26 - 3d08: 04000044 movi r16,1 - 3d0c: 003fed06 br 3cc4 <__divsf3+0x398> - 3d10: 102091ba slli r16,r2,6 - 3d14: 0005883a mov r2,zero - 3d18: 8020d27a srli r16,r16,9 - 3d1c: 003f6206 br 3aa8 <__divsf3+0x17c> - -00003d20 <__eqsf2>: - 3d20: 200cd5fa srli r6,r4,23 - 3d24: 2806d5fa srli r3,r5,23 - 3d28: 00802034 movhi r2,128 - 3d2c: 31803fcc andi r6,r6,255 - 3d30: 10bfffc4 addi r2,r2,-1 - 3d34: 31c03fd8 cmpnei r7,r6,255 - 3d38: 2010d7fa srli r8,r4,31 - 3d3c: 2812d7fa srli r9,r5,31 - 3d40: 1108703a and r4,r2,r4 - 3d44: 18c03fcc andi r3,r3,255 - 3d48: 1144703a and r2,r2,r5 - 3d4c: 38000626 beq r7,zero,3d68 <__eqsf2+0x48> - 3d50: 19403fe0 cmpeqi r5,r3,255 - 3d54: 2800021e bne r5,zero,3d60 <__eqsf2+0x40> - 3d58: 30c0011e bne r6,r3,3d60 <__eqsf2+0x40> - 3d5c: 20800626 beq r4,r2,3d78 <__eqsf2+0x58> - 3d60: 00800044 movi r2,1 - 3d64: f800283a ret - 3d68: 203ffd1e bne r4,zero,3d60 <__eqsf2+0x40> - 3d6c: 18c03fd8 cmpnei r3,r3,255 - 3d70: 183ffb1e bne r3,zero,3d60 <__eqsf2+0x40> - 3d74: 103ffa1e bne r2,zero,3d60 <__eqsf2+0x40> - 3d78: 42400326 beq r8,r9,3d88 <__eqsf2+0x68> - 3d7c: 303ff81e bne r6,zero,3d60 <__eqsf2+0x40> - 3d80: 2004c03a cmpne r2,r4,zero - 3d84: f800283a ret - 3d88: 0005883a mov r2,zero - 3d8c: f800283a ret - -00003d90 <__gesf2>: - 3d90: 200cd5fa srli r6,r4,23 - 3d94: 280ed5fa srli r7,r5,23 - 3d98: 00c02034 movhi r3,128 - 3d9c: 31803fcc andi r6,r6,255 - 3da0: 18ffffc4 addi r3,r3,-1 - 3da4: 32003fd8 cmpnei r8,r6,255 - 3da8: 2012d7fa srli r9,r4,31 - 3dac: 2804d7fa srli r2,r5,31 - 3db0: 1908703a and r4,r3,r4 - 3db4: 1946703a and r3,r3,r5 - 3db8: 39403fcc andi r5,r7,255 - 3dbc: 40000826 beq r8,zero,3de0 <__gesf2+0x50> - 3dc0: 29c03fd8 cmpnei r7,r5,255 - 3dc4: 38000926 beq r7,zero,3dec <__gesf2+0x5c> - 3dc8: 3000121e bne r6,zero,3e14 <__gesf2+0x84> - 3dcc: 28000e1e bne r5,zero,3e08 <__gesf2+0x78> - 3dd0: 18000d1e bne r3,zero,3e08 <__gesf2+0x78> - 3dd4: 2000081e bne r4,zero,3df8 <__gesf2+0x68> - 3dd8: 0005883a mov r2,zero - 3ddc: f800283a ret - 3de0: 2000171e bne r4,zero,3e40 <__gesf2+0xb0> - 3de4: 29c03fe0 cmpeqi r7,r5,255 - 3de8: 38000a26 beq r7,zero,3e14 <__gesf2+0x84> - 3dec: 1800141e bne r3,zero,3e40 <__gesf2+0xb0> - 3df0: 30000526 beq r6,zero,3e08 <__gesf2+0x78> - 3df4: 48800a26 beq r9,r2,3e20 <__gesf2+0x90> - 3df8: 00800044 movi r2,1 - 3dfc: 48000426 beq r9,zero,3e10 <__gesf2+0x80> - 3e00: 00bfffc4 movi r2,-1 - 3e04: f800283a ret - 3e08: 203ffa1e bne r4,zero,3df4 <__gesf2+0x64> - 3e0c: 103ffc26 beq r2,zero,3e00 <__gesf2+0x70> - 3e10: f800283a ret - 3e14: 283ff71e bne r5,zero,3df4 <__gesf2+0x64> - 3e18: 183ff61e bne r3,zero,3df4 <__gesf2+0x64> - 3e1c: 003ff606 br 3df8 <__gesf2+0x68> - 3e20: 29800416 blt r5,r6,3e34 <__gesf2+0xa4> - 3e24: 317ff916 blt r6,r5,3e0c <__gesf2+0x7c> - 3e28: 19000236 bltu r3,r4,3e34 <__gesf2+0xa4> - 3e2c: 20ffea2e bgeu r4,r3,3dd8 <__gesf2+0x48> - 3e30: 003ff606 br 3e0c <__gesf2+0x7c> - 3e34: 103ff21e bne r2,zero,3e00 <__gesf2+0x70> - 3e38: 00800044 movi r2,1 - 3e3c: f800283a ret - 3e40: 00bfff84 movi r2,-2 - 3e44: f800283a ret - -00003e48 <__lesf2>: - 3e48: 200cd5fa srli r6,r4,23 - 3e4c: 280ed5fa srli r7,r5,23 - 3e50: 00c02034 movhi r3,128 - 3e54: 31803fcc andi r6,r6,255 - 3e58: 18ffffc4 addi r3,r3,-1 - 3e5c: 32003fd8 cmpnei r8,r6,255 - 3e60: 2012d7fa srli r9,r4,31 - 3e64: 2804d7fa srli r2,r5,31 - 3e68: 1908703a and r4,r3,r4 - 3e6c: 1946703a and r3,r3,r5 - 3e70: 39403fcc andi r5,r7,255 - 3e74: 40000826 beq r8,zero,3e98 <__lesf2+0x50> - 3e78: 29c03fd8 cmpnei r7,r5,255 - 3e7c: 38000926 beq r7,zero,3ea4 <__lesf2+0x5c> - 3e80: 3000181e bne r6,zero,3ee4 <__lesf2+0x9c> - 3e84: 2800091e bne r5,zero,3eac <__lesf2+0x64> - 3e88: 1800081e bne r3,zero,3eac <__lesf2+0x64> - 3e8c: 2000091e bne r4,zero,3eb4 <__lesf2+0x6c> - 3e90: 0005883a mov r2,zero - 3e94: f800283a ret - 3e98: 20000a1e bne r4,zero,3ec4 <__lesf2+0x7c> - 3e9c: 29c03fe0 cmpeqi r7,r5,255 - 3ea0: 38001026 beq r7,zero,3ee4 <__lesf2+0x9c> - 3ea4: 1800071e bne r3,zero,3ec4 <__lesf2+0x7c> - 3ea8: 3000011e bne r6,zero,3eb0 <__lesf2+0x68> - 3eac: 20000b26 beq r4,zero,3edc <__lesf2+0x94> - 3eb0: 48800626 beq r9,r2,3ecc <__lesf2+0x84> - 3eb4: 00800044 movi r2,1 - 3eb8: 48000926 beq r9,zero,3ee0 <__lesf2+0x98> - 3ebc: 00bfffc4 movi r2,-1 - 3ec0: f800283a ret - 3ec4: 00800084 movi r2,2 - 3ec8: f800283a ret - 3ecc: 29800816 blt r5,r6,3ef0 <__lesf2+0xa8> - 3ed0: 31400216 blt r6,r5,3edc <__lesf2+0x94> - 3ed4: 19000636 bltu r3,r4,3ef0 <__lesf2+0xa8> - 3ed8: 20ffed2e bgeu r4,r3,3e90 <__lesf2+0x48> - 3edc: 103ff726 beq r2,zero,3ebc <__lesf2+0x74> - 3ee0: f800283a ret - 3ee4: 283ff21e bne r5,zero,3eb0 <__lesf2+0x68> - 3ee8: 183ff11e bne r3,zero,3eb0 <__lesf2+0x68> - 3eec: 003ff106 br 3eb4 <__lesf2+0x6c> - 3ef0: 103ff21e bne r2,zero,3ebc <__lesf2+0x74> - 3ef4: 00800044 movi r2,1 - 3ef8: f800283a ret - -00003efc <__mulsf3>: - 3efc: defff704 addi sp,sp,-36 - 3f00: dc400215 stw r17,8(sp) - 3f04: 2022d5fa srli r17,r4,23 - 3f08: dc000115 stw r16,4(sp) - 3f0c: 04002034 movhi r16,128 - 3f10: dd000515 stw r20,20(sp) - 3f14: 843fffc4 addi r16,r16,-1 - 3f18: dfc00815 stw ra,32(sp) - 3f1c: dd800715 stw r22,28(sp) - 3f20: dd400615 stw r21,24(sp) - 3f24: dcc00415 stw r19,16(sp) - 3f28: dc800315 stw r18,12(sp) - 3f2c: 8c403fcc andi r17,r17,255 - 3f30: 2028d7fa srli r20,r4,31 - 3f34: 8120703a and r16,r16,r4 - 3f38: 88008026 beq r17,zero,413c <__mulsf3+0x240> - 3f3c: 88803fe0 cmpeqi r2,r17,255 - 3f40: 1000831e bne r2,zero,4150 <__mulsf3+0x254> - 3f44: 802090fa slli r16,r16,3 - 3f48: 8c7fe044 addi r17,r17,-127 - 3f4c: 002d883a mov r22,zero - 3f50: 84010034 orhi r16,r16,1024 - 3f54: 0027883a mov r19,zero - 3f58: 2804d5fa srli r2,r5,23 - 3f5c: 01002034 movhi r4,128 - 3f60: 213fffc4 addi r4,r4,-1 - 3f64: 10803fcc andi r2,r2,255 - 3f68: 282ad7fa srli r21,r5,31 - 3f6c: 2164703a and r18,r4,r5 - 3f70: 10006e26 beq r2,zero,412c <__mulsf3+0x230> - 3f74: 11003fe0 cmpeqi r4,r2,255 - 3f78: 20007a1e bne r4,zero,4164 <__mulsf3+0x268> - 3f7c: 900890fa slli r4,r18,3 - 3f80: 10bfe044 addi r2,r2,-127 - 3f84: 88a3883a add r17,r17,r2 - 3f88: 24810034 orhi r18,r4,1024 - 3f8c: 0009883a mov r4,zero - 3f90: b1800428 cmpgeui r6,r22,16 - 3f94: a544f03a xor r2,r20,r21 - 3f98: 89c00044 addi r7,r17,1 - 3f9c: 3000321e bne r6,zero,4068 <__mulsf3+0x16c> - 3fa0: b00690ba slli r3,r22,2 - 3fa4: 01800034 movhi r6,0 - 3fa8: 198d883a add r6,r3,r6 - 3fac: 30cfed17 ldw r3,16308(r6) - 3fb0: 1800683a jmp r3 - 3fb4: 00004068 cmpgeui zero,zero,257 - 3fb8: 00003ff8 rdprs zero,zero,255 - 3fbc: 00003ff8 rdprs zero,zero,255 - 3fc0: 00003ff4 movhi zero,255 - 3fc4: 00004000 call 400 - 3fc8: 00004000 call 400 - 3fcc: 000041f0 cmpltui zero,zero,263 - 3fd0: 00003ff4 movhi zero,255 - 3fd4: 00004000 call 400 - 3fd8: 000041f0 cmpltui zero,zero,263 - 3fdc: 00004000 call 400 - 3fe0: 00003ff4 movhi zero,255 - 3fe4: 00004178 rdprs zero,zero,261 - 3fe8: 00004178 rdprs zero,zero,261 - 3fec: 00004178 rdprs zero,zero,261 - 3ff0: 00004254 movui zero,265 - 3ff4: a805883a mov r2,r21 - 3ff8: 9021883a mov r16,r18 - 3ffc: 2027883a mov r19,r4 - 4000: 98c000a0 cmpeqi r3,r19,2 - 4004: 1800151e bne r3,zero,405c <__mulsf3+0x160> - 4008: 98c000e0 cmpeqi r3,r19,3 - 400c: 1800a31e bne r3,zero,429c <__mulsf3+0x3a0> - 4010: 98c00060 cmpeqi r3,r19,1 - 4014: 18003226 beq r3,zero,40e0 <__mulsf3+0x1e4> - 4018: 0007883a mov r3,zero - 401c: 0009883a mov r4,zero - 4020: 1c003fcc andi r16,r3,255 - 4024: 802095fa slli r16,r16,23 - 4028: 100497fa slli r2,r2,31 - 402c: 8120b03a or r16,r16,r4 - 4030: 8084b03a or r2,r16,r2 - 4034: dfc00817 ldw ra,32(sp) - 4038: dd800717 ldw r22,28(sp) - 403c: dd400617 ldw r21,24(sp) - 4040: dd000517 ldw r20,20(sp) - 4044: dcc00417 ldw r19,16(sp) - 4048: dc800317 ldw r18,12(sp) - 404c: dc400217 ldw r17,8(sp) - 4050: dc000117 ldw r16,4(sp) - 4054: dec00904 addi sp,sp,36 - 4058: f800283a ret - 405c: 00ffffc4 movi r3,-1 - 4060: 0009883a mov r4,zero - 4064: 003fee06 br 4020 <__mulsf3+0x124> - 4068: 9012d43a srli r9,r18,16 - 406c: 80ffffcc andi r3,r16,65535 - 4070: 8010d43a srli r8,r16,16 - 4074: 913fffcc andi r4,r18,65535 - 4078: 190b383a mul r5,r3,r4 - 407c: 4125383a mul r18,r8,r4 - 4080: 48cd383a mul r6,r9,r3 - 4084: 2806d43a srli r3,r5,16 - 4088: 4251383a mul r8,r8,r9 - 408c: 348d883a add r6,r6,r18 - 4090: 1987883a add r3,r3,r6 - 4094: 1c80022e bgeu r3,r18,40a0 <__mulsf3+0x1a4> - 4098: 01000074 movhi r4,1 - 409c: 4111883a add r8,r8,r4 - 40a0: 1808943a slli r4,r3,16 - 40a4: 1820d43a srli r16,r3,16 - 40a8: 297fffcc andi r5,r5,65535 - 40ac: 2149883a add r4,r4,r5 - 40b0: 200691ba slli r3,r4,6 - 40b4: 8221883a add r16,r16,r8 - 40b8: 802091ba slli r16,r16,6 - 40bc: 2008d6ba srli r4,r4,26 - 40c0: 1806c03a cmpne r3,r3,zero - 40c4: 8142002c andhi r5,r16,2048 - 40c8: 1908b03a or r4,r3,r4 - 40cc: 8120b03a or r16,r16,r4 - 40d0: 28007026 beq r5,zero,4294 <__mulsf3+0x398> - 40d4: 8006d07a srli r3,r16,1 - 40d8: 8400004c andi r16,r16,1 - 40dc: 1c20b03a or r16,r3,r16 - 40e0: 38c01fc4 addi r3,r7,127 - 40e4: 00c0470e bge zero,r3,4204 <__mulsf3+0x308> - 40e8: 810001cc andi r4,r16,7 - 40ec: 20000426 beq r4,zero,4100 <__mulsf3+0x204> - 40f0: 810003cc andi r4,r16,15 - 40f4: 21000120 cmpeqi r4,r4,4 - 40f8: 2000011e bne r4,zero,4100 <__mulsf3+0x204> - 40fc: 84000104 addi r16,r16,4 - 4100: 8102002c andhi r4,r16,2048 - 4104: 20000426 beq r4,zero,4118 <__mulsf3+0x21c> - 4108: 00fe0034 movhi r3,63488 - 410c: 18ffffc4 addi r3,r3,-1 - 4110: 80e0703a and r16,r16,r3 - 4114: 38c02004 addi r3,r7,128 - 4118: 19003fc8 cmpgei r4,r3,255 - 411c: 203fcf1e bne r4,zero,405c <__mulsf3+0x160> - 4120: 802091ba slli r16,r16,6 - 4124: 8008d27a srli r4,r16,9 - 4128: 003fbd06 br 4020 <__mulsf3+0x124> - 412c: 9000281e bne r18,zero,41d0 <__mulsf3+0x2d4> - 4130: b5800054 ori r22,r22,1 - 4134: 01000044 movi r4,1 - 4138: 003f9506 br 3f90 <__mulsf3+0x94> - 413c: 8000191e bne r16,zero,41a4 <__mulsf3+0x2a8> - 4140: 05800104 movi r22,4 - 4144: 0023883a mov r17,zero - 4148: 04c00044 movi r19,1 - 414c: 003f8206 br 3f58 <__mulsf3+0x5c> - 4150: 8000101e bne r16,zero,4194 <__mulsf3+0x298> - 4154: 05800204 movi r22,8 - 4158: 04403fc4 movi r17,255 - 415c: 04c00084 movi r19,2 - 4160: 003f7d06 br 3f58 <__mulsf3+0x5c> - 4164: 8c403fc4 addi r17,r17,255 - 4168: 9000071e bne r18,zero,4188 <__mulsf3+0x28c> - 416c: b5800094 ori r22,r22,2 - 4170: 01000084 movi r4,2 - 4174: 003f8606 br 3f90 <__mulsf3+0x94> - 4178: 98c000a0 cmpeqi r3,r19,2 - 417c: a005883a mov r2,r20 - 4180: 183fa126 beq r3,zero,4008 <__mulsf3+0x10c> - 4184: 003fb506 br 405c <__mulsf3+0x160> - 4188: b58000d4 ori r22,r22,3 - 418c: 010000c4 movi r4,3 - 4190: 003f7f06 br 3f90 <__mulsf3+0x94> - 4194: 05800304 movi r22,12 - 4198: 04403fc4 movi r17,255 - 419c: 04c000c4 movi r19,3 - 41a0: 003f6d06 br 3f58 <__mulsf3+0x5c> - 41a4: 8009883a mov r4,r16 - 41a8: d9400015 stw r5,0(sp) - 41ac: 0004a200 call 4a20 <__clzsi2> - 41b0: 10fffec4 addi r3,r2,-5 - 41b4: 047fe284 movi r17,-118 - 41b8: 80e0983a sll r16,r16,r3 - 41bc: d9400017 ldw r5,0(sp) - 41c0: 88a3c83a sub r17,r17,r2 - 41c4: 002d883a mov r22,zero - 41c8: 0027883a mov r19,zero - 41cc: 003f6206 br 3f58 <__mulsf3+0x5c> - 41d0: 9009883a mov r4,r18 - 41d4: 0004a200 call 4a20 <__clzsi2> - 41d8: 10fffec4 addi r3,r2,-5 - 41dc: 88a3c83a sub r17,r17,r2 - 41e0: 90e4983a sll r18,r18,r3 - 41e4: 8c7fe284 addi r17,r17,-118 - 41e8: 0009883a mov r4,zero - 41ec: 003f6806 br 3f90 <__mulsf3+0x94> - 41f0: 01002034 movhi r4,128 - 41f4: 0005883a mov r2,zero - 41f8: 213fffc4 addi r4,r4,-1 - 41fc: 00ffffc4 movi r3,-1 - 4200: 003f8706 br 4020 <__mulsf3+0x124> - 4204: 01000044 movi r4,1 - 4208: 20c7c83a sub r3,r4,r3 - 420c: 19000708 cmpgei r4,r3,28 - 4210: 203f811e bne r4,zero,4018 <__mulsf3+0x11c> - 4214: 39002784 addi r4,r7,158 - 4218: 8108983a sll r4,r16,r4 - 421c: 80e0d83a srl r16,r16,r3 - 4220: 2008c03a cmpne r4,r4,zero - 4224: 8120b03a or r16,r16,r4 - 4228: 80c001cc andi r3,r16,7 - 422c: 18000426 beq r3,zero,4240 <__mulsf3+0x344> - 4230: 80c003cc andi r3,r16,15 - 4234: 18c00120 cmpeqi r3,r3,4 - 4238: 1800011e bne r3,zero,4240 <__mulsf3+0x344> - 423c: 84000104 addi r16,r16,4 - 4240: 80c1002c andhi r3,r16,1024 - 4244: 183fb626 beq r3,zero,4120 <__mulsf3+0x224> - 4248: 00c00044 movi r3,1 - 424c: 0009883a mov r4,zero - 4250: 003f7306 br 4020 <__mulsf3+0x124> - 4254: 8080102c andhi r2,r16,64 - 4258: 10000826 beq r2,zero,427c <__mulsf3+0x380> - 425c: 9080102c andhi r2,r18,64 - 4260: 1000061e bne r2,zero,427c <__mulsf3+0x380> - 4264: 00802034 movhi r2,128 - 4268: 10bfffc4 addi r2,r2,-1 - 426c: 91001034 orhi r4,r18,64 - 4270: 2088703a and r4,r4,r2 - 4274: a805883a mov r2,r21 - 4278: 003fe006 br 41fc <__mulsf3+0x300> - 427c: 00802034 movhi r2,128 - 4280: 10bfffc4 addi r2,r2,-1 - 4284: 81001034 orhi r4,r16,64 - 4288: 2088703a and r4,r4,r2 - 428c: a005883a mov r2,r20 - 4290: 003fda06 br 41fc <__mulsf3+0x300> - 4294: 880f883a mov r7,r17 - 4298: 003f9106 br 40e0 <__mulsf3+0x1e4> - 429c: 00c02034 movhi r3,128 - 42a0: 81001034 orhi r4,r16,64 - 42a4: 18ffffc4 addi r3,r3,-1 - 42a8: 20c8703a and r4,r4,r3 - 42ac: 003fd306 br 41fc <__mulsf3+0x300> - -000042b0 <__subsf3>: - 42b0: 2804d5fa srli r2,r5,23 - 42b4: 2006d5fa srli r3,r4,23 - 42b8: 200cd7fa srli r6,r4,31 - 42bc: 01c02034 movhi r7,128 - 42c0: defffc04 addi sp,sp,-16 - 42c4: 39ffffc4 addi r7,r7,-1 - 42c8: 12803fcc andi r10,r2,255 - 42cc: 3908703a and r4,r7,r4 - 42d0: dc800215 stw r18,8(sp) - 42d4: 394e703a and r7,r7,r5 - 42d8: dc400115 stw r17,4(sp) - 42dc: 1c803fcc andi r18,r3,255 - 42e0: dfc00315 stw ra,12(sp) - 42e4: dc000015 stw r16,0(sp) - 42e8: 50803fd8 cmpnei r2,r10,255 - 42ec: 3023883a mov r17,r6 - 42f0: 201090fa slli r8,r4,3 - 42f4: 280ad7fa srli r5,r5,31 - 42f8: 381290fa slli r9,r7,3 - 42fc: 2019883a mov r12,r4 - 4300: 31803fcc andi r6,r6,255 - 4304: 9297c83a sub r11,r18,r10 - 4308: 10003f26 beq r2,zero,4408 <__subsf3+0x158> - 430c: 2880005c xori r2,r5,1 - 4310: 30804526 beq r6,r2,4428 <__subsf3+0x178> - 4314: 02c0310e bge zero,r11,43dc <__subsf3+0x12c> - 4318: 50003f1e bne r10,zero,4418 <__subsf3+0x168> - 431c: 48009526 beq r9,zero,4574 <__subsf3+0x2c4> - 4320: 58bfffc4 addi r2,r11,-1 - 4324: 1000de26 beq r2,zero,46a0 <__subsf3+0x3f0> - 4328: 59003fe0 cmpeqi r4,r11,255 - 432c: 20007d1e bne r4,zero,4524 <__subsf3+0x274> - 4330: 1017883a mov r11,r2 - 4334: 58800710 cmplti r2,r11,28 - 4338: 10009a1e bne r2,zero,45a4 <__subsf3+0x2f4> - 433c: 01000044 movi r4,1 - 4340: 4109c83a sub r4,r8,r4 - 4344: 2081002c andhi r2,r4,1024 - 4348: 10006a26 beq r2,zero,44f4 <__subsf3+0x244> - 434c: 04010034 movhi r16,1024 - 4350: 843fffc4 addi r16,r16,-1 - 4354: 2420703a and r16,r4,r16 - 4358: 8009883a mov r4,r16 - 435c: 0004a200 call 4a20 <__clzsi2> - 4360: 10bffec4 addi r2,r2,-5 - 4364: 8088983a sll r4,r16,r2 - 4368: 1480840e bge r2,r18,457c <__subsf3+0x2cc> - 436c: 00ff0034 movhi r3,64512 - 4370: 18ffffc4 addi r3,r3,-1 - 4374: 90a5c83a sub r18,r18,r2 - 4378: 20c8703a and r4,r4,r3 - 437c: 208001cc andi r2,r4,7 - 4380: 10000426 beq r2,zero,4394 <__subsf3+0xe4> - 4384: 208003cc andi r2,r4,15 - 4388: 10800120 cmpeqi r2,r2,4 - 438c: 1000011e bne r2,zero,4394 <__subsf3+0xe4> - 4390: 21000104 addi r4,r4,4 - 4394: 2081002c andhi r2,r4,1024 - 4398: 10005826 beq r2,zero,44fc <__subsf3+0x24c> - 439c: 90c00044 addi r3,r18,1 - 43a0: 18803fe0 cmpeqi r2,r3,255 - 43a4: 1000481e bne r2,zero,44c8 <__subsf3+0x218> - 43a8: 200891ba slli r4,r4,6 - 43ac: 2008d27a srli r4,r4,9 - 43b0: 18803fcc andi r2,r3,255 - 43b4: 100495fa slli r2,r2,23 - 43b8: 880697fa slli r3,r17,31 - 43bc: 1108b03a or r4,r2,r4 - 43c0: 20c4b03a or r2,r4,r3 - 43c4: dfc00317 ldw ra,12(sp) - 43c8: dc800217 ldw r18,8(sp) - 43cc: dc400117 ldw r17,4(sp) - 43d0: dc000017 ldw r16,0(sp) - 43d4: dec00404 addi sp,sp,16 - 43d8: f800283a ret - 43dc: 58002726 beq r11,zero,447c <__subsf3+0x1cc> - 43e0: 5497c83a sub r11,r10,r18 - 43e4: 1023883a mov r17,r2 - 43e8: 9000751e bne r18,zero,45c0 <__subsf3+0x310> - 43ec: 40006026 beq r8,zero,4570 <__subsf3+0x2c0> - 43f0: 58bfffc4 addi r2,r11,-1 - 43f4: 1000cb26 beq r2,zero,4724 <__subsf3+0x474> - 43f8: 5ac03fe0 cmpeqi r11,r11,255 - 43fc: 5800481e bne r11,zero,4520 <__subsf3+0x270> - 4400: 1017883a mov r11,r2 - 4404: 00007106 br 45cc <__subsf3+0x31c> - 4408: 483fc026 beq r9,zero,430c <__subsf3+0x5c> - 440c: 28803fcc andi r2,r5,255 - 4410: 31404b26 beq r6,r5,4540 <__subsf3+0x290> - 4414: 02fff10e bge zero,r11,43dc <__subsf3+0x12c> - 4418: 90803fe0 cmpeqi r2,r18,255 - 441c: 1000411e bne r2,zero,4524 <__subsf3+0x274> - 4420: 4a410034 orhi r9,r9,1024 - 4424: 003fc306 br 4334 <__subsf3+0x84> - 4428: 02c0450e bge zero,r11,4540 <__subsf3+0x290> - 442c: 50001f26 beq r10,zero,44ac <__subsf3+0x1fc> - 4430: 90803fe0 cmpeqi r2,r18,255 - 4434: 10003b1e bne r2,zero,4524 <__subsf3+0x274> - 4438: 4a410034 orhi r9,r9,1024 - 443c: 58800710 cmplti r2,r11,28 - 4440: 1000701e bne r2,zero,4604 <__subsf3+0x354> - 4444: 01000044 movi r4,1 - 4448: 2209883a add r4,r4,r8 - 444c: 2081002c andhi r2,r4,1024 - 4450: 10002826 beq r2,zero,44f4 <__subsf3+0x244> - 4454: 94800044 addi r18,r18,1 - 4458: 90803fe0 cmpeqi r2,r18,255 - 445c: 10001a1e bne r2,zero,44c8 <__subsf3+0x218> - 4460: 2004d07a srli r2,r4,1 - 4464: 00df8034 movhi r3,32256 - 4468: 18ffffc4 addi r3,r3,-1 - 446c: 2100004c andi r4,r4,1 - 4470: 10c4703a and r2,r2,r3 - 4474: 1108b03a or r4,r2,r4 - 4478: 003fc006 br 437c <__subsf3+0xcc> - 447c: 90c00044 addi r3,r18,1 - 4480: 18c03f8c andi r3,r3,254 - 4484: 1800571e bne r3,zero,45e4 <__subsf3+0x334> - 4488: 90007a1e bne r18,zero,4674 <__subsf3+0x3c4> - 448c: 4000a126 beq r8,zero,4714 <__subsf3+0x464> - 4490: 48008d26 beq r9,zero,46c8 <__subsf3+0x418> - 4494: 4249c83a sub r4,r8,r9 - 4498: 20c1002c andhi r3,r4,1024 - 449c: 1800a726 beq r3,zero,473c <__subsf3+0x48c> - 44a0: 4a09c83a sub r4,r9,r8 - 44a4: 1023883a mov r17,r2 - 44a8: 003fb406 br 437c <__subsf3+0xcc> - 44ac: 48003126 beq r9,zero,4574 <__subsf3+0x2c4> - 44b0: 58bfffc4 addi r2,r11,-1 - 44b4: 10007526 beq r2,zero,468c <__subsf3+0x3dc> - 44b8: 5ac03fe0 cmpeqi r11,r11,255 - 44bc: 5800191e bne r11,zero,4524 <__subsf3+0x274> - 44c0: 1017883a mov r11,r2 - 44c4: 003fdd06 br 443c <__subsf3+0x18c> - 44c8: 00ffffc4 movi r3,-1 - 44cc: 0009883a mov r4,zero - 44d0: 003fb706 br 43b0 <__subsf3+0x100> - 44d4: 90c00044 addi r3,r18,1 - 44d8: 19403f8c andi r5,r3,254 - 44dc: 28005026 beq r5,zero,4620 <__subsf3+0x370> - 44e0: 18803fe0 cmpeqi r2,r3,255 - 44e4: 103ff81e bne r2,zero,44c8 <__subsf3+0x218> - 44e8: 4249883a add r4,r8,r9 - 44ec: 2008d07a srli r4,r4,1 - 44f0: 1825883a mov r18,r3 - 44f4: 208001cc andi r2,r4,7 - 44f8: 103fa21e bne r2,zero,4384 <__subsf3+0xd4> - 44fc: 2018d0fa srli r12,r4,3 - 4500: 90803fe0 cmpeqi r2,r18,255 - 4504: 1000071e bne r2,zero,4524 <__subsf3+0x274> - 4508: 01002034 movhi r4,128 - 450c: 213fffc4 addi r4,r4,-1 - 4510: 6108703a and r4,r12,r4 - 4514: 9007883a mov r3,r18 - 4518: 003fa506 br 43b0 <__subsf3+0x100> - 451c: 40006c1e bne r8,zero,46d0 <__subsf3+0x420> - 4520: 3819883a mov r12,r7 - 4524: 603fe826 beq r12,zero,44c8 <__subsf3+0x218> - 4528: 00802034 movhi r2,128 - 452c: 61001034 orhi r4,r12,64 - 4530: 10bfffc4 addi r2,r2,-1 - 4534: 2088703a and r4,r4,r2 - 4538: 00ffffc4 movi r3,-1 - 453c: 003f9c06 br 43b0 <__subsf3+0x100> - 4540: 583fe426 beq r11,zero,44d4 <__subsf3+0x224> - 4544: 5497c83a sub r11,r10,r18 - 4548: 90004026 beq r18,zero,464c <__subsf3+0x39c> - 454c: 50803fe0 cmpeqi r2,r10,255 - 4550: 103ff31e bne r2,zero,4520 <__subsf3+0x270> - 4554: 42010034 orhi r8,r8,1024 - 4558: 58800710 cmplti r2,r11,28 - 455c: 1000641e bne r2,zero,46f0 <__subsf3+0x440> - 4560: 01000044 movi r4,1 - 4564: 2249883a add r4,r4,r9 - 4568: 5025883a mov r18,r10 - 456c: 003fb706 br 444c <__subsf3+0x19c> - 4570: 3819883a mov r12,r7 - 4574: 5825883a mov r18,r11 - 4578: 003fe106 br 4500 <__subsf3+0x250> - 457c: 1485c83a sub r2,r2,r18 - 4580: 14000044 addi r16,r2,1 - 4584: 00800804 movi r2,32 - 4588: 1405c83a sub r2,r2,r16 - 458c: 2084983a sll r2,r4,r2 - 4590: 2408d83a srl r4,r4,r16 - 4594: 0025883a mov r18,zero - 4598: 1004c03a cmpne r2,r2,zero - 459c: 1108b03a or r4,r2,r4 - 45a0: 003f7606 br 437c <__subsf3+0xcc> - 45a4: 01000804 movi r4,32 - 45a8: 22c9c83a sub r4,r4,r11 - 45ac: 4908983a sll r4,r9,r4 - 45b0: 4ad2d83a srl r9,r9,r11 - 45b4: 2008c03a cmpne r4,r4,zero - 45b8: 2248b03a or r4,r4,r9 - 45bc: 003f6006 br 4340 <__subsf3+0x90> - 45c0: 50803fe0 cmpeqi r2,r10,255 - 45c4: 103fd61e bne r2,zero,4520 <__subsf3+0x270> - 45c8: 42010034 orhi r8,r8,1024 - 45cc: 58800710 cmplti r2,r11,28 - 45d0: 1000361e bne r2,zero,46ac <__subsf3+0x3fc> - 45d4: 01000044 movi r4,1 - 45d8: 4909c83a sub r4,r9,r4 - 45dc: 5025883a mov r18,r10 - 45e0: 003f5806 br 4344 <__subsf3+0x94> - 45e4: 4261c83a sub r16,r8,r9 - 45e8: 80c1002c andhi r3,r16,1024 - 45ec: 18001e1e bne r3,zero,4668 <__subsf3+0x3b8> - 45f0: 803f591e bne r16,zero,4358 <__subsf3+0xa8> - 45f4: 0023883a mov r17,zero - 45f8: 0007883a mov r3,zero - 45fc: 0009883a mov r4,zero - 4600: 003f6b06 br 43b0 <__subsf3+0x100> - 4604: 01000804 movi r4,32 - 4608: 22c9c83a sub r4,r4,r11 - 460c: 4908983a sll r4,r9,r4 - 4610: 4ad2d83a srl r9,r9,r11 - 4614: 2008c03a cmpne r4,r4,zero - 4618: 2248b03a or r4,r4,r9 - 461c: 003f8a06 br 4448 <__subsf3+0x198> - 4620: 903fbe1e bne r18,zero,451c <__subsf3+0x26c> - 4624: 40004226 beq r8,zero,4730 <__subsf3+0x480> - 4628: 48002726 beq r9,zero,46c8 <__subsf3+0x418> - 462c: 4249883a add r4,r8,r9 - 4630: 2081002c andhi r2,r4,1024 - 4634: 103faf26 beq r2,zero,44f4 <__subsf3+0x244> - 4638: 00bf0034 movhi r2,64512 - 463c: 10bfffc4 addi r2,r2,-1 - 4640: 2088703a and r4,r4,r2 - 4644: 04800044 movi r18,1 - 4648: 003faa06 br 44f4 <__subsf3+0x244> - 464c: 403fc826 beq r8,zero,4570 <__subsf3+0x2c0> - 4650: 58bfffc4 addi r2,r11,-1 - 4654: 10000d26 beq r2,zero,468c <__subsf3+0x3dc> - 4658: 5ac03fe0 cmpeqi r11,r11,255 - 465c: 583fb01e bne r11,zero,4520 <__subsf3+0x270> - 4660: 1017883a mov r11,r2 - 4664: 003fbc06 br 4558 <__subsf3+0x2a8> - 4668: 4a21c83a sub r16,r9,r8 - 466c: 1023883a mov r17,r2 - 4670: 003f3906 br 4358 <__subsf3+0xa8> - 4674: 4000161e bne r8,zero,46d0 <__subsf3+0x420> - 4678: 48001a1e bne r9,zero,46e4 <__subsf3+0x434> - 467c: 01002034 movhi r4,128 - 4680: 0023883a mov r17,zero - 4684: 213fffc4 addi r4,r4,-1 - 4688: 003fab06 br 4538 <__subsf3+0x288> - 468c: 4249883a add r4,r8,r9 - 4690: 2081002c andhi r2,r4,1024 - 4694: 10001d26 beq r2,zero,470c <__subsf3+0x45c> - 4698: 04800084 movi r18,2 - 469c: 003f7006 br 4460 <__subsf3+0x1b0> - 46a0: 4249c83a sub r4,r8,r9 - 46a4: 04800044 movi r18,1 - 46a8: 003f2606 br 4344 <__subsf3+0x94> - 46ac: 00c00804 movi r3,32 - 46b0: 1ac7c83a sub r3,r3,r11 - 46b4: 40c6983a sll r3,r8,r3 - 46b8: 42d0d83a srl r8,r8,r11 - 46bc: 1808c03a cmpne r4,r3,zero - 46c0: 2208b03a or r4,r4,r8 - 46c4: 003fc406 br 45d8 <__subsf3+0x328> - 46c8: 0007883a mov r3,zero - 46cc: 003f3806 br 43b0 <__subsf3+0x100> - 46d0: 483f9426 beq r9,zero,4524 <__subsf3+0x274> - 46d4: 2100102c andhi r4,r4,64 - 46d8: 203f9226 beq r4,zero,4524 <__subsf3+0x274> - 46dc: 38c0102c andhi r3,r7,64 - 46e0: 183f901e bne r3,zero,4524 <__subsf3+0x274> - 46e4: 1023883a mov r17,r2 - 46e8: 3819883a mov r12,r7 - 46ec: 003f8d06 br 4524 <__subsf3+0x274> - 46f0: 01000804 movi r4,32 - 46f4: 22c9c83a sub r4,r4,r11 - 46f8: 4106983a sll r3,r8,r4 - 46fc: 42d0d83a srl r8,r8,r11 - 4700: 1808c03a cmpne r4,r3,zero - 4704: 2208b03a or r4,r4,r8 - 4708: 003f9606 br 4564 <__subsf3+0x2b4> - 470c: 04800044 movi r18,1 - 4710: 003f7806 br 44f4 <__subsf3+0x244> - 4714: 483fb726 beq r9,zero,45f4 <__subsf3+0x344> - 4718: 1023883a mov r17,r2 - 471c: 3809883a mov r4,r7 - 4720: 003f2306 br 43b0 <__subsf3+0x100> - 4724: 4a09c83a sub r4,r9,r8 - 4728: 04800044 movi r18,1 - 472c: 003f0506 br 4344 <__subsf3+0x94> - 4730: 3809883a mov r4,r7 - 4734: 0007883a mov r3,zero - 4738: 003f1d06 br 43b0 <__subsf3+0x100> - 473c: 203fad26 beq r4,zero,45f4 <__subsf3+0x344> - 4740: 003f6c06 br 44f4 <__subsf3+0x244> - -00004744 <__unordsf2>: - 4744: 2006d5fa srli r3,r4,23 - 4748: 00802034 movhi r2,128 - 474c: 10bfffc4 addi r2,r2,-1 - 4750: 18c03fcc andi r3,r3,255 - 4754: 18c03fd8 cmpnei r3,r3,255 - 4758: 1108703a and r4,r2,r4 - 475c: 280cd5fa srli r6,r5,23 - 4760: 1144703a and r2,r2,r5 - 4764: 18000526 beq r3,zero,477c <__unordsf2+0x38> - 4768: 31803fcc andi r6,r6,255 - 476c: 31803fd8 cmpnei r6,r6,255 - 4770: 30000526 beq r6,zero,4788 <__unordsf2+0x44> - 4774: 0005883a mov r2,zero + 399c: 2249d83a sra r4,r4,r9 + 39a0: 2906703a and r3,r5,r4 + 39a4: 1886b03a or r3,r3,r2 + 39a8: 18002826 beq r3,zero,3a4c + 39ac: 2008d07a srli r4,r4,1 + 39b0: 2904703a and r2,r5,r4 + 39b4: 308cb03a or r6,r6,r2 + 39b8: 30000826 beq r6,zero,39dc + 39bc: 488004e0 cmpeqi r2,r9,19 + 39c0: 1000581e bne r2,zero,3b24 + 39c4: 000d883a mov r6,zero + 39c8: 01c00134 movhi r7,4 + 39cc: 3a47d83a sra r3,r7,r9 + 39d0: 0108303a nor r4,zero,r4 + 39d4: 2408703a and r4,r4,r16 + 39d8: 20ceb03a or r7,r4,r3 + 39dc: 580890fa slli r4,r11,3 + 39e0: 00800074 movhi r2,1 + 39e4: 10ae7b04 addi r2,r2,-17940 + 39e8: 1105883a add r2,r2,r4 + 39ec: 14400017 ldw r17,0(r2) + 39f0: 14000117 ldw r16,4(r2) + 39f4: 8809883a mov r4,r17 + 39f8: 800b883a mov r5,r16 + 39fc: 00045b80 call 45b8 <__adddf3> + 3a00: d8800015 stw r2,0(sp) + 3a04: d8c00115 stw r3,4(sp) + 3a08: d9000017 ldw r4,0(sp) + 3a0c: d9400117 ldw r5,4(sp) + 3a10: 880d883a mov r6,r17 + 3a14: 800f883a mov r7,r16 + 3a18: 0005fc80 call 5fc8 <__subdf3> + 3a1c: 00000c06 br 3a50 + 3a20: 04600034 movhi r17,32768 + 3a24: 8c7fffc4 addi r17,r17,-1 + 3a28: 2c46703a and r3,r5,r17 + 3a2c: 1906b03a or r3,r3,r4 + 3a30: 18001c1e bne r3,zero,3aa4 + 3a34: 8007883a mov r3,r16 + 3a38: 00000506 br 3a50 + 3a3c: 48c00d10 cmplti r3,r9,52 + 3a40: 18000a1e bne r3,zero,3a6c + 3a44: 4a410018 cmpnei r9,r9,1024 + 3a48: 48003426 beq r9,zero,3b1c + 3a4c: 3807883a mov r3,r7 + 3a50: dfc00617 ldw ra,24(sp) + 3a54: dcc00517 ldw r19,20(sp) + 3a58: dc800417 ldw r18,16(sp) + 3a5c: dc400317 ldw r17,12(sp) + 3a60: dc000217 ldw r16,8(sp) + 3a64: dec00704 addi sp,sp,28 + 3a68: f800283a ret + 3a6c: 423efb44 addi r8,r8,-1043 + 3a70: 00ffffc4 movi r3,-1 + 3a74: 1a06d83a srl r3,r3,r8 + 3a78: 20c8703a and r4,r4,r3 + 3a7c: 203fed26 beq r4,zero,3a34 + 3a80: 1806d07a srli r3,r3,1 + 3a84: 10c4703a and r2,r2,r3 + 3a88: 103fd426 beq r2,zero,39dc + 3a8c: 00900034 movhi r2,16384 + 3a90: 1211d83a sra r8,r2,r8 + 3a94: 00c6303a nor r3,zero,r3 + 3a98: 1986703a and r3,r3,r6 + 3a9c: 1a0cb03a or r6,r3,r8 + 3aa0: 003fce06 br 39dc + 3aa4: 00c00434 movhi r3,16 + 3aa8: 18ffffc4 addi r3,r3,-1 + 3aac: 28c6703a and r3,r5,r3 + 3ab0: 1906b03a or r3,r3,r4 + 3ab4: 580890fa slli r4,r11,3 + 3ab8: 00cfc83a sub r7,zero,r3 + 3abc: 01400074 movhi r5,1 + 3ac0: 38c6b03a or r3,r7,r3 + 3ac4: 296e7b04 addi r5,r5,-17940 + 3ac8: 290b883a add r5,r5,r4 + 3acc: 1806d33a srli r3,r3,12 + 3ad0: 2cc00017 ldw r19,0(r5) + 3ad4: 2c800117 ldw r18,4(r5) + 3ad8: 18c0022c andhi r3,r3,8 + 3adc: 81ffffac andhi r7,r16,65534 + 3ae0: 19ceb03a or r7,r3,r7 + 3ae4: 9809883a mov r4,r19 + 3ae8: 900b883a mov r5,r18 + 3aec: 00045b80 call 45b8 <__adddf3> + 3af0: d8800015 stw r2,0(sp) + 3af4: d8c00115 stw r3,4(sp) + 3af8: d9000017 ldw r4,0(sp) + 3afc: d9400117 ldw r5,4(sp) + 3b00: 900f883a mov r7,r18 + 3b04: 980d883a mov r6,r19 + 3b08: 0005fc80 call 5fc8 <__subdf3> + 3b0c: 1c4e703a and r7,r3,r17 + 3b10: 80e0002c andhi r3,r16,32768 + 3b14: 38c6b03a or r3,r7,r3 + 3b18: 003fcd06 br 3a50 + 3b1c: 00045b80 call 45b8 <__adddf3> + 3b20: 003fcb06 br 3a50 + 3b24: 01a00034 movhi r6,32768 + 3b28: 003fa706 br 39c8 + +00003b2c : + 3b2c: 2807d53a srai r3,r5,20 + 3b30: defffe04 addi sp,sp,-8 + 3b34: dc000015 stw r16,0(sp) + 3b38: dfc00115 stw ra,4(sp) + 3b3c: 18c1ffcc andi r3,r3,2047 + 3b40: 280f883a mov r7,r5 + 3b44: 2005883a mov r2,r4 + 3b48: 3021883a mov r16,r6 + 3b4c: 1800241e bne r3,zero,3be0 + 3b50: 00e00034 movhi r3,32768 + 3b54: 18ffffc4 addi r3,r3,-1 + 3b58: 28c6703a and r3,r5,r3 + 3b5c: 1906b03a or r3,r3,r4 + 3b60: 18003626 beq r3,zero,3c3c + 3b64: 000d883a mov r6,zero + 3b68: 01d0d434 movhi r7,17232 + 3b6c: 00059540 call 5954 <__muldf3> + 3b70: 01bffff4 movhi r6,65535 + 3b74: 318f2c04 addi r6,r6,15536 + 3b78: 1009883a mov r4,r2 + 3b7c: 180f883a mov r7,r3 + 3b80: 81804d16 blt r16,r6,3cb8 + 3b84: 1807d53a srai r3,r3,20 + 3b88: 3811883a mov r8,r7 + 3b8c: 18c1ffcc andi r3,r3,2047 + 3b90: 18fff284 addi r3,r3,-54 + 3b94: 80c7883a add r3,r16,r3 + 3b98: 1901ffd0 cmplti r4,r3,2047 + 3b9c: 20001926 beq r4,zero,3c04 + 3ba0: 00c03c16 blt zero,r3,3c94 + 3ba4: 193ff2c8 cmpgei r4,r3,-53 + 3ba8: 20002c1e bne r4,zero,3c5c + 3bac: 00b0d414 movui r2,50000 + 3bb0: 14001416 blt r2,r16,3c04 + 3bb4: 0130be74 movhi r4,49913 + 3bb8: 01406974 movhi r5,421 + 3bbc: 213cd644 addi r4,r4,-3239 + 3bc0: 295b87c4 addi r5,r5,28191 + 3bc4: 38004616 blt r7,zero,3ce0 + 3bc8: 01b0be74 movhi r6,49913 + 3bcc: 01c06974 movhi r7,421 + 3bd0: 31bcd644 addi r6,r6,-3239 + 3bd4: 39db87c4 addi r7,r7,28191 + 3bd8: 00059540 call 5954 <__muldf3> + 3bdc: 00001306 br 3c2c + 3be0: 1981ffd8 cmpnei r6,r3,2047 + 3be4: 2811883a mov r8,r5 + 3be8: 303fea1e bne r6,zero,3b94 + 3bec: 200d883a mov r6,r4 + 3bf0: 00045b80 call 45b8 <__adddf3> + 3bf4: dfc00117 ldw ra,4(sp) + 3bf8: dc000017 ldw r16,0(sp) + 3bfc: dec00204 addi sp,sp,8 + 3c00: f800283a ret + 3c04: 01220034 movhi r4,34816 + 3c08: 015f8e34 movhi r5,32312 + 3c0c: 211d6704 addi r4,r4,30108 + 3c10: 29790f04 addi r5,r5,-7108 + 3c14: 38000e16 blt r7,zero,3c50 + 3c18: 01a20034 movhi r6,34816 + 3c1c: 01df8e34 movhi r7,32312 + 3c20: 319d6704 addi r6,r6,30108 + 3c24: 39f90f04 addi r7,r7,-7108 + 3c28: 00059540 call 5954 <__muldf3> + 3c2c: dfc00117 ldw ra,4(sp) + 3c30: dc000017 ldw r16,0(sp) + 3c34: dec00204 addi sp,sp,8 + 3c38: f800283a ret + 3c3c: 2807883a mov r3,r5 + 3c40: dfc00117 ldw ra,4(sp) + 3c44: dc000017 ldw r16,0(sp) + 3c48: dec00204 addi sp,sp,8 + 3c4c: f800283a ret + 3c50: 017f8e34 movhi r5,65080 + 3c54: 29790f04 addi r5,r5,-7108 + 3c58: 003fef06 br 3c18 + 3c5c: 18c00d84 addi r3,r3,54 + 3c60: 1806953a slli r3,r3,20 + 3c64: 01600434 movhi r5,32784 + 3c68: 297fffc4 addi r5,r5,-1 + 3c6c: 414a703a and r5,r8,r5 + 3c70: 000d883a mov r6,zero + 3c74: 01cf2434 movhi r7,15504 + 3c78: 1009883a mov r4,r2 + 3c7c: 194ab03a or r5,r3,r5 + 3c80: 00059540 call 5954 <__muldf3> + 3c84: dfc00117 ldw ra,4(sp) + 3c88: dc000017 ldw r16,0(sp) + 3c8c: dec00204 addi sp,sp,8 + 3c90: f800283a ret + 3c94: 1806953a slli r3,r3,20 + 3c98: 01e00434 movhi r7,32784 + 3c9c: 39ffffc4 addi r7,r7,-1 + 3ca0: 41ce703a and r7,r8,r7 + 3ca4: 38c6b03a or r3,r7,r3 + 3ca8: dfc00117 ldw ra,4(sp) + 3cac: dc000017 ldw r16,0(sp) + 3cb0: dec00204 addi sp,sp,8 + 3cb4: f800283a ret + 3cb8: 01b0be74 movhi r6,49913 + 3cbc: 01c06974 movhi r7,421 + 3cc0: 31bcd644 addi r6,r6,-3239 + 3cc4: 39db87c4 addi r7,r7,28191 + 3cc8: 180b883a mov r5,r3 + 3ccc: 00059540 call 5954 <__muldf3> + 3cd0: dfc00117 ldw ra,4(sp) + 3cd4: dc000017 ldw r16,0(sp) + 3cd8: dec00204 addi sp,sp,8 + 3cdc: f800283a ret + 3ce0: 01606974 movhi r5,33189 + 3ce4: 295b87c4 addi r5,r5,28191 + 3ce8: 003fb706 br 3bc8 + +00003cec <__muldi3>: + 3cec: 20bfffcc andi r2,r4,65535 + 3cf0: 2010d43a srli r8,r4,16 + 3cf4: 3016d43a srli r11,r6,16 + 3cf8: 327fffcc andi r9,r6,65535 + 3cfc: 1255383a mul r10,r2,r9 + 3d00: 12c7383a mul r3,r2,r11 + 3d04: 4253383a mul r9,r8,r9 + 3d08: 5004d43a srli r2,r10,16 + 3d0c: 42d1383a mul r8,r8,r11 + 3d10: 1a47883a add r3,r3,r9 + 3d14: 10c5883a add r2,r2,r3 + 3d18: 1240022e bgeu r2,r9,3d24 <__muldi3+0x38> + 3d1c: 00c00074 movhi r3,1 + 3d20: 40d1883a add r8,r8,r3 + 3d24: 1006d43a srli r3,r2,16 + 3d28: 21c9383a mul r4,r4,r7 + 3d2c: 314d383a mul r6,r6,r5 + 3d30: 1004943a slli r2,r2,16 + 3d34: 1a11883a add r8,r3,r8 + 3d38: 52bfffcc andi r10,r10,65535 + 3d3c: 2209883a add r4,r4,r8 + 3d40: 1285883a add r2,r2,r10 + 3d44: 2187883a add r3,r4,r6 + 3d48: f800283a ret + +00003d4c <__fixunsdfsi>: + 3d4c: defffd04 addi sp,sp,-12 + 3d50: 000d883a mov r6,zero + 3d54: 01d07834 movhi r7,16864 + 3d58: dc400115 stw r17,4(sp) + 3d5c: dc000015 stw r16,0(sp) + 3d60: dfc00215 stw ra,8(sp) + 3d64: 2023883a mov r17,r4 + 3d68: 2821883a mov r16,r5 + 3d6c: 00057840 call 5784 <__gedf2> + 3d70: 1000080e bge r2,zero,3d94 <__fixunsdfsi+0x48> + 3d74: 8809883a mov r4,r17 + 3d78: 800b883a mov r5,r16 + 3d7c: 00068d00 call 68d0 <__fixdfsi> + 3d80: dfc00217 ldw ra,8(sp) + 3d84: dc400117 ldw r17,4(sp) + 3d88: dc000017 ldw r16,0(sp) + 3d8c: dec00304 addi sp,sp,12 + 3d90: f800283a ret + 3d94: 000d883a mov r6,zero + 3d98: 01d07834 movhi r7,16864 + 3d9c: 8809883a mov r4,r17 + 3da0: 800b883a mov r5,r16 + 3da4: 0005fc80 call 5fc8 <__subdf3> + 3da8: 180b883a mov r5,r3 + 3dac: 1009883a mov r4,r2 + 3db0: 00068d00 call 68d0 <__fixdfsi> + 3db4: 00e00034 movhi r3,32768 + 3db8: 10c5883a add r2,r2,r3 + 3dbc: 003ff006 br 3d80 <__fixunsdfsi+0x34> + +00003dc0 <__udivdi3>: + 3dc0: defff504 addi sp,sp,-44 + 3dc4: dcc00415 stw r19,16(sp) + 3dc8: dc000115 stw r16,4(sp) + 3dcc: dfc00a15 stw ra,40(sp) + 3dd0: df000915 stw fp,36(sp) + 3dd4: ddc00815 stw r23,32(sp) + 3dd8: dd800715 stw r22,28(sp) + 3ddc: dd400615 stw r21,24(sp) + 3de0: dd000515 stw r20,20(sp) + 3de4: dc800315 stw r18,12(sp) + 3de8: dc400215 stw r17,8(sp) + 3dec: 2027883a mov r19,r4 + 3df0: 2821883a mov r16,r5 + 3df4: 3800411e bne r7,zero,3efc <__udivdi3+0x13c> + 3df8: 3829883a mov r20,r7 + 3dfc: 3023883a mov r17,r6 + 3e00: 2025883a mov r18,r4 + 3e04: 29805d2e bgeu r5,r6,3f7c <__udivdi3+0x1bc> + 3e08: 00bfffd4 movui r2,65535 + 3e0c: 282b883a mov r21,r5 + 3e10: 1180a02e bgeu r2,r6,4094 <__udivdi3+0x2d4> + 3e14: 00804034 movhi r2,256 + 3e18: 30813636 bltu r6,r2,42f4 <__udivdi3+0x534> + 3e1c: 3006d63a srli r3,r6,24 + 3e20: 05000604 movi r20,24 + 3e24: 00800074 movhi r2,1 + 3e28: 1885883a add r2,r3,r2 + 3e2c: 10ae7f03 ldbu r2,-17924(r2) + 3e30: 00c00804 movi r3,32 + 3e34: 1505883a add r2,r2,r20 + 3e38: 1889c83a sub r4,r3,r2 + 3e3c: 18800526 beq r3,r2,3e54 <__udivdi3+0x94> + 3e40: 8120983a sll r16,r16,r4 + 3e44: 9884d83a srl r2,r19,r2 + 3e48: 3122983a sll r17,r6,r4 + 3e4c: 9924983a sll r18,r19,r4 + 3e50: 142ab03a or r21,r2,r16 + 3e54: 882cd43a srli r22,r17,16 + 3e58: a809883a mov r4,r21 + 3e5c: 8d3fffcc andi r20,r17,65535 + 3e60: b00b883a mov r5,r22 + 3e64: 00044a80 call 44a8 <__umodsi3> + 3e68: a809883a mov r4,r21 + 3e6c: b00b883a mov r5,r22 + 3e70: 1027883a mov r19,r2 + 3e74: 00044440 call 4444 <__udivsi3> + 3e78: 9826943a slli r19,r19,16 + 3e7c: 9008d43a srli r4,r18,16 + 3e80: 1021883a mov r16,r2 + 3e84: a085383a mul r2,r20,r2 + 3e88: 9908b03a or r4,r19,r4 + 3e8c: 2080052e bgeu r4,r2,3ea4 <__udivdi3+0xe4> + 3e90: 2449883a add r4,r4,r17 + 3e94: 80ffffc4 addi r3,r16,-1 + 3e98: 24400136 bltu r4,r17,3ea0 <__udivdi3+0xe0> + 3e9c: 20812636 bltu r4,r2,4338 <__udivdi3+0x578> + 3ea0: 1821883a mov r16,r3 + 3ea4: 20a7c83a sub r19,r4,r2 + 3ea8: 9809883a mov r4,r19 + 3eac: b00b883a mov r5,r22 + 3eb0: 00044a80 call 44a8 <__umodsi3> + 3eb4: 9809883a mov r4,r19 + 3eb8: b00b883a mov r5,r22 + 3ebc: 1027883a mov r19,r2 + 3ec0: 9826943a slli r19,r19,16 + 3ec4: 00044440 call 4444 <__udivsi3> + 3ec8: a0a9383a mul r20,r20,r2 + 3ecc: 94bfffcc andi r18,r18,65535 + 3ed0: 9ca4b03a or r18,r19,r18 + 3ed4: 9500052e bgeu r18,r20,3eec <__udivdi3+0x12c> + 3ed8: 8ca5883a add r18,r17,r18 + 3edc: 10ffffc4 addi r3,r2,-1 + 3ee0: 94400136 bltu r18,r17,3ee8 <__udivdi3+0x128> + 3ee4: 95011236 bltu r18,r20,4330 <__udivdi3+0x570> + 3ee8: 1805883a mov r2,r3 + 3eec: 8020943a slli r16,r16,16 + 3ef0: 0007883a mov r3,zero + 3ef4: 8084b03a or r2,r16,r2 + 3ef8: 00000306 br 3f08 <__udivdi3+0x148> + 3efc: 29c00e2e bgeu r5,r7,3f38 <__udivdi3+0x178> + 3f00: 0007883a mov r3,zero + 3f04: 0005883a mov r2,zero + 3f08: dfc00a17 ldw ra,40(sp) + 3f0c: df000917 ldw fp,36(sp) + 3f10: ddc00817 ldw r23,32(sp) + 3f14: dd800717 ldw r22,28(sp) + 3f18: dd400617 ldw r21,24(sp) + 3f1c: dd000517 ldw r20,20(sp) + 3f20: dcc00417 ldw r19,16(sp) + 3f24: dc800317 ldw r18,12(sp) + 3f28: dc400217 ldw r17,8(sp) + 3f2c: dc000117 ldw r16,4(sp) + 3f30: dec00b04 addi sp,sp,44 + 3f34: f800283a ret + 3f38: 00bfffd4 movui r2,65535 + 3f3c: 11c05a2e bgeu r2,r7,40a8 <__udivdi3+0x2e8> + 3f40: 00804034 movhi r2,256 + 3f44: 3880dd36 bltu r7,r2,42bc <__udivdi3+0x4fc> + 3f48: 3804d63a srli r2,r7,24 + 3f4c: 01000604 movi r4,24 + 3f50: 00c00074 movhi r3,1 + 3f54: 10c7883a add r3,r2,r3 + 3f58: 18ae7f03 ldbu r2,-17924(r3) + 3f5c: 00c00804 movi r3,32 + 3f60: 1105883a add r2,r2,r4 + 3f64: 18abc83a sub r21,r3,r2 + 3f68: 1880861e bne r3,r2,4184 <__udivdi3+0x3c4> + 3f6c: 3c00d836 bltu r7,r16,42d0 <__udivdi3+0x510> + 3f70: 9985403a cmpgeu r2,r19,r6 + 3f74: 0007883a mov r3,zero + 3f78: 003fe306 br 3f08 <__udivdi3+0x148> + 3f7c: 3000041e bne r6,zero,3f90 <__udivdi3+0x1d0> + 3f80: 000b883a mov r5,zero + 3f84: 01000044 movi r4,1 + 3f88: 00044440 call 4444 <__udivsi3> + 3f8c: 1023883a mov r17,r2 + 3f90: 00bfffd4 movui r2,65535 + 3f94: 14403a2e bgeu r2,r17,4080 <__udivdi3+0x2c0> + 3f98: 00804034 movhi r2,256 + 3f9c: 8880d236 bltu r17,r2,42e8 <__udivdi3+0x528> + 3fa0: 8806d63a srli r3,r17,24 + 3fa4: 05000604 movi r20,24 + 3fa8: 00800074 movhi r2,1 + 3fac: 1885883a add r2,r3,r2 + 3fb0: 10ae7f03 ldbu r2,-17924(r2) + 3fb4: 00c00804 movi r3,32 + 3fb8: 1505883a add r2,r2,r20 + 3fbc: 188dc83a sub r6,r3,r2 + 3fc0: 18803e1e bne r3,r2,40bc <__udivdi3+0x2fc> + 3fc4: 882ad43a srli r21,r17,16 + 3fc8: 8461c83a sub r16,r16,r17 + 3fcc: 8cffffcc andi r19,r17,65535 + 3fd0: 00c00044 movi r3,1 + 3fd4: 8009883a mov r4,r16 + 3fd8: a80b883a mov r5,r21 + 3fdc: d8c00015 stw r3,0(sp) + 3fe0: 00044a80 call 44a8 <__umodsi3> + 3fe4: 8009883a mov r4,r16 + 3fe8: a80b883a mov r5,r21 + 3fec: 1021883a mov r16,r2 + 3ff0: 00044440 call 4444 <__udivsi3> + 3ff4: 8020943a slli r16,r16,16 + 3ff8: 9008d43a srli r4,r18,16 + 3ffc: 1029883a mov r20,r2 + 4000: 14c5383a mul r2,r2,r19 + 4004: 8108b03a or r4,r16,r4 + 4008: d8c00017 ldw r3,0(sp) + 400c: 2080052e bgeu r4,r2,4024 <__udivdi3+0x264> + 4010: 2449883a add r4,r4,r17 + 4014: a17fffc4 addi r5,r20,-1 + 4018: 24400136 bltu r4,r17,4020 <__udivdi3+0x260> + 401c: 2080c936 bltu r4,r2,4344 <__udivdi3+0x584> + 4020: 2829883a mov r20,r5 + 4024: 20a1c83a sub r16,r4,r2 + 4028: 8009883a mov r4,r16 + 402c: a80b883a mov r5,r21 + 4030: d8c00015 stw r3,0(sp) + 4034: 00044a80 call 44a8 <__umodsi3> + 4038: 8009883a mov r4,r16 + 403c: a80b883a mov r5,r21 + 4040: 1021883a mov r16,r2 + 4044: 8020943a slli r16,r16,16 + 4048: 00044440 call 4444 <__udivsi3> + 404c: 14e7383a mul r19,r2,r19 + 4050: 94bfffcc andi r18,r18,65535 + 4054: 84a4b03a or r18,r16,r18 + 4058: d8c00017 ldw r3,0(sp) + 405c: 94c0052e bgeu r18,r19,4074 <__udivdi3+0x2b4> + 4060: 8ca5883a add r18,r17,r18 + 4064: 113fffc4 addi r4,r2,-1 + 4068: 94400136 bltu r18,r17,4070 <__udivdi3+0x2b0> + 406c: 94c0ae36 bltu r18,r19,4328 <__udivdi3+0x568> + 4070: 2005883a mov r2,r4 + 4074: a00c943a slli r6,r20,16 + 4078: 3084b03a or r2,r6,r2 + 407c: 003fa206 br 3f08 <__udivdi3+0x148> + 4080: 88804030 cmpltui r2,r17,256 + 4084: 10009e1e bne r2,zero,4300 <__udivdi3+0x540> + 4088: 8806d23a srli r3,r17,8 + 408c: 05000204 movi r20,8 + 4090: 003fc506 br 3fa8 <__udivdi3+0x1e8> + 4094: 30804030 cmpltui r2,r6,256 + 4098: 10008b1e bne r2,zero,42c8 <__udivdi3+0x508> + 409c: 3006d23a srli r3,r6,8 + 40a0: 05000204 movi r20,8 + 40a4: 003f5f06 br 3e24 <__udivdi3+0x64> + 40a8: 38804030 cmpltui r2,r7,256 + 40ac: 10008b1e bne r2,zero,42dc <__udivdi3+0x51c> + 40b0: 3804d23a srli r2,r7,8 + 40b4: 01000204 movi r4,8 + 40b8: 003fa506 br 3f50 <__udivdi3+0x190> + 40bc: 89a2983a sll r17,r17,r6 + 40c0: 80acd83a srl r22,r16,r2 + 40c4: 81a0983a sll r16,r16,r6 + 40c8: 882ad43a srli r21,r17,16 + 40cc: 9884d83a srl r2,r19,r2 + 40d0: b009883a mov r4,r22 + 40d4: a80b883a mov r5,r21 + 40d8: 99a4983a sll r18,r19,r6 + 40dc: 1428b03a or r20,r2,r16 + 40e0: 00044a80 call 44a8 <__umodsi3> + 40e4: b009883a mov r4,r22 + 40e8: a80b883a mov r5,r21 + 40ec: 1021883a mov r16,r2 + 40f0: 00044440 call 4444 <__udivsi3> + 40f4: 8008943a slli r4,r16,16 + 40f8: a00ad43a srli r5,r20,16 + 40fc: 8cffffcc andi r19,r17,65535 + 4100: 98a1383a mul r16,r19,r2 + 4104: 2148b03a or r4,r4,r5 + 4108: 102d883a mov r22,r2 + 410c: 2400062e bgeu r4,r16,4128 <__udivdi3+0x368> + 4110: 2449883a add r4,r4,r17 + 4114: 10bfffc4 addi r2,r2,-1 + 4118: 24408136 bltu r4,r17,4320 <__udivdi3+0x560> + 411c: 2400802e bgeu r4,r16,4320 <__udivdi3+0x560> + 4120: b5bfff84 addi r22,r22,-2 + 4124: 2449883a add r4,r4,r17 + 4128: 2421c83a sub r16,r4,r16 + 412c: 8009883a mov r4,r16 + 4130: a80b883a mov r5,r21 + 4134: 00044a80 call 44a8 <__umodsi3> + 4138: 8009883a mov r4,r16 + 413c: a80b883a mov r5,r21 + 4140: 1021883a mov r16,r2 + 4144: 8020943a slli r16,r16,16 + 4148: 00044440 call 4444 <__udivsi3> + 414c: 9889383a mul r4,r19,r2 + 4150: a53fffcc andi r20,r20,65535 + 4154: 8520b03a or r16,r16,r20 + 4158: 8100062e bgeu r16,r4,4174 <__udivdi3+0x3b4> + 415c: 8461883a add r16,r16,r17 + 4160: 10ffffc4 addi r3,r2,-1 + 4164: 84406a36 bltu r16,r17,4310 <__udivdi3+0x550> + 4168: 8100692e bgeu r16,r4,4310 <__udivdi3+0x550> + 416c: 10bfff84 addi r2,r2,-2 + 4170: 8461883a add r16,r16,r17 + 4174: b006943a slli r3,r22,16 + 4178: 8121c83a sub r16,r16,r4 + 417c: 1886b03a or r3,r3,r2 + 4180: 003f9406 br 3fd4 <__udivdi3+0x214> + 4184: 30acd83a srl r22,r6,r2 + 4188: 3d4e983a sll r7,r7,r21 + 418c: 80a4d83a srl r18,r16,r2 + 4190: 8546983a sll r3,r16,r21 + 4194: b1ecb03a or r22,r22,r7 + 4198: b038d43a srli fp,r22,16 + 419c: 9884d83a srl r2,r19,r2 + 41a0: 9009883a mov r4,r18 + 41a4: e00b883a mov r5,fp + 41a8: 10e2b03a or r17,r2,r3 + 41ac: 3568983a sll r20,r6,r21 + 41b0: 00044a80 call 44a8 <__umodsi3> + 41b4: 9009883a mov r4,r18 + 41b8: e00b883a mov r5,fp + 41bc: 1025883a mov r18,r2 + 41c0: 00044440 call 4444 <__udivsi3> + 41c4: 9008943a slli r4,r18,16 + 41c8: 8806d43a srli r3,r17,16 + 41cc: b5ffffcc andi r23,r22,65535 + 41d0: b8a5383a mul r18,r23,r2 + 41d4: 20c8b03a or r4,r4,r3 + 41d8: 1021883a mov r16,r2 + 41dc: 2480062e bgeu r4,r18,41f8 <__udivdi3+0x438> + 41e0: 2589883a add r4,r4,r22 + 41e4: 10bfffc4 addi r2,r2,-1 + 41e8: 25804b36 bltu r4,r22,4318 <__udivdi3+0x558> + 41ec: 24804a2e bgeu r4,r18,4318 <__udivdi3+0x558> + 41f0: 843fff84 addi r16,r16,-2 + 41f4: 2589883a add r4,r4,r22 + 41f8: 24a5c83a sub r18,r4,r18 + 41fc: 9009883a mov r4,r18 + 4200: e00b883a mov r5,fp + 4204: 00044a80 call 44a8 <__umodsi3> + 4208: 9009883a mov r4,r18 + 420c: e00b883a mov r5,fp + 4210: 1025883a mov r18,r2 + 4214: 9024943a slli r18,r18,16 + 4218: 00044440 call 4444 <__udivsi3> + 421c: b8af383a mul r23,r23,r2 + 4220: 8c7fffcc andi r17,r17,65535 + 4224: 9462b03a or r17,r18,r17 + 4228: 8dc0062e bgeu r17,r23,4244 <__udivdi3+0x484> + 422c: 8da3883a add r17,r17,r22 + 4230: 10ffffc4 addi r3,r2,-1 + 4234: 8d803436 bltu r17,r22,4308 <__udivdi3+0x548> + 4238: 8dc0332e bgeu r17,r23,4308 <__udivdi3+0x548> + 423c: 10bfff84 addi r2,r2,-2 + 4240: 8da3883a add r17,r17,r22 + 4244: 8020943a slli r16,r16,16 + 4248: 10ffffcc andi r3,r2,65535 + 424c: a00ed43a srli r7,r20,16 + 4250: 8084b03a or r2,r16,r2 + 4254: 1008d43a srli r4,r2,16 + 4258: a1bfffcc andi r6,r20,65535 + 425c: 1991383a mul r8,r3,r6 + 4260: 218d383a mul r6,r4,r6 + 4264: 19c7383a mul r3,r3,r7 + 4268: 400ad43a srli r5,r8,16 + 426c: 21c9383a mul r4,r4,r7 + 4270: 1987883a add r3,r3,r6 + 4274: 28c7883a add r3,r5,r3 + 4278: 8de3c83a sub r17,r17,r23 + 427c: 1980022e bgeu r3,r6,4288 <__udivdi3+0x4c8> + 4280: 01400074 movhi r5,1 + 4284: 2149883a add r4,r4,r5 + 4288: 180ad43a srli r5,r3,16 + 428c: 2909883a add r4,r5,r4 + 4290: 89000836 bltu r17,r4,42b4 <__udivdi3+0x4f4> + 4294: 89000226 beq r17,r4,42a0 <__udivdi3+0x4e0> + 4298: 0007883a mov r3,zero + 429c: 003f1a06 br 3f08 <__udivdi3+0x148> + 42a0: 1806943a slli r3,r3,16 + 42a4: 9d4c983a sll r6,r19,r21 + 42a8: 423fffcc andi r8,r8,65535 + 42ac: 1a07883a add r3,r3,r8 + 42b0: 30fff92e bgeu r6,r3,4298 <__udivdi3+0x4d8> + 42b4: 10bfffc4 addi r2,r2,-1 + 42b8: 003ff706 br 4298 <__udivdi3+0x4d8> + 42bc: 3804d43a srli r2,r7,16 + 42c0: 01000404 movi r4,16 + 42c4: 003f2206 br 3f50 <__udivdi3+0x190> + 42c8: 3007883a mov r3,r6 + 42cc: 003ed506 br 3e24 <__udivdi3+0x64> + 42d0: 0007883a mov r3,zero + 42d4: 00800044 movi r2,1 + 42d8: 003f0b06 br 3f08 <__udivdi3+0x148> + 42dc: 3805883a mov r2,r7 + 42e0: 0009883a mov r4,zero + 42e4: 003f1a06 br 3f50 <__udivdi3+0x190> + 42e8: 8806d43a srli r3,r17,16 + 42ec: 05000404 movi r20,16 + 42f0: 003f2d06 br 3fa8 <__udivdi3+0x1e8> + 42f4: 3006d43a srli r3,r6,16 + 42f8: 05000404 movi r20,16 + 42fc: 003ec906 br 3e24 <__udivdi3+0x64> + 4300: 8807883a mov r3,r17 + 4304: 003f2806 br 3fa8 <__udivdi3+0x1e8> + 4308: 1805883a mov r2,r3 + 430c: 003fcd06 br 4244 <__udivdi3+0x484> + 4310: 1805883a mov r2,r3 + 4314: 003f9706 br 4174 <__udivdi3+0x3b4> + 4318: 1021883a mov r16,r2 + 431c: 003fb606 br 41f8 <__udivdi3+0x438> + 4320: 102d883a mov r22,r2 + 4324: 003f8006 br 4128 <__udivdi3+0x368> + 4328: 10bfff84 addi r2,r2,-2 + 432c: 003f5106 br 4074 <__udivdi3+0x2b4> + 4330: 10bfff84 addi r2,r2,-2 + 4334: 003eed06 br 3eec <__udivdi3+0x12c> + 4338: 843fff84 addi r16,r16,-2 + 433c: 2449883a add r4,r4,r17 + 4340: 003ed806 br 3ea4 <__udivdi3+0xe4> + 4344: a53fff84 addi r20,r20,-2 + 4348: 2449883a add r4,r4,r17 + 434c: 003f3506 br 4024 <__udivdi3+0x264> + +00004350 <__divsi3>: + 4350: 20001a16 blt r4,zero,43bc <__divsi3+0x6c> + 4354: 000f883a mov r7,zero + 4358: 2800020e bge r5,zero,4364 <__divsi3+0x14> + 435c: 014bc83a sub r5,zero,r5 + 4360: 39c0005c xori r7,r7,1 + 4364: 200d883a mov r6,r4 + 4368: 00c00044 movi r3,1 + 436c: 2900092e bgeu r5,r4,4394 <__divsi3+0x44> + 4370: 00800804 movi r2,32 + 4374: 00c00044 movi r3,1 + 4378: 00000106 br 4380 <__divsi3+0x30> + 437c: 10001226 beq r2,zero,43c8 <__divsi3+0x78> + 4380: 294b883a add r5,r5,r5 + 4384: 10bfffc4 addi r2,r2,-1 + 4388: 18c7883a add r3,r3,r3 + 438c: 293ffb36 bltu r5,r4,437c <__divsi3+0x2c> + 4390: 18000d26 beq r3,zero,43c8 <__divsi3+0x78> + 4394: 0005883a mov r2,zero + 4398: 31400236 bltu r6,r5,43a4 <__divsi3+0x54> + 439c: 314dc83a sub r6,r6,r5 + 43a0: 10c4b03a or r2,r2,r3 + 43a4: 1806d07a srli r3,r3,1 + 43a8: 280ad07a srli r5,r5,1 + 43ac: 183ffa1e bne r3,zero,4398 <__divsi3+0x48> + 43b0: 38000126 beq r7,zero,43b8 <__divsi3+0x68> + 43b4: 0085c83a sub r2,zero,r2 + 43b8: f800283a ret + 43bc: 0109c83a sub r4,zero,r4 + 43c0: 01c00044 movi r7,1 + 43c4: 003fe406 br 4358 <__divsi3+0x8> + 43c8: 0005883a mov r2,zero + 43cc: 003ff806 br 43b0 <__divsi3+0x60> + +000043d0 <__modsi3>: + 43d0: 20001916 blt r4,zero,4438 <__modsi3+0x68> + 43d4: 000f883a mov r7,zero + 43d8: 2005883a mov r2,r4 + 43dc: 2800010e bge r5,zero,43e4 <__modsi3+0x14> + 43e0: 014bc83a sub r5,zero,r5 + 43e4: 00c00044 movi r3,1 + 43e8: 2900092e bgeu r5,r4,4410 <__modsi3+0x40> + 43ec: 01800804 movi r6,32 + 43f0: 00c00044 movi r3,1 + 43f4: 00000106 br 43fc <__modsi3+0x2c> + 43f8: 30000d26 beq r6,zero,4430 <__modsi3+0x60> + 43fc: 294b883a add r5,r5,r5 + 4400: 31bfffc4 addi r6,r6,-1 + 4404: 18c7883a add r3,r3,r3 + 4408: 293ffb36 bltu r5,r4,43f8 <__modsi3+0x28> + 440c: 18000826 beq r3,zero,4430 <__modsi3+0x60> + 4410: 1806d07a srli r3,r3,1 + 4414: 11400136 bltu r2,r5,441c <__modsi3+0x4c> + 4418: 1145c83a sub r2,r2,r5 + 441c: 280ad07a srli r5,r5,1 + 4420: 183ffb1e bne r3,zero,4410 <__modsi3+0x40> + 4424: 38000126 beq r7,zero,442c <__modsi3+0x5c> + 4428: 0085c83a sub r2,zero,r2 + 442c: f800283a ret + 4430: 2005883a mov r2,r4 + 4434: 003ffb06 br 4424 <__modsi3+0x54> + 4438: 0109c83a sub r4,zero,r4 + 443c: 01c00044 movi r7,1 + 4440: 003fe506 br 43d8 <__modsi3+0x8> + +00004444 <__udivsi3>: + 4444: 200d883a mov r6,r4 + 4448: 2900152e bgeu r5,r4,44a0 <__udivsi3+0x5c> + 444c: 28001416 blt r5,zero,44a0 <__udivsi3+0x5c> + 4450: 00800804 movi r2,32 + 4454: 00c00044 movi r3,1 + 4458: 00000206 br 4464 <__udivsi3+0x20> + 445c: 10000e26 beq r2,zero,4498 <__udivsi3+0x54> + 4460: 28000516 blt r5,zero,4478 <__udivsi3+0x34> + 4464: 294b883a add r5,r5,r5 + 4468: 10bfffc4 addi r2,r2,-1 + 446c: 18c7883a add r3,r3,r3 + 4470: 293ffa36 bltu r5,r4,445c <__udivsi3+0x18> + 4474: 18000826 beq r3,zero,4498 <__udivsi3+0x54> + 4478: 0005883a mov r2,zero + 447c: 31400236 bltu r6,r5,4488 <__udivsi3+0x44> + 4480: 314dc83a sub r6,r6,r5 + 4484: 10c4b03a or r2,r2,r3 + 4488: 1806d07a srli r3,r3,1 + 448c: 280ad07a srli r5,r5,1 + 4490: 183ffa1e bne r3,zero,447c <__udivsi3+0x38> + 4494: f800283a ret + 4498: 0005883a mov r2,zero + 449c: f800283a ret + 44a0: 00c00044 movi r3,1 + 44a4: 003ff406 br 4478 <__udivsi3+0x34> + +000044a8 <__umodsi3>: + 44a8: 2005883a mov r2,r4 + 44ac: 2900132e bgeu r5,r4,44fc <__umodsi3+0x54> + 44b0: 28001216 blt r5,zero,44fc <__umodsi3+0x54> + 44b4: 01800804 movi r6,32 + 44b8: 00c00044 movi r3,1 + 44bc: 00000206 br 44c8 <__umodsi3+0x20> + 44c0: 30000c26 beq r6,zero,44f4 <__umodsi3+0x4c> + 44c4: 28000516 blt r5,zero,44dc <__umodsi3+0x34> + 44c8: 294b883a add r5,r5,r5 + 44cc: 31bfffc4 addi r6,r6,-1 + 44d0: 18c7883a add r3,r3,r3 + 44d4: 293ffa36 bltu r5,r4,44c0 <__umodsi3+0x18> + 44d8: 18000626 beq r3,zero,44f4 <__umodsi3+0x4c> + 44dc: 1806d07a srli r3,r3,1 + 44e0: 11400136 bltu r2,r5,44e8 <__umodsi3+0x40> + 44e4: 1145c83a sub r2,r2,r5 + 44e8: 280ad07a srli r5,r5,1 + 44ec: 183ffb1e bne r3,zero,44dc <__umodsi3+0x34> + 44f0: f800283a ret + 44f4: 2005883a mov r2,r4 + 44f8: f800283a ret + 44fc: 00c00044 movi r3,1 + 4500: 003ff606 br 44dc <__umodsi3+0x34> + +00004504 <__lesf2>: + 4504: 200cd5fa srli r6,r4,23 + 4508: 280ed5fa srli r7,r5,23 + 450c: 00c02034 movhi r3,128 + 4510: 31803fcc andi r6,r6,255 + 4514: 18ffffc4 addi r3,r3,-1 + 4518: 32003fd8 cmpnei r8,r6,255 + 451c: 2012d7fa srli r9,r4,31 + 4520: 2804d7fa srli r2,r5,31 + 4524: 1908703a and r4,r3,r4 + 4528: 1946703a and r3,r3,r5 + 452c: 39403fcc andi r5,r7,255 + 4530: 40000826 beq r8,zero,4554 <__lesf2+0x50> + 4534: 29c03fd8 cmpnei r7,r5,255 + 4538: 38000926 beq r7,zero,4560 <__lesf2+0x5c> + 453c: 3000181e bne r6,zero,45a0 <__lesf2+0x9c> + 4540: 2800091e bne r5,zero,4568 <__lesf2+0x64> + 4544: 1800081e bne r3,zero,4568 <__lesf2+0x64> + 4548: 2000091e bne r4,zero,4570 <__lesf2+0x6c> + 454c: 0005883a mov r2,zero + 4550: f800283a ret + 4554: 20000a1e bne r4,zero,4580 <__lesf2+0x7c> + 4558: 29c03fe0 cmpeqi r7,r5,255 + 455c: 38001026 beq r7,zero,45a0 <__lesf2+0x9c> + 4560: 1800071e bne r3,zero,4580 <__lesf2+0x7c> + 4564: 3000011e bne r6,zero,456c <__lesf2+0x68> + 4568: 20000b26 beq r4,zero,4598 <__lesf2+0x94> + 456c: 48800626 beq r9,r2,4588 <__lesf2+0x84> + 4570: 00800044 movi r2,1 + 4574: 48000926 beq r9,zero,459c <__lesf2+0x98> + 4578: 00bfffc4 movi r2,-1 + 457c: f800283a ret + 4580: 00800084 movi r2,2 + 4584: f800283a ret + 4588: 29800816 blt r5,r6,45ac <__lesf2+0xa8> + 458c: 31400216 blt r6,r5,4598 <__lesf2+0x94> + 4590: 19000636 bltu r3,r4,45ac <__lesf2+0xa8> + 4594: 20ffed2e bgeu r4,r3,454c <__lesf2+0x48> + 4598: 103ff726 beq r2,zero,4578 <__lesf2+0x74> + 459c: f800283a ret + 45a0: 283ff21e bne r5,zero,456c <__lesf2+0x68> + 45a4: 183ff11e bne r3,zero,456c <__lesf2+0x68> + 45a8: 003ff106 br 4570 <__lesf2+0x6c> + 45ac: 103ff21e bne r2,zero,4578 <__lesf2+0x74> + 45b0: 00800044 movi r2,1 + 45b4: f800283a ret + +000045b8 <__adddf3>: + 45b8: 02000434 movhi r8,16 + 45bc: 423fffc4 addi r8,r8,-1 + 45c0: 2806d53a srli r3,r5,20 + 45c4: 3804d53a srli r2,r7,20 + 45c8: 2a14703a and r10,r5,r8 + 45cc: 3a12703a and r9,r7,r8 + 45d0: 280ad7fa srli r5,r5,31 + 45d4: 501490fa slli r10,r10,3 + 45d8: 2018d77a srli r12,r4,29 + 45dc: 481290fa slli r9,r9,3 + 45e0: 3016d77a srli r11,r6,29 + 45e4: 380ed7fa srli r7,r7,31 + 45e8: defffb04 addi sp,sp,-20 + 45ec: dc800215 stw r18,8(sp) + 45f0: dc000015 stw r16,0(sp) + 45f4: 1c81ffcc andi r18,r3,2047 + 45f8: 1081ffcc andi r2,r2,2047 + 45fc: dfc00415 stw ra,16(sp) + 4600: dcc00315 stw r19,12(sp) + 4604: dc400115 stw r17,4(sp) + 4608: 201c90fa slli r14,r4,3 + 460c: 301a90fa slli r13,r6,3 + 4610: 2821883a mov r16,r5 + 4614: 6294b03a or r10,r12,r10 + 4618: 5a52b03a or r9,r11,r9 + 461c: 9087c83a sub r3,r18,r2 + 4620: 29c06126 beq r5,r7,47a8 <__adddf3+0x1f0> + 4624: 00c0550e bge zero,r3,477c <__adddf3+0x1c4> + 4628: 10007326 beq r2,zero,47f8 <__adddf3+0x240> + 462c: 9081ffd8 cmpnei r2,r18,2047 + 4630: 1000bd26 beq r2,zero,4928 <__adddf3+0x370> + 4634: 4a402034 orhi r9,r9,128 + 4638: 18800e48 cmpgei r2,r3,57 + 463c: 1000ef1e bne r2,zero,49fc <__adddf3+0x444> + 4640: 18800808 cmpgei r2,r3,32 + 4644: 1001321e bne r2,zero,4b10 <__adddf3+0x558> + 4648: 00800804 movi r2,32 + 464c: 10c5c83a sub r2,r2,r3 + 4650: 68c8d83a srl r4,r13,r3 + 4654: 48a2983a sll r17,r9,r2 + 4658: 689a983a sll r13,r13,r2 + 465c: 48c6d83a srl r3,r9,r3 + 4660: 8922b03a or r17,r17,r4 + 4664: 681ac03a cmpne r13,r13,zero + 4668: 8b62b03a or r17,r17,r13 + 466c: 50d5c83a sub r10,r10,r3 + 4670: 7463c83a sub r17,r14,r17 + 4674: 7451803a cmpltu r8,r14,r17 + 4678: 5211c83a sub r8,r10,r8 + 467c: 4080202c andhi r2,r8,128 + 4680: 10008d26 beq r2,zero,48b8 <__adddf3+0x300> + 4684: 02402034 movhi r9,128 + 4688: 4a7fffc4 addi r9,r9,-1 + 468c: 4266703a and r19,r8,r9 + 4690: 9800b326 beq r19,zero,4960 <__adddf3+0x3a8> + 4694: 9809883a mov r4,r19 + 4698: 0006b040 call 6b04 <__clzsi2> + 469c: 10fffe04 addi r3,r2,-8 + 46a0: 02000804 movi r8,32 + 46a4: 40d1c83a sub r8,r8,r3 + 46a8: 8a10d83a srl r8,r17,r8 + 46ac: 98d2983a sll r9,r19,r3 + 46b0: 88e2983a sll r17,r17,r3 + 46b4: 4250b03a or r8,r8,r9 + 46b8: 1c80b216 blt r3,r18,4984 <__adddf3+0x3cc> + 46bc: 1c87c83a sub r3,r3,r18 + 46c0: 19000044 addi r4,r3,1 + 46c4: 20800808 cmpgei r2,r4,32 + 46c8: 10006f1e bne r2,zero,4888 <__adddf3+0x2d0> + 46cc: 00800804 movi r2,32 + 46d0: 1105c83a sub r2,r2,r4 + 46d4: 8906d83a srl r3,r17,r4 + 46d8: 88a2983a sll r17,r17,r2 + 46dc: 4084983a sll r2,r8,r2 + 46e0: 4110d83a srl r8,r8,r4 + 46e4: 8822c03a cmpne r17,r17,zero + 46e8: 10c4b03a or r2,r2,r3 + 46ec: 1462b03a or r17,r2,r17 + 46f0: 0025883a mov r18,zero + 46f4: 888001cc andi r2,r17,7 + 46f8: 10000726 beq r2,zero,4718 <__adddf3+0x160> + 46fc: 888003cc andi r2,r17,15 + 4700: 10800120 cmpeqi r2,r2,4 + 4704: 1000041e bne r2,zero,4718 <__adddf3+0x160> + 4708: 88c00104 addi r3,r17,4 + 470c: 1c63803a cmpltu r17,r3,r17 + 4710: 4451883a add r8,r8,r17 + 4714: 1823883a mov r17,r3 + 4718: 4080202c andhi r2,r8,128 + 471c: 10006826 beq r2,zero,48c0 <__adddf3+0x308> + 4720: 90c00044 addi r3,r18,1 + 4724: 1881ffe0 cmpeqi r2,r3,2047 + 4728: 18c1ffcc andi r3,r3,2047 + 472c: 10007a1e bne r2,zero,4918 <__adddf3+0x360> + 4730: 00bfe034 movhi r2,65408 + 4734: 10bfffc4 addi r2,r2,-1 + 4738: 4090703a and r8,r8,r2 + 473c: 4004977a slli r2,r8,29 + 4740: 4010927a slli r8,r8,9 + 4744: 8822d0fa srli r17,r17,3 + 4748: 4010d33a srli r8,r8,12 + 474c: 1444b03a or r2,r2,r17 + 4750: 1806953a slli r3,r3,20 + 4754: 802097fa slli r16,r16,31 + 4758: 1a06b03a or r3,r3,r8 + 475c: 1c06b03a or r3,r3,r16 + 4760: dfc00417 ldw ra,16(sp) + 4764: dcc00317 ldw r19,12(sp) + 4768: dc800217 ldw r18,8(sp) + 476c: dc400117 ldw r17,4(sp) + 4770: dc000017 ldw r16,0(sp) + 4774: dec00504 addi sp,sp,20 4778: f800283a ret - 477c: 203ffa26 beq r4,zero,4768 <__unordsf2+0x24> - 4780: 00800044 movi r2,1 - 4784: f800283a ret - 4788: 1004c03a cmpne r2,r2,zero - 478c: f800283a ret - -00004790 <__fixsfsi>: - 4790: 200ad5fa srli r5,r4,23 - 4794: 00c02034 movhi r3,128 - 4798: 18ffffc4 addi r3,r3,-1 - 479c: 29403fcc andi r5,r5,255 - 47a0: 29801fd0 cmplti r6,r5,127 - 47a4: 200ed7fa srli r7,r4,31 - 47a8: 1906703a and r3,r3,r4 - 47ac: 3000061e bne r6,zero,47c8 <__fixsfsi+0x38> - 47b0: 28802790 cmplti r2,r5,158 - 47b4: 1000061e bne r2,zero,47d0 <__fixsfsi+0x40> - 47b8: 00a00034 movhi r2,32768 - 47bc: 10bfffc4 addi r2,r2,-1 - 47c0: 3885883a add r2,r7,r2 - 47c4: f800283a ret - 47c8: 0005883a mov r2,zero - 47cc: f800283a ret - 47d0: 28802590 cmplti r2,r5,150 - 47d4: 18c02034 orhi r3,r3,128 - 47d8: 1000051e bne r2,zero,47f0 <__fixsfsi+0x60> - 47dc: 28bfda84 addi r2,r5,-150 - 47e0: 1884983a sll r2,r3,r2 - 47e4: 383ff926 beq r7,zero,47cc <__fixsfsi+0x3c> - 47e8: 0085c83a sub r2,zero,r2 - 47ec: f800283a ret - 47f0: 00802584 movi r2,150 - 47f4: 1145c83a sub r2,r2,r5 - 47f8: 1884d83a srl r2,r3,r2 - 47fc: 003ff906 br 47e4 <__fixsfsi+0x54> - -00004800 <__floatsisf>: - 4800: defffd04 addi sp,sp,-12 - 4804: dfc00215 stw ra,8(sp) - 4808: dc400115 stw r17,4(sp) - 480c: dc000015 stw r16,0(sp) - 4810: 20001226 beq r4,zero,485c <__floatsisf+0x5c> - 4814: 2022d7fa srli r17,r4,31 - 4818: 2021883a mov r16,r4 - 481c: 20003816 blt r4,zero,4900 <__floatsisf+0x100> - 4820: 8009883a mov r4,r16 - 4824: 0004a200 call 4a20 <__clzsi2> - 4828: 1009883a mov r4,r2 - 482c: 00802784 movi r2,158 - 4830: 1105c83a sub r2,r2,r4 - 4834: 10c025c8 cmpgei r3,r2,151 - 4838: 1800151e bne r3,zero,4890 <__floatsisf+0x90> - 483c: 20c00248 cmpgei r3,r4,9 - 4840: 18003126 beq r3,zero,4908 <__floatsisf+0x108> - 4844: 213ffe04 addi r4,r4,-8 - 4848: 8120983a sll r16,r16,r4 - 484c: 00c02034 movhi r3,128 - 4850: 18ffffc4 addi r3,r3,-1 - 4854: 80e0703a and r16,r16,r3 - 4858: 00000306 br 4868 <__floatsisf+0x68> - 485c: 0023883a mov r17,zero - 4860: 0005883a mov r2,zero - 4864: 0021883a mov r16,zero - 4868: 10803fcc andi r2,r2,255 - 486c: 100495fa slli r2,r2,23 - 4870: 882297fa slli r17,r17,31 - 4874: 1404b03a or r2,r2,r16 - 4878: 1444b03a or r2,r2,r17 - 487c: dfc00217 ldw ra,8(sp) - 4880: dc400117 ldw r17,4(sp) - 4884: dc000017 ldw r16,0(sp) - 4888: dec00304 addi sp,sp,12 - 488c: f800283a ret - 4890: 10c02690 cmplti r3,r2,154 - 4894: 1800071e bne r3,zero,48b4 <__floatsisf+0xb4> - 4898: 20c006c4 addi r3,r4,27 - 489c: 01400144 movi r5,5 - 48a0: 80c6983a sll r3,r16,r3 - 48a4: 290bc83a sub r5,r5,r4 - 48a8: 814ad83a srl r5,r16,r5 - 48ac: 1806c03a cmpne r3,r3,zero - 48b0: 28e0b03a or r16,r5,r3 - 48b4: 20c00188 cmpgei r3,r4,6 - 48b8: 1800171e bne r3,zero,4918 <__floatsisf+0x118> - 48bc: 00ff0034 movhi r3,64512 - 48c0: 18ffffc4 addi r3,r3,-1 - 48c4: 818001cc andi r6,r16,7 - 48c8: 80ca703a and r5,r16,r3 - 48cc: 30000926 beq r6,zero,48f4 <__floatsisf+0xf4> - 48d0: 818003cc andi r6,r16,15 - 48d4: 31800120 cmpeqi r6,r6,4 - 48d8: 3000061e bne r6,zero,48f4 <__floatsisf+0xf4> - 48dc: 29400104 addi r5,r5,4 - 48e0: 2981002c andhi r6,r5,1024 - 48e4: 30000326 beq r6,zero,48f4 <__floatsisf+0xf4> - 48e8: 28ca703a and r5,r5,r3 - 48ec: 00c027c4 movi r3,159 - 48f0: 1905c83a sub r2,r3,r4 - 48f4: 282091ba slli r16,r5,6 - 48f8: 8020d27a srli r16,r16,9 - 48fc: 003fda06 br 4868 <__floatsisf+0x68> - 4900: 0121c83a sub r16,zero,r4 - 4904: 003fc606 br 4820 <__floatsisf+0x20> - 4908: 01002034 movhi r4,128 - 490c: 213fffc4 addi r4,r4,-1 - 4910: 8120703a and r16,r16,r4 - 4914: 003fd406 br 4868 <__floatsisf+0x68> - 4918: 20fffec4 addi r3,r4,-5 - 491c: 80e0983a sll r16,r16,r3 - 4920: 003fe606 br 48bc <__floatsisf+0xbc> - -00004924 <__extendsfdf2>: - 4924: 200ad5fa srli r5,r4,23 - 4928: defffd04 addi sp,sp,-12 - 492c: dc000015 stw r16,0(sp) - 4930: 29403fcc andi r5,r5,255 - 4934: 04002034 movhi r16,128 - 4938: 28800044 addi r2,r5,1 - 493c: dc400115 stw r17,4(sp) - 4940: 843fffc4 addi r16,r16,-1 - 4944: dfc00215 stw ra,8(sp) - 4948: 10803f8c andi r2,r2,254 - 494c: 2022d7fa srli r17,r4,31 - 4950: 8120703a and r16,r16,r4 - 4954: 10000d26 beq r2,zero,498c <__extendsfdf2+0x68> - 4958: 8008d0fa srli r4,r16,3 - 495c: 8020977a slli r16,r16,29 - 4960: 28c0e004 addi r3,r5,896 - 4964: 180a953a slli r5,r3,20 - 4968: 880697fa slli r3,r17,31 - 496c: 8005883a mov r2,r16 - 4970: 290ab03a or r5,r5,r4 - 4974: 28c6b03a or r3,r5,r3 - 4978: dfc00217 ldw ra,8(sp) - 497c: dc400117 ldw r17,4(sp) - 4980: dc000017 ldw r16,0(sp) - 4984: dec00304 addi sp,sp,12 - 4988: f800283a ret - 498c: 2800111e bne r5,zero,49d4 <__extendsfdf2+0xb0> - 4990: 80001926 beq r16,zero,49f8 <__extendsfdf2+0xd4> - 4994: 8009883a mov r4,r16 - 4998: 0004a200 call 4a20 <__clzsi2> - 499c: 10c002c8 cmpgei r3,r2,11 - 49a0: 18001b1e bne r3,zero,4a10 <__extendsfdf2+0xec> - 49a4: 010002c4 movi r4,11 - 49a8: 2089c83a sub r4,r4,r2 - 49ac: 10c00544 addi r3,r2,21 - 49b0: 810ad83a srl r5,r16,r4 - 49b4: 80e0983a sll r16,r16,r3 - 49b8: 01000434 movhi r4,16 - 49bc: 00c0e244 movi r3,905 - 49c0: 213fffc4 addi r4,r4,-1 - 49c4: 1887c83a sub r3,r3,r2 - 49c8: 2908703a and r4,r5,r4 - 49cc: 18c1ffcc andi r3,r3,2047 - 49d0: 003fe406 br 4964 <__extendsfdf2+0x40> - 49d4: 80000b26 beq r16,zero,4a04 <__extendsfdf2+0xe0> - 49d8: 800ad0fa srli r5,r16,3 - 49dc: 00800434 movhi r2,16 - 49e0: 10bfffc4 addi r2,r2,-1 - 49e4: 29000234 orhi r4,r5,8 - 49e8: 8020977a slli r16,r16,29 - 49ec: 2088703a and r4,r4,r2 - 49f0: 00c1ffc4 movi r3,2047 - 49f4: 003fdb06 br 4964 <__extendsfdf2+0x40> - 49f8: 0007883a mov r3,zero - 49fc: 0009883a mov r4,zero - 4a00: 003fd806 br 4964 <__extendsfdf2+0x40> - 4a04: 00c1ffc4 movi r3,2047 - 4a08: 0009883a mov r4,zero - 4a0c: 003fd506 br 4964 <__extendsfdf2+0x40> - 4a10: 113ffd44 addi r4,r2,-11 - 4a14: 810a983a sll r5,r16,r4 - 4a18: 0021883a mov r16,zero - 4a1c: 003fe606 br 49b8 <__extendsfdf2+0x94> - -00004a20 <__clzsi2>: - 4a20: 00bfffd4 movui r2,65535 - 4a24: 11000436 bltu r2,r4,4a38 <__clzsi2+0x18> - 4a28: 20804030 cmpltui r2,r4,256 - 4a2c: 10000e26 beq r2,zero,4a68 <__clzsi2+0x48> - 4a30: 01400804 movi r5,32 - 4a34: 00000406 br 4a48 <__clzsi2+0x28> - 4a38: 00804034 movhi r2,256 - 4a3c: 20800736 bltu r4,r2,4a5c <__clzsi2+0x3c> - 4a40: 2008d63a srli r4,r4,24 - 4a44: 01400204 movi r5,8 - 4a48: 00c00074 movhi r3,1 - 4a4c: 20c7883a add r3,r4,r3 - 4a50: 18a55703 ldbu r2,-27300(r3) - 4a54: 2885c83a sub r2,r5,r2 - 4a58: f800283a ret - 4a5c: 2008d43a srli r4,r4,16 - 4a60: 01400404 movi r5,16 - 4a64: 003ff806 br 4a48 <__clzsi2+0x28> - 4a68: 2008d23a srli r4,r4,8 - 4a6c: 01400604 movi r5,24 - 4a70: 003ff506 br 4a48 <__clzsi2+0x28> - -00004a74 <__errno>: - 4a74: 00800074 movhi r2,1 - 4a78: 10a66f17 ldw r2,-26180(r2) - 4a7c: f800283a ret - -00004a80 : - 4a80: 2005883a mov r2,r4 - 4a84: 0007883a mov r3,zero - 4a88: 30c0011e bne r6,r3,4a90 - 4a8c: f800283a ret - 4a90: 28cf883a add r7,r5,r3 - 4a94: 39c00003 ldbu r7,0(r7) - 4a98: 10c9883a add r4,r2,r3 - 4a9c: 18c00044 addi r3,r3,1 - 4aa0: 21c00005 stb r7,0(r4) - 4aa4: 003ff806 br 4a88 - -00004aa8 <_printf_r>: - 4aa8: defffd04 addi sp,sp,-12 - 4aac: dfc00015 stw ra,0(sp) - 4ab0: d9800115 stw r6,4(sp) - 4ab4: d9c00215 stw r7,8(sp) - 4ab8: 21800217 ldw r6,8(r4) - 4abc: 00c00034 movhi r3,0 - 4ac0: 18d45a04 addi r3,r3,20840 - 4ac4: 30c00115 stw r3,4(r6) - 4ac8: 280d883a mov r6,r5 - 4acc: 21400217 ldw r5,8(r4) - 4ad0: d9c00104 addi r7,sp,4 - 4ad4: 0004c640 call 4c64 <___vfprintf_internal_r> - 4ad8: dfc00017 ldw ra,0(sp) - 4adc: dec00304 addi sp,sp,12 - 4ae0: f800283a ret - -00004ae4 : - 4ae4: defffc04 addi sp,sp,-16 - 4ae8: dfc00015 stw ra,0(sp) - 4aec: d9400115 stw r5,4(sp) - 4af0: d9800215 stw r6,8(sp) - 4af4: d9c00315 stw r7,12(sp) - 4af8: 00800074 movhi r2,1 - 4afc: 10e66f17 ldw r3,-26180(r2) - 4b00: 00800034 movhi r2,0 - 4b04: 10945a04 addi r2,r2,20840 - 4b08: 19400217 ldw r5,8(r3) - 4b0c: d9800104 addi r6,sp,4 - 4b10: 28800115 stw r2,4(r5) - 4b14: 200b883a mov r5,r4 - 4b18: 19000217 ldw r4,8(r3) - 4b1c: 00051500 call 5150 <__vfprintf_internal> - 4b20: dfc00017 ldw ra,0(sp) - 4b24: dec00404 addi sp,sp,16 - 4b28: f800283a ret - -00004b2c <_putchar_r>: - 4b2c: 21800217 ldw r6,8(r4) - 4b30: 00052601 jmpi 5260 <_putc_r> - -00004b34 : - 4b34: 00800074 movhi r2,1 - 4b38: 10a66f17 ldw r2,-26180(r2) - 4b3c: 200b883a mov r5,r4 - 4b40: 11800217 ldw r6,8(r2) - 4b44: 1009883a mov r4,r2 - 4b48: 00052601 jmpi 5260 <_putc_r> - -00004b4c <_puts_r>: - 4b4c: defffd04 addi sp,sp,-12 - 4b50: dc000015 stw r16,0(sp) - 4b54: 2021883a mov r16,r4 - 4b58: 2809883a mov r4,r5 - 4b5c: dfc00215 stw ra,8(sp) - 4b60: dc400115 stw r17,4(sp) - 4b64: 2823883a mov r17,r5 - 4b68: 0004bdc0 call 4bdc - 4b6c: 81400217 ldw r5,8(r16) - 4b70: 00c00034 movhi r3,0 - 4b74: 18d45a04 addi r3,r3,20840 - 4b78: 28c00115 stw r3,4(r5) - 4b7c: 100f883a mov r7,r2 - 4b80: 880d883a mov r6,r17 - 4b84: 8009883a mov r4,r16 - 4b88: 00051680 call 5168 <__sfvwrite_small_dev> - 4b8c: 10ffffe0 cmpeqi r3,r2,-1 - 4b90: 1800091e bne r3,zero,4bb8 <_puts_r+0x6c> - 4b94: 81400217 ldw r5,8(r16) - 4b98: 01800074 movhi r6,1 - 4b9c: 01c00044 movi r7,1 - 4ba0: 28800117 ldw r2,4(r5) - 4ba4: 31a59704 addi r6,r6,-27044 - 4ba8: 8009883a mov r4,r16 - 4bac: 103ee83a callr r2 - 4bb0: 10bfffe0 cmpeqi r2,r2,-1 - 4bb4: 0085c83a sub r2,zero,r2 - 4bb8: dfc00217 ldw ra,8(sp) - 4bbc: dc400117 ldw r17,4(sp) - 4bc0: dc000017 ldw r16,0(sp) - 4bc4: dec00304 addi sp,sp,12 - 4bc8: f800283a ret - -00004bcc : - 4bcc: 00800074 movhi r2,1 - 4bd0: 200b883a mov r5,r4 - 4bd4: 11266f17 ldw r4,-26180(r2) - 4bd8: 0004b4c1 jmpi 4b4c <_puts_r> - -00004bdc : - 4bdc: 2005883a mov r2,r4 - 4be0: 10c00007 ldb r3,0(r2) - 4be4: 1800021e bne r3,zero,4bf0 - 4be8: 1105c83a sub r2,r2,r4 - 4bec: f800283a ret - 4bf0: 10800044 addi r2,r2,1 - 4bf4: 003ffa06 br 4be0 - -00004bf8 : - 4bf8: defffb04 addi sp,sp,-20 - 4bfc: dc800315 stw r18,12(sp) - 4c00: dc400215 stw r17,8(sp) - 4c04: dc000115 stw r16,4(sp) - 4c08: dfc00415 stw ra,16(sp) - 4c0c: 2025883a mov r18,r4 - 4c10: 2823883a mov r17,r5 - 4c14: d9800005 stb r6,0(sp) - 4c18: 3821883a mov r16,r7 - 4c1c: 04000716 blt zero,r16,4c3c - 4c20: 0005883a mov r2,zero - 4c24: dfc00417 ldw ra,16(sp) - 4c28: dc800317 ldw r18,12(sp) - 4c2c: dc400217 ldw r17,8(sp) - 4c30: dc000117 ldw r16,4(sp) - 4c34: dec00504 addi sp,sp,20 - 4c38: f800283a ret - 4c3c: 88800117 ldw r2,4(r17) - 4c40: 01c00044 movi r7,1 - 4c44: d80d883a mov r6,sp - 4c48: 880b883a mov r5,r17 - 4c4c: 9009883a mov r4,r18 - 4c50: 103ee83a callr r2 - 4c54: 843fffc4 addi r16,r16,-1 - 4c58: 103ff026 beq r2,zero,4c1c - 4c5c: 00bfffc4 movi r2,-1 - 4c60: 003ff006 br 4c24 - -00004c64 <___vfprintf_internal_r>: - 4c64: deffe604 addi sp,sp,-104 - 4c68: df001815 stw fp,96(sp) - 4c6c: ddc01715 stw r23,92(sp) - 4c70: dd801615 stw r22,88(sp) - 4c74: dd001415 stw r20,80(sp) - 4c78: dcc01315 stw r19,76(sp) - 4c7c: dc801215 stw r18,72(sp) - 4c80: dc401115 stw r17,68(sp) - 4c84: dc001015 stw r16,64(sp) - 4c88: dfc01915 stw ra,100(sp) - 4c8c: dd401515 stw r21,84(sp) - 4c90: 2021883a mov r16,r4 - 4c94: 282f883a mov r23,r5 - 4c98: d9800515 stw r6,20(sp) - 4c9c: 3839883a mov fp,r7 - 4ca0: 002d883a mov r22,zero - 4ca4: d8000215 stw zero,8(sp) - 4ca8: 0027883a mov r19,zero - 4cac: 0029883a mov r20,zero - 4cb0: 0025883a mov r18,zero - 4cb4: 0023883a mov r17,zero - 4cb8: d8000115 stw zero,4(sp) - 4cbc: d8000015 stw zero,0(sp) - 4cc0: 0005883a mov r2,zero - 4cc4: 00000206 br 4cd0 <___vfprintf_internal_r+0x6c> - 4cc8: 118000e0 cmpeqi r6,r2,3 - 4ccc: 30003d1e bne r6,zero,4dc4 <___vfprintf_internal_r+0x160> - 4cd0: d8c00517 ldw r3,20(sp) - 4cd4: 19000003 ldbu r4,0(r3) - 4cd8: 18c00044 addi r3,r3,1 - 4cdc: d8c00515 stw r3,20(sp) - 4ce0: 21403fcc andi r5,r4,255 - 4ce4: 2940201c xori r5,r5,128 - 4ce8: 297fe004 addi r5,r5,-128 - 4cec: 28001426 beq r5,zero,4d40 <___vfprintf_internal_r+0xdc> - 4cf0: 118000a0 cmpeqi r6,r2,2 - 4cf4: 3000231e bne r6,zero,4d84 <___vfprintf_internal_r+0x120> - 4cf8: 118000c8 cmpgei r6,r2,3 - 4cfc: 303ff21e bne r6,zero,4cc8 <___vfprintf_internal_r+0x64> - 4d00: 10000426 beq r2,zero,4d14 <___vfprintf_internal_r+0xb0> - 4d04: 10800060 cmpeqi r2,r2,1 - 4d08: 10001a1e bne r2,zero,4d74 <___vfprintf_internal_r+0x110> - 4d0c: 00800084 movi r2,2 - 4d10: 003fef06 br 4cd0 <___vfprintf_internal_r+0x6c> - 4d14: 29400960 cmpeqi r5,r5,37 - 4d18: 2800f61e bne r5,zero,50f4 <___vfprintf_internal_r+0x490> - 4d1c: b8800117 ldw r2,4(r23) - 4d20: d9000805 stb r4,32(sp) - 4d24: 01c00044 movi r7,1 - 4d28: d9800804 addi r6,sp,32 - 4d2c: b80b883a mov r5,r23 - 4d30: 8009883a mov r4,r16 - 4d34: 103ee83a callr r2 - 4d38: 10001b26 beq r2,zero,4da8 <___vfprintf_internal_r+0x144> - 4d3c: 05bfffc4 movi r22,-1 - 4d40: b005883a mov r2,r22 - 4d44: dfc01917 ldw ra,100(sp) - 4d48: df001817 ldw fp,96(sp) - 4d4c: ddc01717 ldw r23,92(sp) - 4d50: dd801617 ldw r22,88(sp) - 4d54: dd401517 ldw r21,84(sp) - 4d58: dd001417 ldw r20,80(sp) - 4d5c: dcc01317 ldw r19,76(sp) - 4d60: dc801217 ldw r18,72(sp) - 4d64: dc401117 ldw r17,68(sp) - 4d68: dc001017 ldw r16,64(sp) - 4d6c: dec01a04 addi sp,sp,104 - 4d70: f800283a ret - 4d74: 28800c20 cmpeqi r2,r5,48 - 4d78: 1000e71e bne r2,zero,5118 <___vfprintf_internal_r+0x4b4> - 4d7c: 28800958 cmpnei r2,r5,37 - 4d80: 103fe626 beq r2,zero,4d1c <___vfprintf_internal_r+0xb8> - 4d84: 20bff404 addi r2,r4,-48 - 4d88: 10803fcc andi r2,r2,255 - 4d8c: 118002a8 cmpgeui r6,r2,10 - 4d90: 3000091e bne r6,zero,4db8 <___vfprintf_internal_r+0x154> - 4d94: 893fffe0 cmpeqi r4,r17,-1 - 4d98: 2000051e bne r4,zero,4db0 <___vfprintf_internal_r+0x14c> - 4d9c: 8c4002a4 muli r17,r17,10 - 4da0: 1463883a add r17,r2,r17 - 4da4: 003fd906 br 4d0c <___vfprintf_internal_r+0xa8> - 4da8: b5800044 addi r22,r22,1 - 4dac: 003fc806 br 4cd0 <___vfprintf_internal_r+0x6c> - 4db0: 0023883a mov r17,zero - 4db4: 003ffa06 br 4da0 <___vfprintf_internal_r+0x13c> - 4db8: 28800ba0 cmpeqi r2,r5,46 - 4dbc: 1000db1e bne r2,zero,512c <___vfprintf_internal_r+0x4c8> - 4dc0: 00800084 movi r2,2 - 4dc4: 213ff404 addi r4,r4,-48 - 4dc8: 21003fcc andi r4,r4,255 - 4dcc: 218002a8 cmpgeui r6,r4,10 - 4dd0: 3000071e bne r6,zero,4df0 <___vfprintf_internal_r+0x18c> - 4dd4: 917fffe0 cmpeqi r5,r18,-1 - 4dd8: 2800031e bne r5,zero,4de8 <___vfprintf_internal_r+0x184> - 4ddc: 948002a4 muli r18,r18,10 - 4de0: 24a5883a add r18,r4,r18 - 4de4: 003fba06 br 4cd0 <___vfprintf_internal_r+0x6c> - 4de8: 0025883a mov r18,zero - 4dec: 003ffc06 br 4de0 <___vfprintf_internal_r+0x17c> - 4df0: 28801b20 cmpeqi r2,r5,108 - 4df4: 1000cb1e bne r2,zero,5124 <___vfprintf_internal_r+0x4c0> - 4df8: 90bfffe0 cmpeqi r2,r18,-1 - 4dfc: 10000f1e bne r2,zero,4e3c <___vfprintf_internal_r+0x1d8> - 4e00: d8000015 stw zero,0(sp) - 4e04: 28801be0 cmpeqi r2,r5,111 - 4e08: 1000ca1e bne r2,zero,5134 <___vfprintf_internal_r+0x4d0> - 4e0c: 28801c08 cmpgei r2,r5,112 - 4e10: 1000171e bne r2,zero,4e70 <___vfprintf_internal_r+0x20c> - 4e14: 288018e0 cmpeqi r2,r5,99 - 4e18: 10009f1e bne r2,zero,5098 <___vfprintf_internal_r+0x434> - 4e1c: 28801908 cmpgei r2,r5,100 - 4e20: 1000081e bne r2,zero,4e44 <___vfprintf_internal_r+0x1e0> - 4e24: 29401620 cmpeqi r5,r5,88 - 4e28: 283fa526 beq r5,zero,4cc0 <___vfprintf_internal_r+0x5c> - 4e2c: 00800044 movi r2,1 - 4e30: d8800215 stw r2,8(sp) - 4e34: 05000404 movi r20,16 - 4e38: 0000bf06 br 5138 <___vfprintf_internal_r+0x4d4> - 4e3c: 04800044 movi r18,1 - 4e40: 003ff006 br 4e04 <___vfprintf_internal_r+0x1a0> - 4e44: 28801920 cmpeqi r2,r5,100 - 4e48: 1000021e bne r2,zero,4e54 <___vfprintf_internal_r+0x1f0> - 4e4c: 29401a60 cmpeqi r5,r5,105 - 4e50: 283f9b26 beq r5,zero,4cc0 <___vfprintf_internal_r+0x5c> - 4e54: e0800104 addi r2,fp,4 - 4e58: d8800415 stw r2,16(sp) - 4e5c: 9800b626 beq r19,zero,5138 <___vfprintf_internal_r+0x4d4> - 4e60: e5400017 ldw r21,0(fp) - 4e64: a8002216 blt r21,zero,4ef0 <___vfprintf_internal_r+0x28c> - 4e68: 04c00044 movi r19,1 - 4e6c: 0000b606 br 5148 <___vfprintf_internal_r+0x4e4> - 4e70: 28801d60 cmpeqi r2,r5,117 - 4e74: 1000b01e bne r2,zero,5138 <___vfprintf_internal_r+0x4d4> - 4e78: 28801e20 cmpeqi r2,r5,120 - 4e7c: 103fed1e bne r2,zero,4e34 <___vfprintf_internal_r+0x1d0> - 4e80: 29401ce0 cmpeqi r5,r5,115 - 4e84: 283f8e26 beq r5,zero,4cc0 <___vfprintf_internal_r+0x5c> - 4e88: e5400017 ldw r21,0(fp) - 4e8c: e0800104 addi r2,fp,4 - 4e90: d8800315 stw r2,12(sp) - 4e94: a809883a mov r4,r21 - 4e98: 0004bdc0 call 4bdc - 4e9c: 888fc83a sub r7,r17,r2 - 4ea0: 1039883a mov fp,r2 - 4ea4: 01c0080e bge zero,r7,4ec8 <___vfprintf_internal_r+0x264> - 4ea8: 01800804 movi r6,32 - 4eac: b80b883a mov r5,r23 - 4eb0: 8009883a mov r4,r16 - 4eb4: d9c00415 stw r7,16(sp) - 4eb8: 0004bf80 call 4bf8 - 4ebc: 103f9f1e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 4ec0: d9c00417 ldw r7,16(sp) - 4ec4: b1ed883a add r22,r22,r7 - 4ec8: b8800117 ldw r2,4(r23) - 4ecc: e00f883a mov r7,fp - 4ed0: a80d883a mov r6,r21 - 4ed4: b80b883a mov r5,r23 - 4ed8: 8009883a mov r4,r16 - 4edc: 103ee83a callr r2 - 4ee0: 103f961e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 4ee4: b72d883a add r22,r22,fp - 4ee8: df000317 ldw fp,12(sp) - 4eec: 003f7806 br 4cd0 <___vfprintf_internal_r+0x6c> - 4ef0: 056bc83a sub r21,zero,r21 - 4ef4: 04c00044 movi r19,1 - 4ef8: 00c00044 movi r3,1 - 4efc: df000804 addi fp,sp,32 - 4f00: e00d883a mov r6,fp - 4f04: a8002e1e bne r21,zero,4fc0 <___vfprintf_internal_r+0x35c> - 4f08: e185c83a sub r2,fp,r6 - 4f0c: d8800315 stw r2,12(sp) - 4f10: 9085c83a sub r2,r18,r2 - 4f14: 0080090e bge zero,r2,4f3c <___vfprintf_internal_r+0x2d8> - 4f18: e085883a add r2,fp,r2 - 4f1c: d9001004 addi r4,sp,64 - 4f20: e100042e bgeu fp,r4,4f34 <___vfprintf_internal_r+0x2d0> - 4f24: e7000044 addi fp,fp,1 - 4f28: 01000c04 movi r4,48 - 4f2c: e13fffc5 stb r4,-1(fp) - 4f30: e0bffa1e bne fp,r2,4f1c <___vfprintf_internal_r+0x2b8> - 4f34: e185c83a sub r2,fp,r6 - 4f38: d8800315 stw r2,12(sp) - 4f3c: d8800317 ldw r2,12(sp) - 4f40: 1897883a add r11,r3,r2 - 4f44: d8800017 ldw r2,0(sp) - 4f48: 8aebc83a sub r21,r17,r11 - 4f4c: 10003126 beq r2,zero,5014 <___vfprintf_internal_r+0x3b0> - 4f50: 18000a26 beq r3,zero,4f7c <___vfprintf_internal_r+0x318> - 4f54: 00800b44 movi r2,45 - 4f58: d88007c5 stb r2,31(sp) - 4f5c: b8800117 ldw r2,4(r23) - 4f60: 01c00044 movi r7,1 - 4f64: d98007c4 addi r6,sp,31 - 4f68: b80b883a mov r5,r23 - 4f6c: 8009883a mov r4,r16 - 4f70: 103ee83a callr r2 - 4f74: 103f711e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 4f78: b5800044 addi r22,r22,1 - 4f7c: 0540070e bge zero,r21,4f9c <___vfprintf_internal_r+0x338> - 4f80: a80f883a mov r7,r21 - 4f84: 01800c04 movi r6,48 - 4f88: b80b883a mov r5,r23 - 4f8c: 8009883a mov r4,r16 - 4f90: 0004bf80 call 4bf8 - 4f94: 103f691e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 4f98: b56d883a add r22,r22,r21 - 4f9c: d8800317 ldw r2,12(sp) - 4fa0: b72d883a add r22,r22,fp - 4fa4: 172bc83a sub r21,r2,fp - 4fa8: af05883a add r2,r21,fp - 4fac: b707c83a sub r3,r22,fp - 4fb0: 00802e16 blt zero,r2,506c <___vfprintf_internal_r+0x408> - 4fb4: df000417 ldw fp,16(sp) - 4fb8: 182d883a mov r22,r3 - 4fbc: 003f4006 br 4cc0 <___vfprintf_internal_r+0x5c> - 4fc0: a809883a mov r4,r21 - 4fc4: a00b883a mov r5,r20 - 4fc8: d8c00315 stw r3,12(sp) - 4fcc: 00034000 call 3400 <__udivsi3> - 4fd0: 1509383a mul r4,r2,r20 - 4fd4: d8c00317 ldw r3,12(sp) - 4fd8: d9800804 addi r6,sp,32 - 4fdc: a92bc83a sub r21,r21,r4 - 4fe0: a9000288 cmpgei r4,r21,10 - 4fe4: 2000051e bne r4,zero,4ffc <___vfprintf_internal_r+0x398> - 4fe8: ad400c04 addi r21,r21,48 - 4fec: e7000044 addi fp,fp,1 - 4ff0: e57fffc5 stb r21,-1(fp) - 4ff4: 102b883a mov r21,r2 - 4ff8: 003fc206 br 4f04 <___vfprintf_internal_r+0x2a0> - 4ffc: d9000217 ldw r4,8(sp) - 5000: 20000226 beq r4,zero,500c <___vfprintf_internal_r+0x3a8> - 5004: ad400dc4 addi r21,r21,55 - 5008: 003ff806 br 4fec <___vfprintf_internal_r+0x388> - 500c: ad4015c4 addi r21,r21,87 - 5010: 003ff606 br 4fec <___vfprintf_internal_r+0x388> - 5014: 0540090e bge zero,r21,503c <___vfprintf_internal_r+0x3d8> - 5018: a80f883a mov r7,r21 - 501c: 01800804 movi r6,32 - 5020: b80b883a mov r5,r23 - 5024: 8009883a mov r4,r16 - 5028: d8c00615 stw r3,24(sp) - 502c: 0004bf80 call 4bf8 - 5030: 103f421e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 5034: d8c00617 ldw r3,24(sp) - 5038: b56d883a add r22,r22,r21 - 503c: 183fd726 beq r3,zero,4f9c <___vfprintf_internal_r+0x338> - 5040: 00800b44 movi r2,45 - 5044: d88007c5 stb r2,31(sp) - 5048: b8800117 ldw r2,4(r23) - 504c: 01c00044 movi r7,1 - 5050: d98007c4 addi r6,sp,31 - 5054: b80b883a mov r5,r23 - 5058: 8009883a mov r4,r16 - 505c: 103ee83a callr r2 - 5060: 103f361e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 5064: b5800044 addi r22,r22,1 - 5068: 003fcc06 br 4f9c <___vfprintf_internal_r+0x338> - 506c: e0bfffc3 ldbu r2,-1(fp) - 5070: 01c00044 movi r7,1 - 5074: d98007c4 addi r6,sp,31 - 5078: d88007c5 stb r2,31(sp) - 507c: b8800117 ldw r2,4(r23) - 5080: b80b883a mov r5,r23 - 5084: 8009883a mov r4,r16 - 5088: e73fffc4 addi fp,fp,-1 - 508c: 103ee83a callr r2 - 5090: 103fc526 beq r2,zero,4fa8 <___vfprintf_internal_r+0x344> - 5094: 003f2906 br 4d3c <___vfprintf_internal_r+0xd8> - 5098: 88800090 cmplti r2,r17,2 - 509c: 1000081e bne r2,zero,50c0 <___vfprintf_internal_r+0x45c> - 50a0: 8d7fffc4 addi r21,r17,-1 - 50a4: a80f883a mov r7,r21 - 50a8: 01800804 movi r6,32 - 50ac: b80b883a mov r5,r23 - 50b0: 8009883a mov r4,r16 - 50b4: 0004bf80 call 4bf8 - 50b8: 103f201e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 50bc: b56d883a add r22,r22,r21 - 50c0: e0800017 ldw r2,0(fp) - 50c4: 01c00044 movi r7,1 - 50c8: d9800804 addi r6,sp,32 - 50cc: d8800805 stb r2,32(sp) - 50d0: b8800117 ldw r2,4(r23) - 50d4: b80b883a mov r5,r23 - 50d8: 8009883a mov r4,r16 - 50dc: e5400104 addi r21,fp,4 - 50e0: 103ee83a callr r2 - 50e4: 103f151e bne r2,zero,4d3c <___vfprintf_internal_r+0xd8> - 50e8: b5800044 addi r22,r22,1 - 50ec: a839883a mov fp,r21 - 50f0: 003ef706 br 4cd0 <___vfprintf_internal_r+0x6c> - 50f4: d8000215 stw zero,8(sp) - 50f8: d8000115 stw zero,4(sp) - 50fc: d8000015 stw zero,0(sp) - 5100: 04c00044 movi r19,1 - 5104: 05000284 movi r20,10 - 5108: 04bfffc4 movi r18,-1 - 510c: 047fffc4 movi r17,-1 - 5110: 00800044 movi r2,1 - 5114: 003eee06 br 4cd0 <___vfprintf_internal_r+0x6c> - 5118: 00800044 movi r2,1 - 511c: d8800015 stw r2,0(sp) - 5120: 003efa06 br 4d0c <___vfprintf_internal_r+0xa8> - 5124: 00800044 movi r2,1 - 5128: d8800115 stw r2,4(sp) - 512c: 008000c4 movi r2,3 - 5130: 003ee706 br 4cd0 <___vfprintf_internal_r+0x6c> - 5134: 05000204 movi r20,8 - 5138: e0800104 addi r2,fp,4 - 513c: d8800415 stw r2,16(sp) - 5140: e5400017 ldw r21,0(fp) - 5144: 0027883a mov r19,zero - 5148: 0007883a mov r3,zero - 514c: 003f6b06 br 4efc <___vfprintf_internal_r+0x298> - -00005150 <__vfprintf_internal>: - 5150: 00800074 movhi r2,1 - 5154: 300f883a mov r7,r6 - 5158: 280d883a mov r6,r5 - 515c: 200b883a mov r5,r4 - 5160: 11266f17 ldw r4,-26180(r2) - 5164: 0004c641 jmpi 4c64 <___vfprintf_internal_r> - -00005168 <__sfvwrite_small_dev>: - 5168: 2880000b ldhu r2,0(r5) - 516c: 1080020c andi r2,r2,8 - 5170: 10002526 beq r2,zero,5208 <__sfvwrite_small_dev+0xa0> - 5174: 2880008f ldh r2,2(r5) - 5178: defffb04 addi sp,sp,-20 - 517c: dcc00315 stw r19,12(sp) - 5180: dc800215 stw r18,8(sp) - 5184: dc400115 stw r17,4(sp) - 5188: dc000015 stw r16,0(sp) - 518c: dfc00415 stw ra,16(sp) - 5190: 2027883a mov r19,r4 - 5194: 2821883a mov r16,r5 - 5198: 3025883a mov r18,r6 - 519c: 3823883a mov r17,r7 - 51a0: 1000100e bge r2,zero,51e4 <__sfvwrite_small_dev+0x7c> - 51a4: 8080000b ldhu r2,0(r16) - 51a8: 10801014 ori r2,r2,64 - 51ac: 8080000d sth r2,0(r16) - 51b0: 00bfffc4 movi r2,-1 - 51b4: 00000d06 br 51ec <__sfvwrite_small_dev+0x84> - 51b8: 88810050 cmplti r2,r17,1025 - 51bc: 880f883a mov r7,r17 - 51c0: 1000011e bne r2,zero,51c8 <__sfvwrite_small_dev+0x60> - 51c4: 01c10004 movi r7,1024 - 51c8: 8140008f ldh r5,2(r16) - 51cc: 900d883a mov r6,r18 - 51d0: 9809883a mov r4,r19 - 51d4: 00052b40 call 52b4 <_write_r> - 51d8: 00bff20e bge zero,r2,51a4 <__sfvwrite_small_dev+0x3c> - 51dc: 88a3c83a sub r17,r17,r2 - 51e0: 90a5883a add r18,r18,r2 - 51e4: 047ff416 blt zero,r17,51b8 <__sfvwrite_small_dev+0x50> - 51e8: 0005883a mov r2,zero - 51ec: dfc00417 ldw ra,16(sp) - 51f0: dcc00317 ldw r19,12(sp) - 51f4: dc800217 ldw r18,8(sp) - 51f8: dc400117 ldw r17,4(sp) - 51fc: dc000017 ldw r16,0(sp) - 5200: dec00504 addi sp,sp,20 - 5204: f800283a ret - 5208: 00bfffc4 movi r2,-1 - 520c: f800283a ret - -00005210 : - 5210: defffd04 addi sp,sp,-12 - 5214: 00800034 movhi r2,0 - 5218: dc000115 stw r16,4(sp) - 521c: dfc00215 stw ra,8(sp) - 5220: 10945a04 addi r2,r2,20840 - 5224: 28800115 stw r2,4(r5) - 5228: 00800074 movhi r2,1 - 522c: d90000c5 stb r4,3(sp) - 5230: 2021883a mov r16,r4 - 5234: 11266f17 ldw r4,-26180(r2) - 5238: 01c00044 movi r7,1 - 523c: d98000c4 addi r6,sp,3 - 5240: 00051680 call 5168 <__sfvwrite_small_dev> - 5244: 10ffffe0 cmpeqi r3,r2,-1 - 5248: 1800011e bne r3,zero,5250 - 524c: 8005883a mov r2,r16 - 5250: dfc00217 ldw ra,8(sp) - 5254: dc000117 ldw r16,4(sp) - 5258: dec00304 addi sp,sp,12 - 525c: f800283a ret - -00005260 <_putc_r>: - 5260: defffd04 addi sp,sp,-12 - 5264: 00800034 movhi r2,0 - 5268: dc000115 stw r16,4(sp) - 526c: dfc00215 stw ra,8(sp) - 5270: 10945a04 addi r2,r2,20840 - 5274: 30800115 stw r2,4(r6) - 5278: 00800074 movhi r2,1 - 527c: 11266f17 ldw r4,-26180(r2) - 5280: 2821883a mov r16,r5 - 5284: 01c00044 movi r7,1 - 5288: 300b883a mov r5,r6 - 528c: d98000c4 addi r6,sp,3 - 5290: dc0000c5 stb r16,3(sp) - 5294: 00051680 call 5168 <__sfvwrite_small_dev> - 5298: 10ffffe0 cmpeqi r3,r2,-1 - 529c: 1800011e bne r3,zero,52a4 <_putc_r+0x44> - 52a0: 8005883a mov r2,r16 - 52a4: dfc00217 ldw ra,8(sp) - 52a8: dc000117 ldw r16,4(sp) - 52ac: dec00304 addi sp,sp,12 - 52b0: f800283a ret - -000052b4 <_write_r>: - 52b4: defffe04 addi sp,sp,-8 - 52b8: dc000015 stw r16,0(sp) - 52bc: 00800074 movhi r2,1 - 52c0: 2021883a mov r16,r4 - 52c4: 2809883a mov r4,r5 - 52c8: 300b883a mov r5,r6 - 52cc: 380d883a mov r6,r7 - 52d0: dfc00115 stw ra,4(sp) - 52d4: 10274a15 stw zero,-25304(r2) - 52d8: 00056dc0 call 56dc - 52dc: 10ffffd8 cmpnei r3,r2,-1 - 52e0: 1800041e bne r3,zero,52f4 <_write_r+0x40> - 52e4: 00c00074 movhi r3,1 - 52e8: 18e74a17 ldw r3,-25304(r3) - 52ec: 18000126 beq r3,zero,52f4 <_write_r+0x40> - 52f0: 80c00015 stw r3,0(r16) - 52f4: dfc00117 ldw ra,4(sp) - 52f8: dc000017 ldw r16,0(sp) - 52fc: dec00204 addi sp,sp,8 - 5300: f800283a ret - -00005304 : - 5304: defffe04 addi sp,sp,-8 - 5308: df000115 stw fp,4(sp) - 530c: df000104 addi fp,sp,4 - 5310: e03fff15 stw zero,-4(fp) - 5314: 00000506 br 532c - 5318: e0bfff17 ldw r2,-4(fp) - 531c: 1000003b flushd 0(r2) - 5320: e0bfff17 ldw r2,-4(fp) - 5324: 10800804 addi r2,r2,32 - 5328: e0bfff15 stw r2,-4(fp) - 532c: e0bfff17 ldw r2,-4(fp) - 5330: 10820030 cmpltui r2,r2,2048 - 5334: 103ff81e bne r2,zero,5318 - 5338: 0001883a nop - 533c: 0001883a nop - 5340: e037883a mov sp,fp - 5344: df000017 ldw fp,0(sp) - 5348: dec00104 addi sp,sp,4 - 534c: f800283a ret - -00005350 : - 5350: defffc04 addi sp,sp,-16 - 5354: df000315 stw fp,12(sp) - 5358: df000304 addi fp,sp,12 - 535c: e13fff15 stw r4,-4(fp) - 5360: e17ffe15 stw r5,-8(fp) - 5364: e1bffd15 stw r6,-12(fp) - 5368: e0fffe17 ldw r3,-8(fp) - 536c: e0bfff17 ldw r2,-4(fp) - 5370: 18800c26 beq r3,r2,53a4 - 5374: 00000806 br 5398 - 5378: e0ffff17 ldw r3,-4(fp) - 537c: 18800104 addi r2,r3,4 - 5380: e0bfff15 stw r2,-4(fp) - 5384: e0bffe17 ldw r2,-8(fp) - 5388: 11000104 addi r4,r2,4 - 538c: e13ffe15 stw r4,-8(fp) - 5390: 18c00017 ldw r3,0(r3) - 5394: 10c00015 stw r3,0(r2) - 5398: e0fffe17 ldw r3,-8(fp) - 539c: e0bffd17 ldw r2,-12(fp) - 53a0: 18bff51e bne r3,r2,5378 - 53a4: 0001883a nop - 53a8: e037883a mov sp,fp - 53ac: df000017 ldw fp,0(sp) - 53b0: dec00104 addi sp,sp,4 - 53b4: f800283a ret - -000053b8 : - 53b8: defffe04 addi sp,sp,-8 - 53bc: dfc00115 stw ra,4(sp) - 53c0: df000015 stw fp,0(sp) - 53c4: d839883a mov fp,sp - 53c8: 01800074 movhi r6,1 - 53cc: 31a67b04 addi r6,r6,-26132 - 53d0: 01400074 movhi r5,1 - 53d4: 2965af04 addi r5,r5,-26948 - 53d8: 01000074 movhi r4,1 - 53dc: 21267b04 addi r4,r4,-26132 - 53e0: 00053500 call 5350 - 53e4: 01800034 movhi r6,0 - 53e8: 31808e04 addi r6,r6,568 - 53ec: 01400034 movhi r5,0 - 53f0: 29400804 addi r5,r5,32 - 53f4: 01000034 movhi r4,0 - 53f8: 21000804 addi r4,r4,32 - 53fc: 00053500 call 5350 - 5400: 01800074 movhi r6,1 - 5404: 31a5af04 addi r6,r6,-26948 - 5408: 01400074 movhi r5,1 - 540c: 2962fa04 addi r5,r5,-29720 - 5410: 01000074 movhi r4,1 - 5414: 2122fa04 addi r4,r4,-29720 - 5418: 00053500 call 5350 - 541c: 00053040 call 5304 - 5420: 0007ce00 call 7ce0 - 5424: 0001883a nop - 5428: e037883a mov sp,fp - 542c: dfc00117 ldw ra,4(sp) - 5430: df000017 ldw fp,0(sp) - 5434: dec00204 addi sp,sp,8 - 5438: f800283a ret - -0000543c : - 543c: defffd04 addi sp,sp,-12 - 5440: dfc00215 stw ra,8(sp) - 5444: df000115 stw fp,4(sp) - 5448: df000104 addi fp,sp,4 - 544c: 0009883a mov r4,zero - 5450: 000580c0 call 580c - 5454: 0001883a nop - 5458: 00058480 call 5848 - 545c: 01800074 movhi r6,1 - 5460: 31a59804 addi r6,r6,-27040 - 5464: 01400074 movhi r5,1 - 5468: 29659804 addi r5,r5,-27040 - 546c: 01000074 movhi r4,1 - 5470: 21259804 addi r4,r4,-27040 - 5474: 00080740 call 8074 - 5478: 0007b880 call 7b88 <_do_ctors> - 547c: 01000034 movhi r4,0 - 5480: 211efb04 addi r4,r4,31724 - 5484: 00089040 call 8904 - 5488: d0a0e017 ldw r2,-31872(gp) - 548c: d0e0e117 ldw r3,-31868(gp) - 5490: d120e217 ldw r4,-31864(gp) - 5494: 200d883a mov r6,r4 - 5498: 180b883a mov r5,r3 - 549c: 1009883a mov r4,r2 - 54a0: 0001a3c0 call 1a3c
- 54a4: e0bfff15 stw r2,-4(fp) - 54a8: 01000044 movi r4,1 - 54ac: 000799c0 call 799c - 54b0: e13fff17 ldw r4,-4(fp) - 54b4: 00089180 call 8918 - -000054b8 : - 54b8: defffa04 addi sp,sp,-24 - 54bc: df000515 stw fp,20(sp) - 54c0: df000504 addi fp,sp,20 - 54c4: e13ffb15 stw r4,-20(fp) - 54c8: 0005303a rdctl r2,status - 54cc: e0bffc15 stw r2,-16(fp) - 54d0: e0fffc17 ldw r3,-16(fp) - 54d4: 00bfff84 movi r2,-2 - 54d8: 1884703a and r2,r3,r2 - 54dc: 1001703a wrctl status,r2 - 54e0: e0bffc17 ldw r2,-16(fp) - 54e4: e0bfff15 stw r2,-4(fp) - 54e8: e0bffb17 ldw r2,-20(fp) - 54ec: e0bffd15 stw r2,-12(fp) - 54f0: e0bffd17 ldw r2,-12(fp) - 54f4: 10800017 ldw r2,0(r2) - 54f8: e0fffd17 ldw r3,-12(fp) - 54fc: 18c00117 ldw r3,4(r3) - 5500: 10c00115 stw r3,4(r2) - 5504: e0bffd17 ldw r2,-12(fp) - 5508: 10800117 ldw r2,4(r2) - 550c: e0fffd17 ldw r3,-12(fp) - 5510: 18c00017 ldw r3,0(r3) - 5514: 10c00015 stw r3,0(r2) - 5518: e0bffd17 ldw r2,-12(fp) - 551c: e0fffd17 ldw r3,-12(fp) - 5520: 10c00115 stw r3,4(r2) - 5524: e0bffd17 ldw r2,-12(fp) - 5528: e0fffd17 ldw r3,-12(fp) - 552c: 10c00015 stw r3,0(r2) - 5530: 0001883a nop - 5534: e0bfff17 ldw r2,-4(fp) - 5538: e0bffe15 stw r2,-8(fp) - 553c: e0bffe17 ldw r2,-8(fp) - 5540: 1001703a wrctl status,r2 - 5544: 0001883a nop - 5548: 0001883a nop - 554c: e037883a mov sp,fp - 5550: df000017 ldw fp,0(sp) - 5554: dec00104 addi sp,sp,4 - 5558: f800283a ret - -0000555c : - 555c: defffb04 addi sp,sp,-20 - 5560: dfc00415 stw ra,16(sp) - 5564: df000315 stw fp,12(sp) - 5568: df000304 addi fp,sp,12 - 556c: d0a00517 ldw r2,-32748(gp) - 5570: e0bfff15 stw r2,-4(fp) - 5574: d0a0e417 ldw r2,-31856(gp) - 5578: 10800044 addi r2,r2,1 - 557c: d0a0e415 stw r2,-31856(gp) - 5580: 00002e06 br 563c - 5584: e0bfff17 ldw r2,-4(fp) - 5588: 10800017 ldw r2,0(r2) - 558c: e0bffe15 stw r2,-8(fp) - 5590: e0bfff17 ldw r2,-4(fp) - 5594: 10800403 ldbu r2,16(r2) - 5598: 10803fcc andi r2,r2,255 - 559c: 10000426 beq r2,zero,55b0 - 55a0: d0a0e417 ldw r2,-31856(gp) - 55a4: 1000021e bne r2,zero,55b0 - 55a8: e0bfff17 ldw r2,-4(fp) - 55ac: 10000405 stb zero,16(r2) - 55b0: e0bfff17 ldw r2,-4(fp) - 55b4: 10800217 ldw r2,8(r2) - 55b8: d0e0e417 ldw r3,-31856(gp) - 55bc: 18801d36 bltu r3,r2,5634 - 55c0: e0bfff17 ldw r2,-4(fp) - 55c4: 10800403 ldbu r2,16(r2) - 55c8: 10803fcc andi r2,r2,255 - 55cc: 1000191e bne r2,zero,5634 - 55d0: e0bfff17 ldw r2,-4(fp) - 55d4: 10800317 ldw r2,12(r2) - 55d8: e0ffff17 ldw r3,-4(fp) - 55dc: 18c00517 ldw r3,20(r3) - 55e0: 1809883a mov r4,r3 - 55e4: 103ee83a callr r2 - 55e8: e0bffd15 stw r2,-12(fp) - 55ec: e0bffd17 ldw r2,-12(fp) - 55f0: 1000031e bne r2,zero,5600 - 55f4: e13fff17 ldw r4,-4(fp) - 55f8: 00054b80 call 54b8 - 55fc: 00000d06 br 5634 - 5600: e0bfff17 ldw r2,-4(fp) - 5604: 10c00217 ldw r3,8(r2) - 5608: e0bffd17 ldw r2,-12(fp) - 560c: 1887883a add r3,r3,r2 - 5610: e0bfff17 ldw r2,-4(fp) - 5614: 10c00215 stw r3,8(r2) - 5618: e0bfff17 ldw r2,-4(fp) - 561c: 10c00217 ldw r3,8(r2) - 5620: d0a0e417 ldw r2,-31856(gp) - 5624: 1880032e bgeu r3,r2,5634 - 5628: e0bfff17 ldw r2,-4(fp) - 562c: 00c00044 movi r3,1 - 5630: 10c00405 stb r3,16(r2) - 5634: e0bffe17 ldw r2,-8(fp) - 5638: e0bfff15 stw r2,-4(fp) - 563c: e0ffff17 ldw r3,-4(fp) - 5640: d0a00504 addi r2,gp,-32748 - 5644: 18bfcf1e bne r3,r2,5584 - 5648: 0001883a nop - 564c: 0001883a nop - 5650: e037883a mov sp,fp - 5654: dfc00117 ldw ra,4(sp) - 5658: df000017 ldw fp,0(sp) - 565c: dec00204 addi sp,sp,8 - 5660: f800283a ret - -00005664 : - 5664: defffd04 addi sp,sp,-12 - 5668: dfc00215 stw ra,8(sp) - 566c: df000115 stw fp,4(sp) - 5670: df000104 addi fp,sp,4 - 5674: e13fff15 stw r4,-4(fp) - 5678: e13fff17 ldw r4,-4(fp) - 567c: 00077fc0 call 77fc - 5680: e037883a mov sp,fp - 5684: dfc00117 ldw ra,4(sp) - 5688: df000017 ldw fp,0(sp) - 568c: dec00204 addi sp,sp,8 - 5690: f800283a ret - -00005694 : - 5694: defffe04 addi sp,sp,-8 - 5698: dfc00115 stw ra,4(sp) - 569c: df000015 stw fp,0(sp) - 56a0: d839883a mov fp,sp - 56a4: 00800074 movhi r2,1 - 56a8: 10a67917 ldw r2,-26140(r2) - 56ac: 10000426 beq r2,zero,56c0 - 56b0: 00800074 movhi r2,1 - 56b4: 10a67917 ldw r2,-26140(r2) - 56b8: 103ee83a callr r2 - 56bc: 00000206 br 56c8 - 56c0: 00800074 movhi r2,1 - 56c4: 10a74a04 addi r2,r2,-25304 - 56c8: e037883a mov sp,fp - 56cc: dfc00117 ldw ra,4(sp) - 56d0: df000017 ldw fp,0(sp) - 56d4: dec00204 addi sp,sp,8 - 56d8: f800283a ret - -000056dc : - 56dc: defff904 addi sp,sp,-28 - 56e0: dfc00615 stw ra,24(sp) - 56e4: df000515 stw fp,20(sp) - 56e8: df000504 addi fp,sp,20 - 56ec: e13ffd15 stw r4,-12(fp) - 56f0: e17ffc15 stw r5,-16(fp) - 56f4: e1bffb15 stw r6,-20(fp) - 56f8: e0bffd17 ldw r2,-12(fp) - 56fc: 10000616 blt r2,zero,5718 - 5700: e0bffd17 ldw r2,-12(fp) - 5704: 10c00324 muli r3,r2,12 - 5708: 00800074 movhi r2,1 - 570c: 10a60b04 addi r2,r2,-26580 - 5710: 1885883a add r2,r3,r2 - 5714: 00000106 br 571c - 5718: 0005883a mov r2,zero - 571c: e0bfff15 stw r2,-4(fp) - 5720: e0bfff17 ldw r2,-4(fp) - 5724: 10002126 beq r2,zero,57ac - 5728: e0bfff17 ldw r2,-4(fp) - 572c: 10800217 ldw r2,8(r2) - 5730: 108000cc andi r2,r2,3 - 5734: 10001826 beq r2,zero,5798 - 5738: e0bfff17 ldw r2,-4(fp) - 573c: 10800017 ldw r2,0(r2) - 5740: 10800617 ldw r2,24(r2) - 5744: 10001426 beq r2,zero,5798 - 5748: e0bfff17 ldw r2,-4(fp) - 574c: 10800017 ldw r2,0(r2) - 5750: 10800617 ldw r2,24(r2) - 5754: e0fffb17 ldw r3,-20(fp) - 5758: 180d883a mov r6,r3 - 575c: e17ffc17 ldw r5,-16(fp) - 5760: e13fff17 ldw r4,-4(fp) - 5764: 103ee83a callr r2 - 5768: e0bffe15 stw r2,-8(fp) - 576c: e0bffe17 ldw r2,-8(fp) - 5770: 1000070e bge r2,zero,5790 - 5774: 00056940 call 5694 - 5778: 1007883a mov r3,r2 - 577c: e0bffe17 ldw r2,-8(fp) - 5780: 0085c83a sub r2,zero,r2 - 5784: 18800015 stw r2,0(r3) - 5788: 00bfffc4 movi r2,-1 - 578c: 00000c06 br 57c0 - 5790: e0bffe17 ldw r2,-8(fp) - 5794: 00000a06 br 57c0 - 5798: 00056940 call 5694 - 579c: 1007883a mov r3,r2 - 57a0: 00800344 movi r2,13 - 57a4: 18800015 stw r2,0(r3) - 57a8: 00000406 br 57bc - 57ac: 00056940 call 5694 - 57b0: 1007883a mov r3,r2 - 57b4: 00801444 movi r2,81 - 57b8: 18800015 stw r2,0(r3) - 57bc: 00bfffc4 movi r2,-1 - 57c0: e037883a mov sp,fp - 57c4: dfc00117 ldw ra,4(sp) - 57c8: df000017 ldw fp,0(sp) - 57cc: dec00204 addi sp,sp,8 - 57d0: f800283a ret - -000057d4 : - 57d4: defffd04 addi sp,sp,-12 - 57d8: dfc00215 stw ra,8(sp) - 57dc: df000115 stw fp,4(sp) - 57e0: df000104 addi fp,sp,4 - 57e4: e13fff15 stw r4,-4(fp) - 57e8: 01400074 movhi r5,1 - 57ec: 29667604 addi r5,r5,-26152 - 57f0: e13fff17 ldw r4,-4(fp) - 57f4: 0007ae00 call 7ae0 - 57f8: e037883a mov sp,fp - 57fc: dfc00117 ldw ra,4(sp) - 5800: df000017 ldw fp,0(sp) - 5804: dec00204 addi sp,sp,8 + 477c: 18002626 beq r3,zero,4818 <__adddf3+0x260> + 4780: 1487c83a sub r3,r2,r18 + 4784: 9000ba1e bne r18,zero,4a70 <__adddf3+0x4b8> + 4788: 5388b03a or r4,r10,r14 + 478c: 20011826 beq r4,zero,4bf0 <__adddf3+0x638> + 4790: 193fffc4 addi r4,r3,-1 + 4794: 20015726 beq r4,zero,4cf4 <__adddf3+0x73c> + 4798: 18c1ffd8 cmpnei r3,r3,2047 + 479c: 18013026 beq r3,zero,4c60 <__adddf3+0x6a8> + 47a0: 2007883a mov r3,r4 + 47a4: 0000b506 br 4a7c <__adddf3+0x4c4> + 47a8: 00c07b0e bge zero,r3,4998 <__adddf3+0x3e0> + 47ac: 10002e26 beq r2,zero,4868 <__adddf3+0x2b0> + 47b0: 9081ffd8 cmpnei r2,r18,2047 + 47b4: 10005c26 beq r2,zero,4928 <__adddf3+0x370> + 47b8: 4a402034 orhi r9,r9,128 + 47bc: 18800e48 cmpgei r2,r3,57 + 47c0: 10004b1e bne r2,zero,48f0 <__adddf3+0x338> + 47c4: 18800808 cmpgei r2,r3,32 + 47c8: 1000ec26 beq r2,zero,4b7c <__adddf3+0x5c4> + 47cc: 1c7ff804 addi r17,r3,-32 + 47d0: 19000820 cmpeqi r4,r3,32 + 47d4: 4c44d83a srl r2,r9,r17 + 47d8: 2000041e bne r4,zero,47ec <__adddf3+0x234> + 47dc: 01001004 movi r4,64 + 47e0: 20c7c83a sub r3,r4,r3 + 47e4: 48d2983a sll r9,r9,r3 + 47e8: 6a5ab03a or r13,r13,r9 + 47ec: 6822c03a cmpne r17,r13,zero + 47f0: 88a2b03a or r17,r17,r2 + 47f4: 00004006 br 48f8 <__adddf3+0x340> + 47f8: 4b44b03a or r2,r9,r13 + 47fc: 10008226 beq r2,zero,4a08 <__adddf3+0x450> + 4800: 18bfffc4 addi r2,r3,-1 + 4804: 10011026 beq r2,zero,4c48 <__adddf3+0x690> + 4808: 18c1ffd8 cmpnei r3,r3,2047 + 480c: 18004626 beq r3,zero,4928 <__adddf3+0x370> + 4810: 1007883a mov r3,r2 + 4814: 003f8806 br 4638 <__adddf3+0x80> + 4818: 90800044 addi r2,r18,1 + 481c: 1081ff8c andi r2,r2,2046 + 4820: 1000a51e bne r2,zero,4ab8 <__adddf3+0x500> + 4824: 538ab03a or r5,r10,r14 + 4828: 4b44b03a or r2,r9,r13 + 482c: 9000f81e bne r18,zero,4c10 <__adddf3+0x658> + 4830: 28013726 beq r5,zero,4d10 <__adddf3+0x758> + 4834: 10011226 beq r2,zero,4c80 <__adddf3+0x6c8> + 4838: 7363c83a sub r17,r14,r13 + 483c: 7445803a cmpltu r2,r14,r17 + 4840: 5251c83a sub r8,r10,r9 + 4844: 4091c83a sub r8,r8,r2 + 4848: 4080202c andhi r2,r8,128 + 484c: 10018f26 beq r2,zero,4e8c <__adddf3+0x8d4> + 4850: 6ba3c83a sub r17,r13,r14 + 4854: 4a95c83a sub r10,r9,r10 + 4858: 6c51803a cmpltu r8,r13,r17 + 485c: 5211c83a sub r8,r10,r8 + 4860: 3821883a mov r16,r7 + 4864: 003fa306 br 46f4 <__adddf3+0x13c> + 4868: 4b44b03a or r2,r9,r13 + 486c: 10006626 beq r2,zero,4a08 <__adddf3+0x450> + 4870: 18bfffc4 addi r2,r3,-1 + 4874: 1000ec26 beq r2,zero,4c28 <__adddf3+0x670> + 4878: 18c1ffd8 cmpnei r3,r3,2047 + 487c: 18012d26 beq r3,zero,4d34 <__adddf3+0x77c> + 4880: 1007883a mov r3,r2 + 4884: 003fcd06 br 47bc <__adddf3+0x204> + 4888: 18fff844 addi r3,r3,-31 + 488c: 20800820 cmpeqi r2,r4,32 + 4890: 40c6d83a srl r3,r8,r3 + 4894: 1000041e bne r2,zero,48a8 <__adddf3+0x2f0> + 4898: 00801004 movi r2,64 + 489c: 1109c83a sub r4,r2,r4 + 48a0: 4110983a sll r8,r8,r4 + 48a4: 8a22b03a or r17,r17,r8 + 48a8: 8822c03a cmpne r17,r17,zero + 48ac: 88e2b03a or r17,r17,r3 + 48b0: 0011883a mov r8,zero + 48b4: 0025883a mov r18,zero + 48b8: 888001cc andi r2,r17,7 + 48bc: 103f8f1e bne r2,zero,46fc <__adddf3+0x144> + 48c0: 8822d0fa srli r17,r17,3 + 48c4: 4004977a slli r2,r8,29 + 48c8: 4014d0fa srli r10,r8,3 + 48cc: 9007883a mov r3,r18 + 48d0: 8884b03a or r2,r17,r2 + 48d4: 1901ffe0 cmpeqi r4,r3,2047 + 48d8: 2000191e bne r4,zero,4940 <__adddf3+0x388> + 48dc: 02000434 movhi r8,16 + 48e0: 423fffc4 addi r8,r8,-1 + 48e4: 5210703a and r8,r10,r8 + 48e8: 18c1ffcc andi r3,r3,2047 + 48ec: 003f9806 br 4750 <__adddf3+0x198> + 48f0: 4b62b03a or r17,r9,r13 + 48f4: 8822c03a cmpne r17,r17,zero + 48f8: 8ba3883a add r17,r17,r14 + 48fc: 8b91803a cmpltu r8,r17,r14 + 4900: 4291883a add r8,r8,r10 + 4904: 4080202c andhi r2,r8,128 + 4908: 103feb26 beq r2,zero,48b8 <__adddf3+0x300> + 490c: 94800044 addi r18,r18,1 + 4910: 9081ffe0 cmpeqi r2,r18,2047 + 4914: 10007426 beq r2,zero,4ae8 <__adddf3+0x530> + 4918: 00c1ffc4 movi r3,2047 + 491c: 0011883a mov r8,zero + 4920: 0005883a mov r2,zero + 4924: 003f8a06 br 4750 <__adddf3+0x198> + 4928: 500a977a slli r5,r10,29 + 492c: 00c80034 movhi r3,8192 + 4930: 18ffffc4 addi r3,r3,-1 + 4934: 5014d0fa srli r10,r10,3 + 4938: 20c4703a and r2,r4,r3 + 493c: 1144b03a or r2,r2,r5 + 4940: 1286b03a or r3,r2,r10 + 4944: 18015426 beq r3,zero,4e98 <__adddf3+0x8e0> + 4948: 00c00434 movhi r3,16 + 494c: 18ffffc4 addi r3,r3,-1 + 4950: 52000234 orhi r8,r10,8 + 4954: 40d0703a and r8,r8,r3 + 4958: 00c1ffc4 movi r3,2047 + 495c: 003f7c06 br 4750 <__adddf3+0x198> + 4960: 8809883a mov r4,r17 + 4964: 0006b040 call 6b04 <__clzsi2> + 4968: 10c00604 addi r3,r2,24 + 496c: 19000808 cmpgei r4,r3,32 + 4970: 203f4b26 beq r4,zero,46a0 <__adddf3+0xe8> + 4974: 123ffe04 addi r8,r2,-8 + 4978: 8a10983a sll r8,r17,r8 + 497c: 0023883a mov r17,zero + 4980: 1cbf4e0e bge r3,r18,46bc <__adddf3+0x104> + 4984: 00bfe034 movhi r2,65408 + 4988: 10bfffc4 addi r2,r2,-1 + 498c: 90e5c83a sub r18,r18,r3 + 4990: 4090703a and r8,r8,r2 + 4994: 003f5706 br 46f4 <__adddf3+0x13c> + 4998: 18002226 beq r3,zero,4a24 <__adddf3+0x46c> + 499c: 1487c83a sub r3,r2,r18 + 49a0: 90006e26 beq r18,zero,4b5c <__adddf3+0x5a4> + 49a4: 1101ffd8 cmpnei r4,r2,2047 + 49a8: 2000e926 beq r4,zero,4d50 <__adddf3+0x798> + 49ac: 52802034 orhi r10,r10,128 + 49b0: 19000e48 cmpgei r4,r3,57 + 49b4: 2000b91e bne r4,zero,4c9c <__adddf3+0x6e4> + 49b8: 19000808 cmpgei r4,r3,32 + 49bc: 2001101e bne r4,zero,4e00 <__adddf3+0x848> + 49c0: 01000804 movi r4,32 + 49c4: 20c9c83a sub r4,r4,r3 + 49c8: 5122983a sll r17,r10,r4 + 49cc: 70cad83a srl r5,r14,r3 + 49d0: 7108983a sll r4,r14,r4 + 49d4: 50d4d83a srl r10,r10,r3 + 49d8: 8962b03a or r17,r17,r5 + 49dc: 2008c03a cmpne r4,r4,zero + 49e0: 8922b03a or r17,r17,r4 + 49e4: 4a93883a add r9,r9,r10 + 49e8: 8b63883a add r17,r17,r13 + 49ec: 8b51803a cmpltu r8,r17,r13 + 49f0: 4251883a add r8,r8,r9 + 49f4: 1025883a mov r18,r2 + 49f8: 003fc206 br 4904 <__adddf3+0x34c> + 49fc: 4b62b03a or r17,r9,r13 + 4a00: 8822c03a cmpne r17,r17,zero + 4a04: 003f1a06 br 4670 <__adddf3+0xb8> + 4a08: 500c977a slli r6,r10,29 + 4a0c: 01480034 movhi r5,8192 + 4a10: 297fffc4 addi r5,r5,-1 + 4a14: 2144703a and r2,r4,r5 + 4a18: 5014d0fa srli r10,r10,3 + 4a1c: 1184b03a or r2,r2,r6 + 4a20: 003fac06 br 48d4 <__adddf3+0x31c> + 4a24: 90800044 addi r2,r18,1 + 4a28: 1141ff8c andi r5,r2,2046 + 4a2c: 28005e1e bne r5,zero,4ba8 <__adddf3+0x5f0> + 4a30: 5384b03a or r2,r10,r14 + 4a34: 9000a71e bne r18,zero,4cd4 <__adddf3+0x71c> + 4a38: 1000e526 beq r2,zero,4dd0 <__adddf3+0x818> + 4a3c: 4b44b03a or r2,r9,r13 + 4a40: 10008f26 beq r2,zero,4c80 <__adddf3+0x6c8> + 4a44: 7363883a add r17,r14,r13 + 4a48: 5255883a add r10,r10,r9 + 4a4c: 8b91803a cmpltu r8,r17,r14 + 4a50: 5211883a add r8,r10,r8 + 4a54: 4080202c andhi r2,r8,128 + 4a58: 103f9726 beq r2,zero,48b8 <__adddf3+0x300> + 4a5c: 00bfe034 movhi r2,65408 + 4a60: 10bfffc4 addi r2,r2,-1 + 4a64: 4090703a and r8,r8,r2 + 4a68: 04800044 movi r18,1 + 4a6c: 003f9206 br 48b8 <__adddf3+0x300> + 4a70: 1101ffd8 cmpnei r4,r2,2047 + 4a74: 20007a26 beq r4,zero,4c60 <__adddf3+0x6a8> + 4a78: 52802034 orhi r10,r10,128 + 4a7c: 19000e48 cmpgei r4,r3,57 + 4a80: 20002e1e bne r4,zero,4b3c <__adddf3+0x584> + 4a84: 19000808 cmpgei r4,r3,32 + 4a88: 2000871e bne r4,zero,4ca8 <__adddf3+0x6f0> + 4a8c: 01000804 movi r4,32 + 4a90: 20c9c83a sub r4,r4,r3 + 4a94: 5122983a sll r17,r10,r4 + 4a98: 70cad83a srl r5,r14,r3 + 4a9c: 711c983a sll r14,r14,r4 + 4aa0: 50d4d83a srl r10,r10,r3 + 4aa4: 8962b03a or r17,r17,r5 + 4aa8: 701cc03a cmpne r14,r14,zero + 4aac: 8ba2b03a or r17,r17,r14 + 4ab0: 4a93c83a sub r9,r9,r10 + 4ab4: 00002306 br 4b44 <__adddf3+0x58c> + 4ab8: 7363c83a sub r17,r14,r13 + 4abc: 5267c83a sub r19,r10,r9 + 4ac0: 7451803a cmpltu r8,r14,r17 + 4ac4: 9a27c83a sub r19,r19,r8 + 4ac8: 9880202c andhi r2,r19,128 + 4acc: 1000421e bne r2,zero,4bd8 <__adddf3+0x620> + 4ad0: 8cc4b03a or r2,r17,r19 + 4ad4: 103eee1e bne r2,zero,4690 <__adddf3+0xd8> + 4ad8: 0015883a mov r10,zero + 4adc: 0021883a mov r16,zero + 4ae0: 003f7e06 br 48dc <__adddf3+0x324> + 4ae4: 04800084 movi r18,2 + 4ae8: 00bfe034 movhi r2,65408 + 4aec: 10bfffc4 addi r2,r2,-1 + 4af0: 8806d07a srli r3,r17,1 + 4af4: 4090703a and r8,r8,r2 + 4af8: 400497fa slli r2,r8,31 + 4afc: 8c40004c andi r17,r17,1 + 4b00: 1c62b03a or r17,r3,r17 + 4b04: 4010d07a srli r8,r8,1 + 4b08: 1462b03a or r17,r2,r17 + 4b0c: 003ef906 br 46f4 <__adddf3+0x13c> + 4b10: 1c7ff804 addi r17,r3,-32 + 4b14: 19000820 cmpeqi r4,r3,32 + 4b18: 4c44d83a srl r2,r9,r17 + 4b1c: 2000041e bne r4,zero,4b30 <__adddf3+0x578> + 4b20: 01001004 movi r4,64 + 4b24: 20c7c83a sub r3,r4,r3 + 4b28: 48d2983a sll r9,r9,r3 + 4b2c: 6a5ab03a or r13,r13,r9 + 4b30: 6822c03a cmpne r17,r13,zero + 4b34: 88a2b03a or r17,r17,r2 + 4b38: 003ecd06 br 4670 <__adddf3+0xb8> + 4b3c: 5394b03a or r10,r10,r14 + 4b40: 5022c03a cmpne r17,r10,zero + 4b44: 6c63c83a sub r17,r13,r17 + 4b48: 6c51803a cmpltu r8,r13,r17 + 4b4c: 4a11c83a sub r8,r9,r8 + 4b50: 3821883a mov r16,r7 + 4b54: 1025883a mov r18,r2 + 4b58: 003ec806 br 467c <__adddf3+0xc4> + 4b5c: 5388b03a or r4,r10,r14 + 4b60: 20008226 beq r4,zero,4d6c <__adddf3+0x7b4> + 4b64: 193fffc4 addi r4,r3,-1 + 4b68: 2000b026 beq r4,zero,4e2c <__adddf3+0x874> + 4b6c: 18c1ffd8 cmpnei r3,r3,2047 + 4b70: 18007726 beq r3,zero,4d50 <__adddf3+0x798> + 4b74: 2007883a mov r3,r4 + 4b78: 003f8d06 br 49b0 <__adddf3+0x3f8> + 4b7c: 00800804 movi r2,32 + 4b80: 10c5c83a sub r2,r2,r3 + 4b84: 68c8d83a srl r4,r13,r3 + 4b88: 48a2983a sll r17,r9,r2 + 4b8c: 689a983a sll r13,r13,r2 + 4b90: 48c6d83a srl r3,r9,r3 + 4b94: 8922b03a or r17,r17,r4 + 4b98: 681ac03a cmpne r13,r13,zero + 4b9c: 8b62b03a or r17,r17,r13 + 4ba0: 50d5883a add r10,r10,r3 + 4ba4: 003f5406 br 48f8 <__adddf3+0x340> + 4ba8: 10c1ffe0 cmpeqi r3,r2,2047 + 4bac: 183f5a1e bne r3,zero,4918 <__adddf3+0x360> + 4bb0: 7351883a add r8,r14,r13 + 4bb4: 4387803a cmpltu r3,r8,r14 + 4bb8: 5255883a add r10,r10,r9 + 4bbc: 50c7883a add r3,r10,r3 + 4bc0: 401ad07a srli r13,r8,1 + 4bc4: 182297fa slli r17,r3,31 + 4bc8: 1810d07a srli r8,r3,1 + 4bcc: 1025883a mov r18,r2 + 4bd0: 8b62b03a or r17,r17,r13 + 4bd4: 003f3806 br 48b8 <__adddf3+0x300> + 4bd8: 6ba3c83a sub r17,r13,r14 + 4bdc: 4a93c83a sub r9,r9,r10 + 4be0: 6c51803a cmpltu r8,r13,r17 + 4be4: 4a27c83a sub r19,r9,r8 + 4be8: 3821883a mov r16,r7 + 4bec: 003ea806 br 4690 <__adddf3+0xd8> + 4bf0: 480a977a slli r5,r9,29 + 4bf4: 01080034 movhi r4,8192 + 4bf8: 213fffc4 addi r4,r4,-1 + 4bfc: 3104703a and r2,r6,r4 + 4c00: 4814d0fa srli r10,r9,3 + 4c04: 1144b03a or r2,r2,r5 + 4c08: 3821883a mov r16,r7 + 4c0c: 003f3106 br 48d4 <__adddf3+0x31c> + 4c10: 28005d1e bne r5,zero,4d88 <__adddf3+0x7d0> + 4c14: 1000121e bne r2,zero,4c60 <__adddf3+0x6a8> + 4c18: 0021883a mov r16,zero + 4c1c: 4015883a mov r10,r8 + 4c20: 00bfffc4 movi r2,-1 + 4c24: 003f4806 br 4948 <__adddf3+0x390> + 4c28: 7363883a add r17,r14,r13 + 4c2c: 5255883a add r10,r10,r9 + 4c30: 8b91803a cmpltu r8,r17,r14 + 4c34: 5211883a add r8,r10,r8 + 4c38: 4080202c andhi r2,r8,128 + 4c3c: 103fa91e bne r2,zero,4ae4 <__adddf3+0x52c> + 4c40: 04800044 movi r18,1 + 4c44: 003f1c06 br 48b8 <__adddf3+0x300> + 4c48: 7363c83a sub r17,r14,r13 + 4c4c: 5255c83a sub r10,r10,r9 + 4c50: 7451803a cmpltu r8,r14,r17 + 4c54: 5211c83a sub r8,r10,r8 + 4c58: 04800044 movi r18,1 + 4c5c: 003e8706 br 467c <__adddf3+0xc4> + 4c60: 4806977a slli r3,r9,29 + 4c64: 00880034 movhi r2,8192 + 4c68: 10bfffc4 addi r2,r2,-1 + 4c6c: 3084703a and r2,r6,r2 + 4c70: 4814d0fa srli r10,r9,3 + 4c74: 10c4b03a or r2,r2,r3 + 4c78: 3821883a mov r16,r7 + 4c7c: 003f3006 br 4940 <__adddf3+0x388> + 4c80: 500a977a slli r5,r10,29 + 4c84: 00880034 movhi r2,8192 + 4c88: 10bfffc4 addi r2,r2,-1 + 4c8c: 2084703a and r2,r4,r2 + 4c90: 5014d0fa srli r10,r10,3 + 4c94: 1144b03a or r2,r2,r5 + 4c98: 003f1006 br 48dc <__adddf3+0x324> + 4c9c: 5394b03a or r10,r10,r14 + 4ca0: 5022c03a cmpne r17,r10,zero + 4ca4: 003f5006 br 49e8 <__adddf3+0x430> + 4ca8: 1c7ff804 addi r17,r3,-32 + 4cac: 19400820 cmpeqi r5,r3,32 + 4cb0: 5448d83a srl r4,r10,r17 + 4cb4: 2800041e bne r5,zero,4cc8 <__adddf3+0x710> + 4cb8: 01401004 movi r5,64 + 4cbc: 28c7c83a sub r3,r5,r3 + 4cc0: 50d4983a sll r10,r10,r3 + 4cc4: 729cb03a or r14,r14,r10 + 4cc8: 7022c03a cmpne r17,r14,zero + 4ccc: 8922b03a or r17,r17,r4 + 4cd0: 003f9c06 br 4b44 <__adddf3+0x58c> + 4cd4: 10005a1e bne r2,zero,4e40 <__adddf3+0x888> + 4cd8: 4804977a slli r2,r9,29 + 4cdc: 00c80034 movhi r3,8192 + 4ce0: 18ffffc4 addi r3,r3,-1 + 4ce4: 30cc703a and r6,r6,r3 + 4ce8: 4814d0fa srli r10,r9,3 + 4cec: 1184b03a or r2,r2,r6 + 4cf0: 003f1306 br 4940 <__adddf3+0x388> + 4cf4: 6ba3c83a sub r17,r13,r14 + 4cf8: 4a95c83a sub r10,r9,r10 + 4cfc: 6c51803a cmpltu r8,r13,r17 + 4d00: 5211c83a sub r8,r10,r8 + 4d04: 3821883a mov r16,r7 + 4d08: 04800044 movi r18,1 + 4d0c: 003e5b06 br 467c <__adddf3+0xc4> + 4d10: 103f7126 beq r2,zero,4ad8 <__adddf3+0x520> + 4d14: 4808977a slli r4,r9,29 + 4d18: 00880034 movhi r2,8192 + 4d1c: 10bfffc4 addi r2,r2,-1 + 4d20: 3084703a and r2,r6,r2 + 4d24: 4814d0fa srli r10,r9,3 + 4d28: 1104b03a or r2,r2,r4 + 4d2c: 3821883a mov r16,r7 + 4d30: 003eea06 br 48dc <__adddf3+0x324> + 4d34: 5006977a slli r3,r10,29 + 4d38: 00880034 movhi r2,8192 + 4d3c: 10bfffc4 addi r2,r2,-1 + 4d40: 2084703a and r2,r4,r2 + 4d44: 5014d0fa srli r10,r10,3 + 4d48: 10c4b03a or r2,r2,r3 + 4d4c: 003efc06 br 4940 <__adddf3+0x388> + 4d50: 4806977a slli r3,r9,29 + 4d54: 00880034 movhi r2,8192 + 4d58: 10bfffc4 addi r2,r2,-1 + 4d5c: 3084703a and r2,r6,r2 + 4d60: 4814d0fa srli r10,r9,3 + 4d64: 10c4b03a or r2,r2,r3 + 4d68: 003ef506 br 4940 <__adddf3+0x388> + 4d6c: 4808977a slli r4,r9,29 + 4d70: 00880034 movhi r2,8192 + 4d74: 10bfffc4 addi r2,r2,-1 + 4d78: 3084703a and r2,r6,r2 + 4d7c: 4814d0fa srli r10,r9,3 + 4d80: 1104b03a or r2,r2,r4 + 4d84: 003ed306 br 48d4 <__adddf3+0x31c> + 4d88: 500a977a slli r5,r10,29 + 4d8c: 5014d0fa srli r10,r10,3 + 4d90: 10001626 beq r2,zero,4dec <__adddf3+0x834> + 4d94: 00c80034 movhi r3,8192 + 4d98: 18ffffc4 addi r3,r3,-1 + 4d9c: 20c4703a and r2,r4,r3 + 4da0: 5100022c andhi r4,r10,8 + 4da4: 1144b03a or r2,r2,r5 + 4da8: 203ee526 beq r4,zero,4940 <__adddf3+0x388> + 4dac: 4808d0fa srli r4,r9,3 + 4db0: 2140022c andhi r5,r4,8 + 4db4: 283ee21e bne r5,zero,4940 <__adddf3+0x388> + 4db8: 4812977a slli r9,r9,29 + 4dbc: 30c4703a and r2,r6,r3 + 4dc0: 3821883a mov r16,r7 + 4dc4: 1244b03a or r2,r2,r9 + 4dc8: 2015883a mov r10,r4 + 4dcc: 003edc06 br 4940 <__adddf3+0x388> + 4dd0: 4804977a slli r2,r9,29 + 4dd4: 01080034 movhi r4,8192 + 4dd8: 213fffc4 addi r4,r4,-1 + 4ddc: 310c703a and r6,r6,r4 + 4de0: 4814d0fa srli r10,r9,3 + 4de4: 1184b03a or r2,r2,r6 + 4de8: 003ebc06 br 48dc <__adddf3+0x324> + 4dec: 00880034 movhi r2,8192 + 4df0: 10bfffc4 addi r2,r2,-1 + 4df4: 2084703a and r2,r4,r2 + 4df8: 1144b03a or r2,r2,r5 + 4dfc: 003ed006 br 4940 <__adddf3+0x388> + 4e00: 193ff804 addi r4,r3,-32 + 4e04: 19400820 cmpeqi r5,r3,32 + 4e08: 5108d83a srl r4,r10,r4 + 4e0c: 2800041e bne r5,zero,4e20 <__adddf3+0x868> + 4e10: 01401004 movi r5,64 + 4e14: 28c7c83a sub r3,r5,r3 + 4e18: 50d4983a sll r10,r10,r3 + 4e1c: 729cb03a or r14,r14,r10 + 4e20: 7022c03a cmpne r17,r14,zero + 4e24: 8922b03a or r17,r17,r4 + 4e28: 003eef06 br 49e8 <__adddf3+0x430> + 4e2c: 7363883a add r17,r14,r13 + 4e30: 5255883a add r10,r10,r9 + 4e34: 8b51803a cmpltu r8,r17,r13 + 4e38: 5211883a add r8,r10,r8 + 4e3c: 003f7e06 br 4c38 <__adddf3+0x680> + 4e40: 4b50b03a or r8,r9,r13 + 4e44: 500a977a slli r5,r10,29 + 4e48: 5014d0fa srli r10,r10,3 + 4e4c: 403fe726 beq r8,zero,4dec <__adddf3+0x834> + 4e50: 00c80034 movhi r3,8192 + 4e54: 18ffffc4 addi r3,r3,-1 + 4e58: 20c4703a and r2,r4,r3 + 4e5c: 5100022c andhi r4,r10,8 + 4e60: 1144b03a or r2,r2,r5 + 4e64: 203eb626 beq r4,zero,4940 <__adddf3+0x388> + 4e68: 4808d0fa srli r4,r9,3 + 4e6c: 2140022c andhi r5,r4,8 + 4e70: 283eb31e bne r5,zero,4940 <__adddf3+0x388> + 4e74: 4804977a slli r2,r9,29 + 4e78: 30cc703a and r6,r6,r3 + 4e7c: 3821883a mov r16,r7 + 4e80: 3084b03a or r2,r6,r2 + 4e84: 2015883a mov r10,r4 + 4e88: 003ead06 br 4940 <__adddf3+0x388> + 4e8c: 8a04b03a or r2,r17,r8 + 4e90: 103f1126 beq r2,zero,4ad8 <__adddf3+0x520> + 4e94: 003e8806 br 48b8 <__adddf3+0x300> + 4e98: 0005883a mov r2,zero + 4e9c: 00c1ffc4 movi r3,2047 + 4ea0: 0011883a mov r8,zero + 4ea4: 003e2a06 br 4750 <__adddf3+0x198> + +00004ea8 <__divdf3>: + 4ea8: 2804d53a srli r2,r5,20 + 4eac: defff204 addi sp,sp,-56 + 4eb0: dc000415 stw r16,16(sp) + 4eb4: 04000434 movhi r16,16 + 4eb8: ddc00b15 stw r23,44(sp) + 4ebc: dd800a15 stw r22,40(sp) + 4ec0: dc800615 stw r18,24(sp) + 4ec4: 843fffc4 addi r16,r16,-1 + 4ec8: dfc00d15 stw ra,52(sp) + 4ecc: df000c15 stw fp,48(sp) + 4ed0: dd400915 stw r21,36(sp) + 4ed4: dd000815 stw r20,32(sp) + 4ed8: dcc00715 stw r19,28(sp) + 4edc: dc400515 stw r17,20(sp) + 4ee0: 1081ffcc andi r2,r2,2047 + 4ee4: 282cd7fa srli r22,r5,31 + 4ee8: 302f883a mov r23,r6 + 4eec: 2025883a mov r18,r4 + 4ef0: 2c20703a and r16,r5,r16 + 4ef4: 10006a26 beq r2,zero,50a0 <__divdf3+0x1f8> + 4ef8: 10c1ffe0 cmpeqi r3,r2,2047 + 4efc: 18007d1e bne r3,zero,50f4 <__divdf3+0x24c> + 4f00: 2028d77a srli r20,r4,29 + 4f04: 800a90fa slli r5,r16,3 + 4f08: 202490fa slli r18,r4,3 + 4f0c: 14ff0044 addi r19,r2,-1023 + 4f10: a14ab03a or r5,r20,r5 + 4f14: 2d002034 orhi r20,r5,128 + 4f18: 0021883a mov r16,zero + 4f1c: 0039883a mov fp,zero + 4f20: 3804d53a srli r2,r7,20 + 4f24: 00c00434 movhi r3,16 + 4f28: 18ffffc4 addi r3,r3,-1 + 4f2c: 1081ffcc andi r2,r2,2047 + 4f30: 3810d7fa srli r8,r7,31 + 4f34: 38e2703a and r17,r7,r3 + 4f38: 10004626 beq r2,zero,5054 <__divdf3+0x1ac> + 4f3c: 10c1ffe0 cmpeqi r3,r2,2047 + 4f40: 1800731e bne r3,zero,5110 <__divdf3+0x268> + 4f44: 880690fa slli r3,r17,3 + 4f48: b822d77a srli r17,r23,29 + 4f4c: b81290fa slli r9,r23,3 + 4f50: 10bf0044 addi r2,r2,-1023 + 4f54: 88c6b03a or r3,r17,r3 + 4f58: 1c402034 orhi r17,r3,128 + 4f5c: 98a7c83a sub r19,r19,r2 + 4f60: 0007883a mov r3,zero + 4f64: 80800428 cmpgeui r2,r16,16 + 4f68: b22af03a xor r21,r22,r8 + 4f6c: 1000ab1e bne r2,zero,521c <__divdf3+0x374> + 4f70: 800490ba slli r2,r16,2 + 4f74: 01800034 movhi r6,0 + 4f78: 118d883a add r6,r2,r6 + 4f7c: 3093e117 ldw r2,20356(r6) + 4f80: 1000683a jmp r2 + 4f84: 0000521c xori zero,zero,328 + 4f88: 00005030 cmpltui zero,zero,320 + 4f8c: 00004fe0 cmpeqi zero,zero,319 + 4f90: 00005040 call 504 + 4f94: 00004fe0 cmpeqi zero,zero,319 + 4f98: 000051c0 call 51c + 4f9c: 00004fe0 cmpeqi zero,zero,319 + 4fa0: 00005040 call 504 + 4fa4: 00005030 cmpltui zero,zero,320 + 4fa8: 00005030 cmpltui zero,zero,320 + 4fac: 000051c0 call 51c + 4fb0: 00005040 call 504 + 4fb4: 00004fc4 movi zero,319 + 4fb8: 00004fc4 movi zero,319 + 4fbc: 00004fc4 movi zero,319 + 4fc0: 000051d8 cmpnei zero,zero,327 + 4fc4: b02b883a mov r21,r22 + 4fc8: e08000a0 cmpeqi r2,fp,2 + 4fcc: 1000181e bne r2,zero,5030 <__divdf3+0x188> + 4fd0: e08000e0 cmpeqi r2,fp,3 + 4fd4: 1001c21e bne r2,zero,56e0 <__divdf3+0x838> + 4fd8: e0800060 cmpeqi r2,fp,1 + 4fdc: 10006526 beq r2,zero,5174 <__divdf3+0x2cc> + 4fe0: 0007883a mov r3,zero + 4fe4: 000b883a mov r5,zero + 4fe8: 0025883a mov r18,zero + 4fec: 1806953a slli r3,r3,20 + 4ff0: a82a97fa slli r21,r21,31 + 4ff4: 9005883a mov r2,r18 + 4ff8: 1946b03a or r3,r3,r5 + 4ffc: 1d46b03a or r3,r3,r21 + 5000: dfc00d17 ldw ra,52(sp) + 5004: df000c17 ldw fp,48(sp) + 5008: ddc00b17 ldw r23,44(sp) + 500c: dd800a17 ldw r22,40(sp) + 5010: dd400917 ldw r21,36(sp) + 5014: dd000817 ldw r20,32(sp) + 5018: dcc00717 ldw r19,28(sp) + 501c: dc800617 ldw r18,24(sp) + 5020: dc400517 ldw r17,20(sp) + 5024: dc000417 ldw r16,16(sp) + 5028: dec00e04 addi sp,sp,56 + 502c: f800283a ret + 5030: 00c1ffc4 movi r3,2047 + 5034: 000b883a mov r5,zero + 5038: 0025883a mov r18,zero + 503c: 003feb06 br 4fec <__divdf3+0x144> + 5040: 402b883a mov r21,r8 + 5044: 8829883a mov r20,r17 + 5048: 4825883a mov r18,r9 + 504c: 1839883a mov fp,r3 + 5050: 003fdd06 br 4fc8 <__divdf3+0x120> + 5054: 8dd2b03a or r9,r17,r23 + 5058: 48004226 beq r9,zero,5164 <__divdf3+0x2bc> + 505c: da000015 stw r8,0(sp) + 5060: 88013d26 beq r17,zero,5558 <__divdf3+0x6b0> + 5064: 8809883a mov r4,r17 + 5068: 0006b040 call 6b04 <__clzsi2> + 506c: da000017 ldw r8,0(sp) + 5070: 117ffd44 addi r5,r2,-11 + 5074: 01000744 movi r4,29 + 5078: 127ffe04 addi r9,r2,-8 + 507c: 2149c83a sub r4,r4,r5 + 5080: 8a46983a sll r3,r17,r9 + 5084: b908d83a srl r4,r23,r4 + 5088: ba52983a sll r9,r23,r9 + 508c: 20e2b03a or r17,r4,r3 + 5090: 14c5883a add r2,r2,r19 + 5094: 14c0fcc4 addi r19,r2,1011 + 5098: 0007883a mov r3,zero + 509c: 003fb106 br 4f64 <__divdf3+0xbc> + 50a0: 8128b03a or r20,r16,r4 + 50a4: 2023883a mov r17,r4 + 50a8: a0002926 beq r20,zero,5150 <__divdf3+0x2a8> + 50ac: d9c00015 stw r7,0(sp) + 50b0: 80013526 beq r16,zero,5588 <__divdf3+0x6e0> + 50b4: 8009883a mov r4,r16 + 50b8: 0006b040 call 6b04 <__clzsi2> + 50bc: d9c00017 ldw r7,0(sp) + 50c0: 10fffd44 addi r3,r2,-11 + 50c4: 05000744 movi r20,29 + 50c8: 113ffe04 addi r4,r2,-8 + 50cc: a0e9c83a sub r20,r20,r3 + 50d0: 810a983a sll r5,r16,r4 + 50d4: 8d28d83a srl r20,r17,r20 + 50d8: 8924983a sll r18,r17,r4 + 50dc: a168b03a or r20,r20,r5 + 50e0: 04ff0344 movi r19,-1011 + 50e4: 98a7c83a sub r19,r19,r2 + 50e8: 0021883a mov r16,zero + 50ec: 0039883a mov fp,zero + 50f0: 003f8b06 br 4f20 <__divdf3+0x78> + 50f4: 8128b03a or r20,r16,r4 + 50f8: a000101e bne r20,zero,513c <__divdf3+0x294> + 50fc: 0025883a mov r18,zero + 5100: 04000204 movi r16,8 + 5104: 04c1ffc4 movi r19,2047 + 5108: 07000084 movi fp,2 + 510c: 003f8406 br 4f20 <__divdf3+0x78> + 5110: 8dd2b03a or r9,r17,r23 + 5114: 9cfe0044 addi r19,r19,-2047 + 5118: 4800041e bne r9,zero,512c <__divdf3+0x284> + 511c: 84000094 ori r16,r16,2 + 5120: 0023883a mov r17,zero + 5124: 00c00084 movi r3,2 + 5128: 003f8e06 br 4f64 <__divdf3+0xbc> + 512c: 840000d4 ori r16,r16,3 + 5130: b813883a mov r9,r23 + 5134: 00c000c4 movi r3,3 + 5138: 003f8a06 br 4f64 <__divdf3+0xbc> + 513c: 8029883a mov r20,r16 + 5140: 04c1ffc4 movi r19,2047 + 5144: 04000304 movi r16,12 + 5148: 070000c4 movi fp,3 + 514c: 003f7406 br 4f20 <__divdf3+0x78> + 5150: 0025883a mov r18,zero + 5154: 04000104 movi r16,4 + 5158: 0027883a mov r19,zero + 515c: 07000044 movi fp,1 + 5160: 003f6f06 br 4f20 <__divdf3+0x78> + 5164: 84000054 ori r16,r16,1 + 5168: 0023883a mov r17,zero + 516c: 00c00044 movi r3,1 + 5170: 003f7c06 br 4f64 <__divdf3+0xbc> + 5174: 9c40ffc4 addi r17,r19,1023 + 5178: 0440c70e bge zero,r17,5498 <__divdf3+0x5f0> + 517c: 908001cc andi r2,r18,7 + 5180: 1001331e bne r2,zero,5650 <__divdf3+0x7a8> + 5184: 900cd0fa srli r6,r18,3 + 5188: a080402c andhi r2,r20,256 + 518c: 10000426 beq r2,zero,51a0 <__divdf3+0x2f8> + 5190: 00bfc034 movhi r2,65280 + 5194: 10bfffc4 addi r2,r2,-1 + 5198: a0a8703a and r20,r20,r2 + 519c: 9c410004 addi r17,r19,1024 + 51a0: 8881ffc8 cmpgei r2,r17,2047 + 51a4: 103fa21e bne r2,zero,5030 <__divdf3+0x188> + 51a8: a008977a slli r4,r20,29 + 51ac: a00a927a slli r5,r20,9 + 51b0: 88c1ffcc andi r3,r17,2047 + 51b4: 21a4b03a or r18,r4,r6 + 51b8: 280ad33a srli r5,r5,12 + 51bc: 003f8b06 br 4fec <__divdf3+0x144> + 51c0: 01400434 movhi r5,16 + 51c4: 002b883a mov r21,zero + 51c8: 297fffc4 addi r5,r5,-1 + 51cc: 04bfffc4 movi r18,-1 + 51d0: 00c1ffc4 movi r3,2047 + 51d4: 003f8506 br 4fec <__divdf3+0x144> + 51d8: a080022c andhi r2,r20,8 + 51dc: 10000926 beq r2,zero,5204 <__divdf3+0x35c> + 51e0: 8880022c andhi r2,r17,8 + 51e4: 1000071e bne r2,zero,5204 <__divdf3+0x35c> + 51e8: 00800434 movhi r2,16 + 51ec: 89400234 orhi r5,r17,8 + 51f0: 10bfffc4 addi r2,r2,-1 + 51f4: 288a703a and r5,r5,r2 + 51f8: 402b883a mov r21,r8 + 51fc: 4825883a mov r18,r9 + 5200: 003ff306 br 51d0 <__divdf3+0x328> + 5204: 00800434 movhi r2,16 + 5208: a1400234 orhi r5,r20,8 + 520c: 10bfffc4 addi r2,r2,-1 + 5210: 288a703a and r5,r5,r2 + 5214: b02b883a mov r21,r22 + 5218: 003fed06 br 51d0 <__divdf3+0x328> + 521c: 8d00c836 bltu r17,r20,5540 <__divdf3+0x698> + 5220: 8d00c626 beq r17,r20,553c <__divdf3+0x694> + 5224: 9cffffc4 addi r19,r19,-1 + 5228: 0021883a mov r16,zero + 522c: 8806923a slli r3,r17,8 + 5230: 480cd63a srli r6,r9,24 + 5234: 4804923a slli r2,r9,8 + 5238: 1838d43a srli fp,r3,16 + 523c: a009883a mov r4,r20 + 5240: 30ecb03a or r22,r6,r3 + 5244: e00b883a mov r5,fp + 5248: d8800015 stw r2,0(sp) + 524c: 00044440 call 4444 <__udivsi3> + 5250: a009883a mov r4,r20 + 5254: e00b883a mov r5,fp + 5258: d8800115 stw r2,4(sp) + 525c: 00044a80 call 44a8 <__umodsi3> + 5260: d8c00117 ldw r3,4(sp) + 5264: 1004943a slli r2,r2,16 + 5268: 9008d43a srli r4,r18,16 + 526c: b5ffffcc andi r23,r22,65535 + 5270: b8e3383a mul r17,r23,r3 + 5274: 2088b03a or r4,r4,r2 + 5278: 2440042e bgeu r4,r17,528c <__divdf3+0x3e4> + 527c: 2589883a add r4,r4,r22 + 5280: 18bfffc4 addi r2,r3,-1 + 5284: 2580d32e bgeu r4,r22,55d4 <__divdf3+0x72c> + 5288: 1007883a mov r3,r2 + 528c: 2463c83a sub r17,r4,r17 + 5290: e00b883a mov r5,fp + 5294: 8809883a mov r4,r17 + 5298: d8c00115 stw r3,4(sp) + 529c: 00044440 call 4444 <__udivsi3> + 52a0: 8809883a mov r4,r17 + 52a4: e00b883a mov r5,fp + 52a8: 1029883a mov r20,r2 + 52ac: 00044a80 call 44a8 <__umodsi3> + 52b0: 1008943a slli r4,r2,16 + 52b4: bd13383a mul r9,r23,r20 + 52b8: 94bfffcc andi r18,r18,65535 + 52bc: 9108b03a or r4,r18,r4 + 52c0: d8c00117 ldw r3,4(sp) + 52c4: 2240042e bgeu r4,r9,52d8 <__divdf3+0x430> + 52c8: 2589883a add r4,r4,r22 + 52cc: a0bfffc4 addi r2,r20,-1 + 52d0: 2580bc2e bgeu r4,r22,55c4 <__divdf3+0x71c> + 52d4: 1029883a mov r20,r2 + 52d8: 180a943a slli r5,r3,16 + 52dc: d8800017 ldw r2,0(sp) + 52e0: 2249c83a sub r4,r4,r9 + 52e4: 2d28b03a or r20,r5,r20 + 52e8: 100ed43a srli r7,r2,16 + 52ec: 123fffcc andi r8,r2,65535 + 52f0: a00ad43a srli r5,r20,16 + 52f4: a0bfffcc andi r2,r20,65535 + 52f8: 1225383a mul r18,r2,r8 + 52fc: 2a15383a mul r10,r5,r8 + 5300: 3887383a mul r3,r7,r2 + 5304: 9004d43a srli r2,r18,16 + 5308: 29cb383a mul r5,r5,r7 + 530c: 1a87883a add r3,r3,r10 + 5310: 10c5883a add r2,r2,r3 + 5314: 1280022e bgeu r2,r10,5320 <__divdf3+0x478> + 5318: 00c00074 movhi r3,1 + 531c: 28cb883a add r5,r5,r3 + 5320: 1006d43a srli r3,r2,16 + 5324: 1004943a slli r2,r2,16 + 5328: 94bfffcc andi r18,r18,65535 + 532c: 1947883a add r3,r3,r5 + 5330: 14a5883a add r18,r2,r18 + 5334: 20c07636 bltu r4,r3,5510 <__divdf3+0x668> + 5338: 20c07426 beq r4,r3,550c <__divdf3+0x664> + 533c: 84a5c83a sub r18,r16,r18 + 5340: 20c9c83a sub r4,r4,r3 + 5344: 84a1803a cmpltu r16,r16,r18 + 5348: 2421c83a sub r16,r4,r16 + 534c: 9c40ffc4 addi r17,r19,1023 + 5350: b400ba26 beq r22,r16,563c <__divdf3+0x794> + 5354: 8009883a mov r4,r16 + 5358: e00b883a mov r5,fp + 535c: da000315 stw r8,12(sp) + 5360: d9c00215 stw r7,8(sp) + 5364: 00044440 call 4444 <__udivsi3> + 5368: 8009883a mov r4,r16 + 536c: e00b883a mov r5,fp + 5370: d8800115 stw r2,4(sp) + 5374: 00044a80 call 44a8 <__umodsi3> + 5378: da400117 ldw r9,4(sp) + 537c: 1004943a slli r2,r2,16 + 5380: 9008d43a srli r4,r18,16 + 5384: ba61383a mul r16,r23,r9 + 5388: d9c00217 ldw r7,8(sp) + 538c: 2088b03a or r4,r4,r2 + 5390: da000317 ldw r8,12(sp) + 5394: 2400062e bgeu r4,r16,53b0 <__divdf3+0x508> + 5398: 2589883a add r4,r4,r22 + 539c: 48bfffc4 addi r2,r9,-1 + 53a0: 2580b536 bltu r4,r22,5678 <__divdf3+0x7d0> + 53a4: 2400b42e bgeu r4,r16,5678 <__divdf3+0x7d0> + 53a8: 4a7fff84 addi r9,r9,-2 + 53ac: 2589883a add r4,r4,r22 + 53b0: 2421c83a sub r16,r4,r16 + 53b4: 8009883a mov r4,r16 + 53b8: e00b883a mov r5,fp + 53bc: da000315 stw r8,12(sp) + 53c0: da400215 stw r9,8(sp) + 53c4: d9c00115 stw r7,4(sp) + 53c8: 00044440 call 4444 <__udivsi3> + 53cc: 8009883a mov r4,r16 + 53d0: e00b883a mov r5,fp + 53d4: 1021883a mov r16,r2 + 53d8: 00044a80 call 44a8 <__umodsi3> + 53dc: 1004943a slli r2,r2,16 + 53e0: bc2f383a mul r23,r23,r16 + 53e4: 90ffffcc andi r3,r18,65535 + 53e8: 1886b03a or r3,r3,r2 + 53ec: d9c00117 ldw r7,4(sp) + 53f0: da400217 ldw r9,8(sp) + 53f4: da000317 ldw r8,12(sp) + 53f8: 1dc0062e bgeu r3,r23,5414 <__divdf3+0x56c> + 53fc: 1d87883a add r3,r3,r22 + 5400: 80bfffc4 addi r2,r16,-1 + 5404: 1d809a36 bltu r3,r22,5670 <__divdf3+0x7c8> + 5408: 1dc0992e bgeu r3,r23,5670 <__divdf3+0x7c8> + 540c: 843fff84 addi r16,r16,-2 + 5410: 1d87883a add r3,r3,r22 + 5414: 4808943a slli r4,r9,16 + 5418: 1defc83a sub r23,r3,r23 + 541c: 2424b03a or r18,r4,r16 + 5420: 900ad43a srli r5,r18,16 + 5424: 90bfffcc andi r2,r18,65535 + 5428: 4087383a mul r3,r8,r2 + 542c: 3885383a mul r2,r7,r2 + 5430: 2a11383a mul r8,r5,r8 + 5434: 1808d43a srli r4,r3,16 + 5438: 394f383a mul r7,r7,r5 + 543c: 1205883a add r2,r2,r8 + 5440: 2089883a add r4,r4,r2 + 5444: 2200022e bgeu r4,r8,5450 <__divdf3+0x5a8> + 5448: 00800074 movhi r2,1 + 544c: 388f883a add r7,r7,r2 + 5450: 2004d43a srli r2,r4,16 + 5454: 2008943a slli r4,r4,16 + 5458: 18ffffcc andi r3,r3,65535 + 545c: 11cf883a add r7,r2,r7 + 5460: 20c9883a add r4,r4,r3 + 5464: b9c00436 bltu r23,r7,5478 <__divdf3+0x5d0> + 5468: b9c00226 beq r23,r7,5474 <__divdf3+0x5cc> + 546c: 94800054 ori r18,r18,1 + 5470: 003f4106 br 5178 <__divdf3+0x2d0> + 5474: 203f4026 beq r4,zero,5178 <__divdf3+0x2d0> + 5478: b5ef883a add r23,r22,r23 + 547c: 90bfffc4 addi r2,r18,-1 + 5480: bd806936 bltu r23,r22,5628 <__divdf3+0x780> + 5484: b9c08636 bltu r23,r7,56a0 <__divdf3+0x7f8> + 5488: b9c09a26 beq r23,r7,56f4 <__divdf3+0x84c> + 548c: 1025883a mov r18,r2 + 5490: 003ff606 br 546c <__divdf3+0x5c4> + 5494: 04bfffc4 movi r18,-1 + 5498: 01400044 movi r5,1 + 549c: 2c4bc83a sub r5,r5,r17 + 54a0: 28800e48 cmpgei r2,r5,57 + 54a4: 103ece1e bne r2,zero,4fe0 <__divdf3+0x138> + 54a8: 28800808 cmpgei r2,r5,32 + 54ac: 10004d1e bne r2,zero,55e4 <__divdf3+0x73c> + 54b0: 98810784 addi r2,r19,1054 + 54b4: a086983a sll r3,r20,r2 + 54b8: 9148d83a srl r4,r18,r5 + 54bc: 9084983a sll r2,r18,r2 + 54c0: a14ad83a srl r5,r20,r5 + 54c4: 1924b03a or r18,r3,r4 + 54c8: 1004c03a cmpne r2,r2,zero + 54cc: 90a4b03a or r18,r18,r2 + 54d0: 908001cc andi r2,r18,7 + 54d4: 10000726 beq r2,zero,54f4 <__divdf3+0x64c> + 54d8: 908003cc andi r2,r18,15 + 54dc: 10800120 cmpeqi r2,r2,4 + 54e0: 1000041e bne r2,zero,54f4 <__divdf3+0x64c> + 54e4: 90800104 addi r2,r18,4 + 54e8: 14a5803a cmpltu r18,r2,r18 + 54ec: 2c8b883a add r5,r5,r18 + 54f0: 1025883a mov r18,r2 + 54f4: 2880202c andhi r2,r5,128 + 54f8: 10007526 beq r2,zero,56d0 <__divdf3+0x828> + 54fc: 00c00044 movi r3,1 + 5500: 000b883a mov r5,zero + 5504: 0025883a mov r18,zero + 5508: 003eb806 br 4fec <__divdf3+0x144> + 550c: 84bf8b2e bgeu r16,r18,533c <__divdf3+0x494> + 5510: d8800017 ldw r2,0(sp) + 5514: 80a1883a add r16,r16,r2 + 5518: 8085803a cmpltu r2,r16,r2 + 551c: 1585883a add r2,r2,r22 + 5520: 2089883a add r4,r4,r2 + 5524: a0bfffc4 addi r2,r20,-1 + 5528: b100222e bgeu r22,r4,55b4 <__divdf3+0x70c> + 552c: 20c05536 bltu r4,r3,5684 <__divdf3+0x7dc> + 5530: 19005326 beq r3,r4,5680 <__divdf3+0x7d8> + 5534: 1029883a mov r20,r2 + 5538: 003f8006 br 533c <__divdf3+0x494> + 553c: 927f3936 bltu r18,r9,5224 <__divdf3+0x37c> + 5540: a00897fa slli r4,r20,31 + 5544: 9004d07a srli r2,r18,1 + 5548: 902097fa slli r16,r18,31 + 554c: a028d07a srli r20,r20,1 + 5550: 20a4b03a or r18,r4,r2 + 5554: 003f3506 br 522c <__divdf3+0x384> + 5558: b809883a mov r4,r23 + 555c: 0006b040 call 6b04 <__clzsi2> + 5560: 11400544 addi r5,r2,21 + 5564: 29000748 cmpgei r4,r5,29 + 5568: 1007883a mov r3,r2 + 556c: da000017 ldw r8,0(sp) + 5570: 10800804 addi r2,r2,32 + 5574: 203ebf26 beq r4,zero,5074 <__divdf3+0x1cc> + 5578: 18fffe04 addi r3,r3,-8 + 557c: b8e2983a sll r17,r23,r3 + 5580: 0013883a mov r9,zero + 5584: 003ec206 br 5090 <__divdf3+0x1e8> + 5588: 0006b040 call 6b04 <__clzsi2> + 558c: 10c00544 addi r3,r2,21 + 5590: 19000748 cmpgei r4,r3,29 + 5594: 100b883a mov r5,r2 + 5598: d9c00017 ldw r7,0(sp) + 559c: 10800804 addi r2,r2,32 + 55a0: 203ec826 beq r4,zero,50c4 <__divdf3+0x21c> + 55a4: 297ffe04 addi r5,r5,-8 + 55a8: 9168983a sll r20,r18,r5 + 55ac: 0025883a mov r18,zero + 55b0: 003ecb06 br 50e0 <__divdf3+0x238> + 55b4: b13fdf1e bne r22,r4,5534 <__divdf3+0x68c> + 55b8: d9400017 ldw r5,0(sp) + 55bc: 817fdd36 bltu r16,r5,5534 <__divdf3+0x68c> + 55c0: 003fda06 br 552c <__divdf3+0x684> + 55c4: 227f432e bgeu r4,r9,52d4 <__divdf3+0x42c> + 55c8: a53fff84 addi r20,r20,-2 + 55cc: 2589883a add r4,r4,r22 + 55d0: 003f4106 br 52d8 <__divdf3+0x430> + 55d4: 247f2c2e bgeu r4,r17,5288 <__divdf3+0x3e0> + 55d8: 18ffff84 addi r3,r3,-2 + 55dc: 2589883a add r4,r4,r22 + 55e0: 003f2a06 br 528c <__divdf3+0x3e4> + 55e4: 00fff844 movi r3,-31 + 55e8: 1c47c83a sub r3,r3,r17 + 55ec: 29400820 cmpeqi r5,r5,32 + 55f0: a0c6d83a srl r3,r20,r3 + 55f4: 2800031e bne r5,zero,5604 <__divdf3+0x75c> + 55f8: 99410f84 addi r5,r19,1086 + 55fc: a14a983a sll r5,r20,r5 + 5600: 9164b03a or r18,r18,r5 + 5604: 9024c03a cmpne r18,r18,zero + 5608: 90e4b03a or r18,r18,r3 + 560c: 910001cc andi r4,r18,7 + 5610: 20002b1e bne r4,zero,56c0 <__divdf3+0x818> + 5614: 000b883a mov r5,zero + 5618: 9024d0fa srli r18,r18,3 + 561c: 0007883a mov r3,zero + 5620: 9124b03a or r18,r18,r4 + 5624: 003e7106 br 4fec <__divdf3+0x144> + 5628: 1025883a mov r18,r2 + 562c: b9ff8f1e bne r23,r7,546c <__divdf3+0x5c4> + 5630: d8800017 ldw r2,0(sp) + 5634: 20bf8d1e bne r4,r2,546c <__divdf3+0x5c4> + 5638: 003ecf06 br 5178 <__divdf3+0x2d0> + 563c: 047f950e bge zero,r17,5494 <__divdf3+0x5ec> + 5640: 000d883a mov r6,zero + 5644: 01000044 movi r4,1 + 5648: a129883a add r20,r20,r4 + 564c: 003ece06 br 5188 <__divdf3+0x2e0> + 5650: 908003cc andi r2,r18,15 + 5654: 10800118 cmpnei r2,r2,4 + 5658: 103eca26 beq r2,zero,5184 <__divdf3+0x2dc> + 565c: 91800104 addi r6,r18,4 + 5660: 013ffec4 movi r4,-5 + 5664: 300cd0fa srli r6,r6,3 + 5668: 2489803a cmpltu r4,r4,r18 + 566c: 003ff606 br 5648 <__divdf3+0x7a0> + 5670: 1021883a mov r16,r2 + 5674: 003f6706 br 5414 <__divdf3+0x56c> + 5678: 1013883a mov r9,r2 + 567c: 003f4c06 br 53b0 <__divdf3+0x508> + 5680: 84bfac2e bgeu r16,r18,5534 <__divdf3+0x68c> + 5684: d8800017 ldw r2,0(sp) + 5688: a53fff84 addi r20,r20,-2 + 568c: 80a1883a add r16,r16,r2 + 5690: 8085803a cmpltu r2,r16,r2 + 5694: 1585883a add r2,r2,r22 + 5698: 2089883a add r4,r4,r2 + 569c: 003f2706 br 533c <__divdf3+0x494> + 56a0: d8c00017 ldw r3,0(sp) + 56a4: 94bfff84 addi r18,r18,-2 + 56a8: 18c5883a add r2,r3,r3 + 56ac: 10c7803a cmpltu r3,r2,r3 + 56b0: 1d8d883a add r6,r3,r22 + 56b4: b9af883a add r23,r23,r6 + 56b8: d8800015 stw r2,0(sp) + 56bc: 003fdb06 br 562c <__divdf3+0x784> + 56c0: 908003cc andi r2,r18,15 + 56c4: 10800118 cmpnei r2,r2,4 + 56c8: 000b883a mov r5,zero + 56cc: 103f851e bne r2,zero,54e4 <__divdf3+0x63c> + 56d0: 2804927a slli r2,r5,9 + 56d4: 2808977a slli r4,r5,29 + 56d8: 100ad33a srli r5,r2,12 + 56dc: 003fce06 br 5618 <__divdf3+0x770> + 56e0: 00800434 movhi r2,16 + 56e4: a1400234 orhi r5,r20,8 + 56e8: 10bfffc4 addi r2,r2,-1 + 56ec: 288a703a and r5,r5,r2 + 56f0: 003eb706 br 51d0 <__divdf3+0x328> + 56f4: d8c00017 ldw r3,0(sp) + 56f8: 193fe936 bltu r3,r4,56a0 <__divdf3+0x7f8> + 56fc: 1025883a mov r18,r2 + 5700: 003fcb06 br 5630 <__divdf3+0x788> + +00005704 <__eqdf2>: + 5704: 2810d53a srli r8,r5,20 + 5708: 3806d53a srli r3,r7,20 + 570c: 00800434 movhi r2,16 + 5710: 4201ffcc andi r8,r8,2047 + 5714: 10bfffc4 addi r2,r2,-1 + 5718: 4241ffd8 cmpnei r9,r8,2047 + 571c: 2814d7fa srli r10,r5,31 + 5720: 3816d7fa srli r11,r7,31 + 5724: 288a703a and r5,r5,r2 + 5728: 388e703a and r7,r7,r2 + 572c: 1881ffcc andi r2,r3,2047 + 5730: 48000626 beq r9,zero,574c <__eqdf2+0x48> + 5734: 10c1ffe0 cmpeqi r3,r2,2047 + 5738: 1800021e bne r3,zero,5744 <__eqdf2+0x40> + 573c: 4080011e bne r8,r2,5744 <__eqdf2+0x40> + 5740: 29c00826 beq r5,r7,5764 <__eqdf2+0x60> + 5744: 00800044 movi r2,1 + 5748: f800283a ret + 574c: 2906b03a or r3,r5,r4 + 5750: 183ffc1e bne r3,zero,5744 <__eqdf2+0x40> + 5754: 1081ffd8 cmpnei r2,r2,2047 + 5758: 103ffa1e bne r2,zero,5744 <__eqdf2+0x40> + 575c: 398eb03a or r7,r7,r6 + 5760: 383ff81e bne r7,zero,5744 <__eqdf2+0x40> + 5764: 21bff71e bne r4,r6,5744 <__eqdf2+0x40> + 5768: 52c00426 beq r10,r11,577c <__eqdf2+0x78> + 576c: 403ff51e bne r8,zero,5744 <__eqdf2+0x40> + 5770: 290ab03a or r5,r5,r4 + 5774: 2804c03a cmpne r2,r5,zero + 5778: f800283a ret + 577c: 0005883a mov r2,zero + 5780: f800283a ret + +00005784 <__gedf2>: + 5784: 2810d53a srli r8,r5,20 + 5788: 3812d53a srli r9,r7,20 + 578c: 00c00434 movhi r3,16 + 5790: 4201ffcc andi r8,r8,2047 + 5794: 18ffffc4 addi r3,r3,-1 + 5798: 4281ffd8 cmpnei r10,r8,2047 + 579c: 2816d7fa srli r11,r5,31 + 57a0: 3804d7fa srli r2,r7,31 + 57a4: 28ca703a and r5,r5,r3 + 57a8: 38ce703a and r7,r7,r3 + 57ac: 48c1ffcc andi r3,r9,2047 + 57b0: 50000a26 beq r10,zero,57dc <__gedf2+0x58> + 57b4: 1a41ffd8 cmpnei r9,r3,2047 + 57b8: 48000c26 beq r9,zero,57ec <__gedf2+0x68> + 57bc: 4000171e bne r8,zero,581c <__gedf2+0x98> + 57c0: 2912b03a or r9,r5,r4 + 57c4: 1800121e bne r3,zero,5810 <__gedf2+0x8c> + 57c8: 3994b03a or r10,r7,r6 + 57cc: 5000101e bne r10,zero,5810 <__gedf2+0x8c> + 57d0: 48000a1e bne r9,zero,57fc <__gedf2+0x78> + 57d4: 0005883a mov r2,zero + 57d8: f800283a ret + 57dc: 2912b03a or r9,r5,r4 + 57e0: 48001d1e bne r9,zero,5858 <__gedf2+0xd4> + 57e4: 1a41ffe0 cmpeqi r9,r3,2047 + 57e8: 48000c26 beq r9,zero,581c <__gedf2+0x98> + 57ec: 3992b03a or r9,r7,r6 + 57f0: 4800191e bne r9,zero,5858 <__gedf2+0xd4> + 57f4: 40000526 beq r8,zero,580c <__gedf2+0x88> + 57f8: 58800c26 beq r11,r2,582c <__gedf2+0xa8> + 57fc: 00800044 movi r2,1 + 5800: 58000526 beq r11,zero,5818 <__gedf2+0x94> + 5804: 00bfffc4 movi r2,-1 5808: f800283a ret - -0000580c : - 580c: defffd04 addi sp,sp,-12 - 5810: dfc00215 stw ra,8(sp) - 5814: df000115 stw fp,4(sp) - 5818: df000104 addi fp,sp,4 - 581c: e13fff15 stw r4,-4(fp) - 5820: 00086000 call 8600 - 5824: 00800044 movi r2,1 - 5828: 1001703a wrctl status,r2 - 582c: 0001883a nop - 5830: 0001883a nop - 5834: e037883a mov sp,fp - 5838: dfc00117 ldw ra,4(sp) - 583c: df000017 ldw fp,0(sp) - 5840: dec00204 addi sp,sp,8 - 5844: f800283a ret - -00005848 : - 5848: defffe04 addi sp,sp,-8 - 584c: dfc00115 stw ra,4(sp) - 5850: df000015 stw fp,0(sp) - 5854: d839883a mov fp,sp - 5858: 01c0fa04 movi r7,1000 - 585c: 01800044 movi r6,1 - 5860: 000b883a mov r5,zero - 5864: 010000b4 movhi r4,2 - 5868: 21002004 addi r4,r4,128 - 586c: 00077700 call 7770 - 5870: 01000074 movhi r4,1 - 5874: 2125e804 addi r4,r4,-26720 - 5878: 0005af40 call 5af4 - 587c: 01000074 movhi r4,1 - 5880: 2125f604 addi r4,r4,-26664 - 5884: 00057d40 call 57d4 - 5888: 0001883a nop - 588c: e037883a mov sp,fp - 5890: dfc00117 ldw ra,4(sp) - 5894: df000017 ldw fp,0(sp) - 5898: dec00204 addi sp,sp,8 - 589c: f800283a ret - -000058a0 : - 58a0: defff904 addi sp,sp,-28 - 58a4: dfc00615 stw ra,24(sp) - 58a8: df000515 stw fp,20(sp) - 58ac: df000504 addi fp,sp,20 - 58b0: e13ffb15 stw r4,-20(fp) - 58b4: 008000b4 movhi r2,2 - 58b8: 10a1a804 addi r2,r2,-31072 - 58bc: e0bfff15 stw r2,-4(fp) - 58c0: e0bffb17 ldw r2,-20(fp) - 58c4: e0bffe15 stw r2,-8(fp) - 58c8: e0bffe17 ldw r2,-8(fp) - 58cc: 10800717 ldw r2,28(r2) - 58d0: e0bffd15 stw r2,-12(fp) - 58d4: e0bffd17 ldw r2,-12(fp) - 58d8: 10800217 ldw r2,8(r2) - 58dc: 10800098 cmpnei r2,r2,2 - 58e0: 1000251e bne r2,zero,5978 - 58e4: e0bffd17 ldw r2,-12(fp) - 58e8: 10c00017 ldw r3,0(r2) - 58ec: e0bffd17 ldw r2,-12(fp) - 58f0: 10800117 ldw r2,4(r2) - 58f4: e13ffc04 addi r4,fp,-16 - 58f8: 200f883a mov r7,r4 - 58fc: 100d883a mov r6,r2 - 5900: 180b883a mov r5,r3 - 5904: e13ffe17 ldw r4,-8(fp) - 5908: 00060540 call 6054 - 590c: e0bffd17 ldw r2,-12(fp) - 5910: 10c00117 ldw r3,4(r2) - 5914: e0bffc17 ldw r2,-16(fp) - 5918: 1887c83a sub r3,r3,r2 - 591c: e0bffd17 ldw r2,-12(fp) - 5920: 10c00115 stw r3,4(r2) - 5924: e0bffd17 ldw r2,-12(fp) - 5928: 10c00017 ldw r3,0(r2) - 592c: e0bffc17 ldw r2,-16(fp) - 5930: 1887883a add r3,r3,r2 - 5934: e0bffd17 ldw r2,-12(fp) - 5938: 10c00015 stw r3,0(r2) - 593c: e0bffd17 ldw r2,-12(fp) - 5940: 10800117 ldw r2,4(r2) - 5944: 10000c26 beq r2,zero,5978 - 5948: 01400704 movi r5,28 - 594c: e13ffe17 ldw r4,-8(fp) - 5950: 00072000 call 7200 - 5954: 01400084 movi r5,2 - 5958: e13ffe17 ldw r4,-8(fp) - 595c: 00072a80 call 72a8 - 5960: 00000e06 br 599c - 5964: e0bfff17 ldw r2,-4(fp) - 5968: 10bfffc4 addi r2,r2,-1 - 596c: e0bfff15 stw r2,-4(fp) - 5970: e0bfff17 ldw r2,-4(fp) - 5974: 10000426 beq r2,zero,5988 - 5978: e13ffe17 ldw r4,-8(fp) - 597c: 00060100 call 6010 - 5980: 103ff81e bne r2,zero,5964 - 5984: 00000106 br 598c - 5988: 0001883a nop - 598c: e13ffe17 ldw r4,-8(fp) - 5990: 0005cb80 call 5cb8 - 5994: e0bffd17 ldw r2,-12(fp) - 5998: 10000215 stw zero,8(r2) - 599c: e037883a mov sp,fp - 59a0: dfc00117 ldw ra,4(sp) - 59a4: df000017 ldw fp,0(sp) - 59a8: dec00204 addi sp,sp,8 - 59ac: f800283a ret - -000059b0 : - 59b0: defffc04 addi sp,sp,-16 - 59b4: dfc00315 stw ra,12(sp) - 59b8: df000215 stw fp,8(sp) - 59bc: df000204 addi fp,sp,8 - 59c0: e13fff15 stw r4,-4(fp) - 59c4: e17ffe15 stw r5,-8(fp) - 59c8: e0bffe17 ldw r2,-8(fp) - 59cc: 10000215 stw zero,8(r2) - 59d0: e1fffe17 ldw r7,-8(fp) - 59d4: 000d883a mov r6,zero - 59d8: 01400034 movhi r5,0 - 59dc: 29562804 addi r5,r5,22688 - 59e0: e13fff17 ldw r4,-4(fp) - 59e4: 0005aa00 call 5aa0 - 59e8: 0001883a nop - 59ec: e037883a mov sp,fp - 59f0: dfc00117 ldw ra,4(sp) - 59f4: df000017 ldw fp,0(sp) - 59f8: dec00204 addi sp,sp,8 - 59fc: f800283a ret - -00005a00 : - 5a00: defff904 addi sp,sp,-28 - 5a04: dfc00615 stw ra,24(sp) - 5a08: df000515 stw fp,20(sp) - 5a0c: df000504 addi fp,sp,20 - 5a10: e13ffb15 stw r4,-20(fp) - 5a14: e0bffb17 ldw r2,-20(fp) - 5a18: e0bfff15 stw r2,-4(fp) - 5a1c: 014007c4 movi r5,31 - 5a20: e13fff17 ldw r4,-4(fp) - 5a24: 000723c0 call 723c - 5a28: 01400704 movi r5,28 - 5a2c: e13fff17 ldw r4,-4(fp) - 5a30: 00072000 call 7200 - 5a34: e0bfff17 ldw r2,-4(fp) - 5a38: 10800617 ldw r2,24(r2) - 5a3c: 10001226 beq r2,zero,5a88 - 5a40: 0005303a rdctl r2,status - 5a44: e0bffc15 stw r2,-16(fp) - 5a48: e0fffc17 ldw r3,-16(fp) - 5a4c: 00bfff84 movi r2,-2 - 5a50: 1884703a and r2,r3,r2 - 5a54: 1001703a wrctl status,r2 - 5a58: e0bffc17 ldw r2,-16(fp) - 5a5c: e0bffe15 stw r2,-8(fp) - 5a60: e0bfff17 ldw r2,-4(fp) - 5a64: 10800617 ldw r2,24(r2) - 5a68: e13fff17 ldw r4,-4(fp) - 5a6c: 103ee83a callr r2 - 5a70: e0bffe17 ldw r2,-8(fp) - 5a74: e0bffd15 stw r2,-12(fp) - 5a78: e0bffd17 ldw r2,-12(fp) - 5a7c: 1001703a wrctl status,r2 - 5a80: 0001883a nop - 5a84: 0001883a nop - 5a88: 0001883a nop - 5a8c: e037883a mov sp,fp - 5a90: dfc00117 ldw ra,4(sp) - 5a94: df000017 ldw fp,0(sp) - 5a98: dec00204 addi sp,sp,8 - 5a9c: f800283a ret - -00005aa0 : - 5aa0: defffb04 addi sp,sp,-20 - 5aa4: df000415 stw fp,16(sp) - 5aa8: df000404 addi fp,sp,16 - 5aac: e13fff15 stw r4,-4(fp) - 5ab0: e17ffe15 stw r5,-8(fp) - 5ab4: e1bffd15 stw r6,-12(fp) - 5ab8: e1fffc15 stw r7,-16(fp) - 5abc: e0bfff17 ldw r2,-4(fp) - 5ac0: e0fffe17 ldw r3,-8(fp) - 5ac4: 10c00615 stw r3,24(r2) - 5ac8: e0bfff17 ldw r2,-4(fp) - 5acc: e0fffc17 ldw r3,-16(fp) - 5ad0: 10c00715 stw r3,28(r2) - 5ad4: e0bfff17 ldw r2,-4(fp) - 5ad8: e0fffd17 ldw r3,-12(fp) - 5adc: 10c00815 stw r3,32(r2) - 5ae0: 0001883a nop - 5ae4: e037883a mov sp,fp - 5ae8: df000017 ldw fp,0(sp) - 5aec: dec00104 addi sp,sp,4 - 5af0: f800283a ret - -00005af4 : - 5af4: defff704 addi sp,sp,-36 - 5af8: dfc00815 stw ra,32(sp) - 5afc: df000715 stw fp,28(sp) - 5b00: df000704 addi fp,sp,28 - 5b04: e13ffa15 stw r4,-24(fp) - 5b08: e13ffa17 ldw r4,-24(fp) - 5b0c: 0005cb80 call 5cb8 - 5b10: 014007c4 movi r5,31 - 5b14: e13ffa17 ldw r4,-24(fp) - 5b18: 000723c0 call 723c - 5b1c: 01400704 movi r5,28 - 5b20: e13ffa17 ldw r4,-24(fp) - 5b24: 00072000 call 7200 - 5b28: 014000c4 movi r5,3 - 5b2c: e13ffa17 ldw r4,-24(fp) - 5b30: 00074500 call 7450 - 5b34: 014000c4 movi r5,3 - 5b38: e13ffa17 ldw r4,-24(fp) - 5b3c: 00073a00 call 73a0 - 5b40: e03ffc15 stw zero,-16(fp) - 5b44: e03ffb15 stw zero,-20(fp) - 5b48: e0bffb04 addi r2,fp,-20 - 5b4c: 018000b4 movhi r6,2 - 5b50: 31a1a804 addi r6,r6,-31072 - 5b54: 100b883a mov r5,r2 - 5b58: e13ffa17 ldw r4,-24(fp) - 5b5c: 0005f140 call 5f14 - 5b60: e0bffb04 addi r2,fp,-20 - 5b64: 100b883a mov r5,r2 - 5b68: e13ffa17 ldw r4,-24(fp) - 5b6c: 0005db40 call 5db4 - 5b70: d1600704 addi r5,gp,-32740 - 5b74: e13ffa17 ldw r4,-24(fp) - 5b78: 0007ae00 call 7ae0 - 5b7c: 0005883a mov r2,zero - 5b80: e0bfff15 stw r2,-4(fp) - 5b84: e0bfff17 ldw r2,-4(fp) - 5b88: 10000c1e bne r2,zero,5bbc - 5b8c: e0bffa17 ldw r2,-24(fp) - 5b90: 10c00417 ldw r3,16(r2) - 5b94: e0bffa17 ldw r2,-24(fp) - 5b98: 10800517 ldw r2,20(r2) - 5b9c: d8000015 stw zero,0(sp) - 5ba0: e1fffa17 ldw r7,-24(fp) - 5ba4: 01800034 movhi r6,0 - 5ba8: 31968004 addi r6,r6,23040 - 5bac: 100b883a mov r5,r2 - 5bb0: 1809883a mov r4,r3 - 5bb4: 0007d140 call 7d14 - 5bb8: 00000406 br 5bcc - 5bbc: 01000074 movhi r4,1 - 5bc0: 2125a404 addi r4,r4,-26992 - 5bc4: 000834c0 call 834c - 5bc8: 0001883a nop - 5bcc: e037883a mov sp,fp - 5bd0: dfc00117 ldw ra,4(sp) - 5bd4: df000017 ldw fp,0(sp) - 5bd8: dec00204 addi sp,sp,8 - 5bdc: f800283a ret - -00005be0 : - 5be0: defffc04 addi sp,sp,-16 - 5be4: dfc00315 stw ra,12(sp) - 5be8: df000215 stw fp,8(sp) - 5bec: df000204 addi fp,sp,8 - 5bf0: e13ffe15 stw r4,-8(fp) - 5bf4: e03fff15 stw zero,-4(fp) - 5bf8: d1600704 addi r5,gp,-32740 - 5bfc: e13ffe17 ldw r4,-8(fp) - 5c00: 0007c500 call 7c50 - 5c04: e0bfff15 stw r2,-4(fp) - 5c08: e0bfff17 ldw r2,-4(fp) - 5c0c: e037883a mov sp,fp - 5c10: dfc00117 ldw ra,4(sp) - 5c14: df000017 ldw fp,0(sp) - 5c18: dec00204 addi sp,sp,8 - 5c1c: f800283a ret - -00005c20 : - 5c20: defffc04 addi sp,sp,-16 - 5c24: df000315 stw fp,12(sp) - 5c28: df000304 addi fp,sp,12 - 5c2c: e13ffd15 stw r4,-12(fp) - 5c30: e0bffd17 ldw r2,-12(fp) - 5c34: 10800717 ldw r2,28(r2) - 5c38: e0bfff15 stw r2,-4(fp) - 5c3c: e0bffd17 ldw r2,-12(fp) - 5c40: 10800317 ldw r2,12(r2) - 5c44: 10800204 addi r2,r2,8 - 5c48: 10800037 ldwio r2,0(r2) - 5c4c: 1080004c andi r2,r2,1 - 5c50: e0bffe15 stw r2,-8(fp) - 5c54: e0bffe17 ldw r2,-8(fp) - 5c58: 10000226 beq r2,zero,5c64 - 5c5c: 00bffe44 movi r2,-7 - 5c60: 00001106 br 5ca8 - 5c64: e0bffd17 ldw r2,-12(fp) - 5c68: 10c00617 ldw r3,24(r2) - 5c6c: 00800034 movhi r2,0 - 5c70: 10962804 addi r2,r2,22688 - 5c74: 1880021e bne r3,r2,5c80 - 5c78: e0bfff17 ldw r2,-4(fp) - 5c7c: 10000215 stw zero,8(r2) - 5c80: e0bffd17 ldw r2,-12(fp) - 5c84: 10800317 ldw r2,12(r2) - 5c88: 10800204 addi r2,r2,8 - 5c8c: e0fffd17 ldw r3,-12(fp) - 5c90: 18c00317 ldw r3,12(r3) - 5c94: 18c00204 addi r3,r3,8 - 5c98: 18c00037 ldwio r3,0(r3) - 5c9c: 18c00054 ori r3,r3,1 - 5ca0: 10c00035 stwio r3,0(r2) - 5ca4: 0005883a mov r2,zero - 5ca8: e037883a mov sp,fp - 5cac: df000017 ldw fp,0(sp) - 5cb0: dec00104 addi sp,sp,4 - 5cb4: f800283a ret - -00005cb8 : - 5cb8: defffe04 addi sp,sp,-8 - 5cbc: df000115 stw fp,4(sp) - 5cc0: df000104 addi fp,sp,4 - 5cc4: e13fff15 stw r4,-4(fp) - 5cc8: e0bfff17 ldw r2,-4(fp) - 5ccc: 10800317 ldw r2,12(r2) - 5cd0: 10800204 addi r2,r2,8 - 5cd4: e0ffff17 ldw r3,-4(fp) - 5cd8: 18c00317 ldw r3,12(r3) - 5cdc: 18c00204 addi r3,r3,8 - 5ce0: 19000037 ldwio r4,0(r3) - 5ce4: 00ffff84 movi r3,-2 - 5ce8: 20c6703a and r3,r4,r3 - 5cec: 10c00035 stwio r3,0(r2) - 5cf0: 0001883a nop - 5cf4: e037883a mov sp,fp - 5cf8: df000017 ldw fp,0(sp) - 5cfc: dec00104 addi sp,sp,4 - 5d00: f800283a ret - -00005d04 : - 5d04: defffd04 addi sp,sp,-12 - 5d08: df000215 stw fp,8(sp) - 5d0c: df000204 addi fp,sp,8 - 5d10: e13fff15 stw r4,-4(fp) - 5d14: e17ffe15 stw r5,-8(fp) - 5d18: e0bfff17 ldw r2,-4(fp) - 5d1c: 10c00d17 ldw r3,52(r2) - 5d20: e0bffe17 ldw r2,-8(fp) - 5d24: 10c00015 stw r3,0(r2) - 5d28: e0bfff17 ldw r2,-4(fp) - 5d2c: 10800317 ldw r2,12(r2) - 5d30: 10800204 addi r2,r2,8 - 5d34: 10800037 ldwio r2,0(r2) - 5d38: 1005d07a srai r2,r2,1 - 5d3c: 1080004c andi r2,r2,1 - 5d40: 1007883a mov r3,r2 - 5d44: e0bffe17 ldw r2,-8(fp) - 5d48: 10c00115 stw r3,4(r2) - 5d4c: e0bfff17 ldw r2,-4(fp) - 5d50: 10800317 ldw r2,12(r2) - 5d54: 10800904 addi r2,r2,36 - 5d58: 10800037 ldwio r2,0(r2) - 5d5c: 1007883a mov r3,r2 - 5d60: e0bffe17 ldw r2,-8(fp) - 5d64: 10c0020d sth r3,8(r2) - 5d68: e0bfff17 ldw r2,-4(fp) - 5d6c: 10800317 ldw r2,12(r2) - 5d70: 10800804 addi r2,r2,32 - 5d74: 10800037 ldwio r2,0(r2) - 5d78: 1007883a mov r3,r2 - 5d7c: e0bffe17 ldw r2,-8(fp) - 5d80: 10c0028d sth r3,10(r2) - 5d84: e0bfff17 ldw r2,-4(fp) - 5d88: 10800317 ldw r2,12(r2) - 5d8c: 10800a04 addi r2,r2,40 - 5d90: 10800037 ldwio r2,0(r2) - 5d94: 1007883a mov r3,r2 - 5d98: e0bffe17 ldw r2,-8(fp) - 5d9c: 10c0030d sth r3,12(r2) - 5da0: 0001883a nop - 5da4: e037883a mov sp,fp - 5da8: df000017 ldw fp,0(sp) - 5dac: dec00104 addi sp,sp,4 - 5db0: f800283a ret - -00005db4 : - 5db4: defffd04 addi sp,sp,-12 - 5db8: df000215 stw fp,8(sp) - 5dbc: df000204 addi fp,sp,8 - 5dc0: e13fff15 stw r4,-4(fp) - 5dc4: e17ffe15 stw r5,-8(fp) - 5dc8: e0bffe17 ldw r2,-8(fp) - 5dcc: 10c00017 ldw r3,0(r2) - 5dd0: e0bfff17 ldw r2,-4(fp) - 5dd4: 10c00d15 stw r3,52(r2) - 5dd8: e0bfff17 ldw r2,-4(fp) - 5ddc: 10800317 ldw r2,12(r2) - 5de0: 10c00204 addi r3,r2,8 - 5de4: e0bfff17 ldw r2,-4(fp) - 5de8: 10800317 ldw r2,12(r2) - 5dec: 10800204 addi r2,r2,8 - 5df0: 10800037 ldwio r2,0(r2) - 5df4: 1009883a mov r4,r2 - 5df8: 00bfff44 movi r2,-3 - 5dfc: 2088703a and r4,r4,r2 - 5e00: e0bffe17 ldw r2,-8(fp) - 5e04: 10800117 ldw r2,4(r2) - 5e08: 1085883a add r2,r2,r2 - 5e0c: 1080008c andi r2,r2,2 - 5e10: 2084b03a or r2,r4,r2 - 5e14: 18800035 stwio r2,0(r3) - 5e18: e0bfff17 ldw r2,-4(fp) - 5e1c: 10800317 ldw r2,12(r2) - 5e20: 10800904 addi r2,r2,36 - 5e24: e0fffe17 ldw r3,-8(fp) - 5e28: 18c0020b ldhu r3,8(r3) - 5e2c: 18ffffcc andi r3,r3,65535 - 5e30: 10c00035 stwio r3,0(r2) - 5e34: e0bfff17 ldw r2,-4(fp) - 5e38: 10800317 ldw r2,12(r2) - 5e3c: 10800804 addi r2,r2,32 - 5e40: e0fffe17 ldw r3,-8(fp) - 5e44: 18c0028b ldhu r3,10(r3) - 5e48: 18ffffcc andi r3,r3,65535 - 5e4c: 10c00035 stwio r3,0(r2) - 5e50: e0bfff17 ldw r2,-4(fp) - 5e54: 10800317 ldw r2,12(r2) - 5e58: 10800a04 addi r2,r2,40 - 5e5c: e0fffe17 ldw r3,-8(fp) - 5e60: 18c0030b ldhu r3,12(r3) - 5e64: 18ffffcc andi r3,r3,65535 - 5e68: 10c00035 stwio r3,0(r2) - 5e6c: 0001883a nop - 5e70: e037883a mov sp,fp - 5e74: df000017 ldw fp,0(sp) - 5e78: dec00104 addi sp,sp,4 - 5e7c: f800283a ret - -00005e80 : - 5e80: defffb04 addi sp,sp,-20 - 5e84: dfc00415 stw ra,16(sp) - 5e88: df000315 stw fp,12(sp) - 5e8c: df000304 addi fp,sp,12 - 5e90: e13fff15 stw r4,-4(fp) - 5e94: e17ffe15 stw r5,-8(fp) - 5e98: e1bffd15 stw r6,-12(fp) - 5e9c: e0bffe17 ldw r2,-8(fp) - 5ea0: 1080028b ldhu r2,10(r2) - 5ea4: 10bfffcc andi r2,r2,65535 - 5ea8: 10000426 beq r2,zero,5ebc - 5eac: e0bffe17 ldw r2,-8(fp) - 5eb0: 1080020b ldhu r2,8(r2) - 5eb4: 10bfffcc andi r2,r2,65535 - 5eb8: 1000021e bne r2,zero,5ec4 - 5ebc: 00bfff44 movi r2,-3 - 5ec0: 00000f06 br 5f00 - 5ec4: e0bfff17 ldw r2,-4(fp) - 5ec8: 11000c17 ldw r4,48(r2) - 5ecc: e0bffe17 ldw r2,-8(fp) - 5ed0: 1080028b ldhu r2,10(r2) - 5ed4: 10ffffcc andi r3,r2,65535 - 5ed8: e0bffe17 ldw r2,-8(fp) - 5edc: 1080020b ldhu r2,8(r2) - 5ee0: 10bfffcc andi r2,r2,65535 - 5ee4: 1885883a add r2,r3,r2 - 5ee8: 100b883a mov r5,r2 - 5eec: 00034000 call 3400 <__udivsi3> - 5ef0: 1007883a mov r3,r2 - 5ef4: e0bffd17 ldw r2,-12(fp) - 5ef8: 10c00015 stw r3,0(r2) - 5efc: 0005883a mov r2,zero - 5f00: e037883a mov sp,fp - 5f04: dfc00117 ldw ra,4(sp) - 5f08: df000017 ldw fp,0(sp) - 5f0c: dec00204 addi sp,sp,8 - 5f10: f800283a ret - -00005f14 : - 5f14: defff904 addi sp,sp,-28 - 5f18: dfc00615 stw ra,24(sp) - 5f1c: df000515 stw fp,20(sp) - 5f20: df000504 addi fp,sp,20 - 5f24: e13ffd15 stw r4,-12(fp) - 5f28: e17ffc15 stw r5,-16(fp) - 5f2c: e1bffb15 stw r6,-20(fp) - 5f30: e0fffb17 ldw r3,-20(fp) - 5f34: 008001b4 movhi r2,6 - 5f38: 1086a004 addi r2,r2,6784 - 5f3c: 10c00436 bltu r2,r3,5f50 - 5f40: e0bffb17 ldw r2,-20(fp) - 5f44: 10000226 beq r2,zero,5f50 - 5f48: e0bffb17 ldw r2,-20(fp) - 5f4c: 1000021e bne r2,zero,5f58 - 5f50: 00bfff04 movi r2,-4 - 5f54: 00002906 br 5ffc - 5f58: e0bffd17 ldw r2,-12(fp) - 5f5c: 10c00c17 ldw r3,48(r2) - 5f60: e0bffb17 ldw r2,-20(fp) - 5f64: 1085883a add r2,r2,r2 - 5f68: 100b883a mov r5,r2 - 5f6c: 1809883a mov r4,r3 - 5f70: 00034000 call 3400 <__udivsi3> - 5f74: e0bfff15 stw r2,-4(fp) - 5f78: e0bfff17 ldw r2,-4(fp) - 5f7c: 10800f04 addi r2,r2,60 - 5f80: e0bffe15 stw r2,-8(fp) - 5f84: e0bfff17 ldw r2,-4(fp) - 5f88: 10bff104 addi r2,r2,-60 - 5f8c: e0bfff15 stw r2,-4(fp) - 5f90: e0fffb17 ldw r3,-20(fp) - 5f94: 008000b4 movhi r2,2 - 5f98: 10a1a804 addi r2,r2,-31072 - 5f9c: 10c0042e bgeu r2,r3,5fb0 - 5fa0: e0bffc17 ldw r2,-16(fp) - 5fa4: 00c00044 movi r3,1 - 5fa8: 10c00115 stw r3,4(r2) - 5fac: 00000206 br 5fb8 - 5fb0: e0bffc17 ldw r2,-16(fp) - 5fb4: 10000115 stw zero,4(r2) - 5fb8: e0bfff17 ldw r2,-4(fp) - 5fbc: 1007883a mov r3,r2 - 5fc0: e0bffc17 ldw r2,-16(fp) - 5fc4: 10c0028d sth r3,10(r2) - 5fc8: e0bffe17 ldw r2,-8(fp) - 5fcc: 1007883a mov r3,r2 - 5fd0: e0bffc17 ldw r2,-16(fp) - 5fd4: 10c0020d sth r3,8(r2) - 5fd8: e0bfff17 ldw r2,-4(fp) - 5fdc: 1007883a mov r3,r2 - 5fe0: e0bfff17 ldw r2,-4(fp) - 5fe4: 1004d07a srli r2,r2,1 - 5fe8: 1885c83a sub r2,r3,r2 - 5fec: 1007883a mov r3,r2 - 5ff0: e0bffc17 ldw r2,-16(fp) - 5ff4: 10c0030d sth r3,12(r2) - 5ff8: 0005883a mov r2,zero - 5ffc: e037883a mov sp,fp - 6000: dfc00117 ldw ra,4(sp) - 6004: df000017 ldw fp,0(sp) - 6008: dec00204 addi sp,sp,8 - 600c: f800283a ret - -00006010 : - 6010: defffe04 addi sp,sp,-8 - 6014: df000115 stw fp,4(sp) - 6018: df000104 addi fp,sp,4 - 601c: e13fff15 stw r4,-4(fp) - 6020: e0bfff17 ldw r2,-4(fp) - 6024: 10800317 ldw r2,12(r2) - 6028: 10800504 addi r2,r2,20 - 602c: 10800037 ldwio r2,0(r2) - 6030: 1080004c andi r2,r2,1 - 6034: 10000226 beq r2,zero,6040 - 6038: 00800044 movi r2,1 - 603c: 00000106 br 6044 - 6040: 0005883a mov r2,zero - 6044: e037883a mov sp,fp - 6048: df000017 ldw fp,0(sp) - 604c: dec00104 addi sp,sp,4 - 6050: f800283a ret - -00006054 : - 6054: defffb04 addi sp,sp,-20 - 6058: df000415 stw fp,16(sp) - 605c: df000404 addi fp,sp,16 - 6060: e13fff15 stw r4,-4(fp) - 6064: e17ffe15 stw r5,-8(fp) - 6068: e1bffd15 stw r6,-12(fp) - 606c: e1fffc15 stw r7,-16(fp) - 6070: e0bffc17 ldw r2,-16(fp) - 6074: 10000015 stw zero,0(r2) - 6078: 00001506 br 60d0 - 607c: e0bfff17 ldw r2,-4(fp) - 6080: 10800317 ldw r2,12(r2) - 6084: 10800104 addi r2,r2,4 - 6088: 11000037 ldwio r4,0(r2) - 608c: e0bffc17 ldw r2,-16(fp) - 6090: 10800017 ldw r2,0(r2) - 6094: e0fffe17 ldw r3,-8(fp) - 6098: 1885883a add r2,r3,r2 - 609c: 2007883a mov r3,r4 - 60a0: 10c00005 stb r3,0(r2) - 60a4: e0bffc17 ldw r2,-16(fp) - 60a8: 10800017 ldw r2,0(r2) - 60ac: 10c00044 addi r3,r2,1 - 60b0: e0bffc17 ldw r2,-16(fp) - 60b4: 10c00015 stw r3,0(r2) - 60b8: e0bffc17 ldw r2,-16(fp) - 60bc: 10800017 ldw r2,0(r2) - 60c0: e0fffd17 ldw r3,-12(fp) - 60c4: 1880021e bne r3,r2,60d0 - 60c8: e0bffd17 ldw r2,-12(fp) - 60cc: 1000061e bne r2,zero,60e8 - 60d0: e0bfff17 ldw r2,-4(fp) - 60d4: 10800317 ldw r2,12(r2) - 60d8: 10800704 addi r2,r2,28 - 60dc: 10800037 ldwio r2,0(r2) - 60e0: 103fe61e bne r2,zero,607c - 60e4: 00000106 br 60ec - 60e8: 0001883a nop - 60ec: 0001883a nop - 60f0: e037883a mov sp,fp - 60f4: df000017 ldw fp,0(sp) - 60f8: dec00104 addi sp,sp,4 - 60fc: f800283a ret - -00006100 : - 6100: defffa04 addi sp,sp,-24 - 6104: dfc00515 stw ra,20(sp) - 6108: df000415 stw fp,16(sp) - 610c: df000404 addi fp,sp,16 - 6110: e13ffd15 stw r4,-12(fp) - 6114: e17ffc15 stw r5,-16(fp) - 6118: e03fff15 stw zero,-4(fp) - 611c: 008000b4 movhi r2,2 - 6120: 10a1a804 addi r2,r2,-31072 - 6124: e0bffe15 stw r2,-8(fp) - 6128: 00000d06 br 6160 - 612c: e0bffe17 ldw r2,-8(fp) - 6130: 108002a8 cmpgeui r2,r2,10 - 6134: 1000021e bne r2,zero,6140 - 6138: 0109c404 movi r4,10000 - 613c: 00077fc0 call 77fc - 6140: e0bffe17 ldw r2,-8(fp) - 6144: 10bfffc4 addi r2,r2,-1 - 6148: e0bffe15 stw r2,-8(fp) - 614c: e0bffe17 ldw r2,-8(fp) - 6150: 1000031e bne r2,zero,6160 - 6154: 00bfff84 movi r2,-2 - 6158: e0bfff15 stw r2,-4(fp) - 615c: 00000506 br 6174 - 6160: e0bffd17 ldw r2,-12(fp) - 6164: 10800317 ldw r2,12(r2) - 6168: 10800704 addi r2,r2,28 - 616c: 10800037 ldwio r2,0(r2) - 6170: 103fee26 beq r2,zero,612c - 6174: e0bffd17 ldw r2,-12(fp) - 6178: 10800317 ldw r2,12(r2) - 617c: 10800104 addi r2,r2,4 - 6180: 10800037 ldwio r2,0(r2) - 6184: 1007883a mov r3,r2 - 6188: e0bffc17 ldw r2,-16(fp) - 618c: 10c00005 stb r3,0(r2) - 6190: e0bfff17 ldw r2,-4(fp) - 6194: e037883a mov sp,fp - 6198: dfc00117 ldw ra,4(sp) - 619c: df000017 ldw fp,0(sp) - 61a0: dec00204 addi sp,sp,8 - 61a4: f800283a ret - -000061a8 : - 61a8: defff804 addi sp,sp,-32 - 61ac: dfc00715 stw ra,28(sp) - 61b0: df000615 stw fp,24(sp) - 61b4: df000604 addi fp,sp,24 - 61b8: e13ffd15 stw r4,-12(fp) - 61bc: 2805883a mov r2,r5 - 61c0: 3009883a mov r4,r6 - 61c4: 3807883a mov r3,r7 - 61c8: e0bffc05 stb r2,-16(fp) - 61cc: 2005883a mov r2,r4 - 61d0: e0bffb05 stb r2,-20(fp) - 61d4: 1805883a mov r2,r3 - 61d8: e0bffa05 stb r2,-24(fp) - 61dc: 0089c404 movi r2,10000 - 61e0: e0bfff15 stw r2,-4(fp) - 61e4: e03ffe15 stw zero,-8(fp) - 61e8: 00000c06 br 621c - 61ec: e0bfff17 ldw r2,-4(fp) - 61f0: 108002a8 cmpgeui r2,r2,10 - 61f4: 1000021e bne r2,zero,6200 - 61f8: 0109c404 movi r4,10000 - 61fc: 00077fc0 call 77fc - 6200: e0bfff17 ldw r2,-4(fp) - 6204: 10bfffc4 addi r2,r2,-1 - 6208: e0bfff15 stw r2,-4(fp) - 620c: e0bfff17 ldw r2,-4(fp) - 6210: 1000021e bne r2,zero,621c - 6214: 00bfff84 movi r2,-2 - 6218: 00001906 br 6280 - 621c: e0bffd17 ldw r2,-12(fp) - 6220: 10800317 ldw r2,12(r2) - 6224: 10800404 addi r2,r2,16 - 6228: 10800037 ldwio r2,0(r2) - 622c: 1080004c andi r2,r2,1 - 6230: 103fee26 beq r2,zero,61ec - 6234: e0bffd17 ldw r2,-12(fp) - 6238: 10800317 ldw r2,12(r2) - 623c: e13ffc03 ldbu r4,-16(fp) - 6240: e0fffb03 ldbu r3,-20(fp) - 6244: 1806927a slli r3,r3,9 - 6248: 20c8b03a or r4,r4,r3 - 624c: e0fffa03 ldbu r3,-24(fp) - 6250: 1806923a slli r3,r3,8 - 6254: 20c6b03a or r3,r4,r3 - 6258: 10c00035 stwio r3,0(r2) - 625c: e0bffe04 addi r2,fp,-8 - 6260: 100b883a mov r5,r2 - 6264: e13ffd17 ldw r4,-12(fp) - 6268: 00063f00 call 63f0 - 626c: e0bffe04 addi r2,fp,-8 - 6270: 100b883a mov r5,r2 - 6274: e13ffd17 ldw r4,-12(fp) - 6278: 000643c0 call 643c - 627c: e0bffe17 ldw r2,-8(fp) - 6280: e037883a mov sp,fp - 6284: dfc00117 ldw ra,4(sp) - 6288: df000017 ldw fp,0(sp) - 628c: dec00204 addi sp,sp,8 - 6290: f800283a ret - -00006294 : - 6294: defffa04 addi sp,sp,-24 - 6298: dfc00515 stw ra,20(sp) - 629c: df000415 stw fp,16(sp) - 62a0: df000404 addi fp,sp,16 - 62a4: e13ffe15 stw r4,-8(fp) - 62a8: e17ffd15 stw r5,-12(fp) - 62ac: 3005883a mov r2,r6 - 62b0: e0bffc05 stb r2,-16(fp) - 62b4: e0bffe17 ldw r2,-8(fp) - 62b8: 10800d17 ldw r2,52(r2) - 62bc: 10800058 cmpnei r2,r2,1 - 62c0: 10001c1e bne r2,zero,6334 - 62c4: e0bffe17 ldw r2,-8(fp) - 62c8: 10800917 ldw r2,36(r2) - 62cc: 1004d1fa srli r2,r2,7 - 62d0: 1080038c andi r2,r2,14 - 62d4: 1007883a mov r3,r2 - 62d8: e0bffd17 ldw r2,-12(fp) - 62dc: 1884b03a or r2,r3,r2 - 62e0: 1007883a mov r3,r2 - 62e4: 00bffc04 movi r2,-16 - 62e8: 1884b03a or r2,r3,r2 - 62ec: 10803fcc andi r2,r2,255 - 62f0: e0fffc03 ldbu r3,-16(fp) - 62f4: 000f883a mov r7,zero - 62f8: 180d883a mov r6,r3 - 62fc: 100b883a mov r5,r2 - 6300: e13ffe17 ldw r4,-8(fp) - 6304: 00061a80 call 61a8 - 6308: e0bfff15 stw r2,-4(fp) - 630c: e0bffe17 ldw r2,-8(fp) - 6310: 10800917 ldw r2,36(r2) - 6314: 10803fcc andi r2,r2,255 - 6318: 000f883a mov r7,zero - 631c: 000d883a mov r6,zero - 6320: 100b883a mov r5,r2 - 6324: e13ffe17 ldw r4,-8(fp) - 6328: 00061a80 call 61a8 - 632c: e0bfff15 stw r2,-4(fp) - 6330: 00000e06 br 636c - 6334: e0bffe17 ldw r2,-8(fp) - 6338: 10800917 ldw r2,36(r2) - 633c: 1085883a add r2,r2,r2 - 6340: 1007883a mov r3,r2 - 6344: e0bffd17 ldw r2,-12(fp) - 6348: 1884b03a or r2,r3,r2 - 634c: 10803fcc andi r2,r2,255 - 6350: e0fffc03 ldbu r3,-16(fp) - 6354: 000f883a mov r7,zero - 6358: 180d883a mov r6,r3 - 635c: 100b883a mov r5,r2 - 6360: e13ffe17 ldw r4,-8(fp) - 6364: 00061a80 call 61a8 - 6368: e0bfff15 stw r2,-4(fp) - 636c: e0bfff17 ldw r2,-4(fp) - 6370: e037883a mov sp,fp - 6374: dfc00117 ldw ra,4(sp) - 6378: df000017 ldw fp,0(sp) - 637c: dec00204 addi sp,sp,8 - 6380: f800283a ret - -00006384 : - 6384: defffd04 addi sp,sp,-12 - 6388: df000215 stw fp,8(sp) - 638c: df000204 addi fp,sp,8 - 6390: e13fff15 stw r4,-4(fp) - 6394: e17ffe15 stw r5,-8(fp) - 6398: e0bfff17 ldw r2,-4(fp) - 639c: 10c00917 ldw r3,36(r2) - 63a0: e0bffe17 ldw r2,-8(fp) - 63a4: 10c00015 stw r3,0(r2) - 63a8: 0001883a nop - 63ac: e037883a mov sp,fp - 63b0: df000017 ldw fp,0(sp) - 63b4: dec00104 addi sp,sp,4 - 63b8: f800283a ret - -000063bc : - 63bc: defffd04 addi sp,sp,-12 - 63c0: df000215 stw fp,8(sp) - 63c4: df000204 addi fp,sp,8 - 63c8: e13fff15 stw r4,-4(fp) - 63cc: e17ffe15 stw r5,-8(fp) - 63d0: e0bfff17 ldw r2,-4(fp) - 63d4: e0fffe17 ldw r3,-8(fp) - 63d8: 10c00915 stw r3,36(r2) - 63dc: 0001883a nop - 63e0: e037883a mov sp,fp - 63e4: df000017 ldw fp,0(sp) - 63e8: dec00104 addi sp,sp,4 - 63ec: f800283a ret - -000063f0 : - 63f0: defffd04 addi sp,sp,-12 - 63f4: df000215 stw fp,8(sp) - 63f8: df000204 addi fp,sp,8 - 63fc: e13fff15 stw r4,-4(fp) - 6400: e17ffe15 stw r5,-8(fp) - 6404: e0bfff17 ldw r2,-4(fp) - 6408: 10800317 ldw r2,12(r2) - 640c: 10800404 addi r2,r2,16 - 6410: 10800037 ldwio r2,0(r2) - 6414: 1080010c andi r2,r2,4 - 6418: 10000326 beq r2,zero,6428 - 641c: e0bffe17 ldw r2,-8(fp) - 6420: 00fffec4 movi r3,-5 - 6424: 10c00015 stw r3,0(r2) - 6428: 0001883a nop - 642c: e037883a mov sp,fp - 6430: df000017 ldw fp,0(sp) - 6434: dec00104 addi sp,sp,4 - 6438: f800283a ret - -0000643c : - 643c: defffd04 addi sp,sp,-12 - 6440: df000215 stw fp,8(sp) - 6444: df000204 addi fp,sp,8 - 6448: e13fff15 stw r4,-4(fp) - 644c: e17ffe15 stw r5,-8(fp) - 6450: e0bfff17 ldw r2,-4(fp) - 6454: 10800317 ldw r2,12(r2) - 6458: 10800404 addi r2,r2,16 - 645c: 10800037 ldwio r2,0(r2) - 6460: 1080020c andi r2,r2,8 - 6464: 10000326 beq r2,zero,6474 - 6468: e0bffe17 ldw r2,-8(fp) - 646c: 00fffe84 movi r3,-6 - 6470: 10c00015 stw r3,0(r2) - 6474: 0001883a nop - 6478: e037883a mov sp,fp - 647c: df000017 ldw fp,0(sp) - 6480: dec00104 addi sp,sp,4 - 6484: f800283a ret - -00006488 : - 6488: defff804 addi sp,sp,-32 - 648c: dfc00715 stw ra,28(sp) - 6490: df000615 stw fp,24(sp) - 6494: df000604 addi fp,sp,24 - 6498: e13ffa15 stw r4,-24(fp) - 649c: e03ffd15 stw zero,-12(fp) - 64a0: e0bffa17 ldw r2,-24(fp) - 64a4: 10800717 ldw r2,28(r2) - 64a8: e0bffe15 stw r2,-8(fp) - 64ac: e0bffe17 ldw r2,-8(fp) - 64b0: 10800117 ldw r2,4(r2) - 64b4: 10800044 addi r2,r2,1 - 64b8: 1089c424 muli r2,r2,10000 - 64bc: e0bfff15 stw r2,-4(fp) - 64c0: e0bffc04 addi r2,fp,-16 - 64c4: 100b883a mov r5,r2 - 64c8: e13ffa17 ldw r4,-24(fp) - 64cc: 00073100 call 7310 - 64d0: e0bffc17 ldw r2,-16(fp) - 64d4: 100b883a mov r5,r2 - 64d8: e13ffa17 ldw r4,-24(fp) - 64dc: 000723c0 call 723c - 64e0: e0bffd04 addi r2,fp,-12 - 64e4: 100b883a mov r5,r2 - 64e8: e13ffa17 ldw r4,-24(fp) - 64ec: 00063f00 call 63f0 - 64f0: e0bffd17 ldw r2,-12(fp) - 64f4: 10002226 beq r2,zero,6580 - 64f8: e0bffe17 ldw r2,-8(fp) - 64fc: 10800217 ldw r2,8(r2) - 6500: 10001d26 beq r2,zero,6578 - 6504: 00000d06 br 653c - 6508: e0bfff17 ldw r2,-4(fp) - 650c: 108002a8 cmpgeui r2,r2,10 - 6510: 1000021e bne r2,zero,651c - 6514: 0109c404 movi r4,10000 - 6518: 00077fc0 call 77fc - 651c: e0bfff17 ldw r2,-4(fp) + 580c: 2912b03a or r9,r5,r4 + 5810: 483ff91e bne r9,zero,57f8 <__gedf2+0x74> + 5814: 103ffb26 beq r2,zero,5804 <__gedf2+0x80> + 5818: f800283a ret + 581c: 183ff61e bne r3,zero,57f8 <__gedf2+0x74> + 5820: 3992b03a or r9,r7,r6 + 5824: 483ff41e bne r9,zero,57f8 <__gedf2+0x74> + 5828: 003ff406 br 57fc <__gedf2+0x78> + 582c: 1a000716 blt r3,r8,584c <__gedf2+0xc8> + 5830: 40fff816 blt r8,r3,5814 <__gedf2+0x90> + 5834: 397ff136 bltu r7,r5,57fc <__gedf2+0x78> + 5838: 29c00926 beq r5,r7,5860 <__gedf2+0xdc> + 583c: 29ffe52e bgeu r5,r7,57d4 <__gedf2+0x50> + 5840: 583ff026 beq r11,zero,5804 <__gedf2+0x80> + 5844: 5805883a mov r2,r11 + 5848: f800283a ret + 584c: 103fed1e bne r2,zero,5804 <__gedf2+0x80> + 5850: 00800044 movi r2,1 + 5854: f800283a ret + 5858: 00bfff84 movi r2,-2 + 585c: f800283a ret + 5860: 313fe636 bltu r6,r4,57fc <__gedf2+0x78> + 5864: 21bfdb2e bgeu r4,r6,57d4 <__gedf2+0x50> + 5868: 003ff506 br 5840 <__gedf2+0xbc> + +0000586c <__ledf2>: + 586c: 2810d53a srli r8,r5,20 + 5870: 3812d53a srli r9,r7,20 + 5874: 00c00434 movhi r3,16 + 5878: 4201ffcc andi r8,r8,2047 + 587c: 18ffffc4 addi r3,r3,-1 + 5880: 4281ffd8 cmpnei r10,r8,2047 + 5884: 2816d7fa srli r11,r5,31 + 5888: 3804d7fa srli r2,r7,31 + 588c: 28ca703a and r5,r5,r3 + 5890: 38ce703a and r7,r7,r3 + 5894: 48c1ffcc andi r3,r9,2047 + 5898: 50000a26 beq r10,zero,58c4 <__ledf2+0x58> + 589c: 1a41ffd8 cmpnei r9,r3,2047 + 58a0: 48000c26 beq r9,zero,58d4 <__ledf2+0x68> + 58a4: 4000191e bne r8,zero,590c <__ledf2+0xa0> + 58a8: 2912b03a or r9,r5,r4 + 58ac: 18000d1e bne r3,zero,58e4 <__ledf2+0x78> + 58b0: 3994b03a or r10,r7,r6 + 58b4: 50000b1e bne r10,zero,58e4 <__ledf2+0x78> + 58b8: 48000c1e bne r9,zero,58ec <__ledf2+0x80> + 58bc: 0005883a mov r2,zero + 58c0: f800283a ret + 58c4: 2912b03a or r9,r5,r4 + 58c8: 48000c1e bne r9,zero,58fc <__ledf2+0x90> + 58cc: 1a41ffe0 cmpeqi r9,r3,2047 + 58d0: 48000e26 beq r9,zero,590c <__ledf2+0xa0> + 58d4: 3992b03a or r9,r7,r6 + 58d8: 4800081e bne r9,zero,58fc <__ledf2+0x90> + 58dc: 4000021e bne r8,zero,58e8 <__ledf2+0x7c> + 58e0: 2912b03a or r9,r5,r4 + 58e4: 48000726 beq r9,zero,5904 <__ledf2+0x98> + 58e8: 58800c26 beq r11,r2,591c <__ledf2+0xb0> + 58ec: 00800044 movi r2,1 + 58f0: 58000526 beq r11,zero,5908 <__ledf2+0x9c> + 58f4: 00bfffc4 movi r2,-1 + 58f8: f800283a ret + 58fc: 00800084 movi r2,2 + 5900: f800283a ret + 5904: 103ffb26 beq r2,zero,58f4 <__ledf2+0x88> + 5908: f800283a ret + 590c: 183ff61e bne r3,zero,58e8 <__ledf2+0x7c> + 5910: 3992b03a or r9,r7,r6 + 5914: 483ff41e bne r9,zero,58e8 <__ledf2+0x7c> + 5918: 003ff406 br 58ec <__ledf2+0x80> + 591c: 1a00030e bge r3,r8,592c <__ledf2+0xc0> + 5920: 103ff41e bne r2,zero,58f4 <__ledf2+0x88> + 5924: 00800044 movi r2,1 + 5928: f800283a ret + 592c: 40fff516 blt r8,r3,5904 <__ledf2+0x98> + 5930: 397fee36 bltu r7,r5,58ec <__ledf2+0x80> + 5934: 29c00426 beq r5,r7,5948 <__ledf2+0xdc> + 5938: 29ffe02e bgeu r5,r7,58bc <__ledf2+0x50> + 593c: 583fed26 beq r11,zero,58f4 <__ledf2+0x88> + 5940: 5805883a mov r2,r11 + 5944: f800283a ret + 5948: 313fe836 bltu r6,r4,58ec <__ledf2+0x80> + 594c: 21bfdb2e bgeu r4,r6,58bc <__ledf2+0x50> + 5950: 003ffa06 br 593c <__ledf2+0xd0> + +00005954 <__muldf3>: + 5954: 2804d53a srli r2,r5,20 + 5958: defff504 addi sp,sp,-44 + 595c: 02000434 movhi r8,16 + 5960: df000915 stw fp,36(sp) + 5964: dd000515 stw r20,20(sp) + 5968: dcc00415 stw r19,16(sp) + 596c: dc000115 stw r16,4(sp) + 5970: 423fffc4 addi r8,r8,-1 + 5974: dfc00a15 stw ra,40(sp) + 5978: ddc00815 stw r23,32(sp) + 597c: dd800715 stw r22,28(sp) + 5980: dd400615 stw r21,24(sp) + 5984: dc800315 stw r18,12(sp) + 5988: dc400215 stw r17,8(sp) + 598c: 1081ffcc andi r2,r2,2047 + 5990: 2828d7fa srli r20,r5,31 + 5994: 2027883a mov r19,r4 + 5998: 3039883a mov fp,r6 + 599c: 2a20703a and r16,r5,r8 + 59a0: 1000e726 beq r2,zero,5d40 <__muldf3+0x3ec> + 59a4: 10c1ffe0 cmpeqi r3,r2,2047 + 59a8: 1800f91e bne r3,zero,5d90 <__muldf3+0x43c> + 59ac: 800a90fa slli r5,r16,3 + 59b0: 2020d77a srli r16,r4,29 + 59b4: 202490fa slli r18,r4,3 + 59b8: 14ff0044 addi r19,r2,-1023 + 59bc: 8160b03a or r16,r16,r5 + 59c0: 84002034 orhi r16,r16,128 + 59c4: 002b883a mov r21,zero + 59c8: 002d883a mov r22,zero + 59cc: 3804d53a srli r2,r7,20 + 59d0: 00c00434 movhi r3,16 + 59d4: 18ffffc4 addi r3,r3,-1 + 59d8: 1081ffcc andi r2,r2,2047 + 59dc: 382ed7fa srli r23,r7,31 + 59e0: 38e2703a and r17,r7,r3 + 59e4: 1000c526 beq r2,zero,5cfc <__muldf3+0x3a8> + 59e8: 10c1ffe0 cmpeqi r3,r2,2047 + 59ec: 1800ef1e bne r3,zero,5dac <__muldf3+0x458> + 59f0: 880690fa slli r3,r17,3 + 59f4: e022d77a srli r17,fp,29 + 59f8: e00a90fa slli r5,fp,3 + 59fc: 10bf0044 addi r2,r2,-1023 + 5a00: 88e2b03a or r17,r17,r3 + 5a04: 8c402034 orhi r17,r17,128 + 5a08: 98a7883a add r19,r19,r2 + 5a0c: 0007883a mov r3,zero + 5a10: a8800428 cmpgeui r2,r21,16 + 5a14: a5ccf03a xor r6,r20,r23 + 5a18: 9a000044 addi r8,r19,1 + 5a1c: 1000371e bne r2,zero,5afc <__muldf3+0x1a8> + 5a20: a80490ba slli r2,r21,2 + 5a24: 01000034 movhi r4,0 + 5a28: 1109883a add r4,r2,r4 + 5a2c: 20968d17 ldw r2,23092(r4) + 5a30: 1000683a jmp r2 + 5a34: 00005afc xorhi zero,zero,363 + 5a38: 00005a78 rdprs zero,zero,361 + 5a3c: 00005a78 rdprs zero,zero,361 + 5a40: 00005a74 movhi zero,361 + 5a44: 00005a84 movi zero,362 + 5a48: 00005a84 movi zero,362 + 5a4c: 00005e20 cmpeqi zero,zero,376 + 5a50: 00005a74 movhi zero,361 + 5a54: 00005a84 movi zero,362 + 5a58: 00005e20 cmpeqi zero,zero,376 + 5a5c: 00005a84 movi zero,362 + 5a60: 00005a74 movhi zero,361 + 5a64: 00005dc8 cmpgei zero,zero,375 + 5a68: 00005dc8 cmpgei zero,zero,375 + 5a6c: 00005dc8 cmpgei zero,zero,375 + 5a70: 00005eac andhi zero,zero,378 + 5a74: b80d883a mov r6,r23 + 5a78: 8821883a mov r16,r17 + 5a7c: 2825883a mov r18,r5 + 5a80: 182d883a mov r22,r3 + 5a84: b08000a0 cmpeqi r2,r22,2 + 5a88: 1000181e bne r2,zero,5aec <__muldf3+0x198> + 5a8c: b08000e0 cmpeqi r2,r22,3 + 5a90: 1001481e bne r2,zero,5fb4 <__muldf3+0x660> + 5a94: b0800060 cmpeqi r2,r22,1 + 5a98: 10007e26 beq r2,zero,5c94 <__muldf3+0x340> + 5a9c: 0007883a mov r3,zero + 5aa0: 0021883a mov r16,zero + 5aa4: 0025883a mov r18,zero + 5aa8: 1806953a slli r3,r3,20 + 5aac: 300c97fa slli r6,r6,31 + 5ab0: 9005883a mov r2,r18 + 5ab4: 1c06b03a or r3,r3,r16 + 5ab8: 1986b03a or r3,r3,r6 + 5abc: dfc00a17 ldw ra,40(sp) + 5ac0: df000917 ldw fp,36(sp) + 5ac4: ddc00817 ldw r23,32(sp) + 5ac8: dd800717 ldw r22,28(sp) + 5acc: dd400617 ldw r21,24(sp) + 5ad0: dd000517 ldw r20,20(sp) + 5ad4: dcc00417 ldw r19,16(sp) + 5ad8: dc800317 ldw r18,12(sp) + 5adc: dc400217 ldw r17,8(sp) + 5ae0: dc000117 ldw r16,4(sp) + 5ae4: dec00b04 addi sp,sp,44 + 5ae8: f800283a ret + 5aec: 00c1ffc4 movi r3,2047 + 5af0: 0021883a mov r16,zero + 5af4: 0025883a mov r18,zero + 5af8: 003feb06 br 5aa8 <__muldf3+0x154> + 5afc: 9004d43a srli r2,r18,16 + 5b00: 281ed43a srli r15,r5,16 + 5b04: 94bfffcc andi r18,r18,65535 + 5b08: 297fffcc andi r5,r5,65535 + 5b0c: 2c89383a mul r4,r5,r18 + 5b10: 114f383a mul r7,r2,r5 + 5b14: 7c87383a mul r3,r15,r18 + 5b18: 2012d43a srli r9,r4,16 + 5b1c: 13dd383a mul r14,r2,r15 + 5b20: 19c7883a add r3,r3,r7 + 5b24: 48d3883a add r9,r9,r3 + 5b28: 49c0022e bgeu r9,r7,5b34 <__muldf3+0x1e0> + 5b2c: 00c00074 movhi r3,1 + 5b30: 70dd883a add r14,r14,r3 + 5b34: 881ad43a srli r13,r17,16 + 5b38: 8c7fffcc andi r17,r17,65535 + 5b3c: 8c87383a mul r3,r17,r18 + 5b40: 144f383a mul r7,r2,r17 + 5b44: 6ca5383a mul r18,r13,r18 + 5b48: 1816d43a srli r11,r3,16 + 5b4c: 4814943a slli r10,r9,16 + 5b50: 91e5883a add r18,r18,r7 + 5b54: 213fffcc andi r4,r4,65535 + 5b58: 5c97883a add r11,r11,r18 + 5b5c: 4818d43a srli r12,r9,16 + 5b60: 1345383a mul r2,r2,r13 + 5b64: 5115883a add r10,r10,r4 + 5b68: 59c0022e bgeu r11,r7,5b74 <__muldf3+0x220> + 5b6c: 01000074 movhi r4,1 + 5b70: 1105883a add r2,r2,r4 + 5b74: 8028d43a srli r20,r16,16 + 5b78: 827fffcc andi r9,r16,65535 + 5b7c: 2a6b383a mul r21,r5,r9 + 5b80: 7a49383a mul r4,r15,r9 + 5b84: a14b383a mul r5,r20,r5 + 5b88: 580e943a slli r7,r11,16 + 5b8c: a82cd43a srli r22,r21,16 + 5b90: 5824d43a srli r18,r11,16 + 5b94: 18ffffcc andi r3,r3,65535 + 5b98: 2149883a add r4,r4,r5 + 5b9c: 38cf883a add r7,r7,r3 + 5ba0: b109883a add r4,r22,r4 + 5ba4: 7d1f383a mul r15,r15,r20 + 5ba8: 9097883a add r11,r18,r2 + 5bac: 61c7883a add r3,r12,r7 + 5bb0: 2140022e bgeu r4,r5,5bbc <__muldf3+0x268> + 5bb4: 00800074 movhi r2,1 + 5bb8: 789f883a add r15,r15,r2 + 5bbc: 8a65383a mul r18,r17,r9 + 5bc0: 6a53383a mul r9,r13,r9 + 5bc4: a463383a mul r17,r20,r17 + 5bc8: 9020d43a srli r16,r18,16 + 5bcc: 200ad43a srli r5,r4,16 + 5bd0: 2008943a slli r4,r4,16 + 5bd4: 4c53883a add r9,r9,r17 + 5bd8: ab3fffcc andi r12,r21,65535 + 5bdc: 8253883a add r9,r16,r9 + 5be0: 6d1b383a mul r13,r13,r20 + 5be4: 2bdf883a add r15,r5,r15 + 5be8: 2309883a add r4,r4,r12 + 5bec: 4c40022e bgeu r9,r17,5bf8 <__muldf3+0x2a4> + 5bf0: 00800074 movhi r2,1 + 5bf4: 689b883a add r13,r13,r2 + 5bf8: 4804943a slli r2,r9,16 + 5bfc: 917fffcc andi r5,r18,65535 + 5c00: 1b87883a add r3,r3,r14 + 5c04: 1145883a add r2,r2,r5 + 5c08: 19cf803a cmpltu r7,r3,r7 + 5c0c: 12c5883a add r2,r2,r11 + 5c10: 1907883a add r3,r3,r4 + 5c14: 11dd883a add r14,r2,r7 + 5c18: 1909803a cmpltu r4,r3,r4 + 5c1c: 73cb883a add r5,r14,r15 + 5c20: 4812d43a srli r9,r9,16 + 5c24: 2919883a add r12,r5,r4 + 5c28: 12c5803a cmpltu r2,r2,r11 + 5c2c: 71e1803a cmpltu r16,r14,r7 + 5c30: 1420b03a or r16,r2,r16 + 5c34: 2bcb803a cmpltu r5,r5,r15 + 5c38: 6109803a cmpltu r4,r12,r4 + 5c3c: 2908b03a or r4,r5,r4 + 5c40: 8261883a add r16,r16,r9 + 5c44: 1824927a slli r18,r3,9 + 5c48: 8121883a add r16,r16,r4 + 5c4c: 8361883a add r16,r16,r13 + 5c50: 8020927a slli r16,r16,9 + 5c54: 1806d5fa srli r3,r3,23 + 5c58: 600ad5fa srli r5,r12,23 + 5c5c: 6004927a slli r2,r12,9 + 5c60: 92a4b03a or r18,r18,r10 + 5c64: 9024c03a cmpne r18,r18,zero + 5c68: 90e4b03a or r18,r18,r3 + 5c6c: 80c0402c andhi r3,r16,256 + 5c70: 90a4b03a or r18,r18,r2 + 5c74: 8160b03a or r16,r16,r5 + 5c78: 1800b326 beq r3,zero,5f48 <__muldf3+0x5f4> + 5c7c: 9006d07a srli r3,r18,1 + 5c80: 800497fa slli r2,r16,31 + 5c84: 9480004c andi r18,r18,1 + 5c88: 8020d07a srli r16,r16,1 + 5c8c: 1c86b03a or r3,r3,r18 + 5c90: 18a4b03a or r18,r3,r2 + 5c94: 4100ffc4 addi r4,r8,1023 + 5c98: 0100670e bge zero,r4,5e38 <__muldf3+0x4e4> + 5c9c: 908001cc andi r2,r18,7 + 5ca0: 10000726 beq r2,zero,5cc0 <__muldf3+0x36c> + 5ca4: 908003cc andi r2,r18,15 + 5ca8: 10800120 cmpeqi r2,r2,4 + 5cac: 1000041e bne r2,zero,5cc0 <__muldf3+0x36c> + 5cb0: 90800104 addi r2,r18,4 + 5cb4: 14a5803a cmpltu r18,r2,r18 + 5cb8: 84a1883a add r16,r16,r18 + 5cbc: 1025883a mov r18,r2 + 5cc0: 8080402c andhi r2,r16,256 + 5cc4: 10000426 beq r2,zero,5cd8 <__muldf3+0x384> + 5cc8: 00bfc034 movhi r2,65280 + 5ccc: 10bfffc4 addi r2,r2,-1 + 5cd0: 80a0703a and r16,r16,r2 + 5cd4: 41010004 addi r4,r8,1024 + 5cd8: 2081ffc8 cmpgei r2,r4,2047 + 5cdc: 103f831e bne r2,zero,5aec <__muldf3+0x198> + 5ce0: 8004977a slli r2,r16,29 + 5ce4: 9024d0fa srli r18,r18,3 + 5ce8: 8020927a slli r16,r16,9 + 5cec: 20c1ffcc andi r3,r4,2047 + 5cf0: 14a4b03a or r18,r2,r18 + 5cf4: 8020d33a srli r16,r16,12 + 5cf8: 003f6b06 br 5aa8 <__muldf3+0x154> + 5cfc: 8f0ab03a or r5,r17,fp + 5d00: 28004326 beq r5,zero,5e10 <__muldf3+0x4bc> + 5d04: 88008526 beq r17,zero,5f1c <__muldf3+0x5c8> + 5d08: 8809883a mov r4,r17 + 5d0c: 0006b040 call 6b04 <__clzsi2> + 5d10: 11bffd44 addi r6,r2,-11 + 5d14: 01000744 movi r4,29 + 5d18: 117ffe04 addi r5,r2,-8 + 5d1c: 2189c83a sub r4,r4,r6 + 5d20: 8962983a sll r17,r17,r5 + 5d24: e108d83a srl r4,fp,r4 + 5d28: e14a983a sll r5,fp,r5 + 5d2c: 2462b03a or r17,r4,r17 + 5d30: 9885c83a sub r2,r19,r2 + 5d34: 14ff0344 addi r19,r2,-1011 + 5d38: 0007883a mov r3,zero + 5d3c: 003f3406 br 5a10 <__muldf3+0xbc> + 5d40: 8124b03a or r18,r16,r4 + 5d44: 90002d26 beq r18,zero,5dfc <__muldf3+0x4a8> + 5d48: d9c00015 stw r7,0(sp) + 5d4c: 80006826 beq r16,zero,5ef0 <__muldf3+0x59c> + 5d50: 8009883a mov r4,r16 + 5d54: 0006b040 call 6b04 <__clzsi2> + 5d58: d9c00017 ldw r7,0(sp) + 5d5c: 113ffd44 addi r4,r2,-11 + 5d60: 00c00744 movi r3,29 + 5d64: 14bffe04 addi r18,r2,-8 + 5d68: 1907c83a sub r3,r3,r4 + 5d6c: 84a0983a sll r16,r16,r18 + 5d70: 98c6d83a srl r3,r19,r3 + 5d74: 9ca4983a sll r18,r19,r18 + 5d78: 1c20b03a or r16,r3,r16 + 5d7c: 04ff0344 movi r19,-1011 + 5d80: 98a7c83a sub r19,r19,r2 + 5d84: 002b883a mov r21,zero + 5d88: 002d883a mov r22,zero + 5d8c: 003f0f06 br 59cc <__muldf3+0x78> + 5d90: 8124b03a or r18,r16,r4 + 5d94: 9000141e bne r18,zero,5de8 <__muldf3+0x494> + 5d98: 0021883a mov r16,zero + 5d9c: 05400204 movi r21,8 + 5da0: 04c1ffc4 movi r19,2047 + 5da4: 05800084 movi r22,2 + 5da8: 003f0806 br 59cc <__muldf3+0x78> + 5dac: 8f0ab03a or r5,r17,fp + 5db0: 9cc1ffc4 addi r19,r19,2047 + 5db4: 2800081e bne r5,zero,5dd8 <__muldf3+0x484> + 5db8: ad400094 ori r21,r21,2 + 5dbc: 0023883a mov r17,zero + 5dc0: 00c00084 movi r3,2 + 5dc4: 003f1206 br 5a10 <__muldf3+0xbc> + 5dc8: b08000a0 cmpeqi r2,r22,2 + 5dcc: a00d883a mov r6,r20 + 5dd0: 103f2e26 beq r2,zero,5a8c <__muldf3+0x138> + 5dd4: 003f4506 br 5aec <__muldf3+0x198> + 5dd8: ad4000d4 ori r21,r21,3 + 5ddc: e00b883a mov r5,fp + 5de0: 00c000c4 movi r3,3 + 5de4: 003f0a06 br 5a10 <__muldf3+0xbc> + 5de8: 2025883a mov r18,r4 + 5dec: 05400304 movi r21,12 + 5df0: 04c1ffc4 movi r19,2047 + 5df4: 058000c4 movi r22,3 + 5df8: 003ef406 br 59cc <__muldf3+0x78> + 5dfc: 0021883a mov r16,zero + 5e00: 05400104 movi r21,4 + 5e04: 0027883a mov r19,zero + 5e08: 05800044 movi r22,1 + 5e0c: 003eef06 br 59cc <__muldf3+0x78> + 5e10: ad400054 ori r21,r21,1 + 5e14: 0023883a mov r17,zero + 5e18: 00c00044 movi r3,1 + 5e1c: 003efc06 br 5a10 <__muldf3+0xbc> + 5e20: 04000434 movhi r16,16 + 5e24: 000d883a mov r6,zero + 5e28: 843fffc4 addi r16,r16,-1 + 5e2c: 04bfffc4 movi r18,-1 + 5e30: 00c1ffc4 movi r3,2047 + 5e34: 003f1c06 br 5aa8 <__muldf3+0x154> + 5e38: 00800044 movi r2,1 + 5e3c: 1105c83a sub r2,r2,r4 + 5e40: 10c00e48 cmpgei r3,r2,57 + 5e44: 183f151e bne r3,zero,5a9c <__muldf3+0x148> + 5e48: 10c00808 cmpgei r3,r2,32 + 5e4c: 1800401e bne r3,zero,5f50 <__muldf3+0x5fc> + 5e50: 42010784 addi r8,r8,1054 + 5e54: 8206983a sll r3,r16,r8 + 5e58: 9088d83a srl r4,r18,r2 + 5e5c: 9210983a sll r8,r18,r8 + 5e60: 80a0d83a srl r16,r16,r2 + 5e64: 1904b03a or r2,r3,r4 + 5e68: 4024c03a cmpne r18,r8,zero + 5e6c: 1484b03a or r2,r2,r18 + 5e70: 10c001cc andi r3,r2,7 + 5e74: 18000726 beq r3,zero,5e94 <__muldf3+0x540> + 5e78: 10c003cc andi r3,r2,15 + 5e7c: 18c00120 cmpeqi r3,r3,4 + 5e80: 1800041e bne r3,zero,5e94 <__muldf3+0x540> + 5e84: 10c00104 addi r3,r2,4 + 5e88: 1885803a cmpltu r2,r3,r2 + 5e8c: 80a1883a add r16,r16,r2 + 5e90: 1805883a mov r2,r3 + 5e94: 80c0202c andhi r3,r16,128 + 5e98: 18004226 beq r3,zero,5fa4 <__muldf3+0x650> + 5e9c: 00c00044 movi r3,1 + 5ea0: 0021883a mov r16,zero + 5ea4: 0025883a mov r18,zero + 5ea8: 003eff06 br 5aa8 <__muldf3+0x154> + 5eac: 8080022c andhi r2,r16,8 + 5eb0: 10000926 beq r2,zero,5ed8 <__muldf3+0x584> + 5eb4: 8880022c andhi r2,r17,8 + 5eb8: 1000071e bne r2,zero,5ed8 <__muldf3+0x584> + 5ebc: 00800434 movhi r2,16 + 5ec0: 8c000234 orhi r16,r17,8 + 5ec4: 10bfffc4 addi r2,r2,-1 + 5ec8: 80a0703a and r16,r16,r2 + 5ecc: b80d883a mov r6,r23 + 5ed0: 2825883a mov r18,r5 + 5ed4: 003fd606 br 5e30 <__muldf3+0x4dc> + 5ed8: 00800434 movhi r2,16 + 5edc: 84000234 orhi r16,r16,8 + 5ee0: 10bfffc4 addi r2,r2,-1 + 5ee4: 80a0703a and r16,r16,r2 + 5ee8: a00d883a mov r6,r20 + 5eec: 003fd006 br 5e30 <__muldf3+0x4dc> + 5ef0: 0006b040 call 6b04 <__clzsi2> + 5ef4: 11000544 addi r4,r2,21 + 5ef8: 21400748 cmpgei r5,r4,29 + 5efc: 1007883a mov r3,r2 + 5f00: d9c00017 ldw r7,0(sp) + 5f04: 10800804 addi r2,r2,32 + 5f08: 283f9526 beq r5,zero,5d60 <__muldf3+0x40c> + 5f0c: 18fffe04 addi r3,r3,-8 + 5f10: 98e0983a sll r16,r19,r3 + 5f14: 0025883a mov r18,zero + 5f18: 003f9806 br 5d7c <__muldf3+0x428> + 5f1c: e009883a mov r4,fp + 5f20: 0006b040 call 6b04 <__clzsi2> + 5f24: 11800544 addi r6,r2,21 + 5f28: 31000748 cmpgei r4,r6,29 + 5f2c: 1007883a mov r3,r2 + 5f30: 10800804 addi r2,r2,32 + 5f34: 203f7726 beq r4,zero,5d14 <__muldf3+0x3c0> + 5f38: 1c7ffe04 addi r17,r3,-8 + 5f3c: e462983a sll r17,fp,r17 + 5f40: 000b883a mov r5,zero + 5f44: 003f7a06 br 5d30 <__muldf3+0x3dc> + 5f48: 9811883a mov r8,r19 + 5f4c: 003f5106 br 5c94 <__muldf3+0x340> + 5f50: 00fff844 movi r3,-31 + 5f54: 1907c83a sub r3,r3,r4 + 5f58: 10800820 cmpeqi r2,r2,32 + 5f5c: 80c6d83a srl r3,r16,r3 + 5f60: 1000031e bne r2,zero,5f70 <__muldf3+0x61c> + 5f64: 42010f84 addi r8,r8,1086 + 5f68: 8220983a sll r16,r16,r8 + 5f6c: 9424b03a or r18,r18,r16 + 5f70: 9024c03a cmpne r18,r18,zero + 5f74: 90c4b03a or r2,r18,r3 + 5f78: 148001cc andi r18,r2,7 + 5f7c: 9000051e bne r18,zero,5f94 <__muldf3+0x640> + 5f80: 0021883a mov r16,zero + 5f84: 1004d0fa srli r2,r2,3 + 5f88: 0007883a mov r3,zero + 5f8c: 14a4b03a or r18,r2,r18 + 5f90: 003ec506 br 5aa8 <__muldf3+0x154> + 5f94: 10c003cc andi r3,r2,15 + 5f98: 18c00118 cmpnei r3,r3,4 + 5f9c: 0021883a mov r16,zero + 5fa0: 183fb81e bne r3,zero,5e84 <__muldf3+0x530> + 5fa4: 8006927a slli r3,r16,9 + 5fa8: 8024977a slli r18,r16,29 + 5fac: 1820d33a srli r16,r3,12 + 5fb0: 003ff406 br 5f84 <__muldf3+0x630> + 5fb4: 00800434 movhi r2,16 + 5fb8: 84000234 orhi r16,r16,8 + 5fbc: 10bfffc4 addi r2,r2,-1 + 5fc0: 80a0703a and r16,r16,r2 + 5fc4: 003f9a06 br 5e30 <__muldf3+0x4dc> + +00005fc8 <__subdf3>: + 5fc8: 00800434 movhi r2,16 + 5fcc: 3810d53a srli r8,r7,20 + 5fd0: 10bfffc4 addi r2,r2,-1 + 5fd4: 2806d53a srli r3,r5,20 + 5fd8: 2892703a and r9,r5,r2 + 5fdc: 3884703a and r2,r7,r2 + 5fe0: 280ad7fa srli r5,r5,31 + 5fe4: 481290fa slli r9,r9,3 + 5fe8: 2018d77a srli r12,r4,29 + 5fec: 100490fa slli r2,r2,3 + 5ff0: 3016d77a srli r11,r6,29 + 5ff4: defffb04 addi sp,sp,-20 + 5ff8: 4201ffcc andi r8,r8,2047 + 5ffc: dc800215 stw r18,8(sp) + 6000: dc400115 stw r17,4(sp) + 6004: 1c81ffcc andi r18,r3,2047 + 6008: dfc00415 stw ra,16(sp) + 600c: dcc00315 stw r19,12(sp) + 6010: dc000015 stw r16,0(sp) + 6014: 4281ffd8 cmpnei r10,r8,2047 + 6018: 2823883a mov r17,r5 + 601c: 201c90fa slli r14,r4,3 + 6020: 380ed7fa srli r7,r7,31 + 6024: 301a90fa slli r13,r6,3 + 6028: 29403fcc andi r5,r5,255 + 602c: 6252b03a or r9,r12,r9 + 6030: 589eb03a or r15,r11,r2 + 6034: 9207c83a sub r3,r18,r8 + 6038: 50006826 beq r10,zero,61dc <__subdf3+0x214> + 603c: 3ac0005c xori r11,r7,1 + 6040: 2ac07326 beq r5,r11,6210 <__subdf3+0x248> + 6044: 00c0590e bge zero,r3,61ac <__subdf3+0x1e4> + 6048: 4000691e bne r8,zero,61f0 <__subdf3+0x228> + 604c: 7b44b03a or r2,r15,r13 + 6050: 1000fb26 beq r2,zero,6440 <__subdf3+0x478> + 6054: 18bfffc4 addi r2,r3,-1 + 6058: 10019126 beq r2,zero,66a0 <__subdf3+0x6d8> + 605c: 18c1ffd8 cmpnei r3,r3,2047 + 6060: 1800c326 beq r3,zero,6370 <__subdf3+0x3a8> + 6064: 1007883a mov r3,r2 + 6068: 18800e48 cmpgei r2,r3,57 + 606c: 1000651e bne r2,zero,6204 <__subdf3+0x23c> + 6070: 18800808 cmpgei r2,r3,32 + 6074: 1001331e bne r2,zero,6544 <__subdf3+0x57c> + 6078: 00800804 movi r2,32 + 607c: 10c5c83a sub r2,r2,r3 + 6080: 78a0983a sll r16,r15,r2 + 6084: 68c8d83a srl r4,r13,r3 + 6088: 689a983a sll r13,r13,r2 + 608c: 78c4d83a srl r2,r15,r3 + 6090: 8120b03a or r16,r16,r4 + 6094: 681ac03a cmpne r13,r13,zero + 6098: 8360b03a or r16,r16,r13 + 609c: 4893c83a sub r9,r9,r2 + 60a0: 7421c83a sub r16,r14,r16 + 60a4: 7409803a cmpltu r4,r14,r16 + 60a8: 4909c83a sub r4,r9,r4 + 60ac: 2080202c andhi r2,r4,128 + 60b0: 10009326 beq r2,zero,6300 <__subdf3+0x338> + 60b4: 04c02034 movhi r19,128 + 60b8: 9cffffc4 addi r19,r19,-1 + 60bc: 24e6703a and r19,r4,r19 + 60c0: 9800b926 beq r19,zero,63a8 <__subdf3+0x3e0> + 60c4: 9809883a mov r4,r19 + 60c8: 0006b040 call 6b04 <__clzsi2> + 60cc: 10fffe04 addi r3,r2,-8 + 60d0: 01000804 movi r4,32 + 60d4: 20c9c83a sub r4,r4,r3 + 60d8: 8108d83a srl r4,r16,r4 + 60dc: 98e6983a sll r19,r19,r3 + 60e0: 80e0983a sll r16,r16,r3 + 60e4: 24c8b03a or r4,r4,r19 + 60e8: 1c80b816 blt r3,r18,63cc <__subdf3+0x404> + 60ec: 1c87c83a sub r3,r3,r18 + 60f0: 19400044 addi r5,r3,1 + 60f4: 28800808 cmpgei r2,r5,32 + 60f8: 1000751e bne r2,zero,62d0 <__subdf3+0x308> + 60fc: 00800804 movi r2,32 + 6100: 1145c83a sub r2,r2,r5 + 6104: 8146d83a srl r3,r16,r5 + 6108: 80a0983a sll r16,r16,r2 + 610c: 2084983a sll r2,r4,r2 + 6110: 2148d83a srl r4,r4,r5 + 6114: 8020c03a cmpne r16,r16,zero + 6118: 10c4b03a or r2,r2,r3 + 611c: 1420b03a or r16,r2,r16 + 6120: 0025883a mov r18,zero + 6124: 808001cc andi r2,r16,7 + 6128: 10000726 beq r2,zero,6148 <__subdf3+0x180> + 612c: 808003cc andi r2,r16,15 + 6130: 10800120 cmpeqi r2,r2,4 + 6134: 1000041e bne r2,zero,6148 <__subdf3+0x180> + 6138: 80800104 addi r2,r16,4 + 613c: 1421803a cmpltu r16,r2,r16 + 6140: 2409883a add r4,r4,r16 + 6144: 1021883a mov r16,r2 + 6148: 2080202c andhi r2,r4,128 + 614c: 10006e26 beq r2,zero,6308 <__subdf3+0x340> + 6150: 90c00044 addi r3,r18,1 + 6154: 1881ffe0 cmpeqi r2,r3,2047 + 6158: 18c1ffcc andi r3,r3,2047 + 615c: 1000801e bne r2,zero,6360 <__subdf3+0x398> + 6160: 00bfe034 movhi r2,65408 + 6164: 10bfffc4 addi r2,r2,-1 + 6168: 2088703a and r4,r4,r2 + 616c: 2004977a slli r2,r4,29 + 6170: 2008927a slli r4,r4,9 + 6174: 8020d0fa srli r16,r16,3 + 6178: 2008d33a srli r4,r4,12 + 617c: 1404b03a or r2,r2,r16 + 6180: 1806953a slli r3,r3,20 + 6184: 882297fa slli r17,r17,31 + 6188: 1906b03a or r3,r3,r4 + 618c: 1c46b03a or r3,r3,r17 + 6190: dfc00417 ldw ra,16(sp) + 6194: dcc00317 ldw r19,12(sp) + 6198: dc800217 ldw r18,8(sp) + 619c: dc400117 ldw r17,4(sp) + 61a0: dc000017 ldw r16,0(sp) + 61a4: dec00504 addi sp,sp,20 + 61a8: f800283a ret + 61ac: 18002c26 beq r3,zero,6260 <__subdf3+0x298> + 61b0: 4487c83a sub r3,r8,r18 + 61b4: 5823883a mov r17,r11 + 61b8: 9000bb1e bne r18,zero,64a8 <__subdf3+0x4e0> + 61bc: 4b84b03a or r2,r9,r14 + 61c0: 10011726 beq r2,zero,6620 <__subdf3+0x658> + 61c4: 18bfffc4 addi r2,r3,-1 + 61c8: 10016326 beq r2,zero,6758 <__subdf3+0x790> + 61cc: 18c1ffd8 cmpnei r3,r3,2047 + 61d0: 18012c26 beq r3,zero,6684 <__subdf3+0x6bc> + 61d4: 1007883a mov r3,r2 + 61d8: 0000b506 br 64b0 <__subdf3+0x4e8> + 61dc: 7b44b03a or r2,r15,r13 + 61e0: 103f9626 beq r2,zero,603c <__subdf3+0x74> + 61e4: 3ac03fcc andi r11,r7,255 + 61e8: 29c07d26 beq r5,r7,63e0 <__subdf3+0x418> + 61ec: 00ffef0e bge zero,r3,61ac <__subdf3+0x1e4> + 61f0: 9081ffd8 cmpnei r2,r18,2047 + 61f4: 10005e26 beq r2,zero,6370 <__subdf3+0x3a8> + 61f8: 18800e48 cmpgei r2,r3,57 + 61fc: 7bc02034 orhi r15,r15,128 + 6200: 103f9b26 beq r2,zero,6070 <__subdf3+0xa8> + 6204: 7b60b03a or r16,r15,r13 + 6208: 8020c03a cmpne r16,r16,zero + 620c: 003fa406 br 60a0 <__subdf3+0xd8> + 6210: 00c0730e bge zero,r3,63e0 <__subdf3+0x418> + 6214: 40002626 beq r8,zero,62b0 <__subdf3+0x2e8> + 6218: 9081ffd8 cmpnei r2,r18,2047 + 621c: 10005426 beq r2,zero,6370 <__subdf3+0x3a8> + 6220: 7bc02034 orhi r15,r15,128 + 6224: 18800e48 cmpgei r2,r3,57 + 6228: 1000431e bne r2,zero,6338 <__subdf3+0x370> + 622c: 18800808 cmpgei r2,r3,32 + 6230: 1000de26 beq r2,zero,65ac <__subdf3+0x5e4> + 6234: 1c3ff804 addi r16,r3,-32 + 6238: 18800820 cmpeqi r2,r3,32 + 623c: 7c0ad83a srl r5,r15,r16 + 6240: 1000041e bne r2,zero,6254 <__subdf3+0x28c> + 6244: 00801004 movi r2,64 + 6248: 10c5c83a sub r2,r2,r3 + 624c: 7884983a sll r2,r15,r2 + 6250: 689ab03a or r13,r13,r2 + 6254: 6820c03a cmpne r16,r13,zero + 6258: 8160b03a or r16,r16,r5 + 625c: 00003806 br 6340 <__subdf3+0x378> + 6260: 90800044 addi r2,r18,1 + 6264: 1081ff8c andi r2,r2,2046 + 6268: 1000a01e bne r2,zero,64ec <__subdf3+0x524> + 626c: 4b8ab03a or r5,r9,r14 + 6270: 7b44b03a or r2,r15,r13 + 6274: 9000f11e bne r18,zero,663c <__subdf3+0x674> + 6278: 28012e26 beq r5,zero,6734 <__subdf3+0x76c> + 627c: 10010e26 beq r2,zero,66b8 <__subdf3+0x6f0> + 6280: 7361c83a sub r16,r14,r13 + 6284: 7405803a cmpltu r2,r14,r16 + 6288: 4bc9c83a sub r4,r9,r15 + 628c: 2089c83a sub r4,r4,r2 + 6290: 2080202c andhi r2,r4,128 + 6294: 10016d26 beq r2,zero,684c <__subdf3+0x884> + 6298: 6ba1c83a sub r16,r13,r14 + 629c: 7a49c83a sub r4,r15,r9 + 62a0: 6c1b803a cmpltu r13,r13,r16 + 62a4: 2349c83a sub r4,r4,r13 + 62a8: 5823883a mov r17,r11 + 62ac: 003f9d06 br 6124 <__subdf3+0x15c> + 62b0: 7b44b03a or r2,r15,r13 + 62b4: 10006226 beq r2,zero,6440 <__subdf3+0x478> + 62b8: 18bfffc4 addi r2,r3,-1 + 62bc: 1000e926 beq r2,zero,6664 <__subdf3+0x69c> + 62c0: 18c1ffd8 cmpnei r3,r3,2047 + 62c4: 18012a26 beq r3,zero,6770 <__subdf3+0x7a8> + 62c8: 1007883a mov r3,r2 + 62cc: 003fd506 br 6224 <__subdf3+0x25c> + 62d0: 18fff844 addi r3,r3,-31 + 62d4: 28800820 cmpeqi r2,r5,32 + 62d8: 20c6d83a srl r3,r4,r3 + 62dc: 1000041e bne r2,zero,62f0 <__subdf3+0x328> + 62e0: 00801004 movi r2,64 + 62e4: 114bc83a sub r5,r2,r5 + 62e8: 2148983a sll r4,r4,r5 + 62ec: 8120b03a or r16,r16,r4 + 62f0: 8020c03a cmpne r16,r16,zero + 62f4: 80e0b03a or r16,r16,r3 + 62f8: 0009883a mov r4,zero + 62fc: 0025883a mov r18,zero + 6300: 808001cc andi r2,r16,7 + 6304: 103f891e bne r2,zero,612c <__subdf3+0x164> + 6308: 8020d0fa srli r16,r16,3 + 630c: 2004977a slli r2,r4,29 + 6310: 2012d0fa srli r9,r4,3 + 6314: 9007883a mov r3,r18 + 6318: 8084b03a or r2,r16,r2 + 631c: 1901ffe0 cmpeqi r4,r3,2047 + 6320: 2000191e bne r4,zero,6388 <__subdf3+0x3c0> + 6324: 01000434 movhi r4,16 + 6328: 213fffc4 addi r4,r4,-1 + 632c: 4908703a and r4,r9,r4 + 6330: 18c1ffcc andi r3,r3,2047 + 6334: 003f9206 br 6180 <__subdf3+0x1b8> + 6338: 7b60b03a or r16,r15,r13 + 633c: 8020c03a cmpne r16,r16,zero + 6340: 83a1883a add r16,r16,r14 + 6344: 8389803a cmpltu r4,r16,r14 + 6348: 2249883a add r4,r4,r9 + 634c: 2080202c andhi r2,r4,128 + 6350: 103feb26 beq r2,zero,6300 <__subdf3+0x338> + 6354: 94800044 addi r18,r18,1 + 6358: 9081ffe0 cmpeqi r2,r18,2047 + 635c: 10006f26 beq r2,zero,651c <__subdf3+0x554> + 6360: 00c1ffc4 movi r3,2047 + 6364: 0009883a mov r4,zero + 6368: 0005883a mov r2,zero + 636c: 003f8406 br 6180 <__subdf3+0x1b8> + 6370: 4806977a slli r3,r9,29 + 6374: 00880034 movhi r2,8192 + 6378: 10bfffc4 addi r2,r2,-1 + 637c: 4812d0fa srli r9,r9,3 + 6380: 2088703a and r4,r4,r2 + 6384: 20c4b03a or r2,r4,r3 + 6388: 4886b03a or r3,r9,r2 + 638c: 18013726 beq r3,zero,686c <__subdf3+0x8a4> + 6390: 00c00434 movhi r3,16 + 6394: 18ffffc4 addi r3,r3,-1 + 6398: 49000234 orhi r4,r9,8 + 639c: 20c8703a and r4,r4,r3 + 63a0: 00c1ffc4 movi r3,2047 + 63a4: 003f7606 br 6180 <__subdf3+0x1b8> + 63a8: 8009883a mov r4,r16 + 63ac: 0006b040 call 6b04 <__clzsi2> + 63b0: 10c00604 addi r3,r2,24 + 63b4: 19000808 cmpgei r4,r3,32 + 63b8: 203f4526 beq r4,zero,60d0 <__subdf3+0x108> + 63bc: 113ffe04 addi r4,r2,-8 + 63c0: 8108983a sll r4,r16,r4 + 63c4: 0021883a mov r16,zero + 63c8: 1cbf480e bge r3,r18,60ec <__subdf3+0x124> + 63cc: 00bfe034 movhi r2,65408 + 63d0: 10bfffc4 addi r2,r2,-1 + 63d4: 90e5c83a sub r18,r18,r3 + 63d8: 2088703a and r4,r4,r2 + 63dc: 003f5106 br 6124 <__subdf3+0x15c> + 63e0: 18001e26 beq r3,zero,645c <__subdf3+0x494> + 63e4: 4487c83a sub r3,r8,r18 + 63e8: 90006826 beq r18,zero,658c <__subdf3+0x5c4> + 63ec: 5000a526 beq r10,zero,6684 <__subdf3+0x6bc> + 63f0: 4a402034 orhi r9,r9,128 + 63f4: 18800e48 cmpgei r2,r3,57 + 63f8: 1000b61e bne r2,zero,66d4 <__subdf3+0x70c> + 63fc: 18800808 cmpgei r2,r3,32 + 6400: 1001021e bne r2,zero,680c <__subdf3+0x844> + 6404: 00800804 movi r2,32 + 6408: 10c5c83a sub r2,r2,r3 + 640c: 48a0983a sll r16,r9,r2 + 6410: 70c8d83a srl r4,r14,r3 + 6414: 7084983a sll r2,r14,r2 + 6418: 48d2d83a srl r9,r9,r3 + 641c: 8120b03a or r16,r16,r4 + 6420: 1004c03a cmpne r2,r2,zero + 6424: 80a0b03a or r16,r16,r2 + 6428: 7a5f883a add r15,r15,r9 + 642c: 8361883a add r16,r16,r13 + 6430: 8349803a cmpltu r4,r16,r13 + 6434: 23c9883a add r4,r4,r15 + 6438: 4025883a mov r18,r8 + 643c: 003fc306 br 634c <__subdf3+0x384> + 6440: 480a977a slli r5,r9,29 + 6444: 00880034 movhi r2,8192 + 6448: 10bfffc4 addi r2,r2,-1 + 644c: 2088703a and r4,r4,r2 + 6450: 4812d0fa srli r9,r9,3 + 6454: 2144b03a or r2,r4,r5 + 6458: 003fb006 br 631c <__subdf3+0x354> + 645c: 90800044 addi r2,r18,1 + 6460: 1141ff8c andi r5,r2,2046 + 6464: 28005c1e bne r5,zero,65d8 <__subdf3+0x610> + 6468: 4b84b03a or r2,r9,r14 + 646c: 9000a71e bne r18,zero,670c <__subdf3+0x744> + 6470: 1000df26 beq r2,zero,67f0 <__subdf3+0x828> + 6474: 7b44b03a or r2,r15,r13 + 6478: 10008f26 beq r2,zero,66b8 <__subdf3+0x6f0> + 647c: 7361883a add r16,r14,r13 + 6480: 4bc9883a add r4,r9,r15 + 6484: 839d803a cmpltu r14,r16,r14 + 6488: 2389883a add r4,r4,r14 + 648c: 2080202c andhi r2,r4,128 + 6490: 103f9b26 beq r2,zero,6300 <__subdf3+0x338> + 6494: 00bfe034 movhi r2,65408 + 6498: 10bfffc4 addi r2,r2,-1 + 649c: 2088703a and r4,r4,r2 + 64a0: 04800044 movi r18,1 + 64a4: 003f9606 br 6300 <__subdf3+0x338> + 64a8: 50007626 beq r10,zero,6684 <__subdf3+0x6bc> + 64ac: 4a402034 orhi r9,r9,128 + 64b0: 18800e48 cmpgei r2,r3,57 + 64b4: 10002e1e bne r2,zero,6570 <__subdf3+0x5a8> + 64b8: 18800808 cmpgei r2,r3,32 + 64bc: 1000881e bne r2,zero,66e0 <__subdf3+0x718> + 64c0: 00800804 movi r2,32 + 64c4: 10c5c83a sub r2,r2,r3 + 64c8: 48a0983a sll r16,r9,r2 + 64cc: 70c8d83a srl r4,r14,r3 + 64d0: 709c983a sll r14,r14,r2 + 64d4: 48d2d83a srl r9,r9,r3 + 64d8: 8120b03a or r16,r16,r4 + 64dc: 701cc03a cmpne r14,r14,zero + 64e0: 83a0b03a or r16,r16,r14 + 64e4: 7a5fc83a sub r15,r15,r9 + 64e8: 00002306 br 6578 <__subdf3+0x5b0> + 64ec: 7361c83a sub r16,r14,r13 + 64f0: 4be7c83a sub r19,r9,r15 + 64f4: 7409803a cmpltu r4,r14,r16 + 64f8: 9927c83a sub r19,r19,r4 + 64fc: 9880202c andhi r2,r19,128 + 6500: 1000411e bne r2,zero,6608 <__subdf3+0x640> + 6504: 84c4b03a or r2,r16,r19 + 6508: 103eed1e bne r2,zero,60c0 <__subdf3+0xf8> + 650c: 0013883a mov r9,zero + 6510: 0023883a mov r17,zero + 6514: 003f8306 br 6324 <__subdf3+0x35c> + 6518: 04800084 movi r18,2 + 651c: 00bfe034 movhi r2,65408 6520: 10bfffc4 addi r2,r2,-1 - 6524: e0bfff15 stw r2,-4(fp) - 6528: e0bfff17 ldw r2,-4(fp) - 652c: 1000031e bne r2,zero,653c - 6530: 00bfff84 movi r2,-2 - 6534: e0bffd15 stw r2,-12(fp) - 6538: 00000306 br 6548 - 653c: e13ffa17 ldw r4,-24(fp) - 6540: 00060100 call 6010 - 6544: 103ff01e bne r2,zero,6508 - 6548: e0bffe17 ldw r2,-8(fp) - 654c: 10800017 ldw r2,0(r2) - 6550: e0fffb04 addi r3,fp,-20 - 6554: 180f883a mov r7,r3 - 6558: 000d883a mov r6,zero - 655c: 100b883a mov r5,r2 - 6560: e13ffa17 ldw r4,-24(fp) - 6564: 00060540 call 6054 - 6568: e13ffa17 ldw r4,-24(fp) - 656c: 0005cb80 call 5cb8 - 6570: e0bffe17 ldw r2,-8(fp) - 6574: 10000215 stw zero,8(r2) - 6578: e0bffd17 ldw r2,-12(fp) - 657c: 00000a06 br 65a8 - 6580: e0bffe17 ldw r2,-8(fp) - 6584: 10800217 ldw r2,8(r2) - 6588: 10000626 beq r2,zero,65a4 - 658c: e0bffc17 ldw r2,-16(fp) - 6590: 100b883a mov r5,r2 - 6594: e13ffa17 ldw r4,-24(fp) - 6598: 00072a80 call 72a8 - 659c: 00bffe44 movi r2,-7 - 65a0: 00000106 br 65a8 - 65a4: 0005883a mov r2,zero - 65a8: e037883a mov sp,fp - 65ac: dfc00117 ldw ra,4(sp) - 65b0: df000017 ldw fp,0(sp) - 65b4: dec00204 addi sp,sp,8 - 65b8: f800283a ret - -000065bc : - 65bc: defff704 addi sp,sp,-36 - 65c0: dfc00815 stw ra,32(sp) - 65c4: df000715 stw fp,28(sp) - 65c8: df000704 addi fp,sp,28 - 65cc: e13ffd15 stw r4,-12(fp) - 65d0: e17ffc15 stw r5,-16(fp) - 65d4: e1bffb15 stw r6,-20(fp) - 65d8: 3805883a mov r2,r7 - 65dc: e0bffa05 stb r2,-24(fp) - 65e0: 0089c404 movi r2,10000 - 65e4: e0bffe15 stw r2,-8(fp) - 65e8: 00002206 br 6674 - 65ec: e0bffe17 ldw r2,-8(fp) - 65f0: 108002a8 cmpgeui r2,r2,10 - 65f4: 1000021e bne r2,zero,6600 - 65f8: 0109c404 movi r4,10000 - 65fc: 00077fc0 call 77fc - 6600: e0bffa03 ldbu r2,-24(fp) - 6604: 10000926 beq r2,zero,662c - 6608: 00800044 movi r2,1 - 660c: d8800015 stw r2,0(sp) - 6610: 000f883a mov r7,zero - 6614: e1bffb17 ldw r6,-20(fp) - 6618: e17ffc17 ldw r5,-16(fp) - 661c: e13ffd17 ldw r4,-12(fp) - 6620: 0006b640 call 6b64 - 6624: e0bfff15 stw r2,-4(fp) - 6628: 00000806 br 664c - 662c: 00800044 movi r2,1 - 6630: d8800015 stw r2,0(sp) - 6634: 000f883a mov r7,zero - 6638: e1bffb17 ldw r6,-20(fp) - 663c: e17ffc17 ldw r5,-16(fp) - 6640: e13ffd17 ldw r4,-12(fp) - 6644: 00069a80 call 69a8 - 6648: e0bfff15 stw r2,-4(fp) - 664c: e0bfff17 ldw r2,-4(fp) - 6650: 10bffea0 cmpeqi r2,r2,-6 - 6654: 1000061e bne r2,zero,6670 - 6658: e0bfff17 ldw r2,-4(fp) - 665c: 10bffee0 cmpeqi r2,r2,-5 - 6660: 1000031e bne r2,zero,6670 - 6664: e0bfff17 ldw r2,-4(fp) - 6668: 10bffe58 cmpnei r2,r2,-7 - 666c: 1000061e bne r2,zero,6688 - 6670: 0001883a nop - 6674: e0bffe17 ldw r2,-8(fp) - 6678: 10ffffc4 addi r3,r2,-1 - 667c: e0fffe15 stw r3,-8(fp) - 6680: 103fda1e bne r2,zero,65ec - 6684: 00000106 br 668c - 6688: 0001883a nop - 668c: e0bfff17 ldw r2,-4(fp) - 6690: e037883a mov sp,fp - 6694: dfc00117 ldw ra,4(sp) - 6698: df000017 ldw fp,0(sp) - 669c: dec00204 addi sp,sp,8 - 66a0: f800283a ret - -000066a4 : - 66a4: defff704 addi sp,sp,-36 - 66a8: dfc00815 stw ra,32(sp) - 66ac: df000715 stw fp,28(sp) - 66b0: df000704 addi fp,sp,28 - 66b4: e13ffd15 stw r4,-12(fp) - 66b8: e17ffc15 stw r5,-16(fp) - 66bc: e1bffb15 stw r6,-20(fp) - 66c0: 3805883a mov r2,r7 - 66c4: e0bffa05 stb r2,-24(fp) - 66c8: 0089c404 movi r2,10000 - 66cc: e0bffe15 stw r2,-8(fp) - 66d0: e0bffa03 ldbu r2,-24(fp) - 66d4: 10003426 beq r2,zero,67a8 - 66d8: 00001706 br 6738 - 66dc: e0bffe17 ldw r2,-8(fp) - 66e0: 108002a8 cmpgeui r2,r2,10 - 66e4: 1000021e bne r2,zero,66f0 - 66e8: 0109c404 movi r4,10000 - 66ec: 00077fc0 call 77fc - 66f0: 00800044 movi r2,1 - 66f4: d8800015 stw r2,0(sp) - 66f8: 000f883a mov r7,zero - 66fc: e1bffb17 ldw r6,-20(fp) - 6700: e17ffc17 ldw r5,-16(fp) - 6704: e13ffd17 ldw r4,-12(fp) - 6708: 0006f780 call 6f78 - 670c: e0bfff15 stw r2,-4(fp) - 6710: e0bfff17 ldw r2,-4(fp) - 6714: 10bffea0 cmpeqi r2,r2,-6 - 6718: 1000061e bne r2,zero,6734 - 671c: e0bfff17 ldw r2,-4(fp) - 6720: 10bffee0 cmpeqi r2,r2,-5 - 6724: 1000031e bne r2,zero,6734 - 6728: e0bfff17 ldw r2,-4(fp) - 672c: 10bffe58 cmpnei r2,r2,-7 - 6730: 1000221e bne r2,zero,67bc - 6734: 0001883a nop - 6738: e0bffe17 ldw r2,-8(fp) - 673c: 10ffffc4 addi r3,r2,-1 - 6740: e0fffe15 stw r3,-8(fp) - 6744: 103fe51e bne r2,zero,66dc - 6748: 00001f06 br 67c8 - 674c: e0bffe17 ldw r2,-8(fp) - 6750: 108002a8 cmpgeui r2,r2,10 - 6754: 1000021e bne r2,zero,6760 - 6758: 0109c404 movi r4,10000 - 675c: 00077fc0 call 77fc - 6760: 00800044 movi r2,1 - 6764: d8800015 stw r2,0(sp) - 6768: 000f883a mov r7,zero - 676c: e1bffb17 ldw r6,-20(fp) - 6770: e17ffc17 ldw r5,-16(fp) - 6774: e13ffd17 ldw r4,-12(fp) - 6778: 0006d6c0 call 6d6c - 677c: e0bfff15 stw r2,-4(fp) - 6780: e0bfff17 ldw r2,-4(fp) - 6784: 10bffea0 cmpeqi r2,r2,-6 - 6788: 1000061e bne r2,zero,67a4 - 678c: e0bfff17 ldw r2,-4(fp) - 6790: 10bffee0 cmpeqi r2,r2,-5 - 6794: 1000031e bne r2,zero,67a4 - 6798: e0bfff17 ldw r2,-4(fp) - 679c: 10bffe58 cmpnei r2,r2,-7 - 67a0: 1000081e bne r2,zero,67c4 - 67a4: 0001883a nop - 67a8: e0bffe17 ldw r2,-8(fp) - 67ac: 10ffffc4 addi r3,r2,-1 - 67b0: e0fffe15 stw r3,-8(fp) - 67b4: 103fe51e bne r2,zero,674c - 67b8: 00000306 br 67c8 - 67bc: 0001883a nop - 67c0: 00000106 br 67c8 - 67c4: 0001883a nop - 67c8: e0bfff17 ldw r2,-4(fp) - 67cc: e037883a mov sp,fp - 67d0: dfc00117 ldw ra,4(sp) - 67d4: df000017 ldw fp,0(sp) - 67d8: dec00204 addi sp,sp,8 - 67dc: f800283a ret - -000067e0 : - 67e0: defff604 addi sp,sp,-40 - 67e4: dfc00915 stw ra,36(sp) - 67e8: df000815 stw fp,32(sp) - 67ec: df000804 addi fp,sp,32 - 67f0: e13ffd15 stw r4,-12(fp) - 67f4: e17ffc15 stw r5,-16(fp) - 67f8: e1bffb15 stw r6,-20(fp) - 67fc: e1fffa15 stw r7,-24(fp) - 6800: e0800317 ldw r2,12(fp) - 6804: e0bff905 stb r2,-28(fp) - 6808: 0089c404 movi r2,10000 - 680c: e0bffe15 stw r2,-8(fp) - 6810: e0bff903 ldbu r2,-28(fp) - 6814: 10005626 beq r2,zero,6970 - 6818: 00002806 br 68bc - 681c: e0bffe17 ldw r2,-8(fp) - 6820: 108002a8 cmpgeui r2,r2,10 - 6824: 1000021e bne r2,zero,6830 - 6828: 0109c404 movi r4,10000 - 682c: 00077fc0 call 77fc - 6830: d8000015 stw zero,0(sp) - 6834: 000f883a mov r7,zero - 6838: e1bffb17 ldw r6,-20(fp) - 683c: e17ffc17 ldw r5,-16(fp) - 6840: e13ffd17 ldw r4,-12(fp) - 6844: 0006b640 call 6b64 - 6848: e0bfff15 stw r2,-4(fp) - 684c: e0bfff17 ldw r2,-4(fp) - 6850: 10bffea0 cmpeqi r2,r2,-6 - 6854: 1000191e bne r2,zero,68bc - 6858: e0bfff17 ldw r2,-4(fp) - 685c: 10bffee0 cmpeqi r2,r2,-5 - 6860: 1000161e bne r2,zero,68bc - 6864: e0bfff17 ldw r2,-4(fp) - 6868: 10bffe58 cmpnei r2,r2,-7 - 686c: 1000011e bne r2,zero,6874 - 6870: 00001206 br 68bc - 6874: 00800044 movi r2,1 - 6878: d8800015 stw r2,0(sp) - 687c: 01c00044 movi r7,1 - 6880: e1800217 ldw r6,8(fp) - 6884: e17ffa17 ldw r5,-24(fp) - 6888: e13ffd17 ldw r4,-12(fp) - 688c: 0006f780 call 6f78 - 6890: e0bfff15 stw r2,-4(fp) - 6894: e0bfff17 ldw r2,-4(fp) - 6898: 10bffea0 cmpeqi r2,r2,-6 - 689c: 1000061e bne r2,zero,68b8 - 68a0: e0bfff17 ldw r2,-4(fp) - 68a4: 10bffee0 cmpeqi r2,r2,-5 - 68a8: 1000031e bne r2,zero,68b8 - 68ac: e0bfff17 ldw r2,-4(fp) - 68b0: 10bffe58 cmpnei r2,r2,-7 - 68b4: 1000331e bne r2,zero,6984 - 68b8: 0001883a nop - 68bc: e0bffe17 ldw r2,-8(fp) - 68c0: 10ffffc4 addi r3,r2,-1 - 68c4: e0fffe15 stw r3,-8(fp) - 68c8: 103fd41e bne r2,zero,681c - 68cc: 00003006 br 6990 - 68d0: e0bffe17 ldw r2,-8(fp) - 68d4: 108002a8 cmpgeui r2,r2,10 - 68d8: 1000021e bne r2,zero,68e4 - 68dc: 0109c404 movi r4,10000 - 68e0: 00077fc0 call 77fc - 68e4: d8000015 stw zero,0(sp) - 68e8: 000f883a mov r7,zero - 68ec: e1bffb17 ldw r6,-20(fp) - 68f0: e17ffc17 ldw r5,-16(fp) - 68f4: e13ffd17 ldw r4,-12(fp) - 68f8: 00069a80 call 69a8 - 68fc: e0bfff15 stw r2,-4(fp) - 6900: e0bfff17 ldw r2,-4(fp) - 6904: 10bffea0 cmpeqi r2,r2,-6 - 6908: 1000191e bne r2,zero,6970 - 690c: e0bfff17 ldw r2,-4(fp) - 6910: 10bffee0 cmpeqi r2,r2,-5 - 6914: 1000161e bne r2,zero,6970 - 6918: e0bfff17 ldw r2,-4(fp) - 691c: 10bffe58 cmpnei r2,r2,-7 - 6920: 1000011e bne r2,zero,6928 - 6924: 00001206 br 6970 - 6928: 00800044 movi r2,1 - 692c: d8800015 stw r2,0(sp) - 6930: 01c00044 movi r7,1 - 6934: e1800217 ldw r6,8(fp) - 6938: e17ffa17 ldw r5,-24(fp) - 693c: e13ffd17 ldw r4,-12(fp) - 6940: 0006d6c0 call 6d6c - 6944: e0bfff15 stw r2,-4(fp) - 6948: e0bfff17 ldw r2,-4(fp) - 694c: 10bffea0 cmpeqi r2,r2,-6 - 6950: 1000061e bne r2,zero,696c - 6954: e0bfff17 ldw r2,-4(fp) - 6958: 10bffee0 cmpeqi r2,r2,-5 - 695c: 1000031e bne r2,zero,696c - 6960: e0bfff17 ldw r2,-4(fp) - 6964: 10bffe58 cmpnei r2,r2,-7 - 6968: 1000081e bne r2,zero,698c - 696c: 0001883a nop - 6970: e0bffe17 ldw r2,-8(fp) - 6974: 10ffffc4 addi r3,r2,-1 - 6978: e0fffe15 stw r3,-8(fp) - 697c: 103fd41e bne r2,zero,68d0 - 6980: 00000306 br 6990 - 6984: 0001883a nop - 6988: 00000106 br 6990 - 698c: 0001883a nop - 6990: e0bfff17 ldw r2,-4(fp) - 6994: e037883a mov sp,fp - 6998: dfc00117 ldw ra,4(sp) - 699c: df000017 ldw fp,0(sp) - 69a0: dec00204 addi sp,sp,8 - 69a4: f800283a ret - -000069a8 : - 69a8: defff704 addi sp,sp,-36 - 69ac: dfc00815 stw ra,32(sp) - 69b0: df000715 stw fp,28(sp) - 69b4: df000704 addi fp,sp,28 - 69b8: e13ffd15 stw r4,-12(fp) - 69bc: e17ffc15 stw r5,-16(fp) - 69c0: e1bffb15 stw r6,-20(fp) - 69c4: 3807883a mov r3,r7 - 69c8: e0800217 ldw r2,8(fp) - 69cc: e0fffa05 stb r3,-24(fp) - 69d0: e0bff905 stb r2,-28(fp) - 69d4: e03ffe15 stw zero,-8(fp) - 69d8: e0bffb17 ldw r2,-20(fp) - 69dc: 1089c424 muli r2,r2,10000 - 69e0: e0bfff15 stw r2,-4(fp) - 69e4: e0bffb17 ldw r2,-20(fp) - 69e8: 1000021e bne r2,zero,69f4 - 69ec: 0005883a mov r2,zero - 69f0: 00005706 br 6b50 - 69f4: e0bffa03 ldbu r2,-24(fp) - 69f8: 10000a1e bne r2,zero,6a24 - 69fc: e13ffd17 ldw r4,-12(fp) - 6a00: 0005c200 call 5c20 - 6a04: e0bffe15 stw r2,-8(fp) - 6a08: e0bffe17 ldw r2,-8(fp) - 6a0c: 10000226 beq r2,zero,6a18 - 6a10: e0bffe17 ldw r2,-8(fp) - 6a14: 00004e06 br 6b50 - 6a18: 01400704 movi r5,28 - 6a1c: e13ffd17 ldw r4,-12(fp) - 6a20: 00072000 call 7200 - 6a24: e0bffa03 ldbu r2,-24(fp) - 6a28: 100d883a mov r6,r2 - 6a2c: 000b883a mov r5,zero - 6a30: e13ffd17 ldw r4,-12(fp) - 6a34: 00062940 call 6294 - 6a38: e0bffe15 stw r2,-8(fp) - 6a3c: e0bffe17 ldw r2,-8(fp) - 6a40: 1000271e bne r2,zero,6ae0 - 6a44: 00000f06 br 6a84 - 6a48: e0bffc17 ldw r2,-16(fp) - 6a4c: 10800003 ldbu r2,0(r2) - 6a50: 10803fcc andi r2,r2,255 - 6a54: 000f883a mov r7,zero - 6a58: 000d883a mov r6,zero - 6a5c: 100b883a mov r5,r2 - 6a60: e13ffd17 ldw r4,-12(fp) - 6a64: 00061a80 call 61a8 - 6a68: e0bffe15 stw r2,-8(fp) - 6a6c: e0bffc17 ldw r2,-16(fp) - 6a70: 10800044 addi r2,r2,1 - 6a74: e0bffc15 stw r2,-16(fp) - 6a78: e0bffb17 ldw r2,-20(fp) - 6a7c: 10bfffc4 addi r2,r2,-1 - 6a80: e0bffb15 stw r2,-20(fp) - 6a84: e0bffb17 ldw r2,-20(fp) - 6a88: 108000b0 cmpltui r2,r2,2 - 6a8c: 1000021e bne r2,zero,6a98 - 6a90: e0bffe17 ldw r2,-8(fp) - 6a94: 103fec26 beq r2,zero,6a48 - 6a98: e0bffe17 ldw r2,-8(fp) - 6a9c: 1000101e bne r2,zero,6ae0 - 6aa0: e0bffc17 ldw r2,-16(fp) - 6aa4: 10800003 ldbu r2,0(r2) - 6aa8: 10803fcc andi r2,r2,255 - 6aac: e0fff903 ldbu r3,-28(fp) - 6ab0: 180f883a mov r7,r3 - 6ab4: 000d883a mov r6,zero - 6ab8: 100b883a mov r5,r2 - 6abc: e13ffd17 ldw r4,-12(fp) - 6ac0: 00061a80 call 61a8 - 6ac4: e0bffe15 stw r2,-8(fp) - 6ac8: e0bffc17 ldw r2,-16(fp) - 6acc: 10800044 addi r2,r2,1 - 6ad0: e0bffc15 stw r2,-16(fp) - 6ad4: e0bffb17 ldw r2,-20(fp) - 6ad8: 10bfffc4 addi r2,r2,-1 - 6adc: e0bffb15 stw r2,-20(fp) - 6ae0: e0bff903 ldbu r2,-28(fp) - 6ae4: 1000101e bne r2,zero,6b28 - 6ae8: e0bffe17 ldw r2,-8(fp) - 6aec: 10001726 beq r2,zero,6b4c - 6af0: 00000d06 br 6b28 - 6af4: e0bfff17 ldw r2,-4(fp) - 6af8: 108002a8 cmpgeui r2,r2,10 - 6afc: 1000021e bne r2,zero,6b08 - 6b00: 0109c404 movi r4,10000 - 6b04: 00077fc0 call 77fc - 6b08: e0bfff17 ldw r2,-4(fp) - 6b0c: 10bfffc4 addi r2,r2,-1 - 6b10: e0bfff15 stw r2,-4(fp) - 6b14: e0bfff17 ldw r2,-4(fp) - 6b18: 1000031e bne r2,zero,6b28 - 6b1c: 00bfff84 movi r2,-2 - 6b20: e0bffe15 stw r2,-8(fp) - 6b24: 00000306 br 6b34 - 6b28: e13ffd17 ldw r4,-12(fp) - 6b2c: 00060100 call 6010 - 6b30: 103ff01e bne r2,zero,6af4 - 6b34: e0bffe04 addi r2,fp,-8 - 6b38: 100b883a mov r5,r2 - 6b3c: e13ffd17 ldw r4,-12(fp) - 6b40: 00063f00 call 63f0 - 6b44: e13ffd17 ldw r4,-12(fp) - 6b48: 0005cb80 call 5cb8 - 6b4c: e0bffe17 ldw r2,-8(fp) - 6b50: e037883a mov sp,fp - 6b54: dfc00117 ldw ra,4(sp) - 6b58: df000017 ldw fp,0(sp) - 6b5c: dec00204 addi sp,sp,8 + 6524: 8006d07a srli r3,r16,1 + 6528: 2088703a and r4,r4,r2 + 652c: 200497fa slli r2,r4,31 + 6530: 8400004c andi r16,r16,1 + 6534: 1c20b03a or r16,r3,r16 + 6538: 2008d07a srli r4,r4,1 + 653c: 1420b03a or r16,r2,r16 + 6540: 003ef806 br 6124 <__subdf3+0x15c> + 6544: 1c3ff804 addi r16,r3,-32 + 6548: 18800820 cmpeqi r2,r3,32 + 654c: 7c0ad83a srl r5,r15,r16 + 6550: 1000041e bne r2,zero,6564 <__subdf3+0x59c> + 6554: 00801004 movi r2,64 + 6558: 10c5c83a sub r2,r2,r3 + 655c: 7884983a sll r2,r15,r2 + 6560: 689ab03a or r13,r13,r2 + 6564: 6820c03a cmpne r16,r13,zero + 6568: 8160b03a or r16,r16,r5 + 656c: 003ecc06 br 60a0 <__subdf3+0xd8> + 6570: 4b92b03a or r9,r9,r14 + 6574: 4820c03a cmpne r16,r9,zero + 6578: 6c21c83a sub r16,r13,r16 + 657c: 6c09803a cmpltu r4,r13,r16 + 6580: 7909c83a sub r4,r15,r4 + 6584: 4025883a mov r18,r8 + 6588: 003ec806 br 60ac <__subdf3+0xe4> + 658c: 4b84b03a or r2,r9,r14 + 6590: 10007e26 beq r2,zero,678c <__subdf3+0x7c4> + 6594: 18bfffc4 addi r2,r3,-1 + 6598: 1000a726 beq r2,zero,6838 <__subdf3+0x870> + 659c: 18c1ffd8 cmpnei r3,r3,2047 + 65a0: 18003826 beq r3,zero,6684 <__subdf3+0x6bc> + 65a4: 1007883a mov r3,r2 + 65a8: 003f9206 br 63f4 <__subdf3+0x42c> + 65ac: 00800804 movi r2,32 + 65b0: 10c5c83a sub r2,r2,r3 + 65b4: 78a0983a sll r16,r15,r2 + 65b8: 68c8d83a srl r4,r13,r3 + 65bc: 689a983a sll r13,r13,r2 + 65c0: 78c4d83a srl r2,r15,r3 + 65c4: 8120b03a or r16,r16,r4 + 65c8: 681ac03a cmpne r13,r13,zero + 65cc: 8360b03a or r16,r16,r13 + 65d0: 4893883a add r9,r9,r2 + 65d4: 003f5a06 br 6340 <__subdf3+0x378> + 65d8: 10c1ffe0 cmpeqi r3,r2,2047 + 65dc: 183f601e bne r3,zero,6360 <__subdf3+0x398> + 65e0: 735b883a add r13,r14,r13 + 65e4: 6b9d803a cmpltu r14,r13,r14 + 65e8: 4bc9883a add r4,r9,r15 + 65ec: 2389883a add r4,r4,r14 + 65f0: 202097fa slli r16,r4,31 + 65f4: 681ad07a srli r13,r13,1 + 65f8: 2008d07a srli r4,r4,1 + 65fc: 1025883a mov r18,r2 + 6600: 8360b03a or r16,r16,r13 + 6604: 003f3e06 br 6300 <__subdf3+0x338> + 6608: 6ba1c83a sub r16,r13,r14 + 660c: 7a49c83a sub r4,r15,r9 + 6610: 6c1b803a cmpltu r13,r13,r16 + 6614: 2367c83a sub r19,r4,r13 + 6618: 5823883a mov r17,r11 + 661c: 003ea806 br 60c0 <__subdf3+0xf8> + 6620: 7808977a slli r4,r15,29 + 6624: 00880034 movhi r2,8192 + 6628: 10bfffc4 addi r2,r2,-1 + 662c: 308c703a and r6,r6,r2 + 6630: 7812d0fa srli r9,r15,3 + 6634: 3104b03a or r2,r6,r4 + 6638: 003f3806 br 631c <__subdf3+0x354> + 663c: 28005a1e bne r5,zero,67a8 <__subdf3+0x7e0> + 6640: 10008526 beq r2,zero,6858 <__subdf3+0x890> + 6644: 7806977a slli r3,r15,29 + 6648: 00880034 movhi r2,8192 + 664c: 10bfffc4 addi r2,r2,-1 + 6650: 3084703a and r2,r6,r2 + 6654: 7812d0fa srli r9,r15,3 + 6658: 10c4b03a or r2,r2,r3 + 665c: 5823883a mov r17,r11 + 6660: 003f4906 br 6388 <__subdf3+0x3c0> + 6664: 7361883a add r16,r14,r13 + 6668: 4bc9883a add r4,r9,r15 + 666c: 839d803a cmpltu r14,r16,r14 + 6670: 2389883a add r4,r4,r14 + 6674: 2080202c andhi r2,r4,128 + 6678: 103fa71e bne r2,zero,6518 <__subdf3+0x550> + 667c: 04800044 movi r18,1 + 6680: 003f1f06 br 6300 <__subdf3+0x338> + 6684: 7806977a slli r3,r15,29 + 6688: 00880034 movhi r2,8192 + 668c: 10bfffc4 addi r2,r2,-1 + 6690: 3084703a and r2,r6,r2 + 6694: 7812d0fa srli r9,r15,3 + 6698: 10c4b03a or r2,r2,r3 + 669c: 003f3a06 br 6388 <__subdf3+0x3c0> + 66a0: 7361c83a sub r16,r14,r13 + 66a4: 4bc9c83a sub r4,r9,r15 + 66a8: 741d803a cmpltu r14,r14,r16 + 66ac: 2389c83a sub r4,r4,r14 + 66b0: 04800044 movi r18,1 + 66b4: 003e7d06 br 60ac <__subdf3+0xe4> + 66b8: 480a977a slli r5,r9,29 + 66bc: 00880034 movhi r2,8192 + 66c0: 10bfffc4 addi r2,r2,-1 + 66c4: 2084703a and r2,r4,r2 + 66c8: 4812d0fa srli r9,r9,3 + 66cc: 1144b03a or r2,r2,r5 + 66d0: 003f1406 br 6324 <__subdf3+0x35c> + 66d4: 4b92b03a or r9,r9,r14 + 66d8: 4820c03a cmpne r16,r9,zero + 66dc: 003f5306 br 642c <__subdf3+0x464> + 66e0: 1c3ff804 addi r16,r3,-32 + 66e4: 19000820 cmpeqi r4,r3,32 + 66e8: 4c04d83a srl r2,r9,r16 + 66ec: 2000041e bne r4,zero,6700 <__subdf3+0x738> + 66f0: 01001004 movi r4,64 + 66f4: 20c7c83a sub r3,r4,r3 + 66f8: 48d2983a sll r9,r9,r3 + 66fc: 725cb03a or r14,r14,r9 + 6700: 7020c03a cmpne r16,r14,zero + 6704: 80a0b03a or r16,r16,r2 + 6708: 003f9b06 br 6578 <__subdf3+0x5b0> + 670c: 103fdd26 beq r2,zero,6684 <__subdf3+0x6bc> + 6710: 7b5ab03a or r13,r15,r13 + 6714: 480a977a slli r5,r9,29 + 6718: 4812d0fa srli r9,r9,3 + 671c: 6800251e bne r13,zero,67b4 <__subdf3+0x7ec> + 6720: 00880034 movhi r2,8192 + 6724: 10bfffc4 addi r2,r2,-1 + 6728: 2084703a and r2,r4,r2 + 672c: 1144b03a or r2,r2,r5 + 6730: 003f1506 br 6388 <__subdf3+0x3c0> + 6734: 103f7526 beq r2,zero,650c <__subdf3+0x544> + 6738: 7808977a slli r4,r15,29 + 673c: 00880034 movhi r2,8192 + 6740: 10bfffc4 addi r2,r2,-1 + 6744: 3084703a and r2,r6,r2 + 6748: 7812d0fa srli r9,r15,3 + 674c: 1104b03a or r2,r2,r4 + 6750: 5823883a mov r17,r11 + 6754: 003ef306 br 6324 <__subdf3+0x35c> + 6758: 6ba1c83a sub r16,r13,r14 + 675c: 7a49c83a sub r4,r15,r9 + 6760: 6c1b803a cmpltu r13,r13,r16 + 6764: 2349c83a sub r4,r4,r13 + 6768: 04800044 movi r18,1 + 676c: 003e4f06 br 60ac <__subdf3+0xe4> + 6770: 4806977a slli r3,r9,29 + 6774: 00880034 movhi r2,8192 + 6778: 10bfffc4 addi r2,r2,-1 + 677c: 2084703a and r2,r4,r2 + 6780: 4812d0fa srli r9,r9,3 + 6784: 10c4b03a or r2,r2,r3 + 6788: 003eff06 br 6388 <__subdf3+0x3c0> + 678c: 7808977a slli r4,r15,29 + 6790: 00880034 movhi r2,8192 + 6794: 10bfffc4 addi r2,r2,-1 + 6798: 3084703a and r2,r6,r2 + 679c: 7812d0fa srli r9,r15,3 + 67a0: 1104b03a or r2,r2,r4 + 67a4: 003edd06 br 631c <__subdf3+0x354> + 67a8: 480a977a slli r5,r9,29 + 67ac: 4812d0fa srli r9,r9,3 + 67b0: 103fdb26 beq r2,zero,6720 <__subdf3+0x758> + 67b4: 00c80034 movhi r3,8192 + 67b8: 18ffffc4 addi r3,r3,-1 + 67bc: 20c4703a and r2,r4,r3 + 67c0: 4900022c andhi r4,r9,8 + 67c4: 1144b03a or r2,r2,r5 + 67c8: 203eef26 beq r4,zero,6388 <__subdf3+0x3c0> + 67cc: 7808d0fa srli r4,r15,3 + 67d0: 2140022c andhi r5,r4,8 + 67d4: 283eec1e bne r5,zero,6388 <__subdf3+0x3c0> + 67d8: 7804977a slli r2,r15,29 + 67dc: 30cc703a and r6,r6,r3 + 67e0: 5823883a mov r17,r11 + 67e4: 3084b03a or r2,r6,r2 + 67e8: 2013883a mov r9,r4 + 67ec: 003ee606 br 6388 <__subdf3+0x3c0> + 67f0: 7808977a slli r4,r15,29 + 67f4: 00880034 movhi r2,8192 + 67f8: 10bfffc4 addi r2,r2,-1 + 67fc: 3084703a and r2,r6,r2 + 6800: 7812d0fa srli r9,r15,3 + 6804: 1104b03a or r2,r2,r4 + 6808: 003ec606 br 6324 <__subdf3+0x35c> + 680c: 18bff804 addi r2,r3,-32 + 6810: 19000820 cmpeqi r4,r3,32 + 6814: 4884d83a srl r2,r9,r2 + 6818: 2000041e bne r4,zero,682c <__subdf3+0x864> + 681c: 01001004 movi r4,64 + 6820: 20c7c83a sub r3,r4,r3 + 6824: 48d2983a sll r9,r9,r3 + 6828: 725cb03a or r14,r14,r9 + 682c: 7020c03a cmpne r16,r14,zero + 6830: 80a0b03a or r16,r16,r2 + 6834: 003efd06 br 642c <__subdf3+0x464> + 6838: 7361883a add r16,r14,r13 + 683c: 4bc9883a add r4,r9,r15 + 6840: 835b803a cmpltu r13,r16,r13 + 6844: 2349883a add r4,r4,r13 + 6848: 003f8a06 br 6674 <__subdf3+0x6ac> + 684c: 8104b03a or r2,r16,r4 + 6850: 103f2e26 beq r2,zero,650c <__subdf3+0x544> + 6854: 003eaa06 br 6300 <__subdf3+0x338> + 6858: 02400434 movhi r9,16 + 685c: 0023883a mov r17,zero + 6860: 00bfffc4 movi r2,-1 + 6864: 4a7fffc4 addi r9,r9,-1 + 6868: 003ec906 br 6390 <__subdf3+0x3c8> + 686c: 0005883a mov r2,zero + 6870: 00c1ffc4 movi r3,2047 + 6874: 0009883a mov r4,zero + 6878: 003e4106 br 6180 <__subdf3+0x1b8> + +0000687c <__unorddf2>: + 687c: 2806d53a srli r3,r5,20 + 6880: 3810d53a srli r8,r7,20 + 6884: 02400434 movhi r9,16 + 6888: 18c1ffcc andi r3,r3,2047 + 688c: 4a7fffc4 addi r9,r9,-1 + 6890: 18c1ffd8 cmpnei r3,r3,2047 + 6894: 2a4a703a and r5,r5,r9 + 6898: 3a4e703a and r7,r7,r9 + 689c: 4201ffcc andi r8,r8,2047 + 68a0: 18000426 beq r3,zero,68b4 <__unorddf2+0x38> + 68a4: 4201ffd8 cmpnei r8,r8,2047 + 68a8: 40000626 beq r8,zero,68c4 <__unorddf2+0x48> + 68ac: 0005883a mov r2,zero + 68b0: f800283a ret + 68b4: 290ab03a or r5,r5,r4 + 68b8: 283ffa26 beq r5,zero,68a4 <__unorddf2+0x28> + 68bc: 00800044 movi r2,1 + 68c0: f800283a ret + 68c4: 398eb03a or r7,r7,r6 + 68c8: 3804c03a cmpne r2,r7,zero + 68cc: f800283a ret + +000068d0 <__fixdfsi>: + 68d0: 2806d53a srli r3,r5,20 + 68d4: 01800434 movhi r6,16 + 68d8: 31bfffc4 addi r6,r6,-1 + 68dc: 18c1ffcc andi r3,r3,2047 + 68e0: 19c0ffd0 cmplti r7,r3,1023 + 68e4: 2810d7fa srli r8,r5,31 + 68e8: 298a703a and r5,r5,r6 + 68ec: 3800061e bne r7,zero,6908 <__fixdfsi+0x38> + 68f0: 18810790 cmplti r2,r3,1054 + 68f4: 1000061e bne r2,zero,6910 <__fixdfsi+0x40> + 68f8: 00a00034 movhi r2,32768 + 68fc: 10bfffc4 addi r2,r2,-1 + 6900: 4085883a add r2,r8,r2 + 6904: f800283a ret + 6908: 0005883a mov r2,zero + 690c: f800283a ret + 6910: 01810cc4 movi r6,1075 + 6914: 30cdc83a sub r6,r6,r3 + 6918: 30800808 cmpgei r2,r6,32 + 691c: 29400434 orhi r5,r5,16 + 6920: 1000071e bne r2,zero,6940 <__fixdfsi+0x70> + 6924: 18befb44 addi r2,r3,-1043 + 6928: 2884983a sll r2,r5,r2 + 692c: 2188d83a srl r4,r4,r6 + 6930: 1104b03a or r2,r2,r4 + 6934: 403ff526 beq r8,zero,690c <__fixdfsi+0x3c> + 6938: 0085c83a sub r2,zero,r2 + 693c: f800283a ret + 6940: 008104c4 movi r2,1043 + 6944: 10c5c83a sub r2,r2,r3 + 6948: 2884d83a srl r2,r5,r2 + 694c: 003ff906 br 6934 <__fixdfsi+0x64> + +00006950 <__floatsidf>: + 6950: defffd04 addi sp,sp,-12 + 6954: dfc00215 stw ra,8(sp) + 6958: dc400115 stw r17,4(sp) + 695c: dc000015 stw r16,0(sp) + 6960: 20001326 beq r4,zero,69b0 <__floatsidf+0x60> + 6964: 2022d7fa srli r17,r4,31 + 6968: 2021883a mov r16,r4 + 696c: 20002416 blt r4,zero,6a00 <__floatsidf+0xb0> + 6970: 8009883a mov r4,r16 + 6974: 0006b040 call 6b04 <__clzsi2> + 6978: 01010784 movi r4,1054 + 697c: 2089c83a sub r4,r4,r2 + 6980: 114002c8 cmpgei r5,r2,11 + 6984: 20c1ffcc andi r3,r4,2047 + 6988: 2800161e bne r5,zero,69e4 <__floatsidf+0x94> + 698c: 010002c4 movi r4,11 + 6990: 2089c83a sub r4,r4,r2 + 6994: 810ad83a srl r5,r16,r4 + 6998: 01000434 movhi r4,16 + 699c: 10800544 addi r2,r2,21 + 69a0: 213fffc4 addi r4,r4,-1 + 69a4: 8084983a sll r2,r16,r2 + 69a8: 290a703a and r5,r5,r4 + 69ac: 00000406 br 69c0 <__floatsidf+0x70> + 69b0: 0023883a mov r17,zero + 69b4: 0007883a mov r3,zero + 69b8: 000b883a mov r5,zero + 69bc: 0005883a mov r2,zero + 69c0: 1808953a slli r4,r3,20 + 69c4: 880697fa slli r3,r17,31 + 69c8: 2148b03a or r4,r4,r5 + 69cc: 20c6b03a or r3,r4,r3 + 69d0: dfc00217 ldw ra,8(sp) + 69d4: dc400117 ldw r17,4(sp) + 69d8: dc000017 ldw r16,0(sp) + 69dc: dec00304 addi sp,sp,12 + 69e0: f800283a ret + 69e4: 10bffd44 addi r2,r2,-11 + 69e8: 808a983a sll r5,r16,r2 + 69ec: 00800434 movhi r2,16 + 69f0: 10bfffc4 addi r2,r2,-1 + 69f4: 288a703a and r5,r5,r2 + 69f8: 0005883a mov r2,zero + 69fc: 003ff006 br 69c0 <__floatsidf+0x70> + 6a00: 0121c83a sub r16,zero,r4 + 6a04: 003fda06 br 6970 <__floatsidf+0x20> + +00006a08 <__extendsfdf2>: + 6a08: 200ad5fa srli r5,r4,23 + 6a0c: defffd04 addi sp,sp,-12 + 6a10: dc000015 stw r16,0(sp) + 6a14: 29403fcc andi r5,r5,255 + 6a18: 04002034 movhi r16,128 + 6a1c: 28800044 addi r2,r5,1 + 6a20: dc400115 stw r17,4(sp) + 6a24: 843fffc4 addi r16,r16,-1 + 6a28: dfc00215 stw ra,8(sp) + 6a2c: 10803f8c andi r2,r2,254 + 6a30: 2022d7fa srli r17,r4,31 + 6a34: 8120703a and r16,r16,r4 + 6a38: 10000d26 beq r2,zero,6a70 <__extendsfdf2+0x68> + 6a3c: 8008d0fa srli r4,r16,3 + 6a40: 8020977a slli r16,r16,29 + 6a44: 28c0e004 addi r3,r5,896 + 6a48: 180a953a slli r5,r3,20 + 6a4c: 880697fa slli r3,r17,31 + 6a50: 8005883a mov r2,r16 + 6a54: 290ab03a or r5,r5,r4 + 6a58: 28c6b03a or r3,r5,r3 + 6a5c: dfc00217 ldw ra,8(sp) + 6a60: dc400117 ldw r17,4(sp) + 6a64: dc000017 ldw r16,0(sp) + 6a68: dec00304 addi sp,sp,12 + 6a6c: f800283a ret + 6a70: 2800111e bne r5,zero,6ab8 <__extendsfdf2+0xb0> + 6a74: 80001926 beq r16,zero,6adc <__extendsfdf2+0xd4> + 6a78: 8009883a mov r4,r16 + 6a7c: 0006b040 call 6b04 <__clzsi2> + 6a80: 10c002c8 cmpgei r3,r2,11 + 6a84: 18001b1e bne r3,zero,6af4 <__extendsfdf2+0xec> + 6a88: 010002c4 movi r4,11 + 6a8c: 2089c83a sub r4,r4,r2 + 6a90: 10c00544 addi r3,r2,21 + 6a94: 810ad83a srl r5,r16,r4 + 6a98: 80e0983a sll r16,r16,r3 + 6a9c: 01000434 movhi r4,16 + 6aa0: 00c0e244 movi r3,905 + 6aa4: 213fffc4 addi r4,r4,-1 + 6aa8: 1887c83a sub r3,r3,r2 + 6aac: 2908703a and r4,r5,r4 + 6ab0: 18c1ffcc andi r3,r3,2047 + 6ab4: 003fe406 br 6a48 <__extendsfdf2+0x40> + 6ab8: 80000b26 beq r16,zero,6ae8 <__extendsfdf2+0xe0> + 6abc: 800ad0fa srli r5,r16,3 + 6ac0: 00800434 movhi r2,16 + 6ac4: 10bfffc4 addi r2,r2,-1 + 6ac8: 29000234 orhi r4,r5,8 + 6acc: 8020977a slli r16,r16,29 + 6ad0: 2088703a and r4,r4,r2 + 6ad4: 00c1ffc4 movi r3,2047 + 6ad8: 003fdb06 br 6a48 <__extendsfdf2+0x40> + 6adc: 0007883a mov r3,zero + 6ae0: 0009883a mov r4,zero + 6ae4: 003fd806 br 6a48 <__extendsfdf2+0x40> + 6ae8: 00c1ffc4 movi r3,2047 + 6aec: 0009883a mov r4,zero + 6af0: 003fd506 br 6a48 <__extendsfdf2+0x40> + 6af4: 113ffd44 addi r4,r2,-11 + 6af8: 810a983a sll r5,r16,r4 + 6afc: 0021883a mov r16,zero + 6b00: 003fe606 br 6a9c <__extendsfdf2+0x94> + +00006b04 <__clzsi2>: + 6b04: 00bfffd4 movui r2,65535 + 6b08: 11000436 bltu r2,r4,6b1c <__clzsi2+0x18> + 6b0c: 20804030 cmpltui r2,r4,256 + 6b10: 10000e26 beq r2,zero,6b4c <__clzsi2+0x48> + 6b14: 01400804 movi r5,32 + 6b18: 00000406 br 6b2c <__clzsi2+0x28> + 6b1c: 00804034 movhi r2,256 + 6b20: 20800736 bltu r4,r2,6b40 <__clzsi2+0x3c> + 6b24: 2008d63a srli r4,r4,24 + 6b28: 01400204 movi r5,8 + 6b2c: 00c00074 movhi r3,1 + 6b30: 20c7883a add r3,r4,r3 + 6b34: 18ae7f03 ldbu r2,-17924(r3) + 6b38: 2885c83a sub r2,r5,r2 + 6b3c: f800283a ret + 6b40: 2008d43a srli r4,r4,16 + 6b44: 01400404 movi r5,16 + 6b48: 003ff806 br 6b2c <__clzsi2+0x28> + 6b4c: 2008d23a srli r4,r4,8 + 6b50: 01400604 movi r5,24 + 6b54: 003ff506 br 6b2c <__clzsi2+0x28> + +00006b58 <__errno>: + 6b58: 00800074 movhi r2,1 + 6b5c: 10af9517 ldw r2,-16812(r2) 6b60: f800283a ret -00006b64 : - 6b64: defff604 addi sp,sp,-40 - 6b68: dfc00915 stw ra,36(sp) - 6b6c: df000815 stw fp,32(sp) - 6b70: df000804 addi fp,sp,32 - 6b74: e13ffc15 stw r4,-16(fp) - 6b78: e17ffb15 stw r5,-20(fp) - 6b7c: e1bffa15 stw r6,-24(fp) - 6b80: 3807883a mov r3,r7 - 6b84: e0800217 ldw r2,8(fp) - 6b88: e0fff905 stb r3,-28(fp) - 6b8c: e0bff805 stb r2,-32(fp) - 6b90: e03fff15 stw zero,-4(fp) - 6b94: e0bffa17 ldw r2,-24(fp) - 6b98: 1089c424 muli r2,r2,10000 - 6b9c: e0bffe15 stw r2,-8(fp) - 6ba0: e0bffc17 ldw r2,-16(fp) - 6ba4: 10800717 ldw r2,28(r2) - 6ba8: e0bffd15 stw r2,-12(fp) - 6bac: e0bffa17 ldw r2,-24(fp) - 6bb0: 1000021e bne r2,zero,6bbc - 6bb4: 0005883a mov r2,zero - 6bb8: 00006706 br 6d58 - 6bbc: e0bffc17 ldw r2,-16(fp) - 6bc0: 10c00617 ldw r3,24(r2) - 6bc4: 00800034 movhi r2,0 - 6bc8: 10962804 addi r2,r2,22688 - 6bcc: 18800226 beq r3,r2,6bd8 - 6bd0: 00bfff44 movi r2,-3 - 6bd4: 00006006 br 6d58 - 6bd8: e0bff903 ldbu r2,-28(fp) - 6bdc: 10000a1e bne r2,zero,6c08 - 6be0: e13ffc17 ldw r4,-16(fp) - 6be4: 0005c200 call 5c20 - 6be8: e0bfff15 stw r2,-4(fp) - 6bec: e0bfff17 ldw r2,-4(fp) - 6bf0: 10000226 beq r2,zero,6bfc - 6bf4: e0bfff17 ldw r2,-4(fp) - 6bf8: 00005706 br 6d58 - 6bfc: 01400704 movi r5,28 - 6c00: e13ffc17 ldw r4,-16(fp) - 6c04: 00072000 call 7200 - 6c08: e0bff903 ldbu r2,-28(fp) - 6c0c: 100d883a mov r6,r2 - 6c10: 000b883a mov r5,zero - 6c14: e13ffc17 ldw r4,-16(fp) - 6c18: 00062940 call 6294 - 6c1c: e0bfff15 stw r2,-4(fp) - 6c20: e0bfff17 ldw r2,-4(fp) - 6c24: 1000271e bne r2,zero,6cc4 - 6c28: 00000f06 br 6c68 - 6c2c: e0bffb17 ldw r2,-20(fp) - 6c30: 10800003 ldbu r2,0(r2) - 6c34: 10803fcc andi r2,r2,255 - 6c38: 000f883a mov r7,zero - 6c3c: 000d883a mov r6,zero - 6c40: 100b883a mov r5,r2 - 6c44: e13ffc17 ldw r4,-16(fp) - 6c48: 00061a80 call 61a8 - 6c4c: e0bfff15 stw r2,-4(fp) - 6c50: e0bffb17 ldw r2,-20(fp) - 6c54: 10800044 addi r2,r2,1 - 6c58: e0bffb15 stw r2,-20(fp) - 6c5c: e0bffa17 ldw r2,-24(fp) - 6c60: 10bfffc4 addi r2,r2,-1 - 6c64: e0bffa15 stw r2,-24(fp) - 6c68: e0bffa17 ldw r2,-24(fp) - 6c6c: 108000b0 cmpltui r2,r2,2 - 6c70: 1000021e bne r2,zero,6c7c - 6c74: e0bfff17 ldw r2,-4(fp) - 6c78: 103fec26 beq r2,zero,6c2c - 6c7c: e0bfff17 ldw r2,-4(fp) - 6c80: 1000101e bne r2,zero,6cc4 - 6c84: e0bffb17 ldw r2,-20(fp) - 6c88: 10800003 ldbu r2,0(r2) - 6c8c: 10803fcc andi r2,r2,255 - 6c90: e0fff803 ldbu r3,-32(fp) - 6c94: 180f883a mov r7,r3 - 6c98: 000d883a mov r6,zero - 6c9c: 100b883a mov r5,r2 - 6ca0: e13ffc17 ldw r4,-16(fp) - 6ca4: 00061a80 call 61a8 - 6ca8: e0bfff15 stw r2,-4(fp) - 6cac: e0bffb17 ldw r2,-20(fp) - 6cb0: 10800044 addi r2,r2,1 - 6cb4: e0bffb15 stw r2,-20(fp) - 6cb8: e0bffa17 ldw r2,-24(fp) - 6cbc: 10bfffc4 addi r2,r2,-1 - 6cc0: e0bffa15 stw r2,-24(fp) - 6cc4: e0bfff17 ldw r2,-4(fp) - 6cc8: 10001426 beq r2,zero,6d1c - 6ccc: 00000d06 br 6d04 - 6cd0: e0bffe17 ldw r2,-8(fp) - 6cd4: 108002a8 cmpgeui r2,r2,10 - 6cd8: 1000021e bne r2,zero,6ce4 - 6cdc: 0109c404 movi r4,10000 - 6ce0: 00077fc0 call 77fc - 6ce4: e0bffe17 ldw r2,-8(fp) - 6ce8: 10bfffc4 addi r2,r2,-1 - 6cec: e0bffe15 stw r2,-8(fp) - 6cf0: e0bffe17 ldw r2,-8(fp) - 6cf4: 1000031e bne r2,zero,6d04 - 6cf8: 00bfff84 movi r2,-2 - 6cfc: e0bfff15 stw r2,-4(fp) - 6d00: 00000306 br 6d10 - 6d04: e13ffc17 ldw r4,-16(fp) - 6d08: 00060100 call 6010 - 6d0c: 103ff01e bne r2,zero,6cd0 - 6d10: e13ffc17 ldw r4,-16(fp) - 6d14: 0005cb80 call 5cb8 - 6d18: 00000e06 br 6d54 - 6d1c: e0bff803 ldbu r2,-32(fp) - 6d20: 10000c26 beq r2,zero,6d54 - 6d24: 01400704 movi r5,28 - 6d28: e13ffc17 ldw r4,-16(fp) - 6d2c: 00072000 call 7200 - 6d30: 000b883a mov r5,zero - 6d34: e13ffc17 ldw r4,-16(fp) - 6d38: 00074500 call 7450 - 6d3c: e0bffd17 ldw r2,-12(fp) - 6d40: 00c00044 movi r3,1 - 6d44: 10c00215 stw r3,8(r2) - 6d48: 01400044 movi r5,1 - 6d4c: e13ffc17 ldw r4,-16(fp) - 6d50: 00072a80 call 72a8 - 6d54: e0bfff17 ldw r2,-4(fp) - 6d58: e037883a mov sp,fp - 6d5c: dfc00117 ldw ra,4(sp) - 6d60: df000017 ldw fp,0(sp) - 6d64: dec00204 addi sp,sp,8 - 6d68: f800283a ret - -00006d6c : - 6d6c: defff404 addi sp,sp,-48 - 6d70: dfc00b15 stw ra,44(sp) - 6d74: df000a15 stw fp,40(sp) - 6d78: df000a04 addi fp,sp,40 - 6d7c: e13ffa15 stw r4,-24(fp) - 6d80: e17ff915 stw r5,-28(fp) - 6d84: e1bff815 stw r6,-32(fp) - 6d88: 3807883a mov r3,r7 - 6d8c: e0800217 ldw r2,8(fp) - 6d90: e0fff705 stb r3,-36(fp) - 6d94: e0bff605 stb r2,-40(fp) - 6d98: e03ffc15 stw zero,-16(fp) - 6d9c: e03ffe15 stw zero,-8(fp) - 6da0: e03ffd15 stw zero,-12(fp) - 6da4: e0bff817 ldw r2,-32(fp) - 6da8: 1000021e bne r2,zero,6db4 - 6dac: 0005883a mov r2,zero - 6db0: 00006c06 br 6f64 - 6db4: e0bff703 ldbu r2,-36(fp) - 6db8: 10000a1e bne r2,zero,6de4 - 6dbc: e13ffa17 ldw r4,-24(fp) - 6dc0: 0005c200 call 5c20 - 6dc4: e0bffc15 stw r2,-16(fp) - 6dc8: e0bffc17 ldw r2,-16(fp) - 6dcc: 10000226 beq r2,zero,6dd8 - 6dd0: e0bffc17 ldw r2,-16(fp) - 6dd4: 00006306 br 6f64 - 6dd8: 01400704 movi r5,28 - 6ddc: e13ffa17 ldw r4,-24(fp) - 6de0: 00072000 call 7200 - 6de4: e0bff703 ldbu r2,-36(fp) - 6de8: 100d883a mov r6,r2 - 6dec: 01400044 movi r5,1 - 6df0: e13ffa17 ldw r4,-24(fp) - 6df4: 00062940 call 6294 - 6df8: e0bffc15 stw r2,-16(fp) - 6dfc: e0bffc17 ldw r2,-16(fp) - 6e00: 1000341e bne r2,zero,6ed4 - 6e04: 00001906 br 6e6c - 6e08: 000f883a mov r7,zero - 6e0c: 000d883a mov r6,zero - 6e10: 000b883a mov r5,zero - 6e14: e13ffa17 ldw r4,-24(fp) - 6e18: 00061a80 call 61a8 - 6e1c: e0bffc15 stw r2,-16(fp) - 6e20: e0bffd17 ldw r2,-12(fp) - 6e24: 10800044 addi r2,r2,1 - 6e28: e0bffd15 stw r2,-12(fp) - 6e2c: e0bffc17 ldw r2,-16(fp) - 6e30: 10000e1e bne r2,zero,6e6c - 6e34: e0bffb04 addi r2,fp,-20 - 6e38: 100f883a mov r7,r2 - 6e3c: 000d883a mov r6,zero - 6e40: e17ff917 ldw r5,-28(fp) - 6e44: e13ffa17 ldw r4,-24(fp) - 6e48: 00060540 call 6054 - 6e4c: e0bffb17 ldw r2,-20(fp) - 6e50: e0fff917 ldw r3,-28(fp) - 6e54: 1885883a add r2,r3,r2 - 6e58: e0bff915 stw r2,-28(fp) - 6e5c: e0bffb17 ldw r2,-20(fp) - 6e60: e0fffe17 ldw r3,-8(fp) - 6e64: 1885883a add r2,r3,r2 - 6e68: e0bffe15 stw r2,-8(fp) - 6e6c: e0bff817 ldw r2,-32(fp) - 6e70: 10bfffc4 addi r2,r2,-1 - 6e74: e0fffd17 ldw r3,-12(fp) - 6e78: 1880022e bgeu r3,r2,6e84 - 6e7c: e0bffc17 ldw r2,-16(fp) - 6e80: 103fe126 beq r2,zero,6e08 - 6e84: e0bffc17 ldw r2,-16(fp) - 6e88: 1000121e bne r2,zero,6ed4 - 6e8c: e0bff603 ldbu r2,-40(fp) - 6e90: 100f883a mov r7,r2 - 6e94: 000d883a mov r6,zero - 6e98: 000b883a mov r5,zero - 6e9c: e13ffa17 ldw r4,-24(fp) - 6ea0: 00061a80 call 61a8 - 6ea4: e0bffc15 stw r2,-16(fp) - 6ea8: 00000a06 br 6ed4 - 6eac: e17ff917 ldw r5,-28(fp) - 6eb0: e13ffa17 ldw r4,-24(fp) - 6eb4: 00061000 call 6100 - 6eb8: e0bffc15 stw r2,-16(fp) - 6ebc: e0bff917 ldw r2,-28(fp) - 6ec0: 10800044 addi r2,r2,1 - 6ec4: e0bff915 stw r2,-28(fp) - 6ec8: e0bffe17 ldw r2,-8(fp) - 6ecc: 10800044 addi r2,r2,1 - 6ed0: e0bffe15 stw r2,-8(fp) - 6ed4: e0fffe17 ldw r3,-8(fp) - 6ed8: e0bff817 ldw r2,-32(fp) - 6edc: 1880022e bgeu r3,r2,6ee8 - 6ee0: e0bffc17 ldw r2,-16(fp) - 6ee4: 103ff126 beq r2,zero,6eac - 6ee8: e0bff603 ldbu r2,-40(fp) - 6eec: 1000021e bne r2,zero,6ef8 - 6ef0: e0bffc17 ldw r2,-16(fp) - 6ef4: 10001a26 beq r2,zero,6f60 - 6ef8: e0bff817 ldw r2,-32(fp) - 6efc: 1089c424 muli r2,r2,10000 - 6f00: e0bfff15 stw r2,-4(fp) - 6f04: 00000d06 br 6f3c - 6f08: e0bfff17 ldw r2,-4(fp) - 6f0c: 108002a8 cmpgeui r2,r2,10 - 6f10: 1000021e bne r2,zero,6f1c - 6f14: 0109c404 movi r4,10000 - 6f18: 00077fc0 call 77fc - 6f1c: e0bfff17 ldw r2,-4(fp) - 6f20: 10bfffc4 addi r2,r2,-1 - 6f24: e0bfff15 stw r2,-4(fp) - 6f28: e0bfff17 ldw r2,-4(fp) - 6f2c: 1000031e bne r2,zero,6f3c - 6f30: 00bfff84 movi r2,-2 - 6f34: e0bffc15 stw r2,-16(fp) - 6f38: 00000306 br 6f48 - 6f3c: e13ffa17 ldw r4,-24(fp) - 6f40: 00060100 call 6010 - 6f44: 103ff01e bne r2,zero,6f08 - 6f48: e0bffc04 addi r2,fp,-16 - 6f4c: 100b883a mov r5,r2 - 6f50: e13ffa17 ldw r4,-24(fp) - 6f54: 00063f00 call 63f0 - 6f58: e13ffa17 ldw r4,-24(fp) - 6f5c: 0005cb80 call 5cb8 - 6f60: e0bffc17 ldw r2,-16(fp) - 6f64: e037883a mov sp,fp - 6f68: dfc00117 ldw ra,4(sp) - 6f6c: df000017 ldw fp,0(sp) - 6f70: dec00204 addi sp,sp,8 - 6f74: f800283a ret - -00006f78 : - 6f78: defff504 addi sp,sp,-44 - 6f7c: dfc00a15 stw ra,40(sp) - 6f80: df000915 stw fp,36(sp) - 6f84: df000904 addi fp,sp,36 - 6f88: e13ffb15 stw r4,-20(fp) - 6f8c: e17ffa15 stw r5,-24(fp) - 6f90: e1bff915 stw r6,-28(fp) - 6f94: 3807883a mov r3,r7 - 6f98: e0800217 ldw r2,8(fp) - 6f9c: e0fff805 stb r3,-32(fp) - 6fa0: e0bff705 stb r2,-36(fp) - 6fa4: e03fff15 stw zero,-4(fp) - 6fa8: e0bffb17 ldw r2,-20(fp) - 6fac: 10800717 ldw r2,28(r2) - 6fb0: e0bffc15 stw r2,-16(fp) - 6fb4: e03ffd15 stw zero,-12(fp) - 6fb8: e0bff917 ldw r2,-28(fp) - 6fbc: 1000021e bne r2,zero,6fc8 - 6fc0: 0005883a mov r2,zero - 6fc4: 00006206 br 7150 - 6fc8: e0bffb17 ldw r2,-20(fp) - 6fcc: 10c00617 ldw r3,24(r2) - 6fd0: 00800034 movhi r2,0 - 6fd4: 10962804 addi r2,r2,22688 - 6fd8: 18800226 beq r3,r2,6fe4 - 6fdc: 00bfff44 movi r2,-3 - 6fe0: 00005b06 br 7150 - 6fe4: e0bff803 ldbu r2,-32(fp) - 6fe8: 10000a1e bne r2,zero,7014 - 6fec: e13ffb17 ldw r4,-20(fp) - 6ff0: 0005c200 call 5c20 - 6ff4: e0bfff15 stw r2,-4(fp) - 6ff8: e0bfff17 ldw r2,-4(fp) - 6ffc: 10000226 beq r2,zero,7008 - 7000: e0bfff17 ldw r2,-4(fp) - 7004: 00005206 br 7150 - 7008: 01400704 movi r5,28 - 700c: e13ffb17 ldw r4,-20(fp) - 7010: 00072000 call 7200 - 7014: e0bff803 ldbu r2,-32(fp) - 7018: 100d883a mov r6,r2 - 701c: 01400044 movi r5,1 - 7020: e13ffb17 ldw r4,-20(fp) - 7024: 00062940 call 6294 - 7028: e0bfff15 stw r2,-4(fp) - 702c: e0bfff17 ldw r2,-4(fp) - 7030: 1000191e bne r2,zero,7098 - 7034: 00000906 br 705c - 7038: 000f883a mov r7,zero - 703c: 000d883a mov r6,zero - 7040: 000b883a mov r5,zero - 7044: e13ffb17 ldw r4,-20(fp) - 7048: 00061a80 call 61a8 - 704c: e0bfff15 stw r2,-4(fp) - 7050: e0bffd17 ldw r2,-12(fp) - 7054: 10800044 addi r2,r2,1 - 7058: e0bffd15 stw r2,-12(fp) - 705c: e0bff917 ldw r2,-28(fp) - 7060: 10bfffc4 addi r2,r2,-1 - 7064: e0fffd17 ldw r3,-12(fp) - 7068: 1880022e bgeu r3,r2,7074 - 706c: e0bfff17 ldw r2,-4(fp) - 7070: 103ff126 beq r2,zero,7038 - 7074: e0bfff17 ldw r2,-4(fp) - 7078: 1000071e bne r2,zero,7098 - 707c: e0bff703 ldbu r2,-36(fp) - 7080: 100f883a mov r7,r2 - 7084: 000d883a mov r6,zero - 7088: 000b883a mov r5,zero - 708c: e13ffb17 ldw r4,-20(fp) - 7090: 00061a80 call 61a8 - 7094: e0bfff15 stw r2,-4(fp) - 7098: e0bfff17 ldw r2,-4(fp) - 709c: 10001726 beq r2,zero,70fc - 70a0: e0bff917 ldw r2,-28(fp) - 70a4: 1089c424 muli r2,r2,10000 - 70a8: e0bffe15 stw r2,-8(fp) - 70ac: 00000d06 br 70e4 - 70b0: e0bffe17 ldw r2,-8(fp) - 70b4: 108002a8 cmpgeui r2,r2,10 - 70b8: 1000021e bne r2,zero,70c4 - 70bc: 0109c404 movi r4,10000 - 70c0: 00077fc0 call 77fc - 70c4: e0bffe17 ldw r2,-8(fp) - 70c8: 10bfffc4 addi r2,r2,-1 - 70cc: e0bffe15 stw r2,-8(fp) - 70d0: e0bffe17 ldw r2,-8(fp) - 70d4: 1000031e bne r2,zero,70e4 - 70d8: 00bfff84 movi r2,-2 - 70dc: e0bfff15 stw r2,-4(fp) - 70e0: 00000306 br 70f0 - 70e4: e13ffb17 ldw r4,-20(fp) - 70e8: 00060100 call 6010 - 70ec: 103ff01e bne r2,zero,70b0 - 70f0: e13ffb17 ldw r4,-20(fp) - 70f4: 0005cb80 call 5cb8 - 70f8: 00001406 br 714c - 70fc: e0bff703 ldbu r2,-36(fp) - 7100: 10001226 beq r2,zero,714c - 7104: 01400704 movi r5,28 - 7108: e13ffb17 ldw r4,-20(fp) - 710c: 00072000 call 7200 - 7110: 000b883a mov r5,zero - 7114: e13ffb17 ldw r4,-20(fp) - 7118: 00073a00 call 73a0 - 711c: e0bffc17 ldw r2,-16(fp) - 7120: 00c00084 movi r3,2 - 7124: 10c00215 stw r3,8(r2) - 7128: e0bffc17 ldw r2,-16(fp) - 712c: e0fffa17 ldw r3,-24(fp) - 7130: 10c00015 stw r3,0(r2) - 7134: e0bffc17 ldw r2,-16(fp) - 7138: e0fff917 ldw r3,-28(fp) - 713c: 10c00115 stw r3,4(r2) - 7140: 01400084 movi r5,2 - 7144: e13ffb17 ldw r4,-20(fp) - 7148: 00072a80 call 72a8 - 714c: e0bfff17 ldw r2,-4(fp) - 7150: e037883a mov sp,fp - 7154: dfc00117 ldw ra,4(sp) - 7158: df000017 ldw fp,0(sp) - 715c: dec00204 addi sp,sp,8 - 7160: f800283a ret - -00007164 : - 7164: defffd04 addi sp,sp,-12 - 7168: df000215 stw fp,8(sp) - 716c: df000204 addi fp,sp,8 - 7170: e13fff15 stw r4,-4(fp) - 7174: e17ffe15 stw r5,-8(fp) - 7178: e0bfff17 ldw r2,-4(fp) - 717c: 10800317 ldw r2,12(r2) - 7180: 10800404 addi r2,r2,16 - 7184: 10c00037 ldwio r3,0(r2) - 7188: e0bfff17 ldw r2,-4(fp) - 718c: 10800317 ldw r2,12(r2) - 7190: 10800304 addi r2,r2,12 - 7194: 10800037 ldwio r2,0(r2) - 7198: 1884703a and r2,r3,r2 - 719c: 1007883a mov r3,r2 - 71a0: e0bffe17 ldw r2,-8(fp) - 71a4: 10c00015 stw r3,0(r2) - 71a8: 0001883a nop - 71ac: e037883a mov sp,fp - 71b0: df000017 ldw fp,0(sp) - 71b4: dec00104 addi sp,sp,4 - 71b8: f800283a ret - -000071bc : - 71bc: defffd04 addi sp,sp,-12 - 71c0: df000215 stw fp,8(sp) - 71c4: df000204 addi fp,sp,8 - 71c8: e13fff15 stw r4,-4(fp) - 71cc: e17ffe15 stw r5,-8(fp) - 71d0: e0bfff17 ldw r2,-4(fp) - 71d4: 10800317 ldw r2,12(r2) - 71d8: 10800404 addi r2,r2,16 - 71dc: 10800037 ldwio r2,0(r2) - 71e0: 1007883a mov r3,r2 - 71e4: e0bffe17 ldw r2,-8(fp) - 71e8: 10c00015 stw r3,0(r2) - 71ec: 0001883a nop - 71f0: e037883a mov sp,fp - 71f4: df000017 ldw fp,0(sp) - 71f8: dec00104 addi sp,sp,4 - 71fc: f800283a ret - -00007200 : - 7200: defffd04 addi sp,sp,-12 - 7204: df000215 stw fp,8(sp) - 7208: df000204 addi fp,sp,8 - 720c: e13fff15 stw r4,-4(fp) - 7210: e17ffe15 stw r5,-8(fp) - 7214: e0bfff17 ldw r2,-4(fp) - 7218: 10800317 ldw r2,12(r2) - 721c: 10800404 addi r2,r2,16 - 7220: e0fffe17 ldw r3,-8(fp) - 7224: 10c00035 stwio r3,0(r2) - 7228: 0001883a nop - 722c: e037883a mov sp,fp - 7230: df000017 ldw fp,0(sp) - 7234: dec00104 addi sp,sp,4 - 7238: f800283a ret - -0000723c : - 723c: defffb04 addi sp,sp,-20 - 7240: dfc00415 stw ra,16(sp) - 7244: df000315 stw fp,12(sp) - 7248: df000304 addi fp,sp,12 - 724c: e13ffe15 stw r4,-8(fp) - 7250: e17ffd15 stw r5,-12(fp) - 7254: e0bfff04 addi r2,fp,-4 - 7258: 100b883a mov r5,r2 - 725c: e13ffe17 ldw r4,-8(fp) - 7260: 00073100 call 7310 - 7264: e0bffd17 ldw r2,-12(fp) - 7268: 0086303a nor r3,zero,r2 - 726c: e0bfff17 ldw r2,-4(fp) - 7270: 1884703a and r2,r3,r2 - 7274: e0bfff15 stw r2,-4(fp) - 7278: e0bffe17 ldw r2,-8(fp) - 727c: 10800317 ldw r2,12(r2) - 7280: 10800304 addi r2,r2,12 - 7284: e0ffff17 ldw r3,-4(fp) - 7288: 18c007cc andi r3,r3,31 - 728c: 10c00035 stwio r3,0(r2) - 7290: 0001883a nop - 7294: e037883a mov sp,fp - 7298: dfc00117 ldw ra,4(sp) - 729c: df000017 ldw fp,0(sp) - 72a0: dec00204 addi sp,sp,8 - 72a4: f800283a ret - -000072a8 : - 72a8: defffb04 addi sp,sp,-20 - 72ac: dfc00415 stw ra,16(sp) - 72b0: df000315 stw fp,12(sp) - 72b4: df000304 addi fp,sp,12 - 72b8: e13ffe15 stw r4,-8(fp) - 72bc: e17ffd15 stw r5,-12(fp) - 72c0: e0bfff04 addi r2,fp,-4 - 72c4: 100b883a mov r5,r2 - 72c8: e13ffe17 ldw r4,-8(fp) - 72cc: 00073100 call 7310 - 72d0: e0ffff17 ldw r3,-4(fp) - 72d4: e0bffd17 ldw r2,-12(fp) - 72d8: 1884b03a or r2,r3,r2 - 72dc: e0bfff15 stw r2,-4(fp) - 72e0: e0bffe17 ldw r2,-8(fp) - 72e4: 10800317 ldw r2,12(r2) - 72e8: 10800304 addi r2,r2,12 - 72ec: e0ffff17 ldw r3,-4(fp) - 72f0: 18c007cc andi r3,r3,31 - 72f4: 10c00035 stwio r3,0(r2) - 72f8: 0001883a nop - 72fc: e037883a mov sp,fp - 7300: dfc00117 ldw ra,4(sp) - 7304: df000017 ldw fp,0(sp) - 7308: dec00204 addi sp,sp,8 - 730c: f800283a ret - -00007310 : - 7310: defffd04 addi sp,sp,-12 - 7314: df000215 stw fp,8(sp) - 7318: df000204 addi fp,sp,8 - 731c: e13fff15 stw r4,-4(fp) - 7320: e17ffe15 stw r5,-8(fp) - 7324: e0bfff17 ldw r2,-4(fp) - 7328: 10800317 ldw r2,12(r2) - 732c: 10800304 addi r2,r2,12 - 7330: 10800037 ldwio r2,0(r2) - 7334: 10c007cc andi r3,r2,31 - 7338: e0bffe17 ldw r2,-8(fp) - 733c: 10c00015 stw r3,0(r2) - 7340: 0001883a nop - 7344: e037883a mov sp,fp - 7348: df000017 ldw fp,0(sp) - 734c: dec00104 addi sp,sp,4 - 7350: f800283a ret - -00007354 : - 7354: defffd04 addi sp,sp,-12 - 7358: df000215 stw fp,8(sp) - 735c: df000204 addi fp,sp,8 - 7360: e13fff15 stw r4,-4(fp) - 7364: e17ffe15 stw r5,-8(fp) - 7368: e0bfff17 ldw r2,-4(fp) - 736c: 10800317 ldw r2,12(r2) - 7370: 10800204 addi r2,r2,8 - 7374: 10800037 ldwio r2,0(r2) - 7378: 1005d13a srai r2,r2,4 - 737c: 108000cc andi r2,r2,3 - 7380: 1007883a mov r3,r2 - 7384: e0bffe17 ldw r2,-8(fp) - 7388: 10c00015 stw r3,0(r2) - 738c: 0001883a nop - 7390: e037883a mov sp,fp - 7394: df000017 ldw fp,0(sp) - 7398: dec00104 addi sp,sp,4 - 739c: f800283a ret - -000073a0 : - 73a0: defffd04 addi sp,sp,-12 - 73a4: df000215 stw fp,8(sp) - 73a8: df000204 addi fp,sp,8 - 73ac: e13fff15 stw r4,-4(fp) - 73b0: e17ffe15 stw r5,-8(fp) - 73b4: e0bfff17 ldw r2,-4(fp) - 73b8: 10800317 ldw r2,12(r2) - 73bc: 10800204 addi r2,r2,8 - 73c0: e0ffff17 ldw r3,-4(fp) - 73c4: 18c00317 ldw r3,12(r3) - 73c8: 18c00204 addi r3,r3,8 - 73cc: 18c00037 ldwio r3,0(r3) - 73d0: 1809883a mov r4,r3 - 73d4: 00fff3c4 movi r3,-49 - 73d8: 20c8703a and r4,r4,r3 - 73dc: e0fffe17 ldw r3,-8(fp) - 73e0: 1806913a slli r3,r3,4 - 73e4: 18c00c0c andi r3,r3,48 - 73e8: 20c6b03a or r3,r4,r3 - 73ec: 10c00035 stwio r3,0(r2) - 73f0: 0001883a nop - 73f4: e037883a mov sp,fp - 73f8: df000017 ldw fp,0(sp) - 73fc: dec00104 addi sp,sp,4 - 7400: f800283a ret - -00007404 : - 7404: defffd04 addi sp,sp,-12 - 7408: df000215 stw fp,8(sp) - 740c: df000204 addi fp,sp,8 - 7410: e13fff15 stw r4,-4(fp) - 7414: e17ffe15 stw r5,-8(fp) - 7418: e0bfff17 ldw r2,-4(fp) - 741c: 10800317 ldw r2,12(r2) - 7420: 10800204 addi r2,r2,8 - 7424: 10800037 ldwio r2,0(r2) - 7428: 1005d0ba srai r2,r2,2 - 742c: 108000cc andi r2,r2,3 - 7430: 1007883a mov r3,r2 - 7434: e0bffe17 ldw r2,-8(fp) - 7438: 10c00015 stw r3,0(r2) - 743c: 0001883a nop - 7440: e037883a mov sp,fp - 7444: df000017 ldw fp,0(sp) - 7448: dec00104 addi sp,sp,4 - 744c: f800283a ret - -00007450 : - 7450: defffd04 addi sp,sp,-12 - 7454: df000215 stw fp,8(sp) - 7458: df000204 addi fp,sp,8 - 745c: e13fff15 stw r4,-4(fp) - 7460: e17ffe15 stw r5,-8(fp) - 7464: e0bfff17 ldw r2,-4(fp) - 7468: 10800317 ldw r2,12(r2) - 746c: 10800204 addi r2,r2,8 - 7470: e0ffff17 ldw r3,-4(fp) - 7474: 18c00317 ldw r3,12(r3) - 7478: 18c00204 addi r3,r3,8 - 747c: 18c00037 ldwio r3,0(r3) - 7480: 1809883a mov r4,r3 - 7484: 00fffcc4 movi r3,-13 - 7488: 20c8703a and r4,r4,r3 - 748c: e0fffe17 ldw r3,-8(fp) - 7490: 180690ba slli r3,r3,2 - 7494: 18c0030c andi r3,r3,12 - 7498: 20c6b03a or r3,r4,r3 - 749c: 10c00035 stwio r3,0(r2) - 74a0: 0001883a nop - 74a4: e037883a mov sp,fp - 74a8: df000017 ldw fp,0(sp) - 74ac: dec00104 addi sp,sp,4 - 74b0: f800283a ret - -000074b4 : - 74b4: defffa04 addi sp,sp,-24 - 74b8: dfc00515 stw ra,20(sp) - 74bc: df000415 stw fp,16(sp) - 74c0: df000404 addi fp,sp,16 - 74c4: e13ffe15 stw r4,-8(fp) - 74c8: e17ffd15 stw r5,-12(fp) - 74cc: e1bffc15 stw r6,-16(fp) - 74d0: e0bffe17 ldw r2,-8(fp) - 74d4: 10800017 ldw r2,0(r2) - 74d8: e0bfff15 stw r2,-4(fp) - 74dc: e0bfff17 ldw r2,-4(fp) - 74e0: 10c00a04 addi r3,r2,40 - 74e4: e0bffe17 ldw r2,-8(fp) - 74e8: 10800217 ldw r2,8(r2) - 74ec: 100f883a mov r7,r2 - 74f0: e1bffc17 ldw r6,-16(fp) - 74f4: e17ffd17 ldw r5,-12(fp) - 74f8: 1809883a mov r4,r3 - 74fc: 00075740 call 7574 - 7500: e037883a mov sp,fp - 7504: dfc00117 ldw ra,4(sp) - 7508: df000017 ldw fp,0(sp) - 750c: dec00204 addi sp,sp,8 - 7510: f800283a ret - -00007514 : - 7514: defffa04 addi sp,sp,-24 - 7518: dfc00515 stw ra,20(sp) - 751c: df000415 stw fp,16(sp) - 7520: df000404 addi fp,sp,16 - 7524: e13ffe15 stw r4,-8(fp) - 7528: e17ffd15 stw r5,-12(fp) - 752c: e1bffc15 stw r6,-16(fp) - 7530: e0bffe17 ldw r2,-8(fp) - 7534: 10800017 ldw r2,0(r2) - 7538: e0bfff15 stw r2,-4(fp) - 753c: e0bfff17 ldw r2,-4(fp) - 7540: 10c00a04 addi r3,r2,40 - 7544: e0bffe17 ldw r2,-8(fp) - 7548: 10800217 ldw r2,8(r2) - 754c: 100f883a mov r7,r2 - 7550: e1bffc17 ldw r6,-16(fp) - 7554: e17ffd17 ldw r5,-12(fp) - 7558: 1809883a mov r4,r3 - 755c: 00076600 call 7660 - 7560: e037883a mov sp,fp - 7564: dfc00117 ldw ra,4(sp) - 7568: df000017 ldw fp,0(sp) - 756c: dec00204 addi sp,sp,8 - 7570: f800283a ret - -00007574 : - 7574: defff704 addi sp,sp,-36 - 7578: df000815 stw fp,32(sp) - 757c: df000804 addi fp,sp,32 - 7580: e13ffb15 stw r4,-20(fp) - 7584: e17ffa15 stw r5,-24(fp) - 7588: e1bff915 stw r6,-28(fp) - 758c: e1fff815 stw r7,-32(fp) - 7590: e0bffb17 ldw r2,-20(fp) - 7594: 10800017 ldw r2,0(r2) - 7598: e0bffe15 stw r2,-8(fp) - 759c: e0bffa17 ldw r2,-24(fp) - 75a0: e0bfff15 stw r2,-4(fp) - 75a4: e0bff917 ldw r2,-28(fp) - 75a8: e0fffa17 ldw r3,-24(fp) - 75ac: 1885883a add r2,r3,r2 - 75b0: e0bffd15 stw r2,-12(fp) - 75b4: 00001206 br 7600 - 75b8: e0bffe17 ldw r2,-8(fp) - 75bc: 10800037 ldwio r2,0(r2) - 75c0: e0bffc15 stw r2,-16(fp) +00006b64 : + 6b64: 2005883a mov r2,r4 + 6b68: 0007883a mov r3,zero + 6b6c: 30c0011e bne r6,r3,6b74 + 6b70: f800283a ret + 6b74: 28cf883a add r7,r5,r3 + 6b78: 39c00003 ldbu r7,0(r7) + 6b7c: 10c9883a add r4,r2,r3 + 6b80: 18c00044 addi r3,r3,1 + 6b84: 21c00005 stb r7,0(r4) + 6b88: 003ff806 br 6b6c + +00006b8c <_printf_r>: + 6b8c: defffd04 addi sp,sp,-12 + 6b90: dfc00015 stw ra,0(sp) + 6b94: d9800115 stw r6,4(sp) + 6b98: d9c00215 stw r7,8(sp) + 6b9c: 21800217 ldw r6,8(r4) + 6ba0: 00c00034 movhi r3,0 + 6ba4: 18dc9304 addi r3,r3,29260 + 6ba8: 30c00115 stw r3,4(r6) + 6bac: 280d883a mov r6,r5 + 6bb0: 21400217 ldw r5,8(r4) + 6bb4: d9c00104 addi r7,sp,4 + 6bb8: 0006d480 call 6d48 <___vfprintf_internal_r> + 6bbc: dfc00017 ldw ra,0(sp) + 6bc0: dec00304 addi sp,sp,12 + 6bc4: f800283a ret + +00006bc8 : + 6bc8: defffc04 addi sp,sp,-16 + 6bcc: dfc00015 stw ra,0(sp) + 6bd0: d9400115 stw r5,4(sp) + 6bd4: d9800215 stw r6,8(sp) + 6bd8: d9c00315 stw r7,12(sp) + 6bdc: 00800074 movhi r2,1 + 6be0: 10ef9517 ldw r3,-16812(r2) + 6be4: 00800034 movhi r2,0 + 6be8: 109c9304 addi r2,r2,29260 + 6bec: 19400217 ldw r5,8(r3) + 6bf0: d9800104 addi r6,sp,4 + 6bf4: 28800115 stw r2,4(r5) + 6bf8: 200b883a mov r5,r4 + 6bfc: 19000217 ldw r4,8(r3) + 6c00: 00072340 call 7234 <__vfprintf_internal> + 6c04: dfc00017 ldw ra,0(sp) + 6c08: dec00404 addi sp,sp,16 + 6c0c: f800283a ret + +00006c10 <_putchar_r>: + 6c10: 21800217 ldw r6,8(r4) + 6c14: 00073441 jmpi 7344 <_putc_r> + +00006c18 : + 6c18: 00800074 movhi r2,1 + 6c1c: 10af9517 ldw r2,-16812(r2) + 6c20: 200b883a mov r5,r4 + 6c24: 11800217 ldw r6,8(r2) + 6c28: 1009883a mov r4,r2 + 6c2c: 00073441 jmpi 7344 <_putc_r> + +00006c30 <_puts_r>: + 6c30: defffd04 addi sp,sp,-12 + 6c34: dc000015 stw r16,0(sp) + 6c38: 2021883a mov r16,r4 + 6c3c: 2809883a mov r4,r5 + 6c40: dfc00215 stw ra,8(sp) + 6c44: dc400115 stw r17,4(sp) + 6c48: 2823883a mov r17,r5 + 6c4c: 0006cc00 call 6cc0 + 6c50: 81400217 ldw r5,8(r16) + 6c54: 00c00034 movhi r3,0 + 6c58: 18dc9304 addi r3,r3,29260 + 6c5c: 28c00115 stw r3,4(r5) + 6c60: 100f883a mov r7,r2 + 6c64: 880d883a mov r6,r17 + 6c68: 8009883a mov r4,r16 + 6c6c: 000724c0 call 724c <__sfvwrite_small_dev> + 6c70: 10ffffe0 cmpeqi r3,r2,-1 + 6c74: 1800091e bne r3,zero,6c9c <_puts_r+0x6c> + 6c78: 81400217 ldw r5,8(r16) + 6c7c: 01800074 movhi r6,1 + 6c80: 01c00044 movi r7,1 + 6c84: 28800117 ldw r2,4(r5) + 6c88: 31aebf04 addi r6,r6,-17668 + 6c8c: 8009883a mov r4,r16 + 6c90: 103ee83a callr r2 + 6c94: 10bfffe0 cmpeqi r2,r2,-1 + 6c98: 0085c83a sub r2,zero,r2 + 6c9c: dfc00217 ldw ra,8(sp) + 6ca0: dc400117 ldw r17,4(sp) + 6ca4: dc000017 ldw r16,0(sp) + 6ca8: dec00304 addi sp,sp,12 + 6cac: f800283a ret + +00006cb0 : + 6cb0: 00800074 movhi r2,1 + 6cb4: 200b883a mov r5,r4 + 6cb8: 112f9517 ldw r4,-16812(r2) + 6cbc: 0006c301 jmpi 6c30 <_puts_r> + +00006cc0 : + 6cc0: 2005883a mov r2,r4 + 6cc4: 10c00007 ldb r3,0(r2) + 6cc8: 1800021e bne r3,zero,6cd4 + 6ccc: 1105c83a sub r2,r2,r4 + 6cd0: f800283a ret + 6cd4: 10800044 addi r2,r2,1 + 6cd8: 003ffa06 br 6cc4 + +00006cdc : + 6cdc: defffb04 addi sp,sp,-20 + 6ce0: dc800315 stw r18,12(sp) + 6ce4: dc400215 stw r17,8(sp) + 6ce8: dc000115 stw r16,4(sp) + 6cec: dfc00415 stw ra,16(sp) + 6cf0: 2025883a mov r18,r4 + 6cf4: 2823883a mov r17,r5 + 6cf8: d9800005 stb r6,0(sp) + 6cfc: 3821883a mov r16,r7 + 6d00: 04000716 blt zero,r16,6d20 + 6d04: 0005883a mov r2,zero + 6d08: dfc00417 ldw ra,16(sp) + 6d0c: dc800317 ldw r18,12(sp) + 6d10: dc400217 ldw r17,8(sp) + 6d14: dc000117 ldw r16,4(sp) + 6d18: dec00504 addi sp,sp,20 + 6d1c: f800283a ret + 6d20: 88800117 ldw r2,4(r17) + 6d24: 01c00044 movi r7,1 + 6d28: d80d883a mov r6,sp + 6d2c: 880b883a mov r5,r17 + 6d30: 9009883a mov r4,r18 + 6d34: 103ee83a callr r2 + 6d38: 843fffc4 addi r16,r16,-1 + 6d3c: 103ff026 beq r2,zero,6d00 + 6d40: 00bfffc4 movi r2,-1 + 6d44: 003ff006 br 6d08 + +00006d48 <___vfprintf_internal_r>: + 6d48: deffe604 addi sp,sp,-104 + 6d4c: df001815 stw fp,96(sp) + 6d50: ddc01715 stw r23,92(sp) + 6d54: dd801615 stw r22,88(sp) + 6d58: dd001415 stw r20,80(sp) + 6d5c: dcc01315 stw r19,76(sp) + 6d60: dc801215 stw r18,72(sp) + 6d64: dc401115 stw r17,68(sp) + 6d68: dc001015 stw r16,64(sp) + 6d6c: dfc01915 stw ra,100(sp) + 6d70: dd401515 stw r21,84(sp) + 6d74: 2021883a mov r16,r4 + 6d78: 282f883a mov r23,r5 + 6d7c: d9800515 stw r6,20(sp) + 6d80: 3839883a mov fp,r7 + 6d84: 002d883a mov r22,zero + 6d88: d8000215 stw zero,8(sp) + 6d8c: 0027883a mov r19,zero + 6d90: 0029883a mov r20,zero + 6d94: 0025883a mov r18,zero + 6d98: 0023883a mov r17,zero + 6d9c: d8000115 stw zero,4(sp) + 6da0: d8000015 stw zero,0(sp) + 6da4: 0005883a mov r2,zero + 6da8: 00000206 br 6db4 <___vfprintf_internal_r+0x6c> + 6dac: 118000e0 cmpeqi r6,r2,3 + 6db0: 30003d1e bne r6,zero,6ea8 <___vfprintf_internal_r+0x160> + 6db4: d8c00517 ldw r3,20(sp) + 6db8: 19000003 ldbu r4,0(r3) + 6dbc: 18c00044 addi r3,r3,1 + 6dc0: d8c00515 stw r3,20(sp) + 6dc4: 21403fcc andi r5,r4,255 + 6dc8: 2940201c xori r5,r5,128 + 6dcc: 297fe004 addi r5,r5,-128 + 6dd0: 28001426 beq r5,zero,6e24 <___vfprintf_internal_r+0xdc> + 6dd4: 118000a0 cmpeqi r6,r2,2 + 6dd8: 3000231e bne r6,zero,6e68 <___vfprintf_internal_r+0x120> + 6ddc: 118000c8 cmpgei r6,r2,3 + 6de0: 303ff21e bne r6,zero,6dac <___vfprintf_internal_r+0x64> + 6de4: 10000426 beq r2,zero,6df8 <___vfprintf_internal_r+0xb0> + 6de8: 10800060 cmpeqi r2,r2,1 + 6dec: 10001a1e bne r2,zero,6e58 <___vfprintf_internal_r+0x110> + 6df0: 00800084 movi r2,2 + 6df4: 003fef06 br 6db4 <___vfprintf_internal_r+0x6c> + 6df8: 29400960 cmpeqi r5,r5,37 + 6dfc: 2800f61e bne r5,zero,71d8 <___vfprintf_internal_r+0x490> + 6e00: b8800117 ldw r2,4(r23) + 6e04: d9000805 stb r4,32(sp) + 6e08: 01c00044 movi r7,1 + 6e0c: d9800804 addi r6,sp,32 + 6e10: b80b883a mov r5,r23 + 6e14: 8009883a mov r4,r16 + 6e18: 103ee83a callr r2 + 6e1c: 10001b26 beq r2,zero,6e8c <___vfprintf_internal_r+0x144> + 6e20: 05bfffc4 movi r22,-1 + 6e24: b005883a mov r2,r22 + 6e28: dfc01917 ldw ra,100(sp) + 6e2c: df001817 ldw fp,96(sp) + 6e30: ddc01717 ldw r23,92(sp) + 6e34: dd801617 ldw r22,88(sp) + 6e38: dd401517 ldw r21,84(sp) + 6e3c: dd001417 ldw r20,80(sp) + 6e40: dcc01317 ldw r19,76(sp) + 6e44: dc801217 ldw r18,72(sp) + 6e48: dc401117 ldw r17,68(sp) + 6e4c: dc001017 ldw r16,64(sp) + 6e50: dec01a04 addi sp,sp,104 + 6e54: f800283a ret + 6e58: 28800c20 cmpeqi r2,r5,48 + 6e5c: 1000e71e bne r2,zero,71fc <___vfprintf_internal_r+0x4b4> + 6e60: 28800958 cmpnei r2,r5,37 + 6e64: 103fe626 beq r2,zero,6e00 <___vfprintf_internal_r+0xb8> + 6e68: 20bff404 addi r2,r4,-48 + 6e6c: 10803fcc andi r2,r2,255 + 6e70: 118002a8 cmpgeui r6,r2,10 + 6e74: 3000091e bne r6,zero,6e9c <___vfprintf_internal_r+0x154> + 6e78: 893fffe0 cmpeqi r4,r17,-1 + 6e7c: 2000051e bne r4,zero,6e94 <___vfprintf_internal_r+0x14c> + 6e80: 8c4002a4 muli r17,r17,10 + 6e84: 1463883a add r17,r2,r17 + 6e88: 003fd906 br 6df0 <___vfprintf_internal_r+0xa8> + 6e8c: b5800044 addi r22,r22,1 + 6e90: 003fc806 br 6db4 <___vfprintf_internal_r+0x6c> + 6e94: 0023883a mov r17,zero + 6e98: 003ffa06 br 6e84 <___vfprintf_internal_r+0x13c> + 6e9c: 28800ba0 cmpeqi r2,r5,46 + 6ea0: 1000db1e bne r2,zero,7210 <___vfprintf_internal_r+0x4c8> + 6ea4: 00800084 movi r2,2 + 6ea8: 213ff404 addi r4,r4,-48 + 6eac: 21003fcc andi r4,r4,255 + 6eb0: 218002a8 cmpgeui r6,r4,10 + 6eb4: 3000071e bne r6,zero,6ed4 <___vfprintf_internal_r+0x18c> + 6eb8: 917fffe0 cmpeqi r5,r18,-1 + 6ebc: 2800031e bne r5,zero,6ecc <___vfprintf_internal_r+0x184> + 6ec0: 948002a4 muli r18,r18,10 + 6ec4: 24a5883a add r18,r4,r18 + 6ec8: 003fba06 br 6db4 <___vfprintf_internal_r+0x6c> + 6ecc: 0025883a mov r18,zero + 6ed0: 003ffc06 br 6ec4 <___vfprintf_internal_r+0x17c> + 6ed4: 28801b20 cmpeqi r2,r5,108 + 6ed8: 1000cb1e bne r2,zero,7208 <___vfprintf_internal_r+0x4c0> + 6edc: 90bfffe0 cmpeqi r2,r18,-1 + 6ee0: 10000f1e bne r2,zero,6f20 <___vfprintf_internal_r+0x1d8> + 6ee4: d8000015 stw zero,0(sp) + 6ee8: 28801be0 cmpeqi r2,r5,111 + 6eec: 1000ca1e bne r2,zero,7218 <___vfprintf_internal_r+0x4d0> + 6ef0: 28801c08 cmpgei r2,r5,112 + 6ef4: 1000171e bne r2,zero,6f54 <___vfprintf_internal_r+0x20c> + 6ef8: 288018e0 cmpeqi r2,r5,99 + 6efc: 10009f1e bne r2,zero,717c <___vfprintf_internal_r+0x434> + 6f00: 28801908 cmpgei r2,r5,100 + 6f04: 1000081e bne r2,zero,6f28 <___vfprintf_internal_r+0x1e0> + 6f08: 29401620 cmpeqi r5,r5,88 + 6f0c: 283fa526 beq r5,zero,6da4 <___vfprintf_internal_r+0x5c> + 6f10: 00800044 movi r2,1 + 6f14: d8800215 stw r2,8(sp) + 6f18: 05000404 movi r20,16 + 6f1c: 0000bf06 br 721c <___vfprintf_internal_r+0x4d4> + 6f20: 04800044 movi r18,1 + 6f24: 003ff006 br 6ee8 <___vfprintf_internal_r+0x1a0> + 6f28: 28801920 cmpeqi r2,r5,100 + 6f2c: 1000021e bne r2,zero,6f38 <___vfprintf_internal_r+0x1f0> + 6f30: 29401a60 cmpeqi r5,r5,105 + 6f34: 283f9b26 beq r5,zero,6da4 <___vfprintf_internal_r+0x5c> + 6f38: e0800104 addi r2,fp,4 + 6f3c: d8800415 stw r2,16(sp) + 6f40: 9800b626 beq r19,zero,721c <___vfprintf_internal_r+0x4d4> + 6f44: e5400017 ldw r21,0(fp) + 6f48: a8002216 blt r21,zero,6fd4 <___vfprintf_internal_r+0x28c> + 6f4c: 04c00044 movi r19,1 + 6f50: 0000b606 br 722c <___vfprintf_internal_r+0x4e4> + 6f54: 28801d60 cmpeqi r2,r5,117 + 6f58: 1000b01e bne r2,zero,721c <___vfprintf_internal_r+0x4d4> + 6f5c: 28801e20 cmpeqi r2,r5,120 + 6f60: 103fed1e bne r2,zero,6f18 <___vfprintf_internal_r+0x1d0> + 6f64: 29401ce0 cmpeqi r5,r5,115 + 6f68: 283f8e26 beq r5,zero,6da4 <___vfprintf_internal_r+0x5c> + 6f6c: e5400017 ldw r21,0(fp) + 6f70: e0800104 addi r2,fp,4 + 6f74: d8800315 stw r2,12(sp) + 6f78: a809883a mov r4,r21 + 6f7c: 0006cc00 call 6cc0 + 6f80: 888fc83a sub r7,r17,r2 + 6f84: 1039883a mov fp,r2 + 6f88: 01c0080e bge zero,r7,6fac <___vfprintf_internal_r+0x264> + 6f8c: 01800804 movi r6,32 + 6f90: b80b883a mov r5,r23 + 6f94: 8009883a mov r4,r16 + 6f98: d9c00415 stw r7,16(sp) + 6f9c: 0006cdc0 call 6cdc + 6fa0: 103f9f1e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 6fa4: d9c00417 ldw r7,16(sp) + 6fa8: b1ed883a add r22,r22,r7 + 6fac: b8800117 ldw r2,4(r23) + 6fb0: e00f883a mov r7,fp + 6fb4: a80d883a mov r6,r21 + 6fb8: b80b883a mov r5,r23 + 6fbc: 8009883a mov r4,r16 + 6fc0: 103ee83a callr r2 + 6fc4: 103f961e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 6fc8: b72d883a add r22,r22,fp + 6fcc: df000317 ldw fp,12(sp) + 6fd0: 003f7806 br 6db4 <___vfprintf_internal_r+0x6c> + 6fd4: 056bc83a sub r21,zero,r21 + 6fd8: 04c00044 movi r19,1 + 6fdc: 00c00044 movi r3,1 + 6fe0: df000804 addi fp,sp,32 + 6fe4: e00d883a mov r6,fp + 6fe8: a8002e1e bne r21,zero,70a4 <___vfprintf_internal_r+0x35c> + 6fec: e185c83a sub r2,fp,r6 + 6ff0: d8800315 stw r2,12(sp) + 6ff4: 9085c83a sub r2,r18,r2 + 6ff8: 0080090e bge zero,r2,7020 <___vfprintf_internal_r+0x2d8> + 6ffc: e085883a add r2,fp,r2 + 7000: d9001004 addi r4,sp,64 + 7004: e100042e bgeu fp,r4,7018 <___vfprintf_internal_r+0x2d0> + 7008: e7000044 addi fp,fp,1 + 700c: 01000c04 movi r4,48 + 7010: e13fffc5 stb r4,-1(fp) + 7014: e0bffa1e bne fp,r2,7000 <___vfprintf_internal_r+0x2b8> + 7018: e185c83a sub r2,fp,r6 + 701c: d8800315 stw r2,12(sp) + 7020: d8800317 ldw r2,12(sp) + 7024: 1897883a add r11,r3,r2 + 7028: d8800017 ldw r2,0(sp) + 702c: 8aebc83a sub r21,r17,r11 + 7030: 10003126 beq r2,zero,70f8 <___vfprintf_internal_r+0x3b0> + 7034: 18000a26 beq r3,zero,7060 <___vfprintf_internal_r+0x318> + 7038: 00800b44 movi r2,45 + 703c: d88007c5 stb r2,31(sp) + 7040: b8800117 ldw r2,4(r23) + 7044: 01c00044 movi r7,1 + 7048: d98007c4 addi r6,sp,31 + 704c: b80b883a mov r5,r23 + 7050: 8009883a mov r4,r16 + 7054: 103ee83a callr r2 + 7058: 103f711e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 705c: b5800044 addi r22,r22,1 + 7060: 0540070e bge zero,r21,7080 <___vfprintf_internal_r+0x338> + 7064: a80f883a mov r7,r21 + 7068: 01800c04 movi r6,48 + 706c: b80b883a mov r5,r23 + 7070: 8009883a mov r4,r16 + 7074: 0006cdc0 call 6cdc + 7078: 103f691e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 707c: b56d883a add r22,r22,r21 + 7080: d8800317 ldw r2,12(sp) + 7084: b72d883a add r22,r22,fp + 7088: 172bc83a sub r21,r2,fp + 708c: af05883a add r2,r21,fp + 7090: b707c83a sub r3,r22,fp + 7094: 00802e16 blt zero,r2,7150 <___vfprintf_internal_r+0x408> + 7098: df000417 ldw fp,16(sp) + 709c: 182d883a mov r22,r3 + 70a0: 003f4006 br 6da4 <___vfprintf_internal_r+0x5c> + 70a4: a809883a mov r4,r21 + 70a8: a00b883a mov r5,r20 + 70ac: d8c00315 stw r3,12(sp) + 70b0: 00044440 call 4444 <__udivsi3> + 70b4: 1509383a mul r4,r2,r20 + 70b8: d8c00317 ldw r3,12(sp) + 70bc: d9800804 addi r6,sp,32 + 70c0: a92bc83a sub r21,r21,r4 + 70c4: a9000288 cmpgei r4,r21,10 + 70c8: 2000051e bne r4,zero,70e0 <___vfprintf_internal_r+0x398> + 70cc: ad400c04 addi r21,r21,48 + 70d0: e7000044 addi fp,fp,1 + 70d4: e57fffc5 stb r21,-1(fp) + 70d8: 102b883a mov r21,r2 + 70dc: 003fc206 br 6fe8 <___vfprintf_internal_r+0x2a0> + 70e0: d9000217 ldw r4,8(sp) + 70e4: 20000226 beq r4,zero,70f0 <___vfprintf_internal_r+0x3a8> + 70e8: ad400dc4 addi r21,r21,55 + 70ec: 003ff806 br 70d0 <___vfprintf_internal_r+0x388> + 70f0: ad4015c4 addi r21,r21,87 + 70f4: 003ff606 br 70d0 <___vfprintf_internal_r+0x388> + 70f8: 0540090e bge zero,r21,7120 <___vfprintf_internal_r+0x3d8> + 70fc: a80f883a mov r7,r21 + 7100: 01800804 movi r6,32 + 7104: b80b883a mov r5,r23 + 7108: 8009883a mov r4,r16 + 710c: d8c00615 stw r3,24(sp) + 7110: 0006cdc0 call 6cdc + 7114: 103f421e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 7118: d8c00617 ldw r3,24(sp) + 711c: b56d883a add r22,r22,r21 + 7120: 183fd726 beq r3,zero,7080 <___vfprintf_internal_r+0x338> + 7124: 00800b44 movi r2,45 + 7128: d88007c5 stb r2,31(sp) + 712c: b8800117 ldw r2,4(r23) + 7130: 01c00044 movi r7,1 + 7134: d98007c4 addi r6,sp,31 + 7138: b80b883a mov r5,r23 + 713c: 8009883a mov r4,r16 + 7140: 103ee83a callr r2 + 7144: 103f361e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 7148: b5800044 addi r22,r22,1 + 714c: 003fcc06 br 7080 <___vfprintf_internal_r+0x338> + 7150: e0bfffc3 ldbu r2,-1(fp) + 7154: 01c00044 movi r7,1 + 7158: d98007c4 addi r6,sp,31 + 715c: d88007c5 stb r2,31(sp) + 7160: b8800117 ldw r2,4(r23) + 7164: b80b883a mov r5,r23 + 7168: 8009883a mov r4,r16 + 716c: e73fffc4 addi fp,fp,-1 + 7170: 103ee83a callr r2 + 7174: 103fc526 beq r2,zero,708c <___vfprintf_internal_r+0x344> + 7178: 003f2906 br 6e20 <___vfprintf_internal_r+0xd8> + 717c: 88800090 cmplti r2,r17,2 + 7180: 1000081e bne r2,zero,71a4 <___vfprintf_internal_r+0x45c> + 7184: 8d7fffc4 addi r21,r17,-1 + 7188: a80f883a mov r7,r21 + 718c: 01800804 movi r6,32 + 7190: b80b883a mov r5,r23 + 7194: 8009883a mov r4,r16 + 7198: 0006cdc0 call 6cdc + 719c: 103f201e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 71a0: b56d883a add r22,r22,r21 + 71a4: e0800017 ldw r2,0(fp) + 71a8: 01c00044 movi r7,1 + 71ac: d9800804 addi r6,sp,32 + 71b0: d8800805 stb r2,32(sp) + 71b4: b8800117 ldw r2,4(r23) + 71b8: b80b883a mov r5,r23 + 71bc: 8009883a mov r4,r16 + 71c0: e5400104 addi r21,fp,4 + 71c4: 103ee83a callr r2 + 71c8: 103f151e bne r2,zero,6e20 <___vfprintf_internal_r+0xd8> + 71cc: b5800044 addi r22,r22,1 + 71d0: a839883a mov fp,r21 + 71d4: 003ef706 br 6db4 <___vfprintf_internal_r+0x6c> + 71d8: d8000215 stw zero,8(sp) + 71dc: d8000115 stw zero,4(sp) + 71e0: d8000015 stw zero,0(sp) + 71e4: 04c00044 movi r19,1 + 71e8: 05000284 movi r20,10 + 71ec: 04bfffc4 movi r18,-1 + 71f0: 047fffc4 movi r17,-1 + 71f4: 00800044 movi r2,1 + 71f8: 003eee06 br 6db4 <___vfprintf_internal_r+0x6c> + 71fc: 00800044 movi r2,1 + 7200: d8800015 stw r2,0(sp) + 7204: 003efa06 br 6df0 <___vfprintf_internal_r+0xa8> + 7208: 00800044 movi r2,1 + 720c: d8800115 stw r2,4(sp) + 7210: 008000c4 movi r2,3 + 7214: 003ee706 br 6db4 <___vfprintf_internal_r+0x6c> + 7218: 05000204 movi r20,8 + 721c: e0800104 addi r2,fp,4 + 7220: d8800415 stw r2,16(sp) + 7224: e5400017 ldw r21,0(fp) + 7228: 0027883a mov r19,zero + 722c: 0007883a mov r3,zero + 7230: 003f6b06 br 6fe0 <___vfprintf_internal_r+0x298> + +00007234 <__vfprintf_internal>: + 7234: 00800074 movhi r2,1 + 7238: 300f883a mov r7,r6 + 723c: 280d883a mov r6,r5 + 7240: 200b883a mov r5,r4 + 7244: 112f9517 ldw r4,-16812(r2) + 7248: 0006d481 jmpi 6d48 <___vfprintf_internal_r> + +0000724c <__sfvwrite_small_dev>: + 724c: 2880000b ldhu r2,0(r5) + 7250: 1080020c andi r2,r2,8 + 7254: 10002526 beq r2,zero,72ec <__sfvwrite_small_dev+0xa0> + 7258: 2880008f ldh r2,2(r5) + 725c: defffb04 addi sp,sp,-20 + 7260: dcc00315 stw r19,12(sp) + 7264: dc800215 stw r18,8(sp) + 7268: dc400115 stw r17,4(sp) + 726c: dc000015 stw r16,0(sp) + 7270: dfc00415 stw ra,16(sp) + 7274: 2027883a mov r19,r4 + 7278: 2821883a mov r16,r5 + 727c: 3025883a mov r18,r6 + 7280: 3823883a mov r17,r7 + 7284: 1000100e bge r2,zero,72c8 <__sfvwrite_small_dev+0x7c> + 7288: 8080000b ldhu r2,0(r16) + 728c: 10801014 ori r2,r2,64 + 7290: 8080000d sth r2,0(r16) + 7294: 00bfffc4 movi r2,-1 + 7298: 00000d06 br 72d0 <__sfvwrite_small_dev+0x84> + 729c: 88810050 cmplti r2,r17,1025 + 72a0: 880f883a mov r7,r17 + 72a4: 1000011e bne r2,zero,72ac <__sfvwrite_small_dev+0x60> + 72a8: 01c10004 movi r7,1024 + 72ac: 8140008f ldh r5,2(r16) + 72b0: 900d883a mov r6,r18 + 72b4: 9809883a mov r4,r19 + 72b8: 00073980 call 7398 <_write_r> + 72bc: 00bff20e bge zero,r2,7288 <__sfvwrite_small_dev+0x3c> + 72c0: 88a3c83a sub r17,r17,r2 + 72c4: 90a5883a add r18,r18,r2 + 72c8: 047ff416 blt zero,r17,729c <__sfvwrite_small_dev+0x50> + 72cc: 0005883a mov r2,zero + 72d0: dfc00417 ldw ra,16(sp) + 72d4: dcc00317 ldw r19,12(sp) + 72d8: dc800217 ldw r18,8(sp) + 72dc: dc400117 ldw r17,4(sp) + 72e0: dc000017 ldw r16,0(sp) + 72e4: dec00504 addi sp,sp,20 + 72e8: f800283a ret + 72ec: 00bfffc4 movi r2,-1 + 72f0: f800283a ret + +000072f4 : + 72f4: defffd04 addi sp,sp,-12 + 72f8: 00800034 movhi r2,0 + 72fc: dc000115 stw r16,4(sp) + 7300: dfc00215 stw ra,8(sp) + 7304: 109c9304 addi r2,r2,29260 + 7308: 28800115 stw r2,4(r5) + 730c: 00800074 movhi r2,1 + 7310: d90000c5 stb r4,3(sp) + 7314: 2021883a mov r16,r4 + 7318: 112f9517 ldw r4,-16812(r2) + 731c: 01c00044 movi r7,1 + 7320: d98000c4 addi r6,sp,3 + 7324: 000724c0 call 724c <__sfvwrite_small_dev> + 7328: 10ffffe0 cmpeqi r3,r2,-1 + 732c: 1800011e bne r3,zero,7334 + 7330: 8005883a mov r2,r16 + 7334: dfc00217 ldw ra,8(sp) + 7338: dc000117 ldw r16,4(sp) + 733c: dec00304 addi sp,sp,12 + 7340: f800283a ret + +00007344 <_putc_r>: + 7344: defffd04 addi sp,sp,-12 + 7348: 00800034 movhi r2,0 + 734c: dc000115 stw r16,4(sp) + 7350: dfc00215 stw ra,8(sp) + 7354: 109c9304 addi r2,r2,29260 + 7358: 30800115 stw r2,4(r6) + 735c: 00800074 movhi r2,1 + 7360: 112f9517 ldw r4,-16812(r2) + 7364: 2821883a mov r16,r5 + 7368: 01c00044 movi r7,1 + 736c: 300b883a mov r5,r6 + 7370: d98000c4 addi r6,sp,3 + 7374: dc0000c5 stb r16,3(sp) + 7378: 000724c0 call 724c <__sfvwrite_small_dev> + 737c: 10ffffe0 cmpeqi r3,r2,-1 + 7380: 1800011e bne r3,zero,7388 <_putc_r+0x44> + 7384: 8005883a mov r2,r16 + 7388: dfc00217 ldw ra,8(sp) + 738c: dc000117 ldw r16,4(sp) + 7390: dec00304 addi sp,sp,12 + 7394: f800283a ret + +00007398 <_write_r>: + 7398: defffe04 addi sp,sp,-8 + 739c: dc000015 stw r16,0(sp) + 73a0: 00800074 movhi r2,1 + 73a4: 2021883a mov r16,r4 + 73a8: 2809883a mov r4,r5 + 73ac: 300b883a mov r5,r6 + 73b0: 380d883a mov r6,r7 + 73b4: dfc00115 stw ra,4(sp) + 73b8: 10306f15 stw zero,-15940(r2) + 73bc: 00077c00 call 77c0 + 73c0: 10ffffd8 cmpnei r3,r2,-1 + 73c4: 1800041e bne r3,zero,73d8 <_write_r+0x40> + 73c8: 00c00074 movhi r3,1 + 73cc: 18f06f17 ldw r3,-15940(r3) + 73d0: 18000126 beq r3,zero,73d8 <_write_r+0x40> + 73d4: 80c00015 stw r3,0(r16) + 73d8: dfc00117 ldw ra,4(sp) + 73dc: dc000017 ldw r16,0(sp) + 73e0: dec00204 addi sp,sp,8 + 73e4: f800283a ret + +000073e8 : + 73e8: defffe04 addi sp,sp,-8 + 73ec: df000115 stw fp,4(sp) + 73f0: df000104 addi fp,sp,4 + 73f4: e03fff15 stw zero,-4(fp) + 73f8: 00000506 br 7410 + 73fc: e0bfff17 ldw r2,-4(fp) + 7400: 1000003b flushd 0(r2) + 7404: e0bfff17 ldw r2,-4(fp) + 7408: 10800804 addi r2,r2,32 + 740c: e0bfff15 stw r2,-4(fp) + 7410: e0bfff17 ldw r2,-4(fp) + 7414: 10820030 cmpltui r2,r2,2048 + 7418: 103ff81e bne r2,zero,73fc + 741c: 0001883a nop + 7420: 0001883a nop + 7424: e037883a mov sp,fp + 7428: df000017 ldw fp,0(sp) + 742c: dec00104 addi sp,sp,4 + 7430: f800283a ret + +00007434 : + 7434: defffc04 addi sp,sp,-16 + 7438: df000315 stw fp,12(sp) + 743c: df000304 addi fp,sp,12 + 7440: e13fff15 stw r4,-4(fp) + 7444: e17ffe15 stw r5,-8(fp) + 7448: e1bffd15 stw r6,-12(fp) + 744c: e0fffe17 ldw r3,-8(fp) + 7450: e0bfff17 ldw r2,-4(fp) + 7454: 18800c26 beq r3,r2,7488 + 7458: 00000806 br 747c + 745c: e0ffff17 ldw r3,-4(fp) + 7460: 18800104 addi r2,r3,4 + 7464: e0bfff15 stw r2,-4(fp) + 7468: e0bffe17 ldw r2,-8(fp) + 746c: 11000104 addi r4,r2,4 + 7470: e13ffe15 stw r4,-8(fp) + 7474: 18c00017 ldw r3,0(r3) + 7478: 10c00015 stw r3,0(r2) + 747c: e0fffe17 ldw r3,-8(fp) + 7480: e0bffd17 ldw r2,-12(fp) + 7484: 18bff51e bne r3,r2,745c + 7488: 0001883a nop + 748c: e037883a mov sp,fp + 7490: df000017 ldw fp,0(sp) + 7494: dec00104 addi sp,sp,4 + 7498: f800283a ret + +0000749c : + 749c: defffe04 addi sp,sp,-8 + 74a0: dfc00115 stw ra,4(sp) + 74a4: df000015 stw fp,0(sp) + 74a8: d839883a mov fp,sp + 74ac: 01800074 movhi r6,1 + 74b0: 31afa104 addi r6,r6,-16764 + 74b4: 01400074 movhi r5,1 + 74b8: 296ed704 addi r5,r5,-17572 + 74bc: 01000074 movhi r4,1 + 74c0: 212fa104 addi r4,r4,-16764 + 74c4: 00074340 call 7434 + 74c8: 01800034 movhi r6,0 + 74cc: 31808e04 addi r6,r6,568 + 74d0: 01400034 movhi r5,0 + 74d4: 29400804 addi r5,r5,32 + 74d8: 01000034 movhi r4,0 + 74dc: 21000804 addi r4,r4,32 + 74e0: 00074340 call 7434 + 74e4: 01800074 movhi r6,1 + 74e8: 31aed704 addi r6,r6,-17572 + 74ec: 01400074 movhi r5,1 + 74f0: 296b3304 addi r5,r5,-21300 + 74f4: 01000074 movhi r4,1 + 74f8: 212b3304 addi r4,r4,-21300 + 74fc: 00074340 call 7434 + 7500: 00073e80 call 73e8 + 7504: 0009dc40 call 9dc4 + 7508: 0001883a nop + 750c: e037883a mov sp,fp + 7510: dfc00117 ldw ra,4(sp) + 7514: df000017 ldw fp,0(sp) + 7518: dec00204 addi sp,sp,8 + 751c: f800283a ret + +00007520 : + 7520: defffd04 addi sp,sp,-12 + 7524: dfc00215 stw ra,8(sp) + 7528: df000115 stw fp,4(sp) + 752c: df000104 addi fp,sp,4 + 7530: 0009883a mov r4,zero + 7534: 00078f00 call 78f0 + 7538: 0001883a nop + 753c: 000792c0 call 792c + 7540: 01800074 movhi r6,1 + 7544: 31aec004 addi r6,r6,-17664 + 7548: 01400074 movhi r5,1 + 754c: 296ec004 addi r5,r5,-17664 + 7550: 01000074 movhi r4,1 + 7554: 212ec004 addi r4,r4,-17664 + 7558: 000a1580 call a158 + 755c: 0009c6c0 call 9c6c <_do_ctors> + 7560: 01000074 movhi r4,1 + 7564: 21273404 addi r4,r4,-25392 + 7568: 000a9e80 call a9e8 + 756c: d0a0dd17 ldw r2,-31884(gp) + 7570: d0e0de17 ldw r3,-31880(gp) + 7574: d120df17 ldw r4,-31876(gp) + 7578: 200d883a mov r6,r4 + 757c: 180b883a mov r5,r3 + 7580: 1009883a mov r4,r2 + 7584: 00021140 call 2114
+ 7588: e0bfff15 stw r2,-4(fp) + 758c: 01000044 movi r4,1 + 7590: 0009a800 call 9a80 + 7594: e13fff17 ldw r4,-4(fp) + 7598: 000a9fc0 call a9fc + +0000759c : + 759c: defffa04 addi sp,sp,-24 + 75a0: df000515 stw fp,20(sp) + 75a4: df000504 addi fp,sp,20 + 75a8: e13ffb15 stw r4,-20(fp) + 75ac: 0005303a rdctl r2,status + 75b0: e0bffc15 stw r2,-16(fp) + 75b4: e0fffc17 ldw r3,-16(fp) + 75b8: 00bfff84 movi r2,-2 + 75bc: 1884703a and r2,r3,r2 + 75c0: 1001703a wrctl status,r2 75c4: e0bffc17 ldw r2,-16(fp) - 75c8: 10a0000c andi r2,r2,32768 - 75cc: 10000626 beq r2,zero,75e8 - 75d0: e0bfff17 ldw r2,-4(fp) - 75d4: 10c00044 addi r3,r2,1 - 75d8: e0ffff15 stw r3,-4(fp) - 75dc: e0fffc17 ldw r3,-16(fp) - 75e0: 10c00005 stb r3,0(r2) - 75e4: 00000606 br 7600 - 75e8: e0ffff17 ldw r3,-4(fp) - 75ec: e0bffa17 ldw r2,-24(fp) - 75f0: 1880071e bne r3,r2,7610 - 75f4: e0bff817 ldw r2,-32(fp) - 75f8: 1090000c andi r2,r2,16384 - 75fc: 1000061e bne r2,zero,7618 - 7600: e0ffff17 ldw r3,-4(fp) - 7604: e0bffd17 ldw r2,-12(fp) - 7608: 18bfeb36 bltu r3,r2,75b8 - 760c: 00000306 br 761c - 7610: 0001883a nop - 7614: 00000106 br 761c - 7618: 0001883a nop - 761c: e0ffff17 ldw r3,-4(fp) - 7620: e0bffa17 ldw r2,-24(fp) - 7624: 18800426 beq r3,r2,7638 - 7628: e0ffff17 ldw r3,-4(fp) - 762c: e0bffa17 ldw r2,-24(fp) - 7630: 1885c83a sub r2,r3,r2 - 7634: 00000606 br 7650 - 7638: e0bff817 ldw r2,-32(fp) - 763c: 1090000c andi r2,r2,16384 - 7640: 10000226 beq r2,zero,764c - 7644: 00bffd44 movi r2,-11 - 7648: 00000106 br 7650 - 764c: 00bffec4 movi r2,-5 - 7650: e037883a mov sp,fp - 7654: df000017 ldw fp,0(sp) - 7658: dec00104 addi sp,sp,4 - 765c: f800283a ret - -00007660 : - 7660: defff904 addi sp,sp,-28 - 7664: df000615 stw fp,24(sp) - 7668: df000604 addi fp,sp,24 - 766c: e13ffd15 stw r4,-12(fp) - 7670: e17ffc15 stw r5,-16(fp) - 7674: e1bffb15 stw r6,-20(fp) - 7678: e1fffa15 stw r7,-24(fp) - 767c: e0bffd17 ldw r2,-12(fp) - 7680: 10800017 ldw r2,0(r2) - 7684: e0bfff15 stw r2,-4(fp) - 7688: e0bffb17 ldw r2,-20(fp) - 768c: e0fffc17 ldw r3,-16(fp) - 7690: 1885883a add r2,r3,r2 - 7694: e0bffe15 stw r2,-8(fp) - 7698: 00000e06 br 76d4 - 769c: e0bfff17 ldw r2,-4(fp) - 76a0: 10800104 addi r2,r2,4 - 76a4: 10800037 ldwio r2,0(r2) - 76a8: 10bfffec andhi r2,r2,65535 - 76ac: 10000926 beq r2,zero,76d4 - 76b0: e0ffff17 ldw r3,-4(fp) - 76b4: e0bffc17 ldw r2,-16(fp) - 76b8: 11000044 addi r4,r2,1 - 76bc: e13ffc15 stw r4,-16(fp) - 76c0: 10800003 ldbu r2,0(r2) - 76c4: 10803fcc andi r2,r2,255 - 76c8: 1080201c xori r2,r2,128 - 76cc: 10bfe004 addi r2,r2,-128 - 76d0: 18800035 stwio r2,0(r3) - 76d4: e0fffc17 ldw r3,-16(fp) - 76d8: e0bffe17 ldw r2,-8(fp) - 76dc: 18bfef36 bltu r3,r2,769c - 76e0: e0bffb17 ldw r2,-20(fp) - 76e4: e037883a mov sp,fp - 76e8: df000017 ldw fp,0(sp) - 76ec: dec00104 addi sp,sp,4 - 76f0: f800283a ret - -000076f4 : - 76f4: defffa04 addi sp,sp,-24 - 76f8: dfc00515 stw ra,20(sp) - 76fc: df000415 stw fp,16(sp) - 7700: df000404 addi fp,sp,16 - 7704: e13ffc15 stw r4,-16(fp) - 7708: 0007883a mov r3,zero - 770c: e0bffc17 ldw r2,-16(fp) - 7710: 10c00035 stwio r3,0(r2) - 7714: e0bffc17 ldw r2,-16(fp) - 7718: 10800104 addi r2,r2,4 - 771c: 10800037 ldwio r2,0(r2) - 7720: 0005303a rdctl r2,status - 7724: e0bffd15 stw r2,-12(fp) - 7728: e0fffd17 ldw r3,-12(fp) - 772c: 00bfff84 movi r2,-2 - 7730: 1884703a and r2,r3,r2 - 7734: 1001703a wrctl status,r2 - 7738: e0bffd17 ldw r2,-12(fp) - 773c: e0bfff15 stw r2,-4(fp) - 7740: 000555c0 call 555c - 7744: e0bfff17 ldw r2,-4(fp) - 7748: e0bffe15 stw r2,-8(fp) - 774c: e0bffe17 ldw r2,-8(fp) - 7750: 1001703a wrctl status,r2 - 7754: 0001883a nop - 7758: 0001883a nop - 775c: e037883a mov sp,fp - 7760: dfc00117 ldw ra,4(sp) - 7764: df000017 ldw fp,0(sp) - 7768: dec00204 addi sp,sp,8 - 776c: f800283a ret - -00007770 : - 7770: defff804 addi sp,sp,-32 - 7774: dfc00715 stw ra,28(sp) - 7778: df000615 stw fp,24(sp) - 777c: df000604 addi fp,sp,24 - 7780: e13ffe15 stw r4,-8(fp) - 7784: e17ffd15 stw r5,-12(fp) - 7788: e1bffc15 stw r6,-16(fp) - 778c: e1fffb15 stw r7,-20(fp) - 7790: e0bffb17 ldw r2,-20(fp) - 7794: e0bfff15 stw r2,-4(fp) - 7798: 00800074 movhi r2,1 - 779c: 10a74e17 ldw r2,-25288(r2) - 77a0: 1000041e bne r2,zero,77b4 - 77a4: e0ffff17 ldw r3,-4(fp) - 77a8: 00800074 movhi r2,1 - 77ac: 10e74e15 stw r3,-25288(r2) - 77b0: 00000106 br 77b8 - 77b4: 0001883a nop - 77b8: e0bffe17 ldw r2,-8(fp) - 77bc: 10800104 addi r2,r2,4 - 77c0: 00c001c4 movi r3,7 - 77c4: 10c00035 stwio r3,0(r2) - 77c8: d8000015 stw zero,0(sp) - 77cc: e1fffe17 ldw r7,-8(fp) - 77d0: 01800034 movhi r6,0 - 77d4: 319dbd04 addi r6,r6,30452 - 77d8: e17ffc17 ldw r5,-16(fp) - 77dc: e13ffd17 ldw r4,-12(fp) - 77e0: 0007d140 call 7d14 - 77e4: 0001883a nop - 77e8: e037883a mov sp,fp - 77ec: dfc00117 ldw ra,4(sp) - 77f0: df000017 ldw fp,0(sp) - 77f4: dec00204 addi sp,sp,8 - 77f8: f800283a ret - -000077fc : - 77fc: defffa04 addi sp,sp,-24 - 7800: dfc00515 stw ra,20(sp) - 7804: df000415 stw fp,16(sp) - 7808: df000404 addi fp,sp,16 - 780c: e13ffc15 stw r4,-16(fp) - 7810: 008000c4 movi r2,3 - 7814: e0bffe15 stw r2,-8(fp) - 7818: e0fffe17 ldw r3,-8(fp) - 781c: 008003f4 movhi r2,15 - 7820: 10909004 addi r2,r2,16960 - 7824: 1885383a mul r2,r3,r2 - 7828: 100b883a mov r5,r2 - 782c: 0100bef4 movhi r4,763 - 7830: 213c2004 addi r4,r4,-3968 - 7834: 00034000 call 3400 <__udivsi3> - 7838: 100b883a mov r5,r2 - 783c: 01200034 movhi r4,32768 - 7840: 213fffc4 addi r4,r4,-1 - 7844: 00034000 call 3400 <__udivsi3> - 7848: 100b883a mov r5,r2 - 784c: e13ffc17 ldw r4,-16(fp) - 7850: 00034000 call 3400 <__udivsi3> - 7854: e0bffd15 stw r2,-12(fp) - 7858: e0bffd17 ldw r2,-12(fp) - 785c: 10002a26 beq r2,zero,7908 - 7860: e03fff15 stw zero,-4(fp) - 7864: 00001706 br 78c4 - 7868: 00a00034 movhi r2,32768 - 786c: 10bfffc4 addi r2,r2,-1 - 7870: 10bfffc4 addi r2,r2,-1 - 7874: 103ffe1e bne r2,zero,7870 - 7878: e0fffe17 ldw r3,-8(fp) - 787c: 008003f4 movhi r2,15 - 7880: 10909004 addi r2,r2,16960 - 7884: 1885383a mul r2,r3,r2 - 7888: 100b883a mov r5,r2 - 788c: 0100bef4 movhi r4,763 - 7890: 213c2004 addi r4,r4,-3968 - 7894: 00034000 call 3400 <__udivsi3> - 7898: 100b883a mov r5,r2 - 789c: 01200034 movhi r4,32768 - 78a0: 213fffc4 addi r4,r4,-1 - 78a4: 00034000 call 3400 <__udivsi3> - 78a8: 1007883a mov r3,r2 - 78ac: e0bffc17 ldw r2,-16(fp) - 78b0: 10c5c83a sub r2,r2,r3 - 78b4: e0bffc15 stw r2,-16(fp) - 78b8: e0bfff17 ldw r2,-4(fp) - 78bc: 10800044 addi r2,r2,1 - 78c0: e0bfff15 stw r2,-4(fp) - 78c4: e0ffff17 ldw r3,-4(fp) - 78c8: e0bffd17 ldw r2,-12(fp) - 78cc: 18bfe616 blt r3,r2,7868 - 78d0: e0fffe17 ldw r3,-8(fp) - 78d4: 008003f4 movhi r2,15 - 78d8: 10909004 addi r2,r2,16960 - 78dc: 1885383a mul r2,r3,r2 - 78e0: 100b883a mov r5,r2 - 78e4: 0100bef4 movhi r4,763 - 78e8: 213c2004 addi r4,r4,-3968 - 78ec: 00034000 call 3400 <__udivsi3> - 78f0: 1007883a mov r3,r2 - 78f4: e0bffc17 ldw r2,-16(fp) - 78f8: 1885383a mul r2,r3,r2 - 78fc: 10bfffc4 addi r2,r2,-1 - 7900: 103ffe1e bne r2,zero,78fc - 7904: 00000d06 br 793c - 7908: e0fffe17 ldw r3,-8(fp) - 790c: 008003f4 movhi r2,15 - 7910: 10909004 addi r2,r2,16960 - 7914: 1885383a mul r2,r3,r2 - 7918: 100b883a mov r5,r2 - 791c: 0100bef4 movhi r4,763 - 7920: 213c2004 addi r4,r4,-3968 - 7924: 00034000 call 3400 <__udivsi3> - 7928: 1007883a mov r3,r2 - 792c: e0bffc17 ldw r2,-16(fp) - 7930: 1885383a mul r2,r3,r2 - 7934: 10bfffc4 addi r2,r2,-1 - 7938: 00bffe16 blt zero,r2,7934 - 793c: 0005883a mov r2,zero - 7940: e037883a mov sp,fp - 7944: dfc00117 ldw ra,4(sp) - 7948: df000017 ldw fp,0(sp) - 794c: dec00204 addi sp,sp,8 - 7950: f800283a ret - -00007954 : - 7954: defffe04 addi sp,sp,-8 - 7958: dfc00115 stw ra,4(sp) - 795c: df000015 stw fp,0(sp) - 7960: d839883a mov fp,sp - 7964: 00800074 movhi r2,1 - 7968: 10a67917 ldw r2,-26140(r2) - 796c: 10000426 beq r2,zero,7980 - 7970: 00800074 movhi r2,1 - 7974: 10a67917 ldw r2,-26140(r2) - 7978: 103ee83a callr r2 - 797c: 00000206 br 7988 - 7980: 00800074 movhi r2,1 - 7984: 10a74a04 addi r2,r2,-25304 - 7988: e037883a mov sp,fp - 798c: dfc00117 ldw ra,4(sp) - 7990: df000017 ldw fp,0(sp) - 7994: dec00204 addi sp,sp,8 - 7998: f800283a ret - -0000799c : - 799c: defffb04 addi sp,sp,-20 - 79a0: dfc00415 stw ra,16(sp) - 79a4: df000315 stw fp,12(sp) - 79a8: df000304 addi fp,sp,12 - 79ac: e13ffd15 stw r4,-12(fp) - 79b0: e0bffd17 ldw r2,-12(fp) - 79b4: 10000616 blt r2,zero,79d0 + 75c8: e0bfff15 stw r2,-4(fp) + 75cc: e0bffb17 ldw r2,-20(fp) + 75d0: e0bffd15 stw r2,-12(fp) + 75d4: e0bffd17 ldw r2,-12(fp) + 75d8: 10800017 ldw r2,0(r2) + 75dc: e0fffd17 ldw r3,-12(fp) + 75e0: 18c00117 ldw r3,4(r3) + 75e4: 10c00115 stw r3,4(r2) + 75e8: e0bffd17 ldw r2,-12(fp) + 75ec: 10800117 ldw r2,4(r2) + 75f0: e0fffd17 ldw r3,-12(fp) + 75f4: 18c00017 ldw r3,0(r3) + 75f8: 10c00015 stw r3,0(r2) + 75fc: e0bffd17 ldw r2,-12(fp) + 7600: e0fffd17 ldw r3,-12(fp) + 7604: 10c00115 stw r3,4(r2) + 7608: e0bffd17 ldw r2,-12(fp) + 760c: e0fffd17 ldw r3,-12(fp) + 7610: 10c00015 stw r3,0(r2) + 7614: 0001883a nop + 7618: e0bfff17 ldw r2,-4(fp) + 761c: e0bffe15 stw r2,-8(fp) + 7620: e0bffe17 ldw r2,-8(fp) + 7624: 1001703a wrctl status,r2 + 7628: 0001883a nop + 762c: 0001883a nop + 7630: e037883a mov sp,fp + 7634: df000017 ldw fp,0(sp) + 7638: dec00104 addi sp,sp,4 + 763c: f800283a ret + +00007640 : + 7640: defffb04 addi sp,sp,-20 + 7644: dfc00415 stw ra,16(sp) + 7648: df000315 stw fp,12(sp) + 764c: df000304 addi fp,sp,12 + 7650: d0a00317 ldw r2,-32756(gp) + 7654: e0bfff15 stw r2,-4(fp) + 7658: d0a0e117 ldw r2,-31868(gp) + 765c: 10800044 addi r2,r2,1 + 7660: d0a0e115 stw r2,-31868(gp) + 7664: 00002e06 br 7720 + 7668: e0bfff17 ldw r2,-4(fp) + 766c: 10800017 ldw r2,0(r2) + 7670: e0bffe15 stw r2,-8(fp) + 7674: e0bfff17 ldw r2,-4(fp) + 7678: 10800403 ldbu r2,16(r2) + 767c: 10803fcc andi r2,r2,255 + 7680: 10000426 beq r2,zero,7694 + 7684: d0a0e117 ldw r2,-31868(gp) + 7688: 1000021e bne r2,zero,7694 + 768c: e0bfff17 ldw r2,-4(fp) + 7690: 10000405 stb zero,16(r2) + 7694: e0bfff17 ldw r2,-4(fp) + 7698: 10800217 ldw r2,8(r2) + 769c: d0e0e117 ldw r3,-31868(gp) + 76a0: 18801d36 bltu r3,r2,7718 + 76a4: e0bfff17 ldw r2,-4(fp) + 76a8: 10800403 ldbu r2,16(r2) + 76ac: 10803fcc andi r2,r2,255 + 76b0: 1000191e bne r2,zero,7718 + 76b4: e0bfff17 ldw r2,-4(fp) + 76b8: 10800317 ldw r2,12(r2) + 76bc: e0ffff17 ldw r3,-4(fp) + 76c0: 18c00517 ldw r3,20(r3) + 76c4: 1809883a mov r4,r3 + 76c8: 103ee83a callr r2 + 76cc: e0bffd15 stw r2,-12(fp) + 76d0: e0bffd17 ldw r2,-12(fp) + 76d4: 1000031e bne r2,zero,76e4 + 76d8: e13fff17 ldw r4,-4(fp) + 76dc: 000759c0 call 759c + 76e0: 00000d06 br 7718 + 76e4: e0bfff17 ldw r2,-4(fp) + 76e8: 10c00217 ldw r3,8(r2) + 76ec: e0bffd17 ldw r2,-12(fp) + 76f0: 1887883a add r3,r3,r2 + 76f4: e0bfff17 ldw r2,-4(fp) + 76f8: 10c00215 stw r3,8(r2) + 76fc: e0bfff17 ldw r2,-4(fp) + 7700: 10c00217 ldw r3,8(r2) + 7704: d0a0e117 ldw r2,-31868(gp) + 7708: 1880032e bgeu r3,r2,7718 + 770c: e0bfff17 ldw r2,-4(fp) + 7710: 00c00044 movi r3,1 + 7714: 10c00405 stb r3,16(r2) + 7718: e0bffe17 ldw r2,-8(fp) + 771c: e0bfff15 stw r2,-4(fp) + 7720: e0ffff17 ldw r3,-4(fp) + 7724: d0a00304 addi r2,gp,-32756 + 7728: 18bfcf1e bne r3,r2,7668 + 772c: 0001883a nop + 7730: 0001883a nop + 7734: e037883a mov sp,fp + 7738: dfc00117 ldw ra,4(sp) + 773c: df000017 ldw fp,0(sp) + 7740: dec00204 addi sp,sp,8 + 7744: f800283a ret + +00007748 : + 7748: defffd04 addi sp,sp,-12 + 774c: dfc00215 stw ra,8(sp) + 7750: df000115 stw fp,4(sp) + 7754: df000104 addi fp,sp,4 + 7758: e13fff15 stw r4,-4(fp) + 775c: e13fff17 ldw r4,-4(fp) + 7760: 00098e00 call 98e0 + 7764: e037883a mov sp,fp + 7768: dfc00117 ldw ra,4(sp) + 776c: df000017 ldw fp,0(sp) + 7770: dec00204 addi sp,sp,8 + 7774: f800283a ret + +00007778 : + 7778: defffe04 addi sp,sp,-8 + 777c: dfc00115 stw ra,4(sp) + 7780: df000015 stw fp,0(sp) + 7784: d839883a mov fp,sp + 7788: 00800074 movhi r2,1 + 778c: 10af9f17 ldw r2,-16772(r2) + 7790: 10000426 beq r2,zero,77a4 + 7794: 00800074 movhi r2,1 + 7798: 10af9f17 ldw r2,-16772(r2) + 779c: 103ee83a callr r2 + 77a0: 00000206 br 77ac + 77a4: 00800074 movhi r2,1 + 77a8: 10b06f04 addi r2,r2,-15940 + 77ac: e037883a mov sp,fp + 77b0: dfc00117 ldw ra,4(sp) + 77b4: df000017 ldw fp,0(sp) + 77b8: dec00204 addi sp,sp,8 + 77bc: f800283a ret + +000077c0 : + 77c0: defff904 addi sp,sp,-28 + 77c4: dfc00615 stw ra,24(sp) + 77c8: df000515 stw fp,20(sp) + 77cc: df000504 addi fp,sp,20 + 77d0: e13ffd15 stw r4,-12(fp) + 77d4: e17ffc15 stw r5,-16(fp) + 77d8: e1bffb15 stw r6,-20(fp) + 77dc: e0bffd17 ldw r2,-12(fp) + 77e0: 10000616 blt r2,zero,77fc + 77e4: e0bffd17 ldw r2,-12(fp) + 77e8: 10c00324 muli r3,r2,12 + 77ec: 00800074 movhi r2,1 + 77f0: 10af3304 addi r2,r2,-17204 + 77f4: 1885883a add r2,r3,r2 + 77f8: 00000106 br 7800 + 77fc: 0005883a mov r2,zero + 7800: e0bfff15 stw r2,-4(fp) + 7804: e0bfff17 ldw r2,-4(fp) + 7808: 10002126 beq r2,zero,7890 + 780c: e0bfff17 ldw r2,-4(fp) + 7810: 10800217 ldw r2,8(r2) + 7814: 108000cc andi r2,r2,3 + 7818: 10001826 beq r2,zero,787c + 781c: e0bfff17 ldw r2,-4(fp) + 7820: 10800017 ldw r2,0(r2) + 7824: 10800617 ldw r2,24(r2) + 7828: 10001426 beq r2,zero,787c + 782c: e0bfff17 ldw r2,-4(fp) + 7830: 10800017 ldw r2,0(r2) + 7834: 10800617 ldw r2,24(r2) + 7838: e0fffb17 ldw r3,-20(fp) + 783c: 180d883a mov r6,r3 + 7840: e17ffc17 ldw r5,-16(fp) + 7844: e13fff17 ldw r4,-4(fp) + 7848: 103ee83a callr r2 + 784c: e0bffe15 stw r2,-8(fp) + 7850: e0bffe17 ldw r2,-8(fp) + 7854: 1000070e bge r2,zero,7874 + 7858: 00077780 call 7778 + 785c: 1007883a mov r3,r2 + 7860: e0bffe17 ldw r2,-8(fp) + 7864: 0085c83a sub r2,zero,r2 + 7868: 18800015 stw r2,0(r3) + 786c: 00bfffc4 movi r2,-1 + 7870: 00000c06 br 78a4 + 7874: e0bffe17 ldw r2,-8(fp) + 7878: 00000a06 br 78a4 + 787c: 00077780 call 7778 + 7880: 1007883a mov r3,r2 + 7884: 00800344 movi r2,13 + 7888: 18800015 stw r2,0(r3) + 788c: 00000406 br 78a0 + 7890: 00077780 call 7778 + 7894: 1007883a mov r3,r2 + 7898: 00801444 movi r2,81 + 789c: 18800015 stw r2,0(r3) + 78a0: 00bfffc4 movi r2,-1 + 78a4: e037883a mov sp,fp + 78a8: dfc00117 ldw ra,4(sp) + 78ac: df000017 ldw fp,0(sp) + 78b0: dec00204 addi sp,sp,8 + 78b4: f800283a ret + +000078b8 : + 78b8: defffd04 addi sp,sp,-12 + 78bc: dfc00215 stw ra,8(sp) + 78c0: df000115 stw fp,4(sp) + 78c4: df000104 addi fp,sp,4 + 78c8: e13fff15 stw r4,-4(fp) + 78cc: 01400074 movhi r5,1 + 78d0: 296f9c04 addi r5,r5,-16784 + 78d4: e13fff17 ldw r4,-4(fp) + 78d8: 0009bc40 call 9bc4 + 78dc: e037883a mov sp,fp + 78e0: dfc00117 ldw ra,4(sp) + 78e4: df000017 ldw fp,0(sp) + 78e8: dec00204 addi sp,sp,8 + 78ec: f800283a ret + +000078f0 : + 78f0: defffd04 addi sp,sp,-12 + 78f4: dfc00215 stw ra,8(sp) + 78f8: df000115 stw fp,4(sp) + 78fc: df000104 addi fp,sp,4 + 7900: e13fff15 stw r4,-4(fp) + 7904: 000a6e40 call a6e4 + 7908: 00800044 movi r2,1 + 790c: 1001703a wrctl status,r2 + 7910: 0001883a nop + 7914: 0001883a nop + 7918: e037883a mov sp,fp + 791c: dfc00117 ldw ra,4(sp) + 7920: df000017 ldw fp,0(sp) + 7924: dec00204 addi sp,sp,8 + 7928: f800283a ret + +0000792c : + 792c: defffe04 addi sp,sp,-8 + 7930: dfc00115 stw ra,4(sp) + 7934: df000015 stw fp,0(sp) + 7938: d839883a mov fp,sp + 793c: 01c0fa04 movi r7,1000 + 7940: 01800044 movi r6,1 + 7944: 000b883a mov r5,zero + 7948: 010000b4 movhi r4,2 + 794c: 21002004 addi r4,r4,128 + 7950: 00098540 call 9854 + 7954: 01000074 movhi r4,1 + 7958: 212f1004 addi r4,r4,-17344 + 795c: 0007bd80 call 7bd8 + 7960: 01000074 movhi r4,1 + 7964: 212f1e04 addi r4,r4,-17288 + 7968: 00078b80 call 78b8 + 796c: 0001883a nop + 7970: e037883a mov sp,fp + 7974: dfc00117 ldw ra,4(sp) + 7978: df000017 ldw fp,0(sp) + 797c: dec00204 addi sp,sp,8 + 7980: f800283a ret + +00007984 : + 7984: defff904 addi sp,sp,-28 + 7988: dfc00615 stw ra,24(sp) + 798c: df000515 stw fp,20(sp) + 7990: df000504 addi fp,sp,20 + 7994: e13ffb15 stw r4,-20(fp) + 7998: 008000b4 movhi r2,2 + 799c: 10a1a804 addi r2,r2,-31072 + 79a0: e0bfff15 stw r2,-4(fp) + 79a4: e0bffb17 ldw r2,-20(fp) + 79a8: e0bffe15 stw r2,-8(fp) + 79ac: e0bffe17 ldw r2,-8(fp) + 79b0: 10800717 ldw r2,28(r2) + 79b4: e0bffd15 stw r2,-12(fp) 79b8: e0bffd17 ldw r2,-12(fp) - 79bc: 10c00324 muli r3,r2,12 - 79c0: 00800074 movhi r2,1 - 79c4: 10a60b04 addi r2,r2,-26580 - 79c8: 1885883a add r2,r3,r2 - 79cc: 00000106 br 79d4 - 79d0: 0005883a mov r2,zero - 79d4: e0bfff15 stw r2,-4(fp) - 79d8: e0bfff17 ldw r2,-4(fp) - 79dc: 10001926 beq r2,zero,7a44 - 79e0: e0bfff17 ldw r2,-4(fp) - 79e4: 10800017 ldw r2,0(r2) - 79e8: 10800417 ldw r2,16(r2) - 79ec: 10000626 beq r2,zero,7a08 - 79f0: e0bfff17 ldw r2,-4(fp) - 79f4: 10800017 ldw r2,0(r2) - 79f8: 10800417 ldw r2,16(r2) - 79fc: e13fff17 ldw r4,-4(fp) - 7a00: 103ee83a callr r2 - 7a04: 00000106 br 7a0c - 7a08: 0005883a mov r2,zero - 7a0c: e0bffe15 stw r2,-8(fp) - 7a10: e13ffd17 ldw r4,-12(fp) - 7a14: 00085a80 call 85a8 - 7a18: e0bffe17 ldw r2,-8(fp) - 7a1c: 1000070e bge r2,zero,7a3c - 7a20: 00079540 call 7954 - 7a24: 1007883a mov r3,r2 - 7a28: e0bffe17 ldw r2,-8(fp) - 7a2c: 0085c83a sub r2,zero,r2 - 7a30: 18800015 stw r2,0(r3) - 7a34: 00bfffc4 movi r2,-1 - 7a38: 00000706 br 7a58 - 7a3c: 0005883a mov r2,zero - 7a40: 00000506 br 7a58 - 7a44: 00079540 call 7954 - 7a48: 1007883a mov r3,r2 - 7a4c: 00801444 movi r2,81 - 7a50: 18800015 stw r2,0(r3) - 7a54: 00bfffc4 movi r2,-1 - 7a58: e037883a mov sp,fp - 7a5c: dfc00117 ldw ra,4(sp) - 7a60: df000017 ldw fp,0(sp) - 7a64: dec00204 addi sp,sp,8 - 7a68: f800283a ret - -00007a6c : - 7a6c: defffc04 addi sp,sp,-16 - 7a70: df000315 stw fp,12(sp) - 7a74: df000304 addi fp,sp,12 - 7a78: e13fff15 stw r4,-4(fp) - 7a7c: e17ffe15 stw r5,-8(fp) - 7a80: e1bffd15 stw r6,-12(fp) - 7a84: e0bffd17 ldw r2,-12(fp) - 7a88: e037883a mov sp,fp - 7a8c: df000017 ldw fp,0(sp) - 7a90: dec00104 addi sp,sp,4 - 7a94: f800283a ret - -00007a98 : - 7a98: defffe04 addi sp,sp,-8 - 7a9c: dfc00115 stw ra,4(sp) - 7aa0: df000015 stw fp,0(sp) - 7aa4: d839883a mov fp,sp - 7aa8: 00800074 movhi r2,1 - 7aac: 10a67917 ldw r2,-26140(r2) - 7ab0: 10000426 beq r2,zero,7ac4 - 7ab4: 00800074 movhi r2,1 - 7ab8: 10a67917 ldw r2,-26140(r2) - 7abc: 103ee83a callr r2 - 7ac0: 00000206 br 7acc - 7ac4: 00800074 movhi r2,1 - 7ac8: 10a74a04 addi r2,r2,-25304 - 7acc: e037883a mov sp,fp - 7ad0: dfc00117 ldw ra,4(sp) - 7ad4: df000017 ldw fp,0(sp) - 7ad8: dec00204 addi sp,sp,8 - 7adc: f800283a ret - -00007ae0 : - 7ae0: defffa04 addi sp,sp,-24 - 7ae4: dfc00515 stw ra,20(sp) - 7ae8: df000415 stw fp,16(sp) - 7aec: df000404 addi fp,sp,16 - 7af0: e13ffd15 stw r4,-12(fp) - 7af4: e17ffc15 stw r5,-16(fp) - 7af8: e0bffd17 ldw r2,-12(fp) - 7afc: 10000326 beq r2,zero,7b0c - 7b00: e0bffd17 ldw r2,-12(fp) - 7b04: 10800217 ldw r2,8(r2) - 7b08: 1000061e bne r2,zero,7b24 - 7b0c: 0007a980 call 7a98 - 7b10: 1007883a mov r3,r2 - 7b14: 00800584 movi r2,22 - 7b18: 18800015 stw r2,0(r3) - 7b1c: 00bffa84 movi r2,-22 - 7b20: 00001406 br 7b74 - 7b24: e0bffd17 ldw r2,-12(fp) - 7b28: e0fffc17 ldw r3,-16(fp) - 7b2c: e0ffff15 stw r3,-4(fp) - 7b30: e0bffe15 stw r2,-8(fp) - 7b34: e0bffe17 ldw r2,-8(fp) - 7b38: e0ffff17 ldw r3,-4(fp) - 7b3c: 10c00115 stw r3,4(r2) - 7b40: e0bfff17 ldw r2,-4(fp) - 7b44: 10c00017 ldw r3,0(r2) - 7b48: e0bffe17 ldw r2,-8(fp) - 7b4c: 10c00015 stw r3,0(r2) - 7b50: e0bfff17 ldw r2,-4(fp) - 7b54: 10800017 ldw r2,0(r2) - 7b58: e0fffe17 ldw r3,-8(fp) - 7b5c: 10c00115 stw r3,4(r2) - 7b60: e0bfff17 ldw r2,-4(fp) - 7b64: e0fffe17 ldw r3,-8(fp) - 7b68: 10c00015 stw r3,0(r2) + 79bc: 10800217 ldw r2,8(r2) + 79c0: 10800098 cmpnei r2,r2,2 + 79c4: 1000251e bne r2,zero,7a5c + 79c8: e0bffd17 ldw r2,-12(fp) + 79cc: 10c00017 ldw r3,0(r2) + 79d0: e0bffd17 ldw r2,-12(fp) + 79d4: 10800117 ldw r2,4(r2) + 79d8: e13ffc04 addi r4,fp,-16 + 79dc: 200f883a mov r7,r4 + 79e0: 100d883a mov r6,r2 + 79e4: 180b883a mov r5,r3 + 79e8: e13ffe17 ldw r4,-8(fp) + 79ec: 00081380 call 8138 + 79f0: e0bffd17 ldw r2,-12(fp) + 79f4: 10c00117 ldw r3,4(r2) + 79f8: e0bffc17 ldw r2,-16(fp) + 79fc: 1887c83a sub r3,r3,r2 + 7a00: e0bffd17 ldw r2,-12(fp) + 7a04: 10c00115 stw r3,4(r2) + 7a08: e0bffd17 ldw r2,-12(fp) + 7a0c: 10c00017 ldw r3,0(r2) + 7a10: e0bffc17 ldw r2,-16(fp) + 7a14: 1887883a add r3,r3,r2 + 7a18: e0bffd17 ldw r2,-12(fp) + 7a1c: 10c00015 stw r3,0(r2) + 7a20: e0bffd17 ldw r2,-12(fp) + 7a24: 10800117 ldw r2,4(r2) + 7a28: 10000c26 beq r2,zero,7a5c + 7a2c: 01400704 movi r5,28 + 7a30: e13ffe17 ldw r4,-8(fp) + 7a34: 00092e40 call 92e4 + 7a38: 01400084 movi r5,2 + 7a3c: e13ffe17 ldw r4,-8(fp) + 7a40: 000938c0 call 938c + 7a44: 00000e06 br 7a80 + 7a48: e0bfff17 ldw r2,-4(fp) + 7a4c: 10bfffc4 addi r2,r2,-1 + 7a50: e0bfff15 stw r2,-4(fp) + 7a54: e0bfff17 ldw r2,-4(fp) + 7a58: 10000426 beq r2,zero,7a6c + 7a5c: e13ffe17 ldw r4,-8(fp) + 7a60: 00080f40 call 80f4 + 7a64: 103ff81e bne r2,zero,7a48 + 7a68: 00000106 br 7a70 + 7a6c: 0001883a nop + 7a70: e13ffe17 ldw r4,-8(fp) + 7a74: 0007d9c0 call 7d9c + 7a78: e0bffd17 ldw r2,-12(fp) + 7a7c: 10000215 stw zero,8(r2) + 7a80: e037883a mov sp,fp + 7a84: dfc00117 ldw ra,4(sp) + 7a88: df000017 ldw fp,0(sp) + 7a8c: dec00204 addi sp,sp,8 + 7a90: f800283a ret + +00007a94 : + 7a94: defffc04 addi sp,sp,-16 + 7a98: dfc00315 stw ra,12(sp) + 7a9c: df000215 stw fp,8(sp) + 7aa0: df000204 addi fp,sp,8 + 7aa4: e13fff15 stw r4,-4(fp) + 7aa8: e17ffe15 stw r5,-8(fp) + 7aac: e0bffe17 ldw r2,-8(fp) + 7ab0: 10000215 stw zero,8(r2) + 7ab4: e1fffe17 ldw r7,-8(fp) + 7ab8: 000d883a mov r6,zero + 7abc: 01400034 movhi r5,0 + 7ac0: 295e6104 addi r5,r5,31108 + 7ac4: e13fff17 ldw r4,-4(fp) + 7ac8: 0007b840 call 7b84 + 7acc: 0001883a nop + 7ad0: e037883a mov sp,fp + 7ad4: dfc00117 ldw ra,4(sp) + 7ad8: df000017 ldw fp,0(sp) + 7adc: dec00204 addi sp,sp,8 + 7ae0: f800283a ret + +00007ae4 : + 7ae4: defff904 addi sp,sp,-28 + 7ae8: dfc00615 stw ra,24(sp) + 7aec: df000515 stw fp,20(sp) + 7af0: df000504 addi fp,sp,20 + 7af4: e13ffb15 stw r4,-20(fp) + 7af8: e0bffb17 ldw r2,-20(fp) + 7afc: e0bfff15 stw r2,-4(fp) + 7b00: 014007c4 movi r5,31 + 7b04: e13fff17 ldw r4,-4(fp) + 7b08: 00093200 call 9320 + 7b0c: 01400704 movi r5,28 + 7b10: e13fff17 ldw r4,-4(fp) + 7b14: 00092e40 call 92e4 + 7b18: e0bfff17 ldw r2,-4(fp) + 7b1c: 10800617 ldw r2,24(r2) + 7b20: 10001226 beq r2,zero,7b6c + 7b24: 0005303a rdctl r2,status + 7b28: e0bffc15 stw r2,-16(fp) + 7b2c: e0fffc17 ldw r3,-16(fp) + 7b30: 00bfff84 movi r2,-2 + 7b34: 1884703a and r2,r3,r2 + 7b38: 1001703a wrctl status,r2 + 7b3c: e0bffc17 ldw r2,-16(fp) + 7b40: e0bffe15 stw r2,-8(fp) + 7b44: e0bfff17 ldw r2,-4(fp) + 7b48: 10800617 ldw r2,24(r2) + 7b4c: e13fff17 ldw r4,-4(fp) + 7b50: 103ee83a callr r2 + 7b54: e0bffe17 ldw r2,-8(fp) + 7b58: e0bffd15 stw r2,-12(fp) + 7b5c: e0bffd17 ldw r2,-12(fp) + 7b60: 1001703a wrctl status,r2 + 7b64: 0001883a nop + 7b68: 0001883a nop 7b6c: 0001883a nop - 7b70: 0005883a mov r2,zero - 7b74: e037883a mov sp,fp - 7b78: dfc00117 ldw ra,4(sp) - 7b7c: df000017 ldw fp,0(sp) - 7b80: dec00204 addi sp,sp,8 - 7b84: f800283a ret - -00007b88 <_do_ctors>: - 7b88: defffd04 addi sp,sp,-12 - 7b8c: dfc00215 stw ra,8(sp) - 7b90: df000115 stw fp,4(sp) - 7b94: df000104 addi fp,sp,4 - 7b98: 00800074 movhi r2,1 - 7b9c: 10a2f904 addi r2,r2,-29724 - 7ba0: e0bfff15 stw r2,-4(fp) - 7ba4: 00000606 br 7bc0 <_do_ctors+0x38> - 7ba8: e0bfff17 ldw r2,-4(fp) - 7bac: 10800017 ldw r2,0(r2) - 7bb0: 103ee83a callr r2 - 7bb4: e0bfff17 ldw r2,-4(fp) - 7bb8: 10bfff04 addi r2,r2,-4 - 7bbc: e0bfff15 stw r2,-4(fp) - 7bc0: e0ffff17 ldw r3,-4(fp) - 7bc4: 00800074 movhi r2,1 - 7bc8: 10a2fa04 addi r2,r2,-29720 - 7bcc: 18bff62e bgeu r3,r2,7ba8 <_do_ctors+0x20> - 7bd0: 0001883a nop - 7bd4: 0001883a nop - 7bd8: e037883a mov sp,fp - 7bdc: dfc00117 ldw ra,4(sp) - 7be0: df000017 ldw fp,0(sp) - 7be4: dec00204 addi sp,sp,8 - 7be8: f800283a ret - -00007bec <_do_dtors>: - 7bec: defffd04 addi sp,sp,-12 - 7bf0: dfc00215 stw ra,8(sp) - 7bf4: df000115 stw fp,4(sp) - 7bf8: df000104 addi fp,sp,4 - 7bfc: 00800074 movhi r2,1 - 7c00: 10a2f904 addi r2,r2,-29724 - 7c04: e0bfff15 stw r2,-4(fp) - 7c08: 00000606 br 7c24 <_do_dtors+0x38> - 7c0c: e0bfff17 ldw r2,-4(fp) - 7c10: 10800017 ldw r2,0(r2) - 7c14: 103ee83a callr r2 - 7c18: e0bfff17 ldw r2,-4(fp) - 7c1c: 10bfff04 addi r2,r2,-4 - 7c20: e0bfff15 stw r2,-4(fp) - 7c24: e0ffff17 ldw r3,-4(fp) - 7c28: 00800074 movhi r2,1 - 7c2c: 10a2fa04 addi r2,r2,-29720 - 7c30: 18bff62e bgeu r3,r2,7c0c <_do_dtors+0x20> - 7c34: 0001883a nop - 7c38: 0001883a nop - 7c3c: e037883a mov sp,fp - 7c40: dfc00117 ldw ra,4(sp) - 7c44: df000017 ldw fp,0(sp) - 7c48: dec00204 addi sp,sp,8 - 7c4c: f800283a ret - -00007c50 : - 7c50: defffa04 addi sp,sp,-24 - 7c54: dfc00515 stw ra,20(sp) - 7c58: df000415 stw fp,16(sp) - 7c5c: df000404 addi fp,sp,16 - 7c60: e13ffd15 stw r4,-12(fp) - 7c64: e17ffc15 stw r5,-16(fp) - 7c68: e0bffc17 ldw r2,-16(fp) - 7c6c: 10800017 ldw r2,0(r2) - 7c70: e0bfff15 stw r2,-4(fp) - 7c74: e13ffd17 ldw r4,-12(fp) - 7c78: 0004bdc0 call 4bdc - 7c7c: 10800044 addi r2,r2,1 - 7c80: e0bffe15 stw r2,-8(fp) - 7c84: 00000d06 br 7cbc - 7c88: e0bfff17 ldw r2,-4(fp) - 7c8c: 10800217 ldw r2,8(r2) - 7c90: e0fffe17 ldw r3,-8(fp) - 7c94: 180d883a mov r6,r3 - 7c98: e17ffd17 ldw r5,-12(fp) - 7c9c: 1009883a mov r4,r2 - 7ca0: 00089380 call 8938 - 7ca4: 1000021e bne r2,zero,7cb0 - 7ca8: e0bfff17 ldw r2,-4(fp) - 7cac: 00000706 br 7ccc - 7cb0: e0bfff17 ldw r2,-4(fp) - 7cb4: 10800017 ldw r2,0(r2) - 7cb8: e0bfff15 stw r2,-4(fp) - 7cbc: e0ffff17 ldw r3,-4(fp) - 7cc0: e0bffc17 ldw r2,-16(fp) - 7cc4: 18bff01e bne r3,r2,7c88 - 7cc8: 0005883a mov r2,zero - 7ccc: e037883a mov sp,fp - 7cd0: dfc00117 ldw ra,4(sp) - 7cd4: df000017 ldw fp,0(sp) - 7cd8: dec00204 addi sp,sp,8 - 7cdc: f800283a ret - -00007ce0 : - 7ce0: defffe04 addi sp,sp,-8 - 7ce4: dfc00115 stw ra,4(sp) - 7ce8: df000015 stw fp,0(sp) - 7cec: d839883a mov fp,sp - 7cf0: 01440004 movi r5,4096 - 7cf4: 0009883a mov r4,zero - 7cf8: 00087dc0 call 87dc - 7cfc: 0001883a nop - 7d00: e037883a mov sp,fp - 7d04: dfc00117 ldw ra,4(sp) - 7d08: df000017 ldw fp,0(sp) - 7d0c: dec00204 addi sp,sp,8 - 7d10: f800283a ret - -00007d14 : - 7d14: defff904 addi sp,sp,-28 - 7d18: dfc00615 stw ra,24(sp) - 7d1c: df000515 stw fp,20(sp) - 7d20: df000504 addi fp,sp,20 - 7d24: e13fff15 stw r4,-4(fp) - 7d28: e17ffe15 stw r5,-8(fp) - 7d2c: e1bffd15 stw r6,-12(fp) - 7d30: e1fffc15 stw r7,-16(fp) - 7d34: e0800217 ldw r2,8(fp) - 7d38: d8800015 stw r2,0(sp) - 7d3c: e1fffc17 ldw r7,-16(fp) - 7d40: e1bffd17 ldw r6,-12(fp) - 7d44: e17ffe17 ldw r5,-8(fp) - 7d48: e13fff17 ldw r4,-4(fp) - 7d4c: 0007edc0 call 7edc - 7d50: e037883a mov sp,fp - 7d54: dfc00117 ldw ra,4(sp) - 7d58: df000017 ldw fp,0(sp) - 7d5c: dec00204 addi sp,sp,8 - 7d60: f800283a ret - -00007d64 : - 7d64: defff904 addi sp,sp,-28 - 7d68: df000615 stw fp,24(sp) - 7d6c: df000604 addi fp,sp,24 - 7d70: e13ffb15 stw r4,-20(fp) - 7d74: e17ffa15 stw r5,-24(fp) - 7d78: e0bffa17 ldw r2,-24(fp) - 7d7c: e0bfff15 stw r2,-4(fp) - 7d80: 0005303a rdctl r2,status - 7d84: e0bffe15 stw r2,-8(fp) - 7d88: e0fffe17 ldw r3,-8(fp) - 7d8c: 00bfff84 movi r2,-2 - 7d90: 1884703a and r2,r3,r2 - 7d94: 1001703a wrctl status,r2 - 7d98: e0bffe17 ldw r2,-8(fp) - 7d9c: e0bffd15 stw r2,-12(fp) - 7da0: 00c00044 movi r3,1 - 7da4: e0bfff17 ldw r2,-4(fp) - 7da8: 1884983a sll r2,r3,r2 - 7dac: 1007883a mov r3,r2 - 7db0: 00800074 movhi r2,1 - 7db4: 10a75017 ldw r2,-25280(r2) - 7db8: 1886b03a or r3,r3,r2 - 7dbc: 00800074 movhi r2,1 - 7dc0: 10e75015 stw r3,-25280(r2) - 7dc4: 00800074 movhi r2,1 - 7dc8: 10a75017 ldw r2,-25280(r2) - 7dcc: 100170fa wrctl ienable,r2 - 7dd0: e0bffd17 ldw r2,-12(fp) - 7dd4: e0bffc15 stw r2,-16(fp) - 7dd8: e0bffc17 ldw r2,-16(fp) - 7ddc: 1001703a wrctl status,r2 - 7de0: 0001883a nop - 7de4: 0005883a mov r2,zero - 7de8: e037883a mov sp,fp - 7dec: df000017 ldw fp,0(sp) - 7df0: dec00104 addi sp,sp,4 - 7df4: f800283a ret - -00007df8 : - 7df8: defff904 addi sp,sp,-28 - 7dfc: df000615 stw fp,24(sp) - 7e00: df000604 addi fp,sp,24 - 7e04: e13ffb15 stw r4,-20(fp) - 7e08: e17ffa15 stw r5,-24(fp) - 7e0c: e0bffa17 ldw r2,-24(fp) - 7e10: e0bfff15 stw r2,-4(fp) - 7e14: 0005303a rdctl r2,status - 7e18: e0bffe15 stw r2,-8(fp) - 7e1c: e0fffe17 ldw r3,-8(fp) - 7e20: 00bfff84 movi r2,-2 - 7e24: 1884703a and r2,r3,r2 - 7e28: 1001703a wrctl status,r2 - 7e2c: e0bffe17 ldw r2,-8(fp) - 7e30: e0bffd15 stw r2,-12(fp) - 7e34: 00c00044 movi r3,1 - 7e38: e0bfff17 ldw r2,-4(fp) - 7e3c: 1884983a sll r2,r3,r2 - 7e40: 0084303a nor r2,zero,r2 - 7e44: 1007883a mov r3,r2 - 7e48: 00800074 movhi r2,1 - 7e4c: 10a75017 ldw r2,-25280(r2) - 7e50: 1886703a and r3,r3,r2 - 7e54: 00800074 movhi r2,1 - 7e58: 10e75015 stw r3,-25280(r2) - 7e5c: 00800074 movhi r2,1 - 7e60: 10a75017 ldw r2,-25280(r2) - 7e64: 100170fa wrctl ienable,r2 - 7e68: e0bffd17 ldw r2,-12(fp) - 7e6c: e0bffc15 stw r2,-16(fp) - 7e70: e0bffc17 ldw r2,-16(fp) - 7e74: 1001703a wrctl status,r2 - 7e78: 0001883a nop - 7e7c: 0005883a mov r2,zero - 7e80: e037883a mov sp,fp - 7e84: df000017 ldw fp,0(sp) - 7e88: dec00104 addi sp,sp,4 - 7e8c: f800283a ret - -00007e90 : - 7e90: defffc04 addi sp,sp,-16 - 7e94: df000315 stw fp,12(sp) - 7e98: df000304 addi fp,sp,12 - 7e9c: e13ffe15 stw r4,-8(fp) - 7ea0: e17ffd15 stw r5,-12(fp) - 7ea4: 000530fa rdctl r2,ienable - 7ea8: e0bfff15 stw r2,-4(fp) - 7eac: 00c00044 movi r3,1 - 7eb0: e0bffd17 ldw r2,-12(fp) - 7eb4: 1884983a sll r2,r3,r2 - 7eb8: 1007883a mov r3,r2 + 7b70: e037883a mov sp,fp + 7b74: dfc00117 ldw ra,4(sp) + 7b78: df000017 ldw fp,0(sp) + 7b7c: dec00204 addi sp,sp,8 + 7b80: f800283a ret + +00007b84 : + 7b84: defffb04 addi sp,sp,-20 + 7b88: df000415 stw fp,16(sp) + 7b8c: df000404 addi fp,sp,16 + 7b90: e13fff15 stw r4,-4(fp) + 7b94: e17ffe15 stw r5,-8(fp) + 7b98: e1bffd15 stw r6,-12(fp) + 7b9c: e1fffc15 stw r7,-16(fp) + 7ba0: e0bfff17 ldw r2,-4(fp) + 7ba4: e0fffe17 ldw r3,-8(fp) + 7ba8: 10c00615 stw r3,24(r2) + 7bac: e0bfff17 ldw r2,-4(fp) + 7bb0: e0fffc17 ldw r3,-16(fp) + 7bb4: 10c00715 stw r3,28(r2) + 7bb8: e0bfff17 ldw r2,-4(fp) + 7bbc: e0fffd17 ldw r3,-12(fp) + 7bc0: 10c00815 stw r3,32(r2) + 7bc4: 0001883a nop + 7bc8: e037883a mov sp,fp + 7bcc: df000017 ldw fp,0(sp) + 7bd0: dec00104 addi sp,sp,4 + 7bd4: f800283a ret + +00007bd8 : + 7bd8: defff704 addi sp,sp,-36 + 7bdc: dfc00815 stw ra,32(sp) + 7be0: df000715 stw fp,28(sp) + 7be4: df000704 addi fp,sp,28 + 7be8: e13ffa15 stw r4,-24(fp) + 7bec: e13ffa17 ldw r4,-24(fp) + 7bf0: 0007d9c0 call 7d9c + 7bf4: 014007c4 movi r5,31 + 7bf8: e13ffa17 ldw r4,-24(fp) + 7bfc: 00093200 call 9320 + 7c00: 01400704 movi r5,28 + 7c04: e13ffa17 ldw r4,-24(fp) + 7c08: 00092e40 call 92e4 + 7c0c: 014000c4 movi r5,3 + 7c10: e13ffa17 ldw r4,-24(fp) + 7c14: 00095340 call 9534 + 7c18: 014000c4 movi r5,3 + 7c1c: e13ffa17 ldw r4,-24(fp) + 7c20: 00094840 call 9484 + 7c24: e03ffc15 stw zero,-16(fp) + 7c28: e03ffb15 stw zero,-20(fp) + 7c2c: e0bffb04 addi r2,fp,-20 + 7c30: 018000b4 movhi r6,2 + 7c34: 31a1a804 addi r6,r6,-31072 + 7c38: 100b883a mov r5,r2 + 7c3c: e13ffa17 ldw r4,-24(fp) + 7c40: 0007ff80 call 7ff8 + 7c44: e0bffb04 addi r2,fp,-20 + 7c48: 100b883a mov r5,r2 + 7c4c: e13ffa17 ldw r4,-24(fp) + 7c50: 0007e980 call 7e98 + 7c54: d1600504 addi r5,gp,-32748 + 7c58: e13ffa17 ldw r4,-24(fp) + 7c5c: 0009bc40 call 9bc4 + 7c60: 0005883a mov r2,zero + 7c64: e0bfff15 stw r2,-4(fp) + 7c68: e0bfff17 ldw r2,-4(fp) + 7c6c: 10000c1e bne r2,zero,7ca0 + 7c70: e0bffa17 ldw r2,-24(fp) + 7c74: 10c00417 ldw r3,16(r2) + 7c78: e0bffa17 ldw r2,-24(fp) + 7c7c: 10800517 ldw r2,20(r2) + 7c80: d8000015 stw zero,0(sp) + 7c84: e1fffa17 ldw r7,-24(fp) + 7c88: 01800034 movhi r6,0 + 7c8c: 319eb904 addi r6,r6,31460 + 7c90: 100b883a mov r5,r2 + 7c94: 1809883a mov r4,r3 + 7c98: 0009df80 call 9df8 + 7c9c: 00000406 br 7cb0 + 7ca0: 01000074 movhi r4,1 + 7ca4: 212ecc04 addi r4,r4,-17616 + 7ca8: 000a4300 call a430 + 7cac: 0001883a nop + 7cb0: e037883a mov sp,fp + 7cb4: dfc00117 ldw ra,4(sp) + 7cb8: df000017 ldw fp,0(sp) + 7cbc: dec00204 addi sp,sp,8 + 7cc0: f800283a ret + +00007cc4 : + 7cc4: defffc04 addi sp,sp,-16 + 7cc8: dfc00315 stw ra,12(sp) + 7ccc: df000215 stw fp,8(sp) + 7cd0: df000204 addi fp,sp,8 + 7cd4: e13ffe15 stw r4,-8(fp) + 7cd8: e03fff15 stw zero,-4(fp) + 7cdc: d1600504 addi r5,gp,-32748 + 7ce0: e13ffe17 ldw r4,-8(fp) + 7ce4: 0009d340 call 9d34 + 7ce8: e0bfff15 stw r2,-4(fp) + 7cec: e0bfff17 ldw r2,-4(fp) + 7cf0: e037883a mov sp,fp + 7cf4: dfc00117 ldw ra,4(sp) + 7cf8: df000017 ldw fp,0(sp) + 7cfc: dec00204 addi sp,sp,8 + 7d00: f800283a ret + +00007d04 : + 7d04: defffc04 addi sp,sp,-16 + 7d08: df000315 stw fp,12(sp) + 7d0c: df000304 addi fp,sp,12 + 7d10: e13ffd15 stw r4,-12(fp) + 7d14: e0bffd17 ldw r2,-12(fp) + 7d18: 10800717 ldw r2,28(r2) + 7d1c: e0bfff15 stw r2,-4(fp) + 7d20: e0bffd17 ldw r2,-12(fp) + 7d24: 10800317 ldw r2,12(r2) + 7d28: 10800204 addi r2,r2,8 + 7d2c: 10800037 ldwio r2,0(r2) + 7d30: 1080004c andi r2,r2,1 + 7d34: e0bffe15 stw r2,-8(fp) + 7d38: e0bffe17 ldw r2,-8(fp) + 7d3c: 10000226 beq r2,zero,7d48 + 7d40: 00bffe44 movi r2,-7 + 7d44: 00001106 br 7d8c + 7d48: e0bffd17 ldw r2,-12(fp) + 7d4c: 10c00617 ldw r3,24(r2) + 7d50: 00800034 movhi r2,0 + 7d54: 109e6104 addi r2,r2,31108 + 7d58: 1880021e bne r3,r2,7d64 + 7d5c: e0bfff17 ldw r2,-4(fp) + 7d60: 10000215 stw zero,8(r2) + 7d64: e0bffd17 ldw r2,-12(fp) + 7d68: 10800317 ldw r2,12(r2) + 7d6c: 10800204 addi r2,r2,8 + 7d70: e0fffd17 ldw r3,-12(fp) + 7d74: 18c00317 ldw r3,12(r3) + 7d78: 18c00204 addi r3,r3,8 + 7d7c: 18c00037 ldwio r3,0(r3) + 7d80: 18c00054 ori r3,r3,1 + 7d84: 10c00035 stwio r3,0(r2) + 7d88: 0005883a mov r2,zero + 7d8c: e037883a mov sp,fp + 7d90: df000017 ldw fp,0(sp) + 7d94: dec00104 addi sp,sp,4 + 7d98: f800283a ret + +00007d9c : + 7d9c: defffe04 addi sp,sp,-8 + 7da0: df000115 stw fp,4(sp) + 7da4: df000104 addi fp,sp,4 + 7da8: e13fff15 stw r4,-4(fp) + 7dac: e0bfff17 ldw r2,-4(fp) + 7db0: 10800317 ldw r2,12(r2) + 7db4: 10800204 addi r2,r2,8 + 7db8: e0ffff17 ldw r3,-4(fp) + 7dbc: 18c00317 ldw r3,12(r3) + 7dc0: 18c00204 addi r3,r3,8 + 7dc4: 19000037 ldwio r4,0(r3) + 7dc8: 00ffff84 movi r3,-2 + 7dcc: 20c6703a and r3,r4,r3 + 7dd0: 10c00035 stwio r3,0(r2) + 7dd4: 0001883a nop + 7dd8: e037883a mov sp,fp + 7ddc: df000017 ldw fp,0(sp) + 7de0: dec00104 addi sp,sp,4 + 7de4: f800283a ret + +00007de8 : + 7de8: defffd04 addi sp,sp,-12 + 7dec: df000215 stw fp,8(sp) + 7df0: df000204 addi fp,sp,8 + 7df4: e13fff15 stw r4,-4(fp) + 7df8: e17ffe15 stw r5,-8(fp) + 7dfc: e0bfff17 ldw r2,-4(fp) + 7e00: 10c00d17 ldw r3,52(r2) + 7e04: e0bffe17 ldw r2,-8(fp) + 7e08: 10c00015 stw r3,0(r2) + 7e0c: e0bfff17 ldw r2,-4(fp) + 7e10: 10800317 ldw r2,12(r2) + 7e14: 10800204 addi r2,r2,8 + 7e18: 10800037 ldwio r2,0(r2) + 7e1c: 1005d07a srai r2,r2,1 + 7e20: 1080004c andi r2,r2,1 + 7e24: 1007883a mov r3,r2 + 7e28: e0bffe17 ldw r2,-8(fp) + 7e2c: 10c00115 stw r3,4(r2) + 7e30: e0bfff17 ldw r2,-4(fp) + 7e34: 10800317 ldw r2,12(r2) + 7e38: 10800904 addi r2,r2,36 + 7e3c: 10800037 ldwio r2,0(r2) + 7e40: 1007883a mov r3,r2 + 7e44: e0bffe17 ldw r2,-8(fp) + 7e48: 10c0020d sth r3,8(r2) + 7e4c: e0bfff17 ldw r2,-4(fp) + 7e50: 10800317 ldw r2,12(r2) + 7e54: 10800804 addi r2,r2,32 + 7e58: 10800037 ldwio r2,0(r2) + 7e5c: 1007883a mov r3,r2 + 7e60: e0bffe17 ldw r2,-8(fp) + 7e64: 10c0028d sth r3,10(r2) + 7e68: e0bfff17 ldw r2,-4(fp) + 7e6c: 10800317 ldw r2,12(r2) + 7e70: 10800a04 addi r2,r2,40 + 7e74: 10800037 ldwio r2,0(r2) + 7e78: 1007883a mov r3,r2 + 7e7c: e0bffe17 ldw r2,-8(fp) + 7e80: 10c0030d sth r3,12(r2) + 7e84: 0001883a nop + 7e88: e037883a mov sp,fp + 7e8c: df000017 ldw fp,0(sp) + 7e90: dec00104 addi sp,sp,4 + 7e94: f800283a ret + +00007e98 : + 7e98: defffd04 addi sp,sp,-12 + 7e9c: df000215 stw fp,8(sp) + 7ea0: df000204 addi fp,sp,8 + 7ea4: e13fff15 stw r4,-4(fp) + 7ea8: e17ffe15 stw r5,-8(fp) + 7eac: e0bffe17 ldw r2,-8(fp) + 7eb0: 10c00017 ldw r3,0(r2) + 7eb4: e0bfff17 ldw r2,-4(fp) + 7eb8: 10c00d15 stw r3,52(r2) 7ebc: e0bfff17 ldw r2,-4(fp) - 7ec0: 1884703a and r2,r3,r2 - 7ec4: 1004c03a cmpne r2,r2,zero - 7ec8: 10803fcc andi r2,r2,255 - 7ecc: e037883a mov sp,fp - 7ed0: df000017 ldw fp,0(sp) - 7ed4: dec00104 addi sp,sp,4 - 7ed8: f800283a ret - -00007edc : - 7edc: defff504 addi sp,sp,-44 - 7ee0: dfc00a15 stw ra,40(sp) - 7ee4: df000915 stw fp,36(sp) - 7ee8: df000904 addi fp,sp,36 - 7eec: e13ffa15 stw r4,-24(fp) - 7ef0: e17ff915 stw r5,-28(fp) - 7ef4: e1bff815 stw r6,-32(fp) - 7ef8: e1fff715 stw r7,-36(fp) - 7efc: 00bffa84 movi r2,-22 - 7f00: e0bfff15 stw r2,-4(fp) - 7f04: e0bff917 ldw r2,-28(fp) - 7f08: e0bffe15 stw r2,-8(fp) - 7f0c: e0bffe17 ldw r2,-8(fp) - 7f10: 10800808 cmpgei r2,r2,32 - 7f14: 1000251e bne r2,zero,7fac - 7f18: 0005303a rdctl r2,status - 7f1c: e0bffc15 stw r2,-16(fp) - 7f20: e0fffc17 ldw r3,-16(fp) - 7f24: 00bfff84 movi r2,-2 - 7f28: 1884703a and r2,r3,r2 - 7f2c: 1001703a wrctl status,r2 - 7f30: e0bffc17 ldw r2,-16(fp) - 7f34: e0bffd15 stw r2,-12(fp) - 7f38: e0bffe17 ldw r2,-8(fp) - 7f3c: 100890fa slli r4,r2,3 - 7f40: e0fff817 ldw r3,-32(fp) - 7f44: 00800074 movhi r2,1 - 7f48: 2085883a add r2,r4,r2 - 7f4c: 10eb5815 stw r3,-21152(r2) - 7f50: e0bffe17 ldw r2,-8(fp) - 7f54: 100890fa slli r4,r2,3 - 7f58: e0fff717 ldw r3,-36(fp) - 7f5c: 00800074 movhi r2,1 - 7f60: 2085883a add r2,r4,r2 - 7f64: 10eb5915 stw r3,-21148(r2) - 7f68: e0bff817 ldw r2,-32(fp) - 7f6c: 10000526 beq r2,zero,7f84 - 7f70: e0bffe17 ldw r2,-8(fp) - 7f74: 100b883a mov r5,r2 - 7f78: e13ffa17 ldw r4,-24(fp) - 7f7c: 0007d640 call 7d64 - 7f80: 00000406 br 7f94 - 7f84: e0bffe17 ldw r2,-8(fp) - 7f88: 100b883a mov r5,r2 - 7f8c: e13ffa17 ldw r4,-24(fp) - 7f90: 0007df80 call 7df8 - 7f94: e0bfff15 stw r2,-4(fp) - 7f98: e0bffd17 ldw r2,-12(fp) - 7f9c: e0bffb15 stw r2,-20(fp) - 7fa0: e0bffb17 ldw r2,-20(fp) - 7fa4: 1001703a wrctl status,r2 - 7fa8: 0001883a nop - 7fac: e0bfff17 ldw r2,-4(fp) - 7fb0: e037883a mov sp,fp - 7fb4: dfc00117 ldw ra,4(sp) - 7fb8: df000017 ldw fp,0(sp) - 7fbc: dec00204 addi sp,sp,8 - 7fc0: f800283a ret - -00007fc4 : - 7fc4: defff904 addi sp,sp,-28 - 7fc8: dfc00615 stw ra,24(sp) - 7fcc: df000515 stw fp,20(sp) - 7fd0: df000504 addi fp,sp,20 - 7fd4: e13ffe15 stw r4,-8(fp) - 7fd8: e17ffd15 stw r5,-12(fp) - 7fdc: e1bffc15 stw r6,-16(fp) - 7fe0: e1fffb15 stw r7,-20(fp) - 7fe4: e1bffb17 ldw r6,-20(fp) - 7fe8: e17ffc17 ldw r5,-16(fp) - 7fec: e13ffd17 ldw r4,-12(fp) - 7ff0: 00081f40 call 81f4 - 7ff4: e0bfff15 stw r2,-4(fp) - 7ff8: e0bfff17 ldw r2,-4(fp) - 7ffc: 10001716 blt r2,zero,805c - 8000: e0bfff17 ldw r2,-4(fp) - 8004: 10c00324 muli r3,r2,12 - 8008: 00800074 movhi r2,1 - 800c: 1885883a add r2,r3,r2 - 8010: 10e60b17 ldw r3,-26580(r2) - 8014: e0bffe17 ldw r2,-8(fp) - 8018: 10c00015 stw r3,0(r2) - 801c: e0bfff17 ldw r2,-4(fp) - 8020: 10c00324 muli r3,r2,12 - 8024: 00800074 movhi r2,1 - 8028: 1885883a add r2,r3,r2 - 802c: 10e60c17 ldw r3,-26576(r2) - 8030: e0bffe17 ldw r2,-8(fp) - 8034: 10c00115 stw r3,4(r2) - 8038: e0bfff17 ldw r2,-4(fp) - 803c: 10c00324 muli r3,r2,12 - 8040: 00800074 movhi r2,1 - 8044: 1885883a add r2,r3,r2 - 8048: 10e60d17 ldw r3,-26572(r2) - 804c: e0bffe17 ldw r2,-8(fp) - 8050: 10c00215 stw r3,8(r2) - 8054: e13fff17 ldw r4,-4(fp) - 8058: 00085a80 call 85a8 - 805c: 0001883a nop - 8060: e037883a mov sp,fp - 8064: dfc00117 ldw ra,4(sp) - 8068: df000017 ldw fp,0(sp) - 806c: dec00204 addi sp,sp,8 - 8070: f800283a ret - -00008074 : - 8074: defffb04 addi sp,sp,-20 - 8078: dfc00415 stw ra,16(sp) - 807c: df000315 stw fp,12(sp) - 8080: df000304 addi fp,sp,12 - 8084: e13fff15 stw r4,-4(fp) - 8088: e17ffe15 stw r5,-8(fp) - 808c: e1bffd15 stw r6,-12(fp) - 8090: 01c07fc4 movi r7,511 - 8094: 01800044 movi r6,1 - 8098: e17fff17 ldw r5,-4(fp) - 809c: 01000074 movhi r4,1 - 80a0: 21260e04 addi r4,r4,-26568 - 80a4: 0007fc40 call 7fc4 - 80a8: 01c07fc4 movi r7,511 - 80ac: 000d883a mov r6,zero - 80b0: e17ffe17 ldw r5,-8(fp) - 80b4: 01000074 movhi r4,1 - 80b8: 21260b04 addi r4,r4,-26580 - 80bc: 0007fc40 call 7fc4 - 80c0: 01c07fc4 movi r7,511 - 80c4: 01800044 movi r6,1 - 80c8: e17ffd17 ldw r5,-12(fp) - 80cc: 01000074 movhi r4,1 - 80d0: 21261104 addi r4,r4,-26556 - 80d4: 0007fc40 call 7fc4 - 80d8: 0001883a nop - 80dc: e037883a mov sp,fp - 80e0: dfc00117 ldw ra,4(sp) - 80e4: df000017 ldw fp,0(sp) - 80e8: dec00204 addi sp,sp,8 - 80ec: f800283a ret - -000080f0 : - 80f0: defffe04 addi sp,sp,-8 - 80f4: dfc00115 stw ra,4(sp) - 80f8: df000015 stw fp,0(sp) - 80fc: d839883a mov fp,sp - 8100: 00800074 movhi r2,1 - 8104: 10a67917 ldw r2,-26140(r2) - 8108: 10000426 beq r2,zero,811c - 810c: 00800074 movhi r2,1 - 8110: 10a67917 ldw r2,-26140(r2) - 8114: 103ee83a callr r2 - 8118: 00000206 br 8124 - 811c: 00800074 movhi r2,1 - 8120: 10a74a04 addi r2,r2,-25304 - 8124: e037883a mov sp,fp - 8128: dfc00117 ldw ra,4(sp) + 7ec0: 10800317 ldw r2,12(r2) + 7ec4: 10c00204 addi r3,r2,8 + 7ec8: e0bfff17 ldw r2,-4(fp) + 7ecc: 10800317 ldw r2,12(r2) + 7ed0: 10800204 addi r2,r2,8 + 7ed4: 10800037 ldwio r2,0(r2) + 7ed8: 1009883a mov r4,r2 + 7edc: 00bfff44 movi r2,-3 + 7ee0: 2088703a and r4,r4,r2 + 7ee4: e0bffe17 ldw r2,-8(fp) + 7ee8: 10800117 ldw r2,4(r2) + 7eec: 1085883a add r2,r2,r2 + 7ef0: 1080008c andi r2,r2,2 + 7ef4: 2084b03a or r2,r4,r2 + 7ef8: 18800035 stwio r2,0(r3) + 7efc: e0bfff17 ldw r2,-4(fp) + 7f00: 10800317 ldw r2,12(r2) + 7f04: 10800904 addi r2,r2,36 + 7f08: e0fffe17 ldw r3,-8(fp) + 7f0c: 18c0020b ldhu r3,8(r3) + 7f10: 18ffffcc andi r3,r3,65535 + 7f14: 10c00035 stwio r3,0(r2) + 7f18: e0bfff17 ldw r2,-4(fp) + 7f1c: 10800317 ldw r2,12(r2) + 7f20: 10800804 addi r2,r2,32 + 7f24: e0fffe17 ldw r3,-8(fp) + 7f28: 18c0028b ldhu r3,10(r3) + 7f2c: 18ffffcc andi r3,r3,65535 + 7f30: 10c00035 stwio r3,0(r2) + 7f34: e0bfff17 ldw r2,-4(fp) + 7f38: 10800317 ldw r2,12(r2) + 7f3c: 10800a04 addi r2,r2,40 + 7f40: e0fffe17 ldw r3,-8(fp) + 7f44: 18c0030b ldhu r3,12(r3) + 7f48: 18ffffcc andi r3,r3,65535 + 7f4c: 10c00035 stwio r3,0(r2) + 7f50: 0001883a nop + 7f54: e037883a mov sp,fp + 7f58: df000017 ldw fp,0(sp) + 7f5c: dec00104 addi sp,sp,4 + 7f60: f800283a ret + +00007f64 : + 7f64: defffb04 addi sp,sp,-20 + 7f68: dfc00415 stw ra,16(sp) + 7f6c: df000315 stw fp,12(sp) + 7f70: df000304 addi fp,sp,12 + 7f74: e13fff15 stw r4,-4(fp) + 7f78: e17ffe15 stw r5,-8(fp) + 7f7c: e1bffd15 stw r6,-12(fp) + 7f80: e0bffe17 ldw r2,-8(fp) + 7f84: 1080028b ldhu r2,10(r2) + 7f88: 10bfffcc andi r2,r2,65535 + 7f8c: 10000426 beq r2,zero,7fa0 + 7f90: e0bffe17 ldw r2,-8(fp) + 7f94: 1080020b ldhu r2,8(r2) + 7f98: 10bfffcc andi r2,r2,65535 + 7f9c: 1000021e bne r2,zero,7fa8 + 7fa0: 00bfff44 movi r2,-3 + 7fa4: 00000f06 br 7fe4 + 7fa8: e0bfff17 ldw r2,-4(fp) + 7fac: 11000c17 ldw r4,48(r2) + 7fb0: e0bffe17 ldw r2,-8(fp) + 7fb4: 1080028b ldhu r2,10(r2) + 7fb8: 10ffffcc andi r3,r2,65535 + 7fbc: e0bffe17 ldw r2,-8(fp) + 7fc0: 1080020b ldhu r2,8(r2) + 7fc4: 10bfffcc andi r2,r2,65535 + 7fc8: 1885883a add r2,r3,r2 + 7fcc: 100b883a mov r5,r2 + 7fd0: 00044440 call 4444 <__udivsi3> + 7fd4: 1007883a mov r3,r2 + 7fd8: e0bffd17 ldw r2,-12(fp) + 7fdc: 10c00015 stw r3,0(r2) + 7fe0: 0005883a mov r2,zero + 7fe4: e037883a mov sp,fp + 7fe8: dfc00117 ldw ra,4(sp) + 7fec: df000017 ldw fp,0(sp) + 7ff0: dec00204 addi sp,sp,8 + 7ff4: f800283a ret + +00007ff8 : + 7ff8: defff904 addi sp,sp,-28 + 7ffc: dfc00615 stw ra,24(sp) + 8000: df000515 stw fp,20(sp) + 8004: df000504 addi fp,sp,20 + 8008: e13ffd15 stw r4,-12(fp) + 800c: e17ffc15 stw r5,-16(fp) + 8010: e1bffb15 stw r6,-20(fp) + 8014: e0fffb17 ldw r3,-20(fp) + 8018: 008001b4 movhi r2,6 + 801c: 1086a004 addi r2,r2,6784 + 8020: 10c00436 bltu r2,r3,8034 + 8024: e0bffb17 ldw r2,-20(fp) + 8028: 10000226 beq r2,zero,8034 + 802c: e0bffb17 ldw r2,-20(fp) + 8030: 1000021e bne r2,zero,803c + 8034: 00bfff04 movi r2,-4 + 8038: 00002906 br 80e0 + 803c: e0bffd17 ldw r2,-12(fp) + 8040: 10c00c17 ldw r3,48(r2) + 8044: e0bffb17 ldw r2,-20(fp) + 8048: 1085883a add r2,r2,r2 + 804c: 100b883a mov r5,r2 + 8050: 1809883a mov r4,r3 + 8054: 00044440 call 4444 <__udivsi3> + 8058: e0bfff15 stw r2,-4(fp) + 805c: e0bfff17 ldw r2,-4(fp) + 8060: 10800f04 addi r2,r2,60 + 8064: e0bffe15 stw r2,-8(fp) + 8068: e0bfff17 ldw r2,-4(fp) + 806c: 10bff104 addi r2,r2,-60 + 8070: e0bfff15 stw r2,-4(fp) + 8074: e0fffb17 ldw r3,-20(fp) + 8078: 008000b4 movhi r2,2 + 807c: 10a1a804 addi r2,r2,-31072 + 8080: 10c0042e bgeu r2,r3,8094 + 8084: e0bffc17 ldw r2,-16(fp) + 8088: 00c00044 movi r3,1 + 808c: 10c00115 stw r3,4(r2) + 8090: 00000206 br 809c + 8094: e0bffc17 ldw r2,-16(fp) + 8098: 10000115 stw zero,4(r2) + 809c: e0bfff17 ldw r2,-4(fp) + 80a0: 1007883a mov r3,r2 + 80a4: e0bffc17 ldw r2,-16(fp) + 80a8: 10c0028d sth r3,10(r2) + 80ac: e0bffe17 ldw r2,-8(fp) + 80b0: 1007883a mov r3,r2 + 80b4: e0bffc17 ldw r2,-16(fp) + 80b8: 10c0020d sth r3,8(r2) + 80bc: e0bfff17 ldw r2,-4(fp) + 80c0: 1007883a mov r3,r2 + 80c4: e0bfff17 ldw r2,-4(fp) + 80c8: 1004d07a srli r2,r2,1 + 80cc: 1885c83a sub r2,r3,r2 + 80d0: 1007883a mov r3,r2 + 80d4: e0bffc17 ldw r2,-16(fp) + 80d8: 10c0030d sth r3,12(r2) + 80dc: 0005883a mov r2,zero + 80e0: e037883a mov sp,fp + 80e4: dfc00117 ldw ra,4(sp) + 80e8: df000017 ldw fp,0(sp) + 80ec: dec00204 addi sp,sp,8 + 80f0: f800283a ret + +000080f4 : + 80f4: defffe04 addi sp,sp,-8 + 80f8: df000115 stw fp,4(sp) + 80fc: df000104 addi fp,sp,4 + 8100: e13fff15 stw r4,-4(fp) + 8104: e0bfff17 ldw r2,-4(fp) + 8108: 10800317 ldw r2,12(r2) + 810c: 10800504 addi r2,r2,20 + 8110: 10800037 ldwio r2,0(r2) + 8114: 1080004c andi r2,r2,1 + 8118: 10000226 beq r2,zero,8124 + 811c: 00800044 movi r2,1 + 8120: 00000106 br 8128 + 8124: 0005883a mov r2,zero + 8128: e037883a mov sp,fp 812c: df000017 ldw fp,0(sp) - 8130: dec00204 addi sp,sp,8 + 8130: dec00104 addi sp,sp,4 8134: f800283a ret -00008138 : - 8138: defffd04 addi sp,sp,-12 - 813c: df000215 stw fp,8(sp) - 8140: df000204 addi fp,sp,8 - 8144: e13ffe15 stw r4,-8(fp) - 8148: e0bffe17 ldw r2,-8(fp) - 814c: 10800217 ldw r2,8(r2) - 8150: 10d00034 orhi r3,r2,16384 - 8154: e0bffe17 ldw r2,-8(fp) - 8158: 10c00215 stw r3,8(r2) - 815c: e03fff15 stw zero,-4(fp) - 8160: 00001a06 br 81cc - 8164: e0bfff17 ldw r2,-4(fp) - 8168: 10c00324 muli r3,r2,12 - 816c: 00800074 movhi r2,1 - 8170: 1885883a add r2,r3,r2 - 8174: 10e60b17 ldw r3,-26580(r2) - 8178: e0bffe17 ldw r2,-8(fp) - 817c: 10800017 ldw r2,0(r2) - 8180: 18800f1e bne r3,r2,81c0 - 8184: e0bfff17 ldw r2,-4(fp) - 8188: 10c00324 muli r3,r2,12 - 818c: 00800074 movhi r2,1 - 8190: 1885883a add r2,r3,r2 - 8194: 10a60d17 ldw r2,-26572(r2) - 8198: 1000090e bge r2,zero,81c0 - 819c: e0bfff17 ldw r2,-4(fp) - 81a0: 10c00324 muli r3,r2,12 - 81a4: 00800074 movhi r2,1 - 81a8: 10a60b04 addi r2,r2,-26580 - 81ac: 1885883a add r2,r3,r2 - 81b0: e0fffe17 ldw r3,-8(fp) - 81b4: 18800226 beq r3,r2,81c0 - 81b8: 00bffcc4 movi r2,-13 - 81bc: 00000906 br 81e4 - 81c0: e0bfff17 ldw r2,-4(fp) - 81c4: 10800044 addi r2,r2,1 - 81c8: e0bfff15 stw r2,-4(fp) - 81cc: 00800074 movhi r2,1 - 81d0: 10a67817 ldw r2,-26144(r2) - 81d4: 1007883a mov r3,r2 - 81d8: e0bfff17 ldw r2,-4(fp) - 81dc: 18bfe12e bgeu r3,r2,8164 - 81e0: 0005883a mov r2,zero - 81e4: e037883a mov sp,fp - 81e8: df000017 ldw fp,0(sp) - 81ec: dec00104 addi sp,sp,4 - 81f0: f800283a ret - -000081f4 : - 81f4: defff604 addi sp,sp,-40 - 81f8: dfc00915 stw ra,36(sp) - 81fc: df000815 stw fp,32(sp) - 8200: df000804 addi fp,sp,32 - 8204: e13ffa15 stw r4,-24(fp) - 8208: e17ff915 stw r5,-28(fp) - 820c: e1bff815 stw r6,-32(fp) - 8210: 00bfffc4 movi r2,-1 - 8214: e0bffe15 stw r2,-8(fp) - 8218: 00bffb44 movi r2,-19 - 821c: e0bffd15 stw r2,-12(fp) - 8220: e03ffc15 stw zero,-16(fp) - 8224: 01400074 movhi r5,1 - 8228: 29667604 addi r5,r5,-26152 - 822c: e13ffa17 ldw r4,-24(fp) - 8230: 0007c500 call 7c50 - 8234: e0bfff15 stw r2,-4(fp) - 8238: e0bfff17 ldw r2,-4(fp) - 823c: 1000051e bne r2,zero,8254 - 8240: e13ffa17 ldw r4,-24(fp) - 8244: 00086240 call 8624 - 8248: e0bfff15 stw r2,-4(fp) - 824c: 00800044 movi r2,1 - 8250: e0bffc15 stw r2,-16(fp) - 8254: e0bfff17 ldw r2,-4(fp) - 8258: 10002926 beq r2,zero,8300 - 825c: e13fff17 ldw r4,-4(fp) - 8260: 00087340 call 8734 - 8264: e0bffe15 stw r2,-8(fp) - 8268: e0bffe17 ldw r2,-8(fp) - 826c: 1000030e bge r2,zero,827c - 8270: e0bffe17 ldw r2,-8(fp) - 8274: e0bffd15 stw r2,-12(fp) - 8278: 00002306 br 8308 - 827c: e0bffe17 ldw r2,-8(fp) - 8280: 10c00324 muli r3,r2,12 - 8284: 00800074 movhi r2,1 - 8288: 10a60b04 addi r2,r2,-26580 - 828c: 1885883a add r2,r3,r2 - 8290: e0bffb15 stw r2,-20(fp) - 8294: e0fff917 ldw r3,-28(fp) - 8298: 00900034 movhi r2,16384 - 829c: 10bfffc4 addi r2,r2,-1 - 82a0: 1886703a and r3,r3,r2 - 82a4: e0bffb17 ldw r2,-20(fp) - 82a8: 10c00215 stw r3,8(r2) - 82ac: e0bffc17 ldw r2,-16(fp) - 82b0: 1000051e bne r2,zero,82c8 - 82b4: e13ffb17 ldw r4,-20(fp) - 82b8: 00081380 call 8138 - 82bc: e0bffd15 stw r2,-12(fp) - 82c0: e0bffd17 ldw r2,-12(fp) - 82c4: 10001016 blt r2,zero,8308 - 82c8: e0bfff17 ldw r2,-4(fp) - 82cc: 10800317 ldw r2,12(r2) - 82d0: 10000826 beq r2,zero,82f4 - 82d4: e0bfff17 ldw r2,-4(fp) - 82d8: 10800317 ldw r2,12(r2) - 82dc: e1fff817 ldw r7,-32(fp) - 82e0: e1bff917 ldw r6,-28(fp) - 82e4: e17ffa17 ldw r5,-24(fp) - 82e8: e13ffb17 ldw r4,-20(fp) - 82ec: 103ee83a callr r2 - 82f0: 00000106 br 82f8 - 82f4: 0005883a mov r2,zero - 82f8: e0bffd15 stw r2,-12(fp) - 82fc: 00000206 br 8308 - 8300: 00bffb44 movi r2,-19 - 8304: e0bffd15 stw r2,-12(fp) - 8308: e0bffd17 ldw r2,-12(fp) - 830c: 1000090e bge r2,zero,8334 - 8310: e13ffe17 ldw r4,-8(fp) - 8314: 00085a80 call 85a8 - 8318: 00080f00 call 80f0 - 831c: 1007883a mov r3,r2 - 8320: e0bffd17 ldw r2,-12(fp) - 8324: 0085c83a sub r2,zero,r2 - 8328: 18800015 stw r2,0(r3) - 832c: 00bfffc4 movi r2,-1 - 8330: 00000106 br 8338 - 8334: e0bffe17 ldw r2,-8(fp) - 8338: e037883a mov sp,fp - 833c: dfc00117 ldw ra,4(sp) - 8340: df000017 ldw fp,0(sp) - 8344: dec00204 addi sp,sp,8 - 8348: f800283a ret - -0000834c : - 834c: defff204 addi sp,sp,-56 - 8350: dfc00a15 stw ra,40(sp) - 8354: df000915 stw fp,36(sp) - 8358: df000904 addi fp,sp,36 - 835c: e13ff715 stw r4,-36(fp) - 8360: e1400215 stw r5,8(fp) - 8364: e1800315 stw r6,12(fp) - 8368: e1c00415 stw r7,16(fp) - 836c: e0800204 addi r2,fp,8 - 8370: e0bff815 stw r2,-32(fp) - 8374: e0bff717 ldw r2,-36(fp) - 8378: e0bfff15 stw r2,-4(fp) - 837c: 00006f06 br 853c - 8380: e0bffec7 ldb r2,-5(fp) - 8384: 10800960 cmpeqi r2,r2,37 - 8388: 1000041e bne r2,zero,839c - 838c: e0bffec7 ldb r2,-5(fp) - 8390: 1009883a mov r4,r2 - 8394: 00085780 call 8578 - 8398: 00006806 br 853c - 839c: e0bfff17 ldw r2,-4(fp) - 83a0: 10c00044 addi r3,r2,1 - 83a4: e0ffff15 stw r3,-4(fp) - 83a8: 10800003 ldbu r2,0(r2) - 83ac: e0bffec5 stb r2,-5(fp) - 83b0: e0bffec7 ldb r2,-5(fp) - 83b4: 10006926 beq r2,zero,855c - 83b8: e0bffec7 ldb r2,-5(fp) - 83bc: 10800958 cmpnei r2,r2,37 - 83c0: 1000041e bne r2,zero,83d4 - 83c4: e0bffec7 ldb r2,-5(fp) - 83c8: 1009883a mov r4,r2 - 83cc: 00085780 call 8578 - 83d0: 00005a06 br 853c - 83d4: e0bffec7 ldb r2,-5(fp) - 83d8: 108018d8 cmpnei r2,r2,99 - 83dc: 1000081e bne r2,zero,8400 - 83e0: e0bff817 ldw r2,-32(fp) - 83e4: 10c00104 addi r3,r2,4 - 83e8: e0fff815 stw r3,-32(fp) - 83ec: 10800017 ldw r2,0(r2) - 83f0: e0bff915 stw r2,-28(fp) - 83f4: e13ff917 ldw r4,-28(fp) - 83f8: 00085780 call 8578 - 83fc: 00004f06 br 853c - 8400: e0bffec7 ldb r2,-5(fp) - 8404: 10801e18 cmpnei r2,r2,120 - 8408: 1000341e bne r2,zero,84dc - 840c: e0bff817 ldw r2,-32(fp) - 8410: 10c00104 addi r3,r2,4 - 8414: e0fff815 stw r3,-32(fp) - 8418: 10800017 ldw r2,0(r2) - 841c: e0bffb15 stw r2,-20(fp) - 8420: e0bffb17 ldw r2,-20(fp) - 8424: 1000031e bne r2,zero,8434 - 8428: 01000c04 movi r4,48 - 842c: 00085780 call 8578 - 8430: 00004206 br 853c - 8434: 00800704 movi r2,28 - 8438: e0bffd15 stw r2,-12(fp) - 843c: 00000306 br 844c - 8440: e0bffd17 ldw r2,-12(fp) - 8444: 10bfff04 addi r2,r2,-4 - 8448: e0bffd15 stw r2,-12(fp) - 844c: 00c003c4 movi r3,15 - 8450: e0bffd17 ldw r2,-12(fp) - 8454: 1884983a sll r2,r3,r2 - 8458: 1007883a mov r3,r2 - 845c: e0bffb17 ldw r2,-20(fp) - 8460: 1884703a and r2,r3,r2 - 8464: 103ff626 beq r2,zero,8440 - 8468: 00001906 br 84d0 - 846c: 00c003c4 movi r3,15 - 8470: e0bffd17 ldw r2,-12(fp) - 8474: 1884983a sll r2,r3,r2 - 8478: 1007883a mov r3,r2 - 847c: e0bffb17 ldw r2,-20(fp) - 8480: 1886703a and r3,r3,r2 - 8484: e0bffd17 ldw r2,-12(fp) - 8488: 1884d83a srl r2,r3,r2 - 848c: e0bffa15 stw r2,-24(fp) - 8490: e0bffa17 ldw r2,-24(fp) - 8494: 108002a8 cmpgeui r2,r2,10 - 8498: 1000041e bne r2,zero,84ac - 849c: e0bffa17 ldw r2,-24(fp) - 84a0: 10800c04 addi r2,r2,48 - 84a4: e0bffec5 stb r2,-5(fp) - 84a8: 00000306 br 84b8 - 84ac: e0bffa17 ldw r2,-24(fp) - 84b0: 108015c4 addi r2,r2,87 - 84b4: e0bffec5 stb r2,-5(fp) - 84b8: e0bffec7 ldb r2,-5(fp) - 84bc: 1009883a mov r4,r2 - 84c0: 00085780 call 8578 - 84c4: e0bffd17 ldw r2,-12(fp) - 84c8: 10bfff04 addi r2,r2,-4 - 84cc: e0bffd15 stw r2,-12(fp) - 84d0: e0bffd17 ldw r2,-12(fp) - 84d4: 103fe50e bge r2,zero,846c - 84d8: 00001806 br 853c - 84dc: e0bffec7 ldb r2,-5(fp) - 84e0: 10801cd8 cmpnei r2,r2,115 - 84e4: 1000151e bne r2,zero,853c - 84e8: e0bff817 ldw r2,-32(fp) - 84ec: 10c00104 addi r3,r2,4 - 84f0: e0fff815 stw r3,-32(fp) - 84f4: 10800017 ldw r2,0(r2) - 84f8: e0bffc15 stw r2,-16(fp) - 84fc: 00000906 br 8524 - 8500: e0bffc17 ldw r2,-16(fp) - 8504: 10c00044 addi r3,r2,1 - 8508: e0fffc15 stw r3,-16(fp) - 850c: 10800003 ldbu r2,0(r2) - 8510: 10803fcc andi r2,r2,255 - 8514: 1080201c xori r2,r2,128 - 8518: 10bfe004 addi r2,r2,-128 - 851c: 1009883a mov r4,r2 - 8520: 00085780 call 8578 - 8524: e0bffc17 ldw r2,-16(fp) - 8528: 10800003 ldbu r2,0(r2) - 852c: 10803fcc andi r2,r2,255 - 8530: 1080201c xori r2,r2,128 - 8534: 10bfe004 addi r2,r2,-128 - 8538: 103ff11e bne r2,zero,8500 - 853c: e0bfff17 ldw r2,-4(fp) - 8540: 10c00044 addi r3,r2,1 - 8544: e0ffff15 stw r3,-4(fp) - 8548: 10800003 ldbu r2,0(r2) - 854c: e0bffec5 stb r2,-5(fp) - 8550: e0bffec7 ldb r2,-5(fp) - 8554: 103f8a1e bne r2,zero,8380 - 8558: 00000106 br 8560 - 855c: 0001883a nop - 8560: 0001883a nop - 8564: e037883a mov sp,fp - 8568: dfc00117 ldw ra,4(sp) - 856c: df000017 ldw fp,0(sp) - 8570: dec00504 addi sp,sp,20 - 8574: f800283a ret - -00008578 : - 8578: defffd04 addi sp,sp,-12 - 857c: dfc00215 stw ra,8(sp) - 8580: df000115 stw fp,4(sp) - 8584: df000104 addi fp,sp,4 - 8588: e13fff15 stw r4,-4(fp) - 858c: e13fff17 ldw r4,-4(fp) - 8590: 0004b340 call 4b34 - 8594: e037883a mov sp,fp - 8598: dfc00117 ldw ra,4(sp) - 859c: df000017 ldw fp,0(sp) - 85a0: dec00204 addi sp,sp,8 - 85a4: f800283a ret - -000085a8 : - 85a8: defffe04 addi sp,sp,-8 - 85ac: df000115 stw fp,4(sp) - 85b0: df000104 addi fp,sp,4 - 85b4: e13fff15 stw r4,-4(fp) - 85b8: e0bfff17 ldw r2,-4(fp) - 85bc: 108000d0 cmplti r2,r2,3 - 85c0: 10000a1e bne r2,zero,85ec - 85c4: e0bfff17 ldw r2,-4(fp) - 85c8: 10c00324 muli r3,r2,12 - 85cc: 00800074 movhi r2,1 - 85d0: 1885883a add r2,r3,r2 - 85d4: 10260d15 stw zero,-26572(r2) - 85d8: e0bfff17 ldw r2,-4(fp) - 85dc: 10c00324 muli r3,r2,12 - 85e0: 00800074 movhi r2,1 - 85e4: 1885883a add r2,r3,r2 - 85e8: 10260b15 stw zero,-26580(r2) - 85ec: 0001883a nop - 85f0: e037883a mov sp,fp - 85f4: df000017 ldw fp,0(sp) - 85f8: dec00104 addi sp,sp,4 - 85fc: f800283a ret - -00008600 : - 8600: deffff04 addi sp,sp,-4 - 8604: df000015 stw fp,0(sp) - 8608: d839883a mov fp,sp - 860c: 000170fa wrctl ienable,zero - 8610: 0001883a nop - 8614: e037883a mov sp,fp - 8618: df000017 ldw fp,0(sp) - 861c: dec00104 addi sp,sp,4 - 8620: f800283a ret - -00008624 : - 8624: defffb04 addi sp,sp,-20 - 8628: dfc00415 stw ra,16(sp) - 862c: df000315 stw fp,12(sp) - 8630: df000304 addi fp,sp,12 - 8634: e13ffd15 stw r4,-12(fp) - 8638: 00800074 movhi r2,1 - 863c: 10a67417 ldw r2,-26160(r2) - 8640: e0bfff15 stw r2,-4(fp) - 8644: 00003106 br 870c - 8648: e0bfff17 ldw r2,-4(fp) - 864c: 10800217 ldw r2,8(r2) - 8650: 1009883a mov r4,r2 - 8654: 0004bdc0 call 4bdc - 8658: e0bffe15 stw r2,-8(fp) - 865c: e0bfff17 ldw r2,-4(fp) - 8660: 10c00217 ldw r3,8(r2) +00008138 : + 8138: defffb04 addi sp,sp,-20 + 813c: df000415 stw fp,16(sp) + 8140: df000404 addi fp,sp,16 + 8144: e13fff15 stw r4,-4(fp) + 8148: e17ffe15 stw r5,-8(fp) + 814c: e1bffd15 stw r6,-12(fp) + 8150: e1fffc15 stw r7,-16(fp) + 8154: e0bffc17 ldw r2,-16(fp) + 8158: 10000015 stw zero,0(r2) + 815c: 00001506 br 81b4 + 8160: e0bfff17 ldw r2,-4(fp) + 8164: 10800317 ldw r2,12(r2) + 8168: 10800104 addi r2,r2,4 + 816c: 11000037 ldwio r4,0(r2) + 8170: e0bffc17 ldw r2,-16(fp) + 8174: 10800017 ldw r2,0(r2) + 8178: e0fffe17 ldw r3,-8(fp) + 817c: 1885883a add r2,r3,r2 + 8180: 2007883a mov r3,r4 + 8184: 10c00005 stb r3,0(r2) + 8188: e0bffc17 ldw r2,-16(fp) + 818c: 10800017 ldw r2,0(r2) + 8190: 10c00044 addi r3,r2,1 + 8194: e0bffc17 ldw r2,-16(fp) + 8198: 10c00015 stw r3,0(r2) + 819c: e0bffc17 ldw r2,-16(fp) + 81a0: 10800017 ldw r2,0(r2) + 81a4: e0fffd17 ldw r3,-12(fp) + 81a8: 1880021e bne r3,r2,81b4 + 81ac: e0bffd17 ldw r2,-12(fp) + 81b0: 1000061e bne r2,zero,81cc + 81b4: e0bfff17 ldw r2,-4(fp) + 81b8: 10800317 ldw r2,12(r2) + 81bc: 10800704 addi r2,r2,28 + 81c0: 10800037 ldwio r2,0(r2) + 81c4: 103fe61e bne r2,zero,8160 + 81c8: 00000106 br 81d0 + 81cc: 0001883a nop + 81d0: 0001883a nop + 81d4: e037883a mov sp,fp + 81d8: df000017 ldw fp,0(sp) + 81dc: dec00104 addi sp,sp,4 + 81e0: f800283a ret + +000081e4 : + 81e4: defffa04 addi sp,sp,-24 + 81e8: dfc00515 stw ra,20(sp) + 81ec: df000415 stw fp,16(sp) + 81f0: df000404 addi fp,sp,16 + 81f4: e13ffd15 stw r4,-12(fp) + 81f8: e17ffc15 stw r5,-16(fp) + 81fc: e03fff15 stw zero,-4(fp) + 8200: 008000b4 movhi r2,2 + 8204: 10a1a804 addi r2,r2,-31072 + 8208: e0bffe15 stw r2,-8(fp) + 820c: 00000d06 br 8244 + 8210: e0bffe17 ldw r2,-8(fp) + 8214: 108002a8 cmpgeui r2,r2,10 + 8218: 1000021e bne r2,zero,8224 + 821c: 0109c404 movi r4,10000 + 8220: 00098e00 call 98e0 + 8224: e0bffe17 ldw r2,-8(fp) + 8228: 10bfffc4 addi r2,r2,-1 + 822c: e0bffe15 stw r2,-8(fp) + 8230: e0bffe17 ldw r2,-8(fp) + 8234: 1000031e bne r2,zero,8244 + 8238: 00bfff84 movi r2,-2 + 823c: e0bfff15 stw r2,-4(fp) + 8240: 00000506 br 8258 + 8244: e0bffd17 ldw r2,-12(fp) + 8248: 10800317 ldw r2,12(r2) + 824c: 10800704 addi r2,r2,28 + 8250: 10800037 ldwio r2,0(r2) + 8254: 103fee26 beq r2,zero,8210 + 8258: e0bffd17 ldw r2,-12(fp) + 825c: 10800317 ldw r2,12(r2) + 8260: 10800104 addi r2,r2,4 + 8264: 10800037 ldwio r2,0(r2) + 8268: 1007883a mov r3,r2 + 826c: e0bffc17 ldw r2,-16(fp) + 8270: 10c00005 stb r3,0(r2) + 8274: e0bfff17 ldw r2,-4(fp) + 8278: e037883a mov sp,fp + 827c: dfc00117 ldw ra,4(sp) + 8280: df000017 ldw fp,0(sp) + 8284: dec00204 addi sp,sp,8 + 8288: f800283a ret + +0000828c : + 828c: defff804 addi sp,sp,-32 + 8290: dfc00715 stw ra,28(sp) + 8294: df000615 stw fp,24(sp) + 8298: df000604 addi fp,sp,24 + 829c: e13ffd15 stw r4,-12(fp) + 82a0: 2805883a mov r2,r5 + 82a4: 3009883a mov r4,r6 + 82a8: 3807883a mov r3,r7 + 82ac: e0bffc05 stb r2,-16(fp) + 82b0: 2005883a mov r2,r4 + 82b4: e0bffb05 stb r2,-20(fp) + 82b8: 1805883a mov r2,r3 + 82bc: e0bffa05 stb r2,-24(fp) + 82c0: 0089c404 movi r2,10000 + 82c4: e0bfff15 stw r2,-4(fp) + 82c8: e03ffe15 stw zero,-8(fp) + 82cc: 00000c06 br 8300 + 82d0: e0bfff17 ldw r2,-4(fp) + 82d4: 108002a8 cmpgeui r2,r2,10 + 82d8: 1000021e bne r2,zero,82e4 + 82dc: 0109c404 movi r4,10000 + 82e0: 00098e00 call 98e0 + 82e4: e0bfff17 ldw r2,-4(fp) + 82e8: 10bfffc4 addi r2,r2,-1 + 82ec: e0bfff15 stw r2,-4(fp) + 82f0: e0bfff17 ldw r2,-4(fp) + 82f4: 1000021e bne r2,zero,8300 + 82f8: 00bfff84 movi r2,-2 + 82fc: 00001906 br 8364 + 8300: e0bffd17 ldw r2,-12(fp) + 8304: 10800317 ldw r2,12(r2) + 8308: 10800404 addi r2,r2,16 + 830c: 10800037 ldwio r2,0(r2) + 8310: 1080004c andi r2,r2,1 + 8314: 103fee26 beq r2,zero,82d0 + 8318: e0bffd17 ldw r2,-12(fp) + 831c: 10800317 ldw r2,12(r2) + 8320: e13ffc03 ldbu r4,-16(fp) + 8324: e0fffb03 ldbu r3,-20(fp) + 8328: 1806927a slli r3,r3,9 + 832c: 20c8b03a or r4,r4,r3 + 8330: e0fffa03 ldbu r3,-24(fp) + 8334: 1806923a slli r3,r3,8 + 8338: 20c6b03a or r3,r4,r3 + 833c: 10c00035 stwio r3,0(r2) + 8340: e0bffe04 addi r2,fp,-8 + 8344: 100b883a mov r5,r2 + 8348: e13ffd17 ldw r4,-12(fp) + 834c: 00084d40 call 84d4 + 8350: e0bffe04 addi r2,fp,-8 + 8354: 100b883a mov r5,r2 + 8358: e13ffd17 ldw r4,-12(fp) + 835c: 00085200 call 8520 + 8360: e0bffe17 ldw r2,-8(fp) + 8364: e037883a mov sp,fp + 8368: dfc00117 ldw ra,4(sp) + 836c: df000017 ldw fp,0(sp) + 8370: dec00204 addi sp,sp,8 + 8374: f800283a ret + +00008378 : + 8378: defffa04 addi sp,sp,-24 + 837c: dfc00515 stw ra,20(sp) + 8380: df000415 stw fp,16(sp) + 8384: df000404 addi fp,sp,16 + 8388: e13ffe15 stw r4,-8(fp) + 838c: e17ffd15 stw r5,-12(fp) + 8390: 3005883a mov r2,r6 + 8394: e0bffc05 stb r2,-16(fp) + 8398: e0bffe17 ldw r2,-8(fp) + 839c: 10800d17 ldw r2,52(r2) + 83a0: 10800058 cmpnei r2,r2,1 + 83a4: 10001c1e bne r2,zero,8418 + 83a8: e0bffe17 ldw r2,-8(fp) + 83ac: 10800917 ldw r2,36(r2) + 83b0: 1004d1fa srli r2,r2,7 + 83b4: 1080038c andi r2,r2,14 + 83b8: 1007883a mov r3,r2 + 83bc: e0bffd17 ldw r2,-12(fp) + 83c0: 1884b03a or r2,r3,r2 + 83c4: 1007883a mov r3,r2 + 83c8: 00bffc04 movi r2,-16 + 83cc: 1884b03a or r2,r3,r2 + 83d0: 10803fcc andi r2,r2,255 + 83d4: e0fffc03 ldbu r3,-16(fp) + 83d8: 000f883a mov r7,zero + 83dc: 180d883a mov r6,r3 + 83e0: 100b883a mov r5,r2 + 83e4: e13ffe17 ldw r4,-8(fp) + 83e8: 000828c0 call 828c + 83ec: e0bfff15 stw r2,-4(fp) + 83f0: e0bffe17 ldw r2,-8(fp) + 83f4: 10800917 ldw r2,36(r2) + 83f8: 10803fcc andi r2,r2,255 + 83fc: 000f883a mov r7,zero + 8400: 000d883a mov r6,zero + 8404: 100b883a mov r5,r2 + 8408: e13ffe17 ldw r4,-8(fp) + 840c: 000828c0 call 828c + 8410: e0bfff15 stw r2,-4(fp) + 8414: 00000e06 br 8450 + 8418: e0bffe17 ldw r2,-8(fp) + 841c: 10800917 ldw r2,36(r2) + 8420: 1085883a add r2,r2,r2 + 8424: 1007883a mov r3,r2 + 8428: e0bffd17 ldw r2,-12(fp) + 842c: 1884b03a or r2,r3,r2 + 8430: 10803fcc andi r2,r2,255 + 8434: e0fffc03 ldbu r3,-16(fp) + 8438: 000f883a mov r7,zero + 843c: 180d883a mov r6,r3 + 8440: 100b883a mov r5,r2 + 8444: e13ffe17 ldw r4,-8(fp) + 8448: 000828c0 call 828c + 844c: e0bfff15 stw r2,-4(fp) + 8450: e0bfff17 ldw r2,-4(fp) + 8454: e037883a mov sp,fp + 8458: dfc00117 ldw ra,4(sp) + 845c: df000017 ldw fp,0(sp) + 8460: dec00204 addi sp,sp,8 + 8464: f800283a ret + +00008468 : + 8468: defffd04 addi sp,sp,-12 + 846c: df000215 stw fp,8(sp) + 8470: df000204 addi fp,sp,8 + 8474: e13fff15 stw r4,-4(fp) + 8478: e17ffe15 stw r5,-8(fp) + 847c: e0bfff17 ldw r2,-4(fp) + 8480: 10c00917 ldw r3,36(r2) + 8484: e0bffe17 ldw r2,-8(fp) + 8488: 10c00015 stw r3,0(r2) + 848c: 0001883a nop + 8490: e037883a mov sp,fp + 8494: df000017 ldw fp,0(sp) + 8498: dec00104 addi sp,sp,4 + 849c: f800283a ret + +000084a0 : + 84a0: defffd04 addi sp,sp,-12 + 84a4: df000215 stw fp,8(sp) + 84a8: df000204 addi fp,sp,8 + 84ac: e13fff15 stw r4,-4(fp) + 84b0: e17ffe15 stw r5,-8(fp) + 84b4: e0bfff17 ldw r2,-4(fp) + 84b8: e0fffe17 ldw r3,-8(fp) + 84bc: 10c00915 stw r3,36(r2) + 84c0: 0001883a nop + 84c4: e037883a mov sp,fp + 84c8: df000017 ldw fp,0(sp) + 84cc: dec00104 addi sp,sp,4 + 84d0: f800283a ret + +000084d4 : + 84d4: defffd04 addi sp,sp,-12 + 84d8: df000215 stw fp,8(sp) + 84dc: df000204 addi fp,sp,8 + 84e0: e13fff15 stw r4,-4(fp) + 84e4: e17ffe15 stw r5,-8(fp) + 84e8: e0bfff17 ldw r2,-4(fp) + 84ec: 10800317 ldw r2,12(r2) + 84f0: 10800404 addi r2,r2,16 + 84f4: 10800037 ldwio r2,0(r2) + 84f8: 1080010c andi r2,r2,4 + 84fc: 10000326 beq r2,zero,850c + 8500: e0bffe17 ldw r2,-8(fp) + 8504: 00fffec4 movi r3,-5 + 8508: 10c00015 stw r3,0(r2) + 850c: 0001883a nop + 8510: e037883a mov sp,fp + 8514: df000017 ldw fp,0(sp) + 8518: dec00104 addi sp,sp,4 + 851c: f800283a ret + +00008520 : + 8520: defffd04 addi sp,sp,-12 + 8524: df000215 stw fp,8(sp) + 8528: df000204 addi fp,sp,8 + 852c: e13fff15 stw r4,-4(fp) + 8530: e17ffe15 stw r5,-8(fp) + 8534: e0bfff17 ldw r2,-4(fp) + 8538: 10800317 ldw r2,12(r2) + 853c: 10800404 addi r2,r2,16 + 8540: 10800037 ldwio r2,0(r2) + 8544: 1080020c andi r2,r2,8 + 8548: 10000326 beq r2,zero,8558 + 854c: e0bffe17 ldw r2,-8(fp) + 8550: 00fffe84 movi r3,-6 + 8554: 10c00015 stw r3,0(r2) + 8558: 0001883a nop + 855c: e037883a mov sp,fp + 8560: df000017 ldw fp,0(sp) + 8564: dec00104 addi sp,sp,4 + 8568: f800283a ret + +0000856c : + 856c: defff804 addi sp,sp,-32 + 8570: dfc00715 stw ra,28(sp) + 8574: df000615 stw fp,24(sp) + 8578: df000604 addi fp,sp,24 + 857c: e13ffa15 stw r4,-24(fp) + 8580: e03ffd15 stw zero,-12(fp) + 8584: e0bffa17 ldw r2,-24(fp) + 8588: 10800717 ldw r2,28(r2) + 858c: e0bffe15 stw r2,-8(fp) + 8590: e0bffe17 ldw r2,-8(fp) + 8594: 10800117 ldw r2,4(r2) + 8598: 10800044 addi r2,r2,1 + 859c: 1089c424 muli r2,r2,10000 + 85a0: e0bfff15 stw r2,-4(fp) + 85a4: e0bffc04 addi r2,fp,-16 + 85a8: 100b883a mov r5,r2 + 85ac: e13ffa17 ldw r4,-24(fp) + 85b0: 00093f40 call 93f4 + 85b4: e0bffc17 ldw r2,-16(fp) + 85b8: 100b883a mov r5,r2 + 85bc: e13ffa17 ldw r4,-24(fp) + 85c0: 00093200 call 9320 + 85c4: e0bffd04 addi r2,fp,-12 + 85c8: 100b883a mov r5,r2 + 85cc: e13ffa17 ldw r4,-24(fp) + 85d0: 00084d40 call 84d4 + 85d4: e0bffd17 ldw r2,-12(fp) + 85d8: 10002226 beq r2,zero,8664 + 85dc: e0bffe17 ldw r2,-8(fp) + 85e0: 10800217 ldw r2,8(r2) + 85e4: 10001d26 beq r2,zero,865c + 85e8: 00000d06 br 8620 + 85ec: e0bfff17 ldw r2,-4(fp) + 85f0: 108002a8 cmpgeui r2,r2,10 + 85f4: 1000021e bne r2,zero,8600 + 85f8: 0109c404 movi r4,10000 + 85fc: 00098e00 call 98e0 + 8600: e0bfff17 ldw r2,-4(fp) + 8604: 10bfffc4 addi r2,r2,-1 + 8608: e0bfff15 stw r2,-4(fp) + 860c: e0bfff17 ldw r2,-4(fp) + 8610: 1000031e bne r2,zero,8620 + 8614: 00bfff84 movi r2,-2 + 8618: e0bffd15 stw r2,-12(fp) + 861c: 00000306 br 862c + 8620: e13ffa17 ldw r4,-24(fp) + 8624: 00080f40 call 80f4 + 8628: 103ff01e bne r2,zero,85ec + 862c: e0bffe17 ldw r2,-8(fp) + 8630: 10800017 ldw r2,0(r2) + 8634: e0fffb04 addi r3,fp,-20 + 8638: 180f883a mov r7,r3 + 863c: 000d883a mov r6,zero + 8640: 100b883a mov r5,r2 + 8644: e13ffa17 ldw r4,-24(fp) + 8648: 00081380 call 8138 + 864c: e13ffa17 ldw r4,-24(fp) + 8650: 0007d9c0 call 7d9c + 8654: e0bffe17 ldw r2,-8(fp) + 8658: 10000215 stw zero,8(r2) + 865c: e0bffd17 ldw r2,-12(fp) + 8660: 00000a06 br 868c 8664: e0bffe17 ldw r2,-8(fp) - 8668: 10bfffc4 addi r2,r2,-1 - 866c: 1885883a add r2,r3,r2 - 8670: 10800003 ldbu r2,0(r2) - 8674: 10803fcc andi r2,r2,255 - 8678: 1080201c xori r2,r2,128 - 867c: 10bfe004 addi r2,r2,-128 - 8680: 10800bd8 cmpnei r2,r2,47 - 8684: 1000031e bne r2,zero,8694 - 8688: e0bffe17 ldw r2,-8(fp) - 868c: 10bfffc4 addi r2,r2,-1 - 8690: e0bffe15 stw r2,-8(fp) - 8694: e0bffe17 ldw r2,-8(fp) - 8698: e0fffd17 ldw r3,-12(fp) - 869c: 1885883a add r2,r3,r2 - 86a0: 10800003 ldbu r2,0(r2) - 86a4: 10803fcc andi r2,r2,255 - 86a8: 1080201c xori r2,r2,128 - 86ac: 10bfe004 addi r2,r2,-128 - 86b0: 10800be0 cmpeqi r2,r2,47 - 86b4: 1000081e bne r2,zero,86d8 - 86b8: e0bffe17 ldw r2,-8(fp) - 86bc: e0fffd17 ldw r3,-12(fp) - 86c0: 1885883a add r2,r3,r2 - 86c4: 10800003 ldbu r2,0(r2) - 86c8: 10803fcc andi r2,r2,255 - 86cc: 1080201c xori r2,r2,128 - 86d0: 10bfe004 addi r2,r2,-128 - 86d4: 10000a1e bne r2,zero,8700 - 86d8: e0bfff17 ldw r2,-4(fp) - 86dc: 10800217 ldw r2,8(r2) - 86e0: e0fffe17 ldw r3,-8(fp) - 86e4: 180d883a mov r6,r3 - 86e8: e17ffd17 ldw r5,-12(fp) - 86ec: 1009883a mov r4,r2 - 86f0: 00089380 call 8938 - 86f4: 1000021e bne r2,zero,8700 - 86f8: e0bfff17 ldw r2,-4(fp) - 86fc: 00000806 br 8720 - 8700: e0bfff17 ldw r2,-4(fp) - 8704: 10800017 ldw r2,0(r2) + 8668: 10800217 ldw r2,8(r2) + 866c: 10000626 beq r2,zero,8688 + 8670: e0bffc17 ldw r2,-16(fp) + 8674: 100b883a mov r5,r2 + 8678: e13ffa17 ldw r4,-24(fp) + 867c: 000938c0 call 938c + 8680: 00bffe44 movi r2,-7 + 8684: 00000106 br 868c + 8688: 0005883a mov r2,zero + 868c: e037883a mov sp,fp + 8690: dfc00117 ldw ra,4(sp) + 8694: df000017 ldw fp,0(sp) + 8698: dec00204 addi sp,sp,8 + 869c: f800283a ret + +000086a0 : + 86a0: defff704 addi sp,sp,-36 + 86a4: dfc00815 stw ra,32(sp) + 86a8: df000715 stw fp,28(sp) + 86ac: df000704 addi fp,sp,28 + 86b0: e13ffd15 stw r4,-12(fp) + 86b4: e17ffc15 stw r5,-16(fp) + 86b8: e1bffb15 stw r6,-20(fp) + 86bc: 3805883a mov r2,r7 + 86c0: e0bffa05 stb r2,-24(fp) + 86c4: 0089c404 movi r2,10000 + 86c8: e0bffe15 stw r2,-8(fp) + 86cc: 00002206 br 8758 + 86d0: e0bffe17 ldw r2,-8(fp) + 86d4: 108002a8 cmpgeui r2,r2,10 + 86d8: 1000021e bne r2,zero,86e4 + 86dc: 0109c404 movi r4,10000 + 86e0: 00098e00 call 98e0 + 86e4: e0bffa03 ldbu r2,-24(fp) + 86e8: 10000926 beq r2,zero,8710 + 86ec: 00800044 movi r2,1 + 86f0: d8800015 stw r2,0(sp) + 86f4: 000f883a mov r7,zero + 86f8: e1bffb17 ldw r6,-20(fp) + 86fc: e17ffc17 ldw r5,-16(fp) + 8700: e13ffd17 ldw r4,-12(fp) + 8704: 0008c480 call 8c48 8708: e0bfff15 stw r2,-4(fp) - 870c: e0ffff17 ldw r3,-4(fp) - 8710: 00800074 movhi r2,1 - 8714: 10a67404 addi r2,r2,-26160 - 8718: 18bfcb1e bne r3,r2,8648 - 871c: 0005883a mov r2,zero - 8720: e037883a mov sp,fp - 8724: dfc00117 ldw ra,4(sp) - 8728: df000017 ldw fp,0(sp) - 872c: dec00204 addi sp,sp,8 - 8730: f800283a ret - -00008734 : - 8734: defffc04 addi sp,sp,-16 - 8738: df000315 stw fp,12(sp) - 873c: df000304 addi fp,sp,12 - 8740: e13ffd15 stw r4,-12(fp) - 8744: 00bffa04 movi r2,-24 - 8748: e0bffe15 stw r2,-8(fp) - 874c: e03fff15 stw zero,-4(fp) - 8750: 00001906 br 87b8 - 8754: e0bfff17 ldw r2,-4(fp) - 8758: 10c00324 muli r3,r2,12 - 875c: 00800074 movhi r2,1 - 8760: 1885883a add r2,r3,r2 - 8764: 10a60b17 ldw r2,-26580(r2) - 8768: 1000101e bne r2,zero,87ac - 876c: e0bfff17 ldw r2,-4(fp) - 8770: 11000324 muli r4,r2,12 - 8774: e0fffd17 ldw r3,-12(fp) - 8778: 00800074 movhi r2,1 - 877c: 2085883a add r2,r4,r2 - 8780: 10e60b15 stw r3,-26580(r2) - 8784: 00800074 movhi r2,1 - 8788: 10e67817 ldw r3,-26144(r2) - 878c: e0bfff17 ldw r2,-4(fp) - 8790: 1880030e bge r3,r2,87a0 - 8794: e0ffff17 ldw r3,-4(fp) - 8798: 00800074 movhi r2,1 - 879c: 10e67815 stw r3,-26144(r2) - 87a0: e0bfff17 ldw r2,-4(fp) - 87a4: e0bffe15 stw r2,-8(fp) - 87a8: 00000706 br 87c8 - 87ac: e0bfff17 ldw r2,-4(fp) - 87b0: 10800044 addi r2,r2,1 - 87b4: e0bfff15 stw r2,-4(fp) - 87b8: e0bfff17 ldw r2,-4(fp) - 87bc: 10800810 cmplti r2,r2,32 - 87c0: 103fe41e bne r2,zero,8754 - 87c4: 0001883a nop - 87c8: e0bffe17 ldw r2,-8(fp) - 87cc: e037883a mov sp,fp - 87d0: df000017 ldw fp,0(sp) - 87d4: dec00104 addi sp,sp,4 - 87d8: f800283a ret - -000087dc : - 87dc: defffb04 addi sp,sp,-20 - 87e0: df000415 stw fp,16(sp) - 87e4: df000404 addi fp,sp,16 - 87e8: e13ffd15 stw r4,-12(fp) - 87ec: e17ffc15 stw r5,-16(fp) - 87f0: e0bffc17 ldw r2,-16(fp) - 87f4: 10840070 cmpltui r2,r2,4097 - 87f8: 1000021e bne r2,zero,8804 - 87fc: 00840004 movi r2,4096 - 8800: e0bffc15 stw r2,-16(fp) - 8804: e0fffd17 ldw r3,-12(fp) - 8808: e0bffc17 ldw r2,-16(fp) - 880c: 1885883a add r2,r3,r2 - 8810: e0bffe15 stw r2,-8(fp) - 8814: e0bffd17 ldw r2,-12(fp) - 8818: e0bfff15 stw r2,-4(fp) - 881c: 00000506 br 8834 - 8820: e0bfff17 ldw r2,-4(fp) - 8824: 1000603a flushi r2 - 8828: e0bfff17 ldw r2,-4(fp) - 882c: 10800804 addi r2,r2,32 - 8830: e0bfff15 stw r2,-4(fp) - 8834: e0ffff17 ldw r3,-4(fp) - 8838: e0bffe17 ldw r2,-8(fp) - 883c: 18bff836 bltu r3,r2,8820 - 8840: e0bffd17 ldw r2,-12(fp) - 8844: 108007cc andi r2,r2,31 - 8848: 10000226 beq r2,zero,8854 - 884c: e0bfff17 ldw r2,-4(fp) - 8850: 1000603a flushi r2 - 8854: 0000203a flushp - 8858: 0001883a nop - 885c: e037883a mov sp,fp - 8860: df000017 ldw fp,0(sp) - 8864: dec00104 addi sp,sp,4 - 8868: f800283a ret - -0000886c : - 886c: defffe04 addi sp,sp,-8 - 8870: df000115 stw fp,4(sp) - 8874: df000104 addi fp,sp,4 - 8878: e13fff15 stw r4,-4(fp) + 870c: 00000806 br 8730 + 8710: 00800044 movi r2,1 + 8714: d8800015 stw r2,0(sp) + 8718: 000f883a mov r7,zero + 871c: e1bffb17 ldw r6,-20(fp) + 8720: e17ffc17 ldw r5,-16(fp) + 8724: e13ffd17 ldw r4,-12(fp) + 8728: 0008a8c0 call 8a8c + 872c: e0bfff15 stw r2,-4(fp) + 8730: e0bfff17 ldw r2,-4(fp) + 8734: 10bffea0 cmpeqi r2,r2,-6 + 8738: 1000061e bne r2,zero,8754 + 873c: e0bfff17 ldw r2,-4(fp) + 8740: 10bffee0 cmpeqi r2,r2,-5 + 8744: 1000031e bne r2,zero,8754 + 8748: e0bfff17 ldw r2,-4(fp) + 874c: 10bffe58 cmpnei r2,r2,-7 + 8750: 1000061e bne r2,zero,876c + 8754: 0001883a nop + 8758: e0bffe17 ldw r2,-8(fp) + 875c: 10ffffc4 addi r3,r2,-1 + 8760: e0fffe15 stw r3,-8(fp) + 8764: 103fda1e bne r2,zero,86d0 + 8768: 00000106 br 8770 + 876c: 0001883a nop + 8770: e0bfff17 ldw r2,-4(fp) + 8774: e037883a mov sp,fp + 8778: dfc00117 ldw ra,4(sp) + 877c: df000017 ldw fp,0(sp) + 8780: dec00204 addi sp,sp,8 + 8784: f800283a ret + +00008788 : + 8788: defff704 addi sp,sp,-36 + 878c: dfc00815 stw ra,32(sp) + 8790: df000715 stw fp,28(sp) + 8794: df000704 addi fp,sp,28 + 8798: e13ffd15 stw r4,-12(fp) + 879c: e17ffc15 stw r5,-16(fp) + 87a0: e1bffb15 stw r6,-20(fp) + 87a4: 3805883a mov r2,r7 + 87a8: e0bffa05 stb r2,-24(fp) + 87ac: 0089c404 movi r2,10000 + 87b0: e0bffe15 stw r2,-8(fp) + 87b4: e0bffa03 ldbu r2,-24(fp) + 87b8: 10003426 beq r2,zero,888c + 87bc: 00001706 br 881c + 87c0: e0bffe17 ldw r2,-8(fp) + 87c4: 108002a8 cmpgeui r2,r2,10 + 87c8: 1000021e bne r2,zero,87d4 + 87cc: 0109c404 movi r4,10000 + 87d0: 00098e00 call 98e0 + 87d4: 00800044 movi r2,1 + 87d8: d8800015 stw r2,0(sp) + 87dc: 000f883a mov r7,zero + 87e0: e1bffb17 ldw r6,-20(fp) + 87e4: e17ffc17 ldw r5,-16(fp) + 87e8: e13ffd17 ldw r4,-12(fp) + 87ec: 000905c0 call 905c + 87f0: e0bfff15 stw r2,-4(fp) + 87f4: e0bfff17 ldw r2,-4(fp) + 87f8: 10bffea0 cmpeqi r2,r2,-6 + 87fc: 1000061e bne r2,zero,8818 + 8800: e0bfff17 ldw r2,-4(fp) + 8804: 10bffee0 cmpeqi r2,r2,-5 + 8808: 1000031e bne r2,zero,8818 + 880c: e0bfff17 ldw r2,-4(fp) + 8810: 10bffe58 cmpnei r2,r2,-7 + 8814: 1000221e bne r2,zero,88a0 + 8818: 0001883a nop + 881c: e0bffe17 ldw r2,-8(fp) + 8820: 10ffffc4 addi r3,r2,-1 + 8824: e0fffe15 stw r3,-8(fp) + 8828: 103fe51e bne r2,zero,87c0 + 882c: 00001f06 br 88ac + 8830: e0bffe17 ldw r2,-8(fp) + 8834: 108002a8 cmpgeui r2,r2,10 + 8838: 1000021e bne r2,zero,8844 + 883c: 0109c404 movi r4,10000 + 8840: 00098e00 call 98e0 + 8844: 00800044 movi r2,1 + 8848: d8800015 stw r2,0(sp) + 884c: 000f883a mov r7,zero + 8850: e1bffb17 ldw r6,-20(fp) + 8854: e17ffc17 ldw r5,-16(fp) + 8858: e13ffd17 ldw r4,-12(fp) + 885c: 0008e500 call 8e50 + 8860: e0bfff15 stw r2,-4(fp) + 8864: e0bfff17 ldw r2,-4(fp) + 8868: 10bffea0 cmpeqi r2,r2,-6 + 886c: 1000061e bne r2,zero,8888 + 8870: e0bfff17 ldw r2,-4(fp) + 8874: 10bffee0 cmpeqi r2,r2,-5 + 8878: 1000031e bne r2,zero,8888 887c: e0bfff17 ldw r2,-4(fp) - 8880: 10bffe84 addi r2,r2,-6 - 8884: 10c00428 cmpgeui r3,r2,16 - 8888: 1800191e bne r3,zero,88f0 - 888c: 100690ba slli r3,r2,2 - 8890: 00800074 movhi r2,1 - 8894: 1885883a add r2,r3,r2 - 8898: 10a22817 ldw r2,-30560(r2) - 889c: 1000683a jmp r2 - 88a0: 000088e0 cmpeqi zero,zero,547 - 88a4: 000088e0 cmpeqi zero,zero,547 - 88a8: 000088f0 cmpltui zero,zero,547 - 88ac: 000088f0 cmpltui zero,zero,547 - 88b0: 000088f0 cmpltui zero,zero,547 - 88b4: 000088e0 cmpeqi zero,zero,547 - 88b8: 000088e8 cmpgeui zero,zero,547 - 88bc: 000088f0 cmpltui zero,zero,547 - 88c0: 000088e0 cmpeqi zero,zero,547 - 88c4: 000088e0 cmpeqi zero,zero,547 - 88c8: 000088f0 cmpltui zero,zero,547 - 88cc: 000088e0 cmpeqi zero,zero,547 - 88d0: 000088e8 cmpgeui zero,zero,547 - 88d4: 000088f0 cmpltui zero,zero,547 - 88d8: 000088f0 cmpltui zero,zero,547 - 88dc: 000088e0 cmpeqi zero,zero,547 - 88e0: 00800044 movi r2,1 - 88e4: 00000306 br 88f4 - 88e8: 0005883a mov r2,zero - 88ec: 00000106 br 88f4 - 88f0: 0005883a mov r2,zero - 88f4: e037883a mov sp,fp - 88f8: df000017 ldw fp,0(sp) - 88fc: dec00104 addi sp,sp,4 - 8900: f800283a ret - -00008904 : - 8904: 200b883a mov r5,r4 - 8908: 000f883a mov r7,zero - 890c: 000d883a mov r6,zero - 8910: 0009883a mov r4,zero - 8914: 00089681 jmpi 8968 <__register_exitproc> - -00008918 : - 8918: defffe04 addi sp,sp,-8 - 891c: 000b883a mov r5,zero - 8920: dc000015 stw r16,0(sp) - 8924: dfc00115 stw ra,4(sp) - 8928: 2021883a mov r16,r4 - 892c: 0008a840 call 8a84 <__call_exitprocs> - 8930: 8009883a mov r4,r16 - 8934: 0008bb00 call 8bb0 <_exit> - -00008938 : - 8938: 0007883a mov r3,zero - 893c: 30c0021e bne r6,r3,8948 - 8940: 0005883a mov r2,zero - 8944: f800283a ret - 8948: 20c5883a add r2,r4,r3 - 894c: 18c00044 addi r3,r3,1 - 8950: 28cf883a add r7,r5,r3 - 8954: 10800003 ldbu r2,0(r2) - 8958: 39ffffc3 ldbu r7,-1(r7) - 895c: 11fff726 beq r2,r7,893c - 8960: 11c5c83a sub r2,r2,r7 - 8964: f800283a ret - -00008968 <__register_exitproc>: - 8968: 00800074 movhi r2,1 - 896c: 10a66e17 ldw r2,-26184(r2) - 8970: defff904 addi sp,sp,-28 - 8974: dc000015 stw r16,0(sp) - 8978: 14000d17 ldw r16,52(r2) - 897c: dd400515 stw r21,20(sp) - 8980: dd000415 stw r20,16(sp) - 8984: dcc00315 stw r19,12(sp) - 8988: dc800215 stw r18,8(sp) - 898c: dfc00615 stw ra,24(sp) - 8990: dc400115 stw r17,4(sp) - 8994: 2025883a mov r18,r4 - 8998: 2827883a mov r19,r5 - 899c: 302b883a mov r21,r6 - 89a0: 3829883a mov r20,r7 - 89a4: 8000081e bne r16,zero,89c8 <__register_exitproc+0x60> - 89a8: 14000e04 addi r16,r2,56 - 89ac: 00c00034 movhi r3,0 - 89b0: 14000d15 stw r16,52(r2) - 89b4: 18c00004 addi r3,r3,0 - 89b8: 18000326 beq r3,zero,89c8 <__register_exitproc+0x60> - 89bc: 00c00034 movhi r3,0 - 89c0: 18c00017 ldw r3,0(r3) - 89c4: 10c03015 stw r3,192(r2) - 89c8: 84400117 ldw r17,4(r16) - 89cc: 88800810 cmplti r2,r17,32 - 89d0: 10000a1e bne r2,zero,89fc <__register_exitproc+0x94> - 89d4: 00bfffc4 movi r2,-1 - 89d8: dfc00617 ldw ra,24(sp) - 89dc: dd400517 ldw r21,20(sp) - 89e0: dd000417 ldw r20,16(sp) - 89e4: dcc00317 ldw r19,12(sp) - 89e8: dc800217 ldw r18,8(sp) - 89ec: dc400117 ldw r17,4(sp) - 89f0: dc000017 ldw r16,0(sp) - 89f4: dec00704 addi sp,sp,28 - 89f8: f800283a ret - 89fc: 90001926 beq r18,zero,8a64 <__register_exitproc+0xfc> - 8a00: 80802217 ldw r2,136(r16) - 8a04: 1000091e bne r2,zero,8a2c <__register_exitproc+0xc4> - 8a08: 00800034 movhi r2,0 - 8a0c: 10800004 addi r2,r2,0 - 8a10: 103ff026 beq r2,zero,89d4 <__register_exitproc+0x6c> - 8a14: 01004204 movi r4,264 - 8a18: 00000000 call 0 <__alt_mem_onchip_memory2_0> - 8a1c: 103fed26 beq r2,zero,89d4 <__register_exitproc+0x6c> - 8a20: 10004015 stw zero,256(r2) - 8a24: 10004115 stw zero,260(r2) - 8a28: 80802215 stw r2,136(r16) - 8a2c: 880890ba slli r4,r17,2 - 8a30: 00c00044 movi r3,1 - 8a34: 1c46983a sll r3,r3,r17 - 8a38: 1109883a add r4,r2,r4 - 8a3c: 25400015 stw r21,0(r4) - 8a40: 11404017 ldw r5,256(r2) - 8a44: 94800098 cmpnei r18,r18,2 - 8a48: 28cab03a or r5,r5,r3 - 8a4c: 11404015 stw r5,256(r2) - 8a50: 25002015 stw r20,128(r4) - 8a54: 9000031e bne r18,zero,8a64 <__register_exitproc+0xfc> - 8a58: 11004117 ldw r4,260(r2) - 8a5c: 20c6b03a or r3,r4,r3 - 8a60: 10c04115 stw r3,260(r2) - 8a64: 88800044 addi r2,r17,1 - 8a68: 8c400084 addi r17,r17,2 - 8a6c: 882290ba slli r17,r17,2 - 8a70: 80800115 stw r2,4(r16) - 8a74: 0005883a mov r2,zero - 8a78: 8461883a add r16,r16,r17 - 8a7c: 84c00015 stw r19,0(r16) - 8a80: 003fd506 br 89d8 <__register_exitproc+0x70> - -00008a84 <__call_exitprocs>: - 8a84: defff604 addi sp,sp,-40 - 8a88: 00800074 movhi r2,1 - 8a8c: dd800615 stw r22,24(sp) - 8a90: 15a66e17 ldw r22,-26184(r2) - 8a94: dd400515 stw r21,20(sp) - 8a98: dd000415 stw r20,16(sp) - 8a9c: dfc00915 stw ra,36(sp) - 8aa0: df000815 stw fp,32(sp) - 8aa4: ddc00715 stw r23,28(sp) - 8aa8: dcc00315 stw r19,12(sp) - 8aac: dc800215 stw r18,8(sp) - 8ab0: dc400115 stw r17,4(sp) - 8ab4: dc000015 stw r16,0(sp) - 8ab8: 202b883a mov r21,r4 - 8abc: 2829883a mov r20,r5 - 8ac0: b4400d17 ldw r17,52(r22) - 8ac4: 88000726 beq r17,zero,8ae4 <__call_exitprocs+0x60> - 8ac8: 8c000117 ldw r16,4(r17) - 8acc: 8cc02217 ldw r19,136(r17) - 8ad0: 84bfffc4 addi r18,r16,-1 - 8ad4: 802090ba slli r16,r16,2 - 8ad8: 9c2f883a add r23,r19,r16 - 8adc: 8c21883a add r16,r17,r16 - 8ae0: 90000c0e bge r18,zero,8b14 <__call_exitprocs+0x90> - 8ae4: dfc00917 ldw ra,36(sp) - 8ae8: df000817 ldw fp,32(sp) - 8aec: ddc00717 ldw r23,28(sp) - 8af0: dd800617 ldw r22,24(sp) - 8af4: dd400517 ldw r21,20(sp) - 8af8: dd000417 ldw r20,16(sp) - 8afc: dcc00317 ldw r19,12(sp) - 8b00: dc800217 ldw r18,8(sp) - 8b04: dc400117 ldw r17,4(sp) - 8b08: dc000017 ldw r16,0(sp) - 8b0c: dec00a04 addi sp,sp,40 - 8b10: f800283a ret - 8b14: a0000726 beq r20,zero,8b34 <__call_exitprocs+0xb0> - 8b18: 9800041e bne r19,zero,8b2c <__call_exitprocs+0xa8> - 8b1c: 94bfffc4 addi r18,r18,-1 - 8b20: bdffff04 addi r23,r23,-4 - 8b24: 843fff04 addi r16,r16,-4 - 8b28: 003fed06 br 8ae0 <__call_exitprocs+0x5c> - 8b2c: b8c01f17 ldw r3,124(r23) - 8b30: 1d3ffa1e bne r3,r20,8b1c <__call_exitprocs+0x98> - 8b34: 89000117 ldw r4,4(r17) - 8b38: 80c00117 ldw r3,4(r16) - 8b3c: 213fffc4 addi r4,r4,-1 - 8b40: 24800f1e bne r4,r18,8b80 <__call_exitprocs+0xfc> - 8b44: 8c800115 stw r18,4(r17) - 8b48: 183ff426 beq r3,zero,8b1c <__call_exitprocs+0x98> - 8b4c: 8f000117 ldw fp,4(r17) - 8b50: 98000526 beq r19,zero,8b68 <__call_exitprocs+0xe4> - 8b54: 00800044 movi r2,1 - 8b58: 148c983a sll r6,r2,r18 - 8b5c: 99004017 ldw r4,256(r19) - 8b60: 3108703a and r4,r6,r4 - 8b64: 2000081e bne r4,zero,8b88 <__call_exitprocs+0x104> - 8b68: 183ee83a callr r3 - 8b6c: 89000117 ldw r4,4(r17) - 8b70: b0c00d17 ldw r3,52(r22) - 8b74: 273fd21e bne r4,fp,8ac0 <__call_exitprocs+0x3c> - 8b78: 88ffe826 beq r17,r3,8b1c <__call_exitprocs+0x98> - 8b7c: 003fd006 br 8ac0 <__call_exitprocs+0x3c> - 8b80: 80000115 stw zero,4(r16) - 8b84: 003ff006 br 8b48 <__call_exitprocs+0xc4> - 8b88: 99404117 ldw r5,260(r19) - 8b8c: b93fff17 ldw r4,-4(r23) - 8b90: 314c703a and r6,r6,r5 - 8b94: 3000041e bne r6,zero,8ba8 <__call_exitprocs+0x124> - 8b98: 200b883a mov r5,r4 - 8b9c: a809883a mov r4,r21 - 8ba0: 183ee83a callr r3 - 8ba4: 003ff106 br 8b6c <__call_exitprocs+0xe8> - 8ba8: 183ee83a callr r3 - 8bac: 003fef06 br 8b6c <__call_exitprocs+0xe8> - -00008bb0 <_exit>: - 8bb0: defffd04 addi sp,sp,-12 - 8bb4: df000215 stw fp,8(sp) - 8bb8: df000204 addi fp,sp,8 - 8bbc: e13ffe15 stw r4,-8(fp) - 8bc0: 0001883a nop - 8bc4: e0bffe17 ldw r2,-8(fp) - 8bc8: e0bfff15 stw r2,-4(fp) - 8bcc: e0bfff17 ldw r2,-4(fp) - 8bd0: 10000226 beq r2,zero,8bdc <_exit+0x2c> - 8bd4: 002af070 cmpltui zero,zero,43969 - 8bd8: 00000106 br 8be0 <_exit+0x30> - 8bdc: 002af0b0 cmpltui zero,zero,43970 - 8be0: 0001883a nop - 8be4: 003fff06 br 8be4 <_exit+0x34> + 8880: 10bffe58 cmpnei r2,r2,-7 + 8884: 1000081e bne r2,zero,88a8 + 8888: 0001883a nop + 888c: e0bffe17 ldw r2,-8(fp) + 8890: 10ffffc4 addi r3,r2,-1 + 8894: e0fffe15 stw r3,-8(fp) + 8898: 103fe51e bne r2,zero,8830 + 889c: 00000306 br 88ac + 88a0: 0001883a nop + 88a4: 00000106 br 88ac + 88a8: 0001883a nop + 88ac: e0bfff17 ldw r2,-4(fp) + 88b0: e037883a mov sp,fp + 88b4: dfc00117 ldw ra,4(sp) + 88b8: df000017 ldw fp,0(sp) + 88bc: dec00204 addi sp,sp,8 + 88c0: f800283a ret + +000088c4 : + 88c4: defff604 addi sp,sp,-40 + 88c8: dfc00915 stw ra,36(sp) + 88cc: df000815 stw fp,32(sp) + 88d0: df000804 addi fp,sp,32 + 88d4: e13ffd15 stw r4,-12(fp) + 88d8: e17ffc15 stw r5,-16(fp) + 88dc: e1bffb15 stw r6,-20(fp) + 88e0: e1fffa15 stw r7,-24(fp) + 88e4: e0800317 ldw r2,12(fp) + 88e8: e0bff905 stb r2,-28(fp) + 88ec: 0089c404 movi r2,10000 + 88f0: e0bffe15 stw r2,-8(fp) + 88f4: e0bff903 ldbu r2,-28(fp) + 88f8: 10005626 beq r2,zero,8a54 + 88fc: 00002806 br 89a0 + 8900: e0bffe17 ldw r2,-8(fp) + 8904: 108002a8 cmpgeui r2,r2,10 + 8908: 1000021e bne r2,zero,8914 + 890c: 0109c404 movi r4,10000 + 8910: 00098e00 call 98e0 + 8914: d8000015 stw zero,0(sp) + 8918: 000f883a mov r7,zero + 891c: e1bffb17 ldw r6,-20(fp) + 8920: e17ffc17 ldw r5,-16(fp) + 8924: e13ffd17 ldw r4,-12(fp) + 8928: 0008c480 call 8c48 + 892c: e0bfff15 stw r2,-4(fp) + 8930: e0bfff17 ldw r2,-4(fp) + 8934: 10bffea0 cmpeqi r2,r2,-6 + 8938: 1000191e bne r2,zero,89a0 + 893c: e0bfff17 ldw r2,-4(fp) + 8940: 10bffee0 cmpeqi r2,r2,-5 + 8944: 1000161e bne r2,zero,89a0 + 8948: e0bfff17 ldw r2,-4(fp) + 894c: 10bffe58 cmpnei r2,r2,-7 + 8950: 1000011e bne r2,zero,8958 + 8954: 00001206 br 89a0 + 8958: 00800044 movi r2,1 + 895c: d8800015 stw r2,0(sp) + 8960: 01c00044 movi r7,1 + 8964: e1800217 ldw r6,8(fp) + 8968: e17ffa17 ldw r5,-24(fp) + 896c: e13ffd17 ldw r4,-12(fp) + 8970: 000905c0 call 905c + 8974: e0bfff15 stw r2,-4(fp) + 8978: e0bfff17 ldw r2,-4(fp) + 897c: 10bffea0 cmpeqi r2,r2,-6 + 8980: 1000061e bne r2,zero,899c + 8984: e0bfff17 ldw r2,-4(fp) + 8988: 10bffee0 cmpeqi r2,r2,-5 + 898c: 1000031e bne r2,zero,899c + 8990: e0bfff17 ldw r2,-4(fp) + 8994: 10bffe58 cmpnei r2,r2,-7 + 8998: 1000331e bne r2,zero,8a68 + 899c: 0001883a nop + 89a0: e0bffe17 ldw r2,-8(fp) + 89a4: 10ffffc4 addi r3,r2,-1 + 89a8: e0fffe15 stw r3,-8(fp) + 89ac: 103fd41e bne r2,zero,8900 + 89b0: 00003006 br 8a74 + 89b4: e0bffe17 ldw r2,-8(fp) + 89b8: 108002a8 cmpgeui r2,r2,10 + 89bc: 1000021e bne r2,zero,89c8 + 89c0: 0109c404 movi r4,10000 + 89c4: 00098e00 call 98e0 + 89c8: d8000015 stw zero,0(sp) + 89cc: 000f883a mov r7,zero + 89d0: e1bffb17 ldw r6,-20(fp) + 89d4: e17ffc17 ldw r5,-16(fp) + 89d8: e13ffd17 ldw r4,-12(fp) + 89dc: 0008a8c0 call 8a8c + 89e0: e0bfff15 stw r2,-4(fp) + 89e4: e0bfff17 ldw r2,-4(fp) + 89e8: 10bffea0 cmpeqi r2,r2,-6 + 89ec: 1000191e bne r2,zero,8a54 + 89f0: e0bfff17 ldw r2,-4(fp) + 89f4: 10bffee0 cmpeqi r2,r2,-5 + 89f8: 1000161e bne r2,zero,8a54 + 89fc: e0bfff17 ldw r2,-4(fp) + 8a00: 10bffe58 cmpnei r2,r2,-7 + 8a04: 1000011e bne r2,zero,8a0c + 8a08: 00001206 br 8a54 + 8a0c: 00800044 movi r2,1 + 8a10: d8800015 stw r2,0(sp) + 8a14: 01c00044 movi r7,1 + 8a18: e1800217 ldw r6,8(fp) + 8a1c: e17ffa17 ldw r5,-24(fp) + 8a20: e13ffd17 ldw r4,-12(fp) + 8a24: 0008e500 call 8e50 + 8a28: e0bfff15 stw r2,-4(fp) + 8a2c: e0bfff17 ldw r2,-4(fp) + 8a30: 10bffea0 cmpeqi r2,r2,-6 + 8a34: 1000061e bne r2,zero,8a50 + 8a38: e0bfff17 ldw r2,-4(fp) + 8a3c: 10bffee0 cmpeqi r2,r2,-5 + 8a40: 1000031e bne r2,zero,8a50 + 8a44: e0bfff17 ldw r2,-4(fp) + 8a48: 10bffe58 cmpnei r2,r2,-7 + 8a4c: 1000081e bne r2,zero,8a70 + 8a50: 0001883a nop + 8a54: e0bffe17 ldw r2,-8(fp) + 8a58: 10ffffc4 addi r3,r2,-1 + 8a5c: e0fffe15 stw r3,-8(fp) + 8a60: 103fd41e bne r2,zero,89b4 + 8a64: 00000306 br 8a74 + 8a68: 0001883a nop + 8a6c: 00000106 br 8a74 + 8a70: 0001883a nop + 8a74: e0bfff17 ldw r2,-4(fp) + 8a78: e037883a mov sp,fp + 8a7c: dfc00117 ldw ra,4(sp) + 8a80: df000017 ldw fp,0(sp) + 8a84: dec00204 addi sp,sp,8 + 8a88: f800283a ret + +00008a8c : + 8a8c: defff704 addi sp,sp,-36 + 8a90: dfc00815 stw ra,32(sp) + 8a94: df000715 stw fp,28(sp) + 8a98: df000704 addi fp,sp,28 + 8a9c: e13ffd15 stw r4,-12(fp) + 8aa0: e17ffc15 stw r5,-16(fp) + 8aa4: e1bffb15 stw r6,-20(fp) + 8aa8: 3807883a mov r3,r7 + 8aac: e0800217 ldw r2,8(fp) + 8ab0: e0fffa05 stb r3,-24(fp) + 8ab4: e0bff905 stb r2,-28(fp) + 8ab8: e03ffe15 stw zero,-8(fp) + 8abc: e0bffb17 ldw r2,-20(fp) + 8ac0: 1089c424 muli r2,r2,10000 + 8ac4: e0bfff15 stw r2,-4(fp) + 8ac8: e0bffb17 ldw r2,-20(fp) + 8acc: 1000021e bne r2,zero,8ad8 + 8ad0: 0005883a mov r2,zero + 8ad4: 00005706 br 8c34 + 8ad8: e0bffa03 ldbu r2,-24(fp) + 8adc: 10000a1e bne r2,zero,8b08 + 8ae0: e13ffd17 ldw r4,-12(fp) + 8ae4: 0007d040 call 7d04 + 8ae8: e0bffe15 stw r2,-8(fp) + 8aec: e0bffe17 ldw r2,-8(fp) + 8af0: 10000226 beq r2,zero,8afc + 8af4: e0bffe17 ldw r2,-8(fp) + 8af8: 00004e06 br 8c34 + 8afc: 01400704 movi r5,28 + 8b00: e13ffd17 ldw r4,-12(fp) + 8b04: 00092e40 call 92e4 + 8b08: e0bffa03 ldbu r2,-24(fp) + 8b0c: 100d883a mov r6,r2 + 8b10: 000b883a mov r5,zero + 8b14: e13ffd17 ldw r4,-12(fp) + 8b18: 00083780 call 8378 + 8b1c: e0bffe15 stw r2,-8(fp) + 8b20: e0bffe17 ldw r2,-8(fp) + 8b24: 1000271e bne r2,zero,8bc4 + 8b28: 00000f06 br 8b68 + 8b2c: e0bffc17 ldw r2,-16(fp) + 8b30: 10800003 ldbu r2,0(r2) + 8b34: 10803fcc andi r2,r2,255 + 8b38: 000f883a mov r7,zero + 8b3c: 000d883a mov r6,zero + 8b40: 100b883a mov r5,r2 + 8b44: e13ffd17 ldw r4,-12(fp) + 8b48: 000828c0 call 828c + 8b4c: e0bffe15 stw r2,-8(fp) + 8b50: e0bffc17 ldw r2,-16(fp) + 8b54: 10800044 addi r2,r2,1 + 8b58: e0bffc15 stw r2,-16(fp) + 8b5c: e0bffb17 ldw r2,-20(fp) + 8b60: 10bfffc4 addi r2,r2,-1 + 8b64: e0bffb15 stw r2,-20(fp) + 8b68: e0bffb17 ldw r2,-20(fp) + 8b6c: 108000b0 cmpltui r2,r2,2 + 8b70: 1000021e bne r2,zero,8b7c + 8b74: e0bffe17 ldw r2,-8(fp) + 8b78: 103fec26 beq r2,zero,8b2c + 8b7c: e0bffe17 ldw r2,-8(fp) + 8b80: 1000101e bne r2,zero,8bc4 + 8b84: e0bffc17 ldw r2,-16(fp) + 8b88: 10800003 ldbu r2,0(r2) + 8b8c: 10803fcc andi r2,r2,255 + 8b90: e0fff903 ldbu r3,-28(fp) + 8b94: 180f883a mov r7,r3 + 8b98: 000d883a mov r6,zero + 8b9c: 100b883a mov r5,r2 + 8ba0: e13ffd17 ldw r4,-12(fp) + 8ba4: 000828c0 call 828c + 8ba8: e0bffe15 stw r2,-8(fp) + 8bac: e0bffc17 ldw r2,-16(fp) + 8bb0: 10800044 addi r2,r2,1 + 8bb4: e0bffc15 stw r2,-16(fp) + 8bb8: e0bffb17 ldw r2,-20(fp) + 8bbc: 10bfffc4 addi r2,r2,-1 + 8bc0: e0bffb15 stw r2,-20(fp) + 8bc4: e0bff903 ldbu r2,-28(fp) + 8bc8: 1000101e bne r2,zero,8c0c + 8bcc: e0bffe17 ldw r2,-8(fp) + 8bd0: 10001726 beq r2,zero,8c30 + 8bd4: 00000d06 br 8c0c + 8bd8: e0bfff17 ldw r2,-4(fp) + 8bdc: 108002a8 cmpgeui r2,r2,10 + 8be0: 1000021e bne r2,zero,8bec + 8be4: 0109c404 movi r4,10000 + 8be8: 00098e00 call 98e0 + 8bec: e0bfff17 ldw r2,-4(fp) + 8bf0: 10bfffc4 addi r2,r2,-1 + 8bf4: e0bfff15 stw r2,-4(fp) + 8bf8: e0bfff17 ldw r2,-4(fp) + 8bfc: 1000031e bne r2,zero,8c0c + 8c00: 00bfff84 movi r2,-2 + 8c04: e0bffe15 stw r2,-8(fp) + 8c08: 00000306 br 8c18 + 8c0c: e13ffd17 ldw r4,-12(fp) + 8c10: 00080f40 call 80f4 + 8c14: 103ff01e bne r2,zero,8bd8 + 8c18: e0bffe04 addi r2,fp,-8 + 8c1c: 100b883a mov r5,r2 + 8c20: e13ffd17 ldw r4,-12(fp) + 8c24: 00084d40 call 84d4 + 8c28: e13ffd17 ldw r4,-12(fp) + 8c2c: 0007d9c0 call 7d9c + 8c30: e0bffe17 ldw r2,-8(fp) + 8c34: e037883a mov sp,fp + 8c38: dfc00117 ldw ra,4(sp) + 8c3c: df000017 ldw fp,0(sp) + 8c40: dec00204 addi sp,sp,8 + 8c44: f800283a ret + +00008c48 : + 8c48: defff604 addi sp,sp,-40 + 8c4c: dfc00915 stw ra,36(sp) + 8c50: df000815 stw fp,32(sp) + 8c54: df000804 addi fp,sp,32 + 8c58: e13ffc15 stw r4,-16(fp) + 8c5c: e17ffb15 stw r5,-20(fp) + 8c60: e1bffa15 stw r6,-24(fp) + 8c64: 3807883a mov r3,r7 + 8c68: e0800217 ldw r2,8(fp) + 8c6c: e0fff905 stb r3,-28(fp) + 8c70: e0bff805 stb r2,-32(fp) + 8c74: e03fff15 stw zero,-4(fp) + 8c78: e0bffa17 ldw r2,-24(fp) + 8c7c: 1089c424 muli r2,r2,10000 + 8c80: e0bffe15 stw r2,-8(fp) + 8c84: e0bffc17 ldw r2,-16(fp) + 8c88: 10800717 ldw r2,28(r2) + 8c8c: e0bffd15 stw r2,-12(fp) + 8c90: e0bffa17 ldw r2,-24(fp) + 8c94: 1000021e bne r2,zero,8ca0 + 8c98: 0005883a mov r2,zero + 8c9c: 00006706 br 8e3c + 8ca0: e0bffc17 ldw r2,-16(fp) + 8ca4: 10c00617 ldw r3,24(r2) + 8ca8: 00800034 movhi r2,0 + 8cac: 109e6104 addi r2,r2,31108 + 8cb0: 18800226 beq r3,r2,8cbc + 8cb4: 00bfff44 movi r2,-3 + 8cb8: 00006006 br 8e3c + 8cbc: e0bff903 ldbu r2,-28(fp) + 8cc0: 10000a1e bne r2,zero,8cec + 8cc4: e13ffc17 ldw r4,-16(fp) + 8cc8: 0007d040 call 7d04 + 8ccc: e0bfff15 stw r2,-4(fp) + 8cd0: e0bfff17 ldw r2,-4(fp) + 8cd4: 10000226 beq r2,zero,8ce0 + 8cd8: e0bfff17 ldw r2,-4(fp) + 8cdc: 00005706 br 8e3c + 8ce0: 01400704 movi r5,28 + 8ce4: e13ffc17 ldw r4,-16(fp) + 8ce8: 00092e40 call 92e4 + 8cec: e0bff903 ldbu r2,-28(fp) + 8cf0: 100d883a mov r6,r2 + 8cf4: 000b883a mov r5,zero + 8cf8: e13ffc17 ldw r4,-16(fp) + 8cfc: 00083780 call 8378 + 8d00: e0bfff15 stw r2,-4(fp) + 8d04: e0bfff17 ldw r2,-4(fp) + 8d08: 1000271e bne r2,zero,8da8 + 8d0c: 00000f06 br 8d4c + 8d10: e0bffb17 ldw r2,-20(fp) + 8d14: 10800003 ldbu r2,0(r2) + 8d18: 10803fcc andi r2,r2,255 + 8d1c: 000f883a mov r7,zero + 8d20: 000d883a mov r6,zero + 8d24: 100b883a mov r5,r2 + 8d28: e13ffc17 ldw r4,-16(fp) + 8d2c: 000828c0 call 828c + 8d30: e0bfff15 stw r2,-4(fp) + 8d34: e0bffb17 ldw r2,-20(fp) + 8d38: 10800044 addi r2,r2,1 + 8d3c: e0bffb15 stw r2,-20(fp) + 8d40: e0bffa17 ldw r2,-24(fp) + 8d44: 10bfffc4 addi r2,r2,-1 + 8d48: e0bffa15 stw r2,-24(fp) + 8d4c: e0bffa17 ldw r2,-24(fp) + 8d50: 108000b0 cmpltui r2,r2,2 + 8d54: 1000021e bne r2,zero,8d60 + 8d58: e0bfff17 ldw r2,-4(fp) + 8d5c: 103fec26 beq r2,zero,8d10 + 8d60: e0bfff17 ldw r2,-4(fp) + 8d64: 1000101e bne r2,zero,8da8 + 8d68: e0bffb17 ldw r2,-20(fp) + 8d6c: 10800003 ldbu r2,0(r2) + 8d70: 10803fcc andi r2,r2,255 + 8d74: e0fff803 ldbu r3,-32(fp) + 8d78: 180f883a mov r7,r3 + 8d7c: 000d883a mov r6,zero + 8d80: 100b883a mov r5,r2 + 8d84: e13ffc17 ldw r4,-16(fp) + 8d88: 000828c0 call 828c + 8d8c: e0bfff15 stw r2,-4(fp) + 8d90: e0bffb17 ldw r2,-20(fp) + 8d94: 10800044 addi r2,r2,1 + 8d98: e0bffb15 stw r2,-20(fp) + 8d9c: e0bffa17 ldw r2,-24(fp) + 8da0: 10bfffc4 addi r2,r2,-1 + 8da4: e0bffa15 stw r2,-24(fp) + 8da8: e0bfff17 ldw r2,-4(fp) + 8dac: 10001426 beq r2,zero,8e00 + 8db0: 00000d06 br 8de8 + 8db4: e0bffe17 ldw r2,-8(fp) + 8db8: 108002a8 cmpgeui r2,r2,10 + 8dbc: 1000021e bne r2,zero,8dc8 + 8dc0: 0109c404 movi r4,10000 + 8dc4: 00098e00 call 98e0 + 8dc8: e0bffe17 ldw r2,-8(fp) + 8dcc: 10bfffc4 addi r2,r2,-1 + 8dd0: e0bffe15 stw r2,-8(fp) + 8dd4: e0bffe17 ldw r2,-8(fp) + 8dd8: 1000031e bne r2,zero,8de8 + 8ddc: 00bfff84 movi r2,-2 + 8de0: e0bfff15 stw r2,-4(fp) + 8de4: 00000306 br 8df4 + 8de8: e13ffc17 ldw r4,-16(fp) + 8dec: 00080f40 call 80f4 + 8df0: 103ff01e bne r2,zero,8db4 + 8df4: e13ffc17 ldw r4,-16(fp) + 8df8: 0007d9c0 call 7d9c + 8dfc: 00000e06 br 8e38 + 8e00: e0bff803 ldbu r2,-32(fp) + 8e04: 10000c26 beq r2,zero,8e38 + 8e08: 01400704 movi r5,28 + 8e0c: e13ffc17 ldw r4,-16(fp) + 8e10: 00092e40 call 92e4 + 8e14: 000b883a mov r5,zero + 8e18: e13ffc17 ldw r4,-16(fp) + 8e1c: 00095340 call 9534 + 8e20: e0bffd17 ldw r2,-12(fp) + 8e24: 00c00044 movi r3,1 + 8e28: 10c00215 stw r3,8(r2) + 8e2c: 01400044 movi r5,1 + 8e30: e13ffc17 ldw r4,-16(fp) + 8e34: 000938c0 call 938c + 8e38: e0bfff17 ldw r2,-4(fp) + 8e3c: e037883a mov sp,fp + 8e40: dfc00117 ldw ra,4(sp) + 8e44: df000017 ldw fp,0(sp) + 8e48: dec00204 addi sp,sp,8 + 8e4c: f800283a ret + +00008e50 : + 8e50: defff404 addi sp,sp,-48 + 8e54: dfc00b15 stw ra,44(sp) + 8e58: df000a15 stw fp,40(sp) + 8e5c: df000a04 addi fp,sp,40 + 8e60: e13ffa15 stw r4,-24(fp) + 8e64: e17ff915 stw r5,-28(fp) + 8e68: e1bff815 stw r6,-32(fp) + 8e6c: 3807883a mov r3,r7 + 8e70: e0800217 ldw r2,8(fp) + 8e74: e0fff705 stb r3,-36(fp) + 8e78: e0bff605 stb r2,-40(fp) + 8e7c: e03ffc15 stw zero,-16(fp) + 8e80: e03ffe15 stw zero,-8(fp) + 8e84: e03ffd15 stw zero,-12(fp) + 8e88: e0bff817 ldw r2,-32(fp) + 8e8c: 1000021e bne r2,zero,8e98 + 8e90: 0005883a mov r2,zero + 8e94: 00006c06 br 9048 + 8e98: e0bff703 ldbu r2,-36(fp) + 8e9c: 10000a1e bne r2,zero,8ec8 + 8ea0: e13ffa17 ldw r4,-24(fp) + 8ea4: 0007d040 call 7d04 + 8ea8: e0bffc15 stw r2,-16(fp) + 8eac: e0bffc17 ldw r2,-16(fp) + 8eb0: 10000226 beq r2,zero,8ebc + 8eb4: e0bffc17 ldw r2,-16(fp) + 8eb8: 00006306 br 9048 + 8ebc: 01400704 movi r5,28 + 8ec0: e13ffa17 ldw r4,-24(fp) + 8ec4: 00092e40 call 92e4 + 8ec8: e0bff703 ldbu r2,-36(fp) + 8ecc: 100d883a mov r6,r2 + 8ed0: 01400044 movi r5,1 + 8ed4: e13ffa17 ldw r4,-24(fp) + 8ed8: 00083780 call 8378 + 8edc: e0bffc15 stw r2,-16(fp) + 8ee0: e0bffc17 ldw r2,-16(fp) + 8ee4: 1000341e bne r2,zero,8fb8 + 8ee8: 00001906 br 8f50 + 8eec: 000f883a mov r7,zero + 8ef0: 000d883a mov r6,zero + 8ef4: 000b883a mov r5,zero + 8ef8: e13ffa17 ldw r4,-24(fp) + 8efc: 000828c0 call 828c + 8f00: e0bffc15 stw r2,-16(fp) + 8f04: e0bffd17 ldw r2,-12(fp) + 8f08: 10800044 addi r2,r2,1 + 8f0c: e0bffd15 stw r2,-12(fp) + 8f10: e0bffc17 ldw r2,-16(fp) + 8f14: 10000e1e bne r2,zero,8f50 + 8f18: e0bffb04 addi r2,fp,-20 + 8f1c: 100f883a mov r7,r2 + 8f20: 000d883a mov r6,zero + 8f24: e17ff917 ldw r5,-28(fp) + 8f28: e13ffa17 ldw r4,-24(fp) + 8f2c: 00081380 call 8138 + 8f30: e0bffb17 ldw r2,-20(fp) + 8f34: e0fff917 ldw r3,-28(fp) + 8f38: 1885883a add r2,r3,r2 + 8f3c: e0bff915 stw r2,-28(fp) + 8f40: e0bffb17 ldw r2,-20(fp) + 8f44: e0fffe17 ldw r3,-8(fp) + 8f48: 1885883a add r2,r3,r2 + 8f4c: e0bffe15 stw r2,-8(fp) + 8f50: e0bff817 ldw r2,-32(fp) + 8f54: 10bfffc4 addi r2,r2,-1 + 8f58: e0fffd17 ldw r3,-12(fp) + 8f5c: 1880022e bgeu r3,r2,8f68 + 8f60: e0bffc17 ldw r2,-16(fp) + 8f64: 103fe126 beq r2,zero,8eec + 8f68: e0bffc17 ldw r2,-16(fp) + 8f6c: 1000121e bne r2,zero,8fb8 + 8f70: e0bff603 ldbu r2,-40(fp) + 8f74: 100f883a mov r7,r2 + 8f78: 000d883a mov r6,zero + 8f7c: 000b883a mov r5,zero + 8f80: e13ffa17 ldw r4,-24(fp) + 8f84: 000828c0 call 828c + 8f88: e0bffc15 stw r2,-16(fp) + 8f8c: 00000a06 br 8fb8 + 8f90: e17ff917 ldw r5,-28(fp) + 8f94: e13ffa17 ldw r4,-24(fp) + 8f98: 00081e40 call 81e4 + 8f9c: e0bffc15 stw r2,-16(fp) + 8fa0: e0bff917 ldw r2,-28(fp) + 8fa4: 10800044 addi r2,r2,1 + 8fa8: e0bff915 stw r2,-28(fp) + 8fac: e0bffe17 ldw r2,-8(fp) + 8fb0: 10800044 addi r2,r2,1 + 8fb4: e0bffe15 stw r2,-8(fp) + 8fb8: e0fffe17 ldw r3,-8(fp) + 8fbc: e0bff817 ldw r2,-32(fp) + 8fc0: 1880022e bgeu r3,r2,8fcc + 8fc4: e0bffc17 ldw r2,-16(fp) + 8fc8: 103ff126 beq r2,zero,8f90 + 8fcc: e0bff603 ldbu r2,-40(fp) + 8fd0: 1000021e bne r2,zero,8fdc + 8fd4: e0bffc17 ldw r2,-16(fp) + 8fd8: 10001a26 beq r2,zero,9044 + 8fdc: e0bff817 ldw r2,-32(fp) + 8fe0: 1089c424 muli r2,r2,10000 + 8fe4: e0bfff15 stw r2,-4(fp) + 8fe8: 00000d06 br 9020 + 8fec: e0bfff17 ldw r2,-4(fp) + 8ff0: 108002a8 cmpgeui r2,r2,10 + 8ff4: 1000021e bne r2,zero,9000 + 8ff8: 0109c404 movi r4,10000 + 8ffc: 00098e00 call 98e0 + 9000: e0bfff17 ldw r2,-4(fp) + 9004: 10bfffc4 addi r2,r2,-1 + 9008: e0bfff15 stw r2,-4(fp) + 900c: e0bfff17 ldw r2,-4(fp) + 9010: 1000031e bne r2,zero,9020 + 9014: 00bfff84 movi r2,-2 + 9018: e0bffc15 stw r2,-16(fp) + 901c: 00000306 br 902c + 9020: e13ffa17 ldw r4,-24(fp) + 9024: 00080f40 call 80f4 + 9028: 103ff01e bne r2,zero,8fec + 902c: e0bffc04 addi r2,fp,-16 + 9030: 100b883a mov r5,r2 + 9034: e13ffa17 ldw r4,-24(fp) + 9038: 00084d40 call 84d4 + 903c: e13ffa17 ldw r4,-24(fp) + 9040: 0007d9c0 call 7d9c + 9044: e0bffc17 ldw r2,-16(fp) + 9048: e037883a mov sp,fp + 904c: dfc00117 ldw ra,4(sp) + 9050: df000017 ldw fp,0(sp) + 9054: dec00204 addi sp,sp,8 + 9058: f800283a ret + +0000905c : + 905c: defff504 addi sp,sp,-44 + 9060: dfc00a15 stw ra,40(sp) + 9064: df000915 stw fp,36(sp) + 9068: df000904 addi fp,sp,36 + 906c: e13ffb15 stw r4,-20(fp) + 9070: e17ffa15 stw r5,-24(fp) + 9074: e1bff915 stw r6,-28(fp) + 9078: 3807883a mov r3,r7 + 907c: e0800217 ldw r2,8(fp) + 9080: e0fff805 stb r3,-32(fp) + 9084: e0bff705 stb r2,-36(fp) + 9088: e03fff15 stw zero,-4(fp) + 908c: e0bffb17 ldw r2,-20(fp) + 9090: 10800717 ldw r2,28(r2) + 9094: e0bffc15 stw r2,-16(fp) + 9098: e03ffd15 stw zero,-12(fp) + 909c: e0bff917 ldw r2,-28(fp) + 90a0: 1000021e bne r2,zero,90ac + 90a4: 0005883a mov r2,zero + 90a8: 00006206 br 9234 + 90ac: e0bffb17 ldw r2,-20(fp) + 90b0: 10c00617 ldw r3,24(r2) + 90b4: 00800034 movhi r2,0 + 90b8: 109e6104 addi r2,r2,31108 + 90bc: 18800226 beq r3,r2,90c8 + 90c0: 00bfff44 movi r2,-3 + 90c4: 00005b06 br 9234 + 90c8: e0bff803 ldbu r2,-32(fp) + 90cc: 10000a1e bne r2,zero,90f8 + 90d0: e13ffb17 ldw r4,-20(fp) + 90d4: 0007d040 call 7d04 + 90d8: e0bfff15 stw r2,-4(fp) + 90dc: e0bfff17 ldw r2,-4(fp) + 90e0: 10000226 beq r2,zero,90ec + 90e4: e0bfff17 ldw r2,-4(fp) + 90e8: 00005206 br 9234 + 90ec: 01400704 movi r5,28 + 90f0: e13ffb17 ldw r4,-20(fp) + 90f4: 00092e40 call 92e4 + 90f8: e0bff803 ldbu r2,-32(fp) + 90fc: 100d883a mov r6,r2 + 9100: 01400044 movi r5,1 + 9104: e13ffb17 ldw r4,-20(fp) + 9108: 00083780 call 8378 + 910c: e0bfff15 stw r2,-4(fp) + 9110: e0bfff17 ldw r2,-4(fp) + 9114: 1000191e bne r2,zero,917c + 9118: 00000906 br 9140 + 911c: 000f883a mov r7,zero + 9120: 000d883a mov r6,zero + 9124: 000b883a mov r5,zero + 9128: e13ffb17 ldw r4,-20(fp) + 912c: 000828c0 call 828c + 9130: e0bfff15 stw r2,-4(fp) + 9134: e0bffd17 ldw r2,-12(fp) + 9138: 10800044 addi r2,r2,1 + 913c: e0bffd15 stw r2,-12(fp) + 9140: e0bff917 ldw r2,-28(fp) + 9144: 10bfffc4 addi r2,r2,-1 + 9148: e0fffd17 ldw r3,-12(fp) + 914c: 1880022e bgeu r3,r2,9158 + 9150: e0bfff17 ldw r2,-4(fp) + 9154: 103ff126 beq r2,zero,911c + 9158: e0bfff17 ldw r2,-4(fp) + 915c: 1000071e bne r2,zero,917c + 9160: e0bff703 ldbu r2,-36(fp) + 9164: 100f883a mov r7,r2 + 9168: 000d883a mov r6,zero + 916c: 000b883a mov r5,zero + 9170: e13ffb17 ldw r4,-20(fp) + 9174: 000828c0 call 828c + 9178: e0bfff15 stw r2,-4(fp) + 917c: e0bfff17 ldw r2,-4(fp) + 9180: 10001726 beq r2,zero,91e0 + 9184: e0bff917 ldw r2,-28(fp) + 9188: 1089c424 muli r2,r2,10000 + 918c: e0bffe15 stw r2,-8(fp) + 9190: 00000d06 br 91c8 + 9194: e0bffe17 ldw r2,-8(fp) + 9198: 108002a8 cmpgeui r2,r2,10 + 919c: 1000021e bne r2,zero,91a8 + 91a0: 0109c404 movi r4,10000 + 91a4: 00098e00 call 98e0 + 91a8: e0bffe17 ldw r2,-8(fp) + 91ac: 10bfffc4 addi r2,r2,-1 + 91b0: e0bffe15 stw r2,-8(fp) + 91b4: e0bffe17 ldw r2,-8(fp) + 91b8: 1000031e bne r2,zero,91c8 + 91bc: 00bfff84 movi r2,-2 + 91c0: e0bfff15 stw r2,-4(fp) + 91c4: 00000306 br 91d4 + 91c8: e13ffb17 ldw r4,-20(fp) + 91cc: 00080f40 call 80f4 + 91d0: 103ff01e bne r2,zero,9194 + 91d4: e13ffb17 ldw r4,-20(fp) + 91d8: 0007d9c0 call 7d9c + 91dc: 00001406 br 9230 + 91e0: e0bff703 ldbu r2,-36(fp) + 91e4: 10001226 beq r2,zero,9230 + 91e8: 01400704 movi r5,28 + 91ec: e13ffb17 ldw r4,-20(fp) + 91f0: 00092e40 call 92e4 + 91f4: 000b883a mov r5,zero + 91f8: e13ffb17 ldw r4,-20(fp) + 91fc: 00094840 call 9484 + 9200: e0bffc17 ldw r2,-16(fp) + 9204: 00c00084 movi r3,2 + 9208: 10c00215 stw r3,8(r2) + 920c: e0bffc17 ldw r2,-16(fp) + 9210: e0fffa17 ldw r3,-24(fp) + 9214: 10c00015 stw r3,0(r2) + 9218: e0bffc17 ldw r2,-16(fp) + 921c: e0fff917 ldw r3,-28(fp) + 9220: 10c00115 stw r3,4(r2) + 9224: 01400084 movi r5,2 + 9228: e13ffb17 ldw r4,-20(fp) + 922c: 000938c0 call 938c + 9230: e0bfff17 ldw r2,-4(fp) + 9234: e037883a mov sp,fp + 9238: dfc00117 ldw ra,4(sp) + 923c: df000017 ldw fp,0(sp) + 9240: dec00204 addi sp,sp,8 + 9244: f800283a ret + +00009248 : + 9248: defffd04 addi sp,sp,-12 + 924c: df000215 stw fp,8(sp) + 9250: df000204 addi fp,sp,8 + 9254: e13fff15 stw r4,-4(fp) + 9258: e17ffe15 stw r5,-8(fp) + 925c: e0bfff17 ldw r2,-4(fp) + 9260: 10800317 ldw r2,12(r2) + 9264: 10800404 addi r2,r2,16 + 9268: 10c00037 ldwio r3,0(r2) + 926c: e0bfff17 ldw r2,-4(fp) + 9270: 10800317 ldw r2,12(r2) + 9274: 10800304 addi r2,r2,12 + 9278: 10800037 ldwio r2,0(r2) + 927c: 1884703a and r2,r3,r2 + 9280: 1007883a mov r3,r2 + 9284: e0bffe17 ldw r2,-8(fp) + 9288: 10c00015 stw r3,0(r2) + 928c: 0001883a nop + 9290: e037883a mov sp,fp + 9294: df000017 ldw fp,0(sp) + 9298: dec00104 addi sp,sp,4 + 929c: f800283a ret + +000092a0 : + 92a0: defffd04 addi sp,sp,-12 + 92a4: df000215 stw fp,8(sp) + 92a8: df000204 addi fp,sp,8 + 92ac: e13fff15 stw r4,-4(fp) + 92b0: e17ffe15 stw r5,-8(fp) + 92b4: e0bfff17 ldw r2,-4(fp) + 92b8: 10800317 ldw r2,12(r2) + 92bc: 10800404 addi r2,r2,16 + 92c0: 10800037 ldwio r2,0(r2) + 92c4: 1007883a mov r3,r2 + 92c8: e0bffe17 ldw r2,-8(fp) + 92cc: 10c00015 stw r3,0(r2) + 92d0: 0001883a nop + 92d4: e037883a mov sp,fp + 92d8: df000017 ldw fp,0(sp) + 92dc: dec00104 addi sp,sp,4 + 92e0: f800283a ret + +000092e4 : + 92e4: defffd04 addi sp,sp,-12 + 92e8: df000215 stw fp,8(sp) + 92ec: df000204 addi fp,sp,8 + 92f0: e13fff15 stw r4,-4(fp) + 92f4: e17ffe15 stw r5,-8(fp) + 92f8: e0bfff17 ldw r2,-4(fp) + 92fc: 10800317 ldw r2,12(r2) + 9300: 10800404 addi r2,r2,16 + 9304: e0fffe17 ldw r3,-8(fp) + 9308: 10c00035 stwio r3,0(r2) + 930c: 0001883a nop + 9310: e037883a mov sp,fp + 9314: df000017 ldw fp,0(sp) + 9318: dec00104 addi sp,sp,4 + 931c: f800283a ret + +00009320 : + 9320: defffb04 addi sp,sp,-20 + 9324: dfc00415 stw ra,16(sp) + 9328: df000315 stw fp,12(sp) + 932c: df000304 addi fp,sp,12 + 9330: e13ffe15 stw r4,-8(fp) + 9334: e17ffd15 stw r5,-12(fp) + 9338: e0bfff04 addi r2,fp,-4 + 933c: 100b883a mov r5,r2 + 9340: e13ffe17 ldw r4,-8(fp) + 9344: 00093f40 call 93f4 + 9348: e0bffd17 ldw r2,-12(fp) + 934c: 0086303a nor r3,zero,r2 + 9350: e0bfff17 ldw r2,-4(fp) + 9354: 1884703a and r2,r3,r2 + 9358: e0bfff15 stw r2,-4(fp) + 935c: e0bffe17 ldw r2,-8(fp) + 9360: 10800317 ldw r2,12(r2) + 9364: 10800304 addi r2,r2,12 + 9368: e0ffff17 ldw r3,-4(fp) + 936c: 18c007cc andi r3,r3,31 + 9370: 10c00035 stwio r3,0(r2) + 9374: 0001883a nop + 9378: e037883a mov sp,fp + 937c: dfc00117 ldw ra,4(sp) + 9380: df000017 ldw fp,0(sp) + 9384: dec00204 addi sp,sp,8 + 9388: f800283a ret + +0000938c : + 938c: defffb04 addi sp,sp,-20 + 9390: dfc00415 stw ra,16(sp) + 9394: df000315 stw fp,12(sp) + 9398: df000304 addi fp,sp,12 + 939c: e13ffe15 stw r4,-8(fp) + 93a0: e17ffd15 stw r5,-12(fp) + 93a4: e0bfff04 addi r2,fp,-4 + 93a8: 100b883a mov r5,r2 + 93ac: e13ffe17 ldw r4,-8(fp) + 93b0: 00093f40 call 93f4 + 93b4: e0ffff17 ldw r3,-4(fp) + 93b8: e0bffd17 ldw r2,-12(fp) + 93bc: 1884b03a or r2,r3,r2 + 93c0: e0bfff15 stw r2,-4(fp) + 93c4: e0bffe17 ldw r2,-8(fp) + 93c8: 10800317 ldw r2,12(r2) + 93cc: 10800304 addi r2,r2,12 + 93d0: e0ffff17 ldw r3,-4(fp) + 93d4: 18c007cc andi r3,r3,31 + 93d8: 10c00035 stwio r3,0(r2) + 93dc: 0001883a nop + 93e0: e037883a mov sp,fp + 93e4: dfc00117 ldw ra,4(sp) + 93e8: df000017 ldw fp,0(sp) + 93ec: dec00204 addi sp,sp,8 + 93f0: f800283a ret + +000093f4 : + 93f4: defffd04 addi sp,sp,-12 + 93f8: df000215 stw fp,8(sp) + 93fc: df000204 addi fp,sp,8 + 9400: e13fff15 stw r4,-4(fp) + 9404: e17ffe15 stw r5,-8(fp) + 9408: e0bfff17 ldw r2,-4(fp) + 940c: 10800317 ldw r2,12(r2) + 9410: 10800304 addi r2,r2,12 + 9414: 10800037 ldwio r2,0(r2) + 9418: 10c007cc andi r3,r2,31 + 941c: e0bffe17 ldw r2,-8(fp) + 9420: 10c00015 stw r3,0(r2) + 9424: 0001883a nop + 9428: e037883a mov sp,fp + 942c: df000017 ldw fp,0(sp) + 9430: dec00104 addi sp,sp,4 + 9434: f800283a ret + +00009438 : + 9438: defffd04 addi sp,sp,-12 + 943c: df000215 stw fp,8(sp) + 9440: df000204 addi fp,sp,8 + 9444: e13fff15 stw r4,-4(fp) + 9448: e17ffe15 stw r5,-8(fp) + 944c: e0bfff17 ldw r2,-4(fp) + 9450: 10800317 ldw r2,12(r2) + 9454: 10800204 addi r2,r2,8 + 9458: 10800037 ldwio r2,0(r2) + 945c: 1005d13a srai r2,r2,4 + 9460: 108000cc andi r2,r2,3 + 9464: 1007883a mov r3,r2 + 9468: e0bffe17 ldw r2,-8(fp) + 946c: 10c00015 stw r3,0(r2) + 9470: 0001883a nop + 9474: e037883a mov sp,fp + 9478: df000017 ldw fp,0(sp) + 947c: dec00104 addi sp,sp,4 + 9480: f800283a ret + +00009484 : + 9484: defffd04 addi sp,sp,-12 + 9488: df000215 stw fp,8(sp) + 948c: df000204 addi fp,sp,8 + 9490: e13fff15 stw r4,-4(fp) + 9494: e17ffe15 stw r5,-8(fp) + 9498: e0bfff17 ldw r2,-4(fp) + 949c: 10800317 ldw r2,12(r2) + 94a0: 10800204 addi r2,r2,8 + 94a4: e0ffff17 ldw r3,-4(fp) + 94a8: 18c00317 ldw r3,12(r3) + 94ac: 18c00204 addi r3,r3,8 + 94b0: 18c00037 ldwio r3,0(r3) + 94b4: 1809883a mov r4,r3 + 94b8: 00fff3c4 movi r3,-49 + 94bc: 20c8703a and r4,r4,r3 + 94c0: e0fffe17 ldw r3,-8(fp) + 94c4: 1806913a slli r3,r3,4 + 94c8: 18c00c0c andi r3,r3,48 + 94cc: 20c6b03a or r3,r4,r3 + 94d0: 10c00035 stwio r3,0(r2) + 94d4: 0001883a nop + 94d8: e037883a mov sp,fp + 94dc: df000017 ldw fp,0(sp) + 94e0: dec00104 addi sp,sp,4 + 94e4: f800283a ret + +000094e8 : + 94e8: defffd04 addi sp,sp,-12 + 94ec: df000215 stw fp,8(sp) + 94f0: df000204 addi fp,sp,8 + 94f4: e13fff15 stw r4,-4(fp) + 94f8: e17ffe15 stw r5,-8(fp) + 94fc: e0bfff17 ldw r2,-4(fp) + 9500: 10800317 ldw r2,12(r2) + 9504: 10800204 addi r2,r2,8 + 9508: 10800037 ldwio r2,0(r2) + 950c: 1005d0ba srai r2,r2,2 + 9510: 108000cc andi r2,r2,3 + 9514: 1007883a mov r3,r2 + 9518: e0bffe17 ldw r2,-8(fp) + 951c: 10c00015 stw r3,0(r2) + 9520: 0001883a nop + 9524: e037883a mov sp,fp + 9528: df000017 ldw fp,0(sp) + 952c: dec00104 addi sp,sp,4 + 9530: f800283a ret + +00009534 : + 9534: defffd04 addi sp,sp,-12 + 9538: df000215 stw fp,8(sp) + 953c: df000204 addi fp,sp,8 + 9540: e13fff15 stw r4,-4(fp) + 9544: e17ffe15 stw r5,-8(fp) + 9548: e0bfff17 ldw r2,-4(fp) + 954c: 10800317 ldw r2,12(r2) + 9550: 10800204 addi r2,r2,8 + 9554: e0ffff17 ldw r3,-4(fp) + 9558: 18c00317 ldw r3,12(r3) + 955c: 18c00204 addi r3,r3,8 + 9560: 18c00037 ldwio r3,0(r3) + 9564: 1809883a mov r4,r3 + 9568: 00fffcc4 movi r3,-13 + 956c: 20c8703a and r4,r4,r3 + 9570: e0fffe17 ldw r3,-8(fp) + 9574: 180690ba slli r3,r3,2 + 9578: 18c0030c andi r3,r3,12 + 957c: 20c6b03a or r3,r4,r3 + 9580: 10c00035 stwio r3,0(r2) + 9584: 0001883a nop + 9588: e037883a mov sp,fp + 958c: df000017 ldw fp,0(sp) + 9590: dec00104 addi sp,sp,4 + 9594: f800283a ret + +00009598 : + 9598: defffa04 addi sp,sp,-24 + 959c: dfc00515 stw ra,20(sp) + 95a0: df000415 stw fp,16(sp) + 95a4: df000404 addi fp,sp,16 + 95a8: e13ffe15 stw r4,-8(fp) + 95ac: e17ffd15 stw r5,-12(fp) + 95b0: e1bffc15 stw r6,-16(fp) + 95b4: e0bffe17 ldw r2,-8(fp) + 95b8: 10800017 ldw r2,0(r2) + 95bc: e0bfff15 stw r2,-4(fp) + 95c0: e0bfff17 ldw r2,-4(fp) + 95c4: 10c00a04 addi r3,r2,40 + 95c8: e0bffe17 ldw r2,-8(fp) + 95cc: 10800217 ldw r2,8(r2) + 95d0: 100f883a mov r7,r2 + 95d4: e1bffc17 ldw r6,-16(fp) + 95d8: e17ffd17 ldw r5,-12(fp) + 95dc: 1809883a mov r4,r3 + 95e0: 00096580 call 9658 + 95e4: e037883a mov sp,fp + 95e8: dfc00117 ldw ra,4(sp) + 95ec: df000017 ldw fp,0(sp) + 95f0: dec00204 addi sp,sp,8 + 95f4: f800283a ret + +000095f8 : + 95f8: defffa04 addi sp,sp,-24 + 95fc: dfc00515 stw ra,20(sp) + 9600: df000415 stw fp,16(sp) + 9604: df000404 addi fp,sp,16 + 9608: e13ffe15 stw r4,-8(fp) + 960c: e17ffd15 stw r5,-12(fp) + 9610: e1bffc15 stw r6,-16(fp) + 9614: e0bffe17 ldw r2,-8(fp) + 9618: 10800017 ldw r2,0(r2) + 961c: e0bfff15 stw r2,-4(fp) + 9620: e0bfff17 ldw r2,-4(fp) + 9624: 10c00a04 addi r3,r2,40 + 9628: e0bffe17 ldw r2,-8(fp) + 962c: 10800217 ldw r2,8(r2) + 9630: 100f883a mov r7,r2 + 9634: e1bffc17 ldw r6,-16(fp) + 9638: e17ffd17 ldw r5,-12(fp) + 963c: 1809883a mov r4,r3 + 9640: 00097440 call 9744 + 9644: e037883a mov sp,fp + 9648: dfc00117 ldw ra,4(sp) + 964c: df000017 ldw fp,0(sp) + 9650: dec00204 addi sp,sp,8 + 9654: f800283a ret + +00009658 : + 9658: defff704 addi sp,sp,-36 + 965c: df000815 stw fp,32(sp) + 9660: df000804 addi fp,sp,32 + 9664: e13ffb15 stw r4,-20(fp) + 9668: e17ffa15 stw r5,-24(fp) + 966c: e1bff915 stw r6,-28(fp) + 9670: e1fff815 stw r7,-32(fp) + 9674: e0bffb17 ldw r2,-20(fp) + 9678: 10800017 ldw r2,0(r2) + 967c: e0bffe15 stw r2,-8(fp) + 9680: e0bffa17 ldw r2,-24(fp) + 9684: e0bfff15 stw r2,-4(fp) + 9688: e0bff917 ldw r2,-28(fp) + 968c: e0fffa17 ldw r3,-24(fp) + 9690: 1885883a add r2,r3,r2 + 9694: e0bffd15 stw r2,-12(fp) + 9698: 00001206 br 96e4 + 969c: e0bffe17 ldw r2,-8(fp) + 96a0: 10800037 ldwio r2,0(r2) + 96a4: e0bffc15 stw r2,-16(fp) + 96a8: e0bffc17 ldw r2,-16(fp) + 96ac: 10a0000c andi r2,r2,32768 + 96b0: 10000626 beq r2,zero,96cc + 96b4: e0bfff17 ldw r2,-4(fp) + 96b8: 10c00044 addi r3,r2,1 + 96bc: e0ffff15 stw r3,-4(fp) + 96c0: e0fffc17 ldw r3,-16(fp) + 96c4: 10c00005 stb r3,0(r2) + 96c8: 00000606 br 96e4 + 96cc: e0ffff17 ldw r3,-4(fp) + 96d0: e0bffa17 ldw r2,-24(fp) + 96d4: 1880071e bne r3,r2,96f4 + 96d8: e0bff817 ldw r2,-32(fp) + 96dc: 1090000c andi r2,r2,16384 + 96e0: 1000061e bne r2,zero,96fc + 96e4: e0ffff17 ldw r3,-4(fp) + 96e8: e0bffd17 ldw r2,-12(fp) + 96ec: 18bfeb36 bltu r3,r2,969c + 96f0: 00000306 br 9700 + 96f4: 0001883a nop + 96f8: 00000106 br 9700 + 96fc: 0001883a nop + 9700: e0ffff17 ldw r3,-4(fp) + 9704: e0bffa17 ldw r2,-24(fp) + 9708: 18800426 beq r3,r2,971c + 970c: e0ffff17 ldw r3,-4(fp) + 9710: e0bffa17 ldw r2,-24(fp) + 9714: 1885c83a sub r2,r3,r2 + 9718: 00000606 br 9734 + 971c: e0bff817 ldw r2,-32(fp) + 9720: 1090000c andi r2,r2,16384 + 9724: 10000226 beq r2,zero,9730 + 9728: 00bffd44 movi r2,-11 + 972c: 00000106 br 9734 + 9730: 00bffec4 movi r2,-5 + 9734: e037883a mov sp,fp + 9738: df000017 ldw fp,0(sp) + 973c: dec00104 addi sp,sp,4 + 9740: f800283a ret + +00009744 : + 9744: defff904 addi sp,sp,-28 + 9748: df000615 stw fp,24(sp) + 974c: df000604 addi fp,sp,24 + 9750: e13ffd15 stw r4,-12(fp) + 9754: e17ffc15 stw r5,-16(fp) + 9758: e1bffb15 stw r6,-20(fp) + 975c: e1fffa15 stw r7,-24(fp) + 9760: e0bffd17 ldw r2,-12(fp) + 9764: 10800017 ldw r2,0(r2) + 9768: e0bfff15 stw r2,-4(fp) + 976c: e0bffb17 ldw r2,-20(fp) + 9770: e0fffc17 ldw r3,-16(fp) + 9774: 1885883a add r2,r3,r2 + 9778: e0bffe15 stw r2,-8(fp) + 977c: 00000e06 br 97b8 + 9780: e0bfff17 ldw r2,-4(fp) + 9784: 10800104 addi r2,r2,4 + 9788: 10800037 ldwio r2,0(r2) + 978c: 10bfffec andhi r2,r2,65535 + 9790: 10000926 beq r2,zero,97b8 + 9794: e0ffff17 ldw r3,-4(fp) + 9798: e0bffc17 ldw r2,-16(fp) + 979c: 11000044 addi r4,r2,1 + 97a0: e13ffc15 stw r4,-16(fp) + 97a4: 10800003 ldbu r2,0(r2) + 97a8: 10803fcc andi r2,r2,255 + 97ac: 1080201c xori r2,r2,128 + 97b0: 10bfe004 addi r2,r2,-128 + 97b4: 18800035 stwio r2,0(r3) + 97b8: e0fffc17 ldw r3,-16(fp) + 97bc: e0bffe17 ldw r2,-8(fp) + 97c0: 18bfef36 bltu r3,r2,9780 + 97c4: e0bffb17 ldw r2,-20(fp) + 97c8: e037883a mov sp,fp + 97cc: df000017 ldw fp,0(sp) + 97d0: dec00104 addi sp,sp,4 + 97d4: f800283a ret + +000097d8 : + 97d8: defffa04 addi sp,sp,-24 + 97dc: dfc00515 stw ra,20(sp) + 97e0: df000415 stw fp,16(sp) + 97e4: df000404 addi fp,sp,16 + 97e8: e13ffc15 stw r4,-16(fp) + 97ec: 0007883a mov r3,zero + 97f0: e0bffc17 ldw r2,-16(fp) + 97f4: 10c00035 stwio r3,0(r2) + 97f8: e0bffc17 ldw r2,-16(fp) + 97fc: 10800104 addi r2,r2,4 + 9800: 10800037 ldwio r2,0(r2) + 9804: 0005303a rdctl r2,status + 9808: e0bffd15 stw r2,-12(fp) + 980c: e0fffd17 ldw r3,-12(fp) + 9810: 00bfff84 movi r2,-2 + 9814: 1884703a and r2,r3,r2 + 9818: 1001703a wrctl status,r2 + 981c: e0bffd17 ldw r2,-12(fp) + 9820: e0bfff15 stw r2,-4(fp) + 9824: 00076400 call 7640 + 9828: e0bfff17 ldw r2,-4(fp) + 982c: e0bffe15 stw r2,-8(fp) + 9830: e0bffe17 ldw r2,-8(fp) + 9834: 1001703a wrctl status,r2 + 9838: 0001883a nop + 983c: 0001883a nop + 9840: e037883a mov sp,fp + 9844: dfc00117 ldw ra,4(sp) + 9848: df000017 ldw fp,0(sp) + 984c: dec00204 addi sp,sp,8 + 9850: f800283a ret + +00009854 : + 9854: defff804 addi sp,sp,-32 + 9858: dfc00715 stw ra,28(sp) + 985c: df000615 stw fp,24(sp) + 9860: df000604 addi fp,sp,24 + 9864: e13ffe15 stw r4,-8(fp) + 9868: e17ffd15 stw r5,-12(fp) + 986c: e1bffc15 stw r6,-16(fp) + 9870: e1fffb15 stw r7,-20(fp) + 9874: e0bffb17 ldw r2,-20(fp) + 9878: e0bfff15 stw r2,-4(fp) + 987c: 00800074 movhi r2,1 + 9880: 10b07317 ldw r2,-15924(r2) + 9884: 1000041e bne r2,zero,9898 + 9888: e0ffff17 ldw r3,-4(fp) + 988c: 00800074 movhi r2,1 + 9890: 10f07315 stw r3,-15924(r2) + 9894: 00000106 br 989c + 9898: 0001883a nop + 989c: e0bffe17 ldw r2,-8(fp) + 98a0: 10800104 addi r2,r2,4 + 98a4: 00c001c4 movi r3,7 + 98a8: 10c00035 stwio r3,0(r2) + 98ac: d8000015 stw zero,0(sp) + 98b0: e1fffe17 ldw r7,-8(fp) + 98b4: 01800074 movhi r6,1 + 98b8: 31a5f604 addi r6,r6,-26664 + 98bc: e17ffc17 ldw r5,-16(fp) + 98c0: e13ffd17 ldw r4,-12(fp) + 98c4: 0009df80 call 9df8 + 98c8: 0001883a nop + 98cc: e037883a mov sp,fp + 98d0: dfc00117 ldw ra,4(sp) + 98d4: df000017 ldw fp,0(sp) + 98d8: dec00204 addi sp,sp,8 + 98dc: f800283a ret + +000098e0 : + 98e0: defffa04 addi sp,sp,-24 + 98e4: dfc00515 stw ra,20(sp) + 98e8: df000415 stw fp,16(sp) + 98ec: df000404 addi fp,sp,16 + 98f0: e13ffc15 stw r4,-16(fp) + 98f4: 008000c4 movi r2,3 + 98f8: e0bffe15 stw r2,-8(fp) + 98fc: e0fffe17 ldw r3,-8(fp) + 9900: 008003f4 movhi r2,15 + 9904: 10909004 addi r2,r2,16960 + 9908: 1885383a mul r2,r3,r2 + 990c: 100b883a mov r5,r2 + 9910: 0100bef4 movhi r4,763 + 9914: 213c2004 addi r4,r4,-3968 + 9918: 00044440 call 4444 <__udivsi3> + 991c: 100b883a mov r5,r2 + 9920: 01200034 movhi r4,32768 + 9924: 213fffc4 addi r4,r4,-1 + 9928: 00044440 call 4444 <__udivsi3> + 992c: 100b883a mov r5,r2 + 9930: e13ffc17 ldw r4,-16(fp) + 9934: 00044440 call 4444 <__udivsi3> + 9938: e0bffd15 stw r2,-12(fp) + 993c: e0bffd17 ldw r2,-12(fp) + 9940: 10002a26 beq r2,zero,99ec + 9944: e03fff15 stw zero,-4(fp) + 9948: 00001706 br 99a8 + 994c: 00a00034 movhi r2,32768 + 9950: 10bfffc4 addi r2,r2,-1 + 9954: 10bfffc4 addi r2,r2,-1 + 9958: 103ffe1e bne r2,zero,9954 + 995c: e0fffe17 ldw r3,-8(fp) + 9960: 008003f4 movhi r2,15 + 9964: 10909004 addi r2,r2,16960 + 9968: 1885383a mul r2,r3,r2 + 996c: 100b883a mov r5,r2 + 9970: 0100bef4 movhi r4,763 + 9974: 213c2004 addi r4,r4,-3968 + 9978: 00044440 call 4444 <__udivsi3> + 997c: 100b883a mov r5,r2 + 9980: 01200034 movhi r4,32768 + 9984: 213fffc4 addi r4,r4,-1 + 9988: 00044440 call 4444 <__udivsi3> + 998c: 1007883a mov r3,r2 + 9990: e0bffc17 ldw r2,-16(fp) + 9994: 10c5c83a sub r2,r2,r3 + 9998: e0bffc15 stw r2,-16(fp) + 999c: e0bfff17 ldw r2,-4(fp) + 99a0: 10800044 addi r2,r2,1 + 99a4: e0bfff15 stw r2,-4(fp) + 99a8: e0ffff17 ldw r3,-4(fp) + 99ac: e0bffd17 ldw r2,-12(fp) + 99b0: 18bfe616 blt r3,r2,994c + 99b4: e0fffe17 ldw r3,-8(fp) + 99b8: 008003f4 movhi r2,15 + 99bc: 10909004 addi r2,r2,16960 + 99c0: 1885383a mul r2,r3,r2 + 99c4: 100b883a mov r5,r2 + 99c8: 0100bef4 movhi r4,763 + 99cc: 213c2004 addi r4,r4,-3968 + 99d0: 00044440 call 4444 <__udivsi3> + 99d4: 1007883a mov r3,r2 + 99d8: e0bffc17 ldw r2,-16(fp) + 99dc: 1885383a mul r2,r3,r2 + 99e0: 10bfffc4 addi r2,r2,-1 + 99e4: 103ffe1e bne r2,zero,99e0 + 99e8: 00000d06 br 9a20 + 99ec: e0fffe17 ldw r3,-8(fp) + 99f0: 008003f4 movhi r2,15 + 99f4: 10909004 addi r2,r2,16960 + 99f8: 1885383a mul r2,r3,r2 + 99fc: 100b883a mov r5,r2 + 9a00: 0100bef4 movhi r4,763 + 9a04: 213c2004 addi r4,r4,-3968 + 9a08: 00044440 call 4444 <__udivsi3> + 9a0c: 1007883a mov r3,r2 + 9a10: e0bffc17 ldw r2,-16(fp) + 9a14: 1885383a mul r2,r3,r2 + 9a18: 10bfffc4 addi r2,r2,-1 + 9a1c: 00bffe16 blt zero,r2,9a18 + 9a20: 0005883a mov r2,zero + 9a24: e037883a mov sp,fp + 9a28: dfc00117 ldw ra,4(sp) + 9a2c: df000017 ldw fp,0(sp) + 9a30: dec00204 addi sp,sp,8 + 9a34: f800283a ret + +00009a38 : + 9a38: defffe04 addi sp,sp,-8 + 9a3c: dfc00115 stw ra,4(sp) + 9a40: df000015 stw fp,0(sp) + 9a44: d839883a mov fp,sp + 9a48: 00800074 movhi r2,1 + 9a4c: 10af9f17 ldw r2,-16772(r2) + 9a50: 10000426 beq r2,zero,9a64 + 9a54: 00800074 movhi r2,1 + 9a58: 10af9f17 ldw r2,-16772(r2) + 9a5c: 103ee83a callr r2 + 9a60: 00000206 br 9a6c + 9a64: 00800074 movhi r2,1 + 9a68: 10b06f04 addi r2,r2,-15940 + 9a6c: e037883a mov sp,fp + 9a70: dfc00117 ldw ra,4(sp) + 9a74: df000017 ldw fp,0(sp) + 9a78: dec00204 addi sp,sp,8 + 9a7c: f800283a ret + +00009a80 : + 9a80: defffb04 addi sp,sp,-20 + 9a84: dfc00415 stw ra,16(sp) + 9a88: df000315 stw fp,12(sp) + 9a8c: df000304 addi fp,sp,12 + 9a90: e13ffd15 stw r4,-12(fp) + 9a94: e0bffd17 ldw r2,-12(fp) + 9a98: 10000616 blt r2,zero,9ab4 + 9a9c: e0bffd17 ldw r2,-12(fp) + 9aa0: 10c00324 muli r3,r2,12 + 9aa4: 00800074 movhi r2,1 + 9aa8: 10af3304 addi r2,r2,-17204 + 9aac: 1885883a add r2,r3,r2 + 9ab0: 00000106 br 9ab8 + 9ab4: 0005883a mov r2,zero + 9ab8: e0bfff15 stw r2,-4(fp) + 9abc: e0bfff17 ldw r2,-4(fp) + 9ac0: 10001926 beq r2,zero,9b28 + 9ac4: e0bfff17 ldw r2,-4(fp) + 9ac8: 10800017 ldw r2,0(r2) + 9acc: 10800417 ldw r2,16(r2) + 9ad0: 10000626 beq r2,zero,9aec + 9ad4: e0bfff17 ldw r2,-4(fp) + 9ad8: 10800017 ldw r2,0(r2) + 9adc: 10800417 ldw r2,16(r2) + 9ae0: e13fff17 ldw r4,-4(fp) + 9ae4: 103ee83a callr r2 + 9ae8: 00000106 br 9af0 + 9aec: 0005883a mov r2,zero + 9af0: e0bffe15 stw r2,-8(fp) + 9af4: e13ffd17 ldw r4,-12(fp) + 9af8: 000a68c0 call a68c + 9afc: e0bffe17 ldw r2,-8(fp) + 9b00: 1000070e bge r2,zero,9b20 + 9b04: 0009a380 call 9a38 + 9b08: 1007883a mov r3,r2 + 9b0c: e0bffe17 ldw r2,-8(fp) + 9b10: 0085c83a sub r2,zero,r2 + 9b14: 18800015 stw r2,0(r3) + 9b18: 00bfffc4 movi r2,-1 + 9b1c: 00000706 br 9b3c + 9b20: 0005883a mov r2,zero + 9b24: 00000506 br 9b3c + 9b28: 0009a380 call 9a38 + 9b2c: 1007883a mov r3,r2 + 9b30: 00801444 movi r2,81 + 9b34: 18800015 stw r2,0(r3) + 9b38: 00bfffc4 movi r2,-1 + 9b3c: e037883a mov sp,fp + 9b40: dfc00117 ldw ra,4(sp) + 9b44: df000017 ldw fp,0(sp) + 9b48: dec00204 addi sp,sp,8 + 9b4c: f800283a ret + +00009b50 : + 9b50: defffc04 addi sp,sp,-16 + 9b54: df000315 stw fp,12(sp) + 9b58: df000304 addi fp,sp,12 + 9b5c: e13fff15 stw r4,-4(fp) + 9b60: e17ffe15 stw r5,-8(fp) + 9b64: e1bffd15 stw r6,-12(fp) + 9b68: e0bffd17 ldw r2,-12(fp) + 9b6c: e037883a mov sp,fp + 9b70: df000017 ldw fp,0(sp) + 9b74: dec00104 addi sp,sp,4 + 9b78: f800283a ret + +00009b7c : + 9b7c: defffe04 addi sp,sp,-8 + 9b80: dfc00115 stw ra,4(sp) + 9b84: df000015 stw fp,0(sp) + 9b88: d839883a mov fp,sp + 9b8c: 00800074 movhi r2,1 + 9b90: 10af9f17 ldw r2,-16772(r2) + 9b94: 10000426 beq r2,zero,9ba8 + 9b98: 00800074 movhi r2,1 + 9b9c: 10af9f17 ldw r2,-16772(r2) + 9ba0: 103ee83a callr r2 + 9ba4: 00000206 br 9bb0 + 9ba8: 00800074 movhi r2,1 + 9bac: 10b06f04 addi r2,r2,-15940 + 9bb0: e037883a mov sp,fp + 9bb4: dfc00117 ldw ra,4(sp) + 9bb8: df000017 ldw fp,0(sp) + 9bbc: dec00204 addi sp,sp,8 + 9bc0: f800283a ret + +00009bc4 : + 9bc4: defffa04 addi sp,sp,-24 + 9bc8: dfc00515 stw ra,20(sp) + 9bcc: df000415 stw fp,16(sp) + 9bd0: df000404 addi fp,sp,16 + 9bd4: e13ffd15 stw r4,-12(fp) + 9bd8: e17ffc15 stw r5,-16(fp) + 9bdc: e0bffd17 ldw r2,-12(fp) + 9be0: 10000326 beq r2,zero,9bf0 + 9be4: e0bffd17 ldw r2,-12(fp) + 9be8: 10800217 ldw r2,8(r2) + 9bec: 1000061e bne r2,zero,9c08 + 9bf0: 0009b7c0 call 9b7c + 9bf4: 1007883a mov r3,r2 + 9bf8: 00800584 movi r2,22 + 9bfc: 18800015 stw r2,0(r3) + 9c00: 00bffa84 movi r2,-22 + 9c04: 00001406 br 9c58 + 9c08: e0bffd17 ldw r2,-12(fp) + 9c0c: e0fffc17 ldw r3,-16(fp) + 9c10: e0ffff15 stw r3,-4(fp) + 9c14: e0bffe15 stw r2,-8(fp) + 9c18: e0bffe17 ldw r2,-8(fp) + 9c1c: e0ffff17 ldw r3,-4(fp) + 9c20: 10c00115 stw r3,4(r2) + 9c24: e0bfff17 ldw r2,-4(fp) + 9c28: 10c00017 ldw r3,0(r2) + 9c2c: e0bffe17 ldw r2,-8(fp) + 9c30: 10c00015 stw r3,0(r2) + 9c34: e0bfff17 ldw r2,-4(fp) + 9c38: 10800017 ldw r2,0(r2) + 9c3c: e0fffe17 ldw r3,-8(fp) + 9c40: 10c00115 stw r3,4(r2) + 9c44: e0bfff17 ldw r2,-4(fp) + 9c48: e0fffe17 ldw r3,-8(fp) + 9c4c: 10c00015 stw r3,0(r2) + 9c50: 0001883a nop + 9c54: 0005883a mov r2,zero + 9c58: e037883a mov sp,fp + 9c5c: dfc00117 ldw ra,4(sp) + 9c60: df000017 ldw fp,0(sp) + 9c64: dec00204 addi sp,sp,8 + 9c68: f800283a ret + +00009c6c <_do_ctors>: + 9c6c: defffd04 addi sp,sp,-12 + 9c70: dfc00215 stw ra,8(sp) + 9c74: df000115 stw fp,4(sp) + 9c78: df000104 addi fp,sp,4 + 9c7c: 00800074 movhi r2,1 + 9c80: 10ab3204 addi r2,r2,-21304 + 9c84: e0bfff15 stw r2,-4(fp) + 9c88: 00000606 br 9ca4 <_do_ctors+0x38> + 9c8c: e0bfff17 ldw r2,-4(fp) + 9c90: 10800017 ldw r2,0(r2) + 9c94: 103ee83a callr r2 + 9c98: e0bfff17 ldw r2,-4(fp) + 9c9c: 10bfff04 addi r2,r2,-4 + 9ca0: e0bfff15 stw r2,-4(fp) + 9ca4: e0ffff17 ldw r3,-4(fp) + 9ca8: 00800074 movhi r2,1 + 9cac: 10ab3304 addi r2,r2,-21300 + 9cb0: 18bff62e bgeu r3,r2,9c8c <_do_ctors+0x20> + 9cb4: 0001883a nop + 9cb8: 0001883a nop + 9cbc: e037883a mov sp,fp + 9cc0: dfc00117 ldw ra,4(sp) + 9cc4: df000017 ldw fp,0(sp) + 9cc8: dec00204 addi sp,sp,8 + 9ccc: f800283a ret + +00009cd0 <_do_dtors>: + 9cd0: defffd04 addi sp,sp,-12 + 9cd4: dfc00215 stw ra,8(sp) + 9cd8: df000115 stw fp,4(sp) + 9cdc: df000104 addi fp,sp,4 + 9ce0: 00800074 movhi r2,1 + 9ce4: 10ab3204 addi r2,r2,-21304 + 9ce8: e0bfff15 stw r2,-4(fp) + 9cec: 00000606 br 9d08 <_do_dtors+0x38> + 9cf0: e0bfff17 ldw r2,-4(fp) + 9cf4: 10800017 ldw r2,0(r2) + 9cf8: 103ee83a callr r2 + 9cfc: e0bfff17 ldw r2,-4(fp) + 9d00: 10bfff04 addi r2,r2,-4 + 9d04: e0bfff15 stw r2,-4(fp) + 9d08: e0ffff17 ldw r3,-4(fp) + 9d0c: 00800074 movhi r2,1 + 9d10: 10ab3304 addi r2,r2,-21300 + 9d14: 18bff62e bgeu r3,r2,9cf0 <_do_dtors+0x20> + 9d18: 0001883a nop + 9d1c: 0001883a nop + 9d20: e037883a mov sp,fp + 9d24: dfc00117 ldw ra,4(sp) + 9d28: df000017 ldw fp,0(sp) + 9d2c: dec00204 addi sp,sp,8 + 9d30: f800283a ret + +00009d34 : + 9d34: defffa04 addi sp,sp,-24 + 9d38: dfc00515 stw ra,20(sp) + 9d3c: df000415 stw fp,16(sp) + 9d40: df000404 addi fp,sp,16 + 9d44: e13ffd15 stw r4,-12(fp) + 9d48: e17ffc15 stw r5,-16(fp) + 9d4c: e0bffc17 ldw r2,-16(fp) + 9d50: 10800017 ldw r2,0(r2) + 9d54: e0bfff15 stw r2,-4(fp) + 9d58: e13ffd17 ldw r4,-12(fp) + 9d5c: 0006cc00 call 6cc0 + 9d60: 10800044 addi r2,r2,1 + 9d64: e0bffe15 stw r2,-8(fp) + 9d68: 00000d06 br 9da0 + 9d6c: e0bfff17 ldw r2,-4(fp) + 9d70: 10800217 ldw r2,8(r2) + 9d74: e0fffe17 ldw r3,-8(fp) + 9d78: 180d883a mov r6,r3 + 9d7c: e17ffd17 ldw r5,-12(fp) + 9d80: 1009883a mov r4,r2 + 9d84: 000aa1c0 call aa1c + 9d88: 1000021e bne r2,zero,9d94 + 9d8c: e0bfff17 ldw r2,-4(fp) + 9d90: 00000706 br 9db0 + 9d94: e0bfff17 ldw r2,-4(fp) + 9d98: 10800017 ldw r2,0(r2) + 9d9c: e0bfff15 stw r2,-4(fp) + 9da0: e0ffff17 ldw r3,-4(fp) + 9da4: e0bffc17 ldw r2,-16(fp) + 9da8: 18bff01e bne r3,r2,9d6c + 9dac: 0005883a mov r2,zero + 9db0: e037883a mov sp,fp + 9db4: dfc00117 ldw ra,4(sp) + 9db8: df000017 ldw fp,0(sp) + 9dbc: dec00204 addi sp,sp,8 + 9dc0: f800283a ret + +00009dc4 : + 9dc4: defffe04 addi sp,sp,-8 + 9dc8: dfc00115 stw ra,4(sp) + 9dcc: df000015 stw fp,0(sp) + 9dd0: d839883a mov fp,sp + 9dd4: 01440004 movi r5,4096 + 9dd8: 0009883a mov r4,zero + 9ddc: 000a8c00 call a8c0 + 9de0: 0001883a nop + 9de4: e037883a mov sp,fp + 9de8: dfc00117 ldw ra,4(sp) + 9dec: df000017 ldw fp,0(sp) + 9df0: dec00204 addi sp,sp,8 + 9df4: f800283a ret + +00009df8 : + 9df8: defff904 addi sp,sp,-28 + 9dfc: dfc00615 stw ra,24(sp) + 9e00: df000515 stw fp,20(sp) + 9e04: df000504 addi fp,sp,20 + 9e08: e13fff15 stw r4,-4(fp) + 9e0c: e17ffe15 stw r5,-8(fp) + 9e10: e1bffd15 stw r6,-12(fp) + 9e14: e1fffc15 stw r7,-16(fp) + 9e18: e0800217 ldw r2,8(fp) + 9e1c: d8800015 stw r2,0(sp) + 9e20: e1fffc17 ldw r7,-16(fp) + 9e24: e1bffd17 ldw r6,-12(fp) + 9e28: e17ffe17 ldw r5,-8(fp) + 9e2c: e13fff17 ldw r4,-4(fp) + 9e30: 0009fc00 call 9fc0 + 9e34: e037883a mov sp,fp + 9e38: dfc00117 ldw ra,4(sp) + 9e3c: df000017 ldw fp,0(sp) + 9e40: dec00204 addi sp,sp,8 + 9e44: f800283a ret + +00009e48 : + 9e48: defff904 addi sp,sp,-28 + 9e4c: df000615 stw fp,24(sp) + 9e50: df000604 addi fp,sp,24 + 9e54: e13ffb15 stw r4,-20(fp) + 9e58: e17ffa15 stw r5,-24(fp) + 9e5c: e0bffa17 ldw r2,-24(fp) + 9e60: e0bfff15 stw r2,-4(fp) + 9e64: 0005303a rdctl r2,status + 9e68: e0bffe15 stw r2,-8(fp) + 9e6c: e0fffe17 ldw r3,-8(fp) + 9e70: 00bfff84 movi r2,-2 + 9e74: 1884703a and r2,r3,r2 + 9e78: 1001703a wrctl status,r2 + 9e7c: e0bffe17 ldw r2,-8(fp) + 9e80: e0bffd15 stw r2,-12(fp) + 9e84: 00c00044 movi r3,1 + 9e88: e0bfff17 ldw r2,-4(fp) + 9e8c: 1884983a sll r2,r3,r2 + 9e90: 1007883a mov r3,r2 + 9e94: 00800074 movhi r2,1 + 9e98: 10b07517 ldw r2,-15916(r2) + 9e9c: 1886b03a or r3,r3,r2 + 9ea0: 00800074 movhi r2,1 + 9ea4: 10f07515 stw r3,-15916(r2) + 9ea8: 00800074 movhi r2,1 + 9eac: 10b07517 ldw r2,-15916(r2) + 9eb0: 100170fa wrctl ienable,r2 + 9eb4: e0bffd17 ldw r2,-12(fp) + 9eb8: e0bffc15 stw r2,-16(fp) + 9ebc: e0bffc17 ldw r2,-16(fp) + 9ec0: 1001703a wrctl status,r2 + 9ec4: 0001883a nop + 9ec8: 0005883a mov r2,zero + 9ecc: e037883a mov sp,fp + 9ed0: df000017 ldw fp,0(sp) + 9ed4: dec00104 addi sp,sp,4 + 9ed8: f800283a ret + +00009edc : + 9edc: defff904 addi sp,sp,-28 + 9ee0: df000615 stw fp,24(sp) + 9ee4: df000604 addi fp,sp,24 + 9ee8: e13ffb15 stw r4,-20(fp) + 9eec: e17ffa15 stw r5,-24(fp) + 9ef0: e0bffa17 ldw r2,-24(fp) + 9ef4: e0bfff15 stw r2,-4(fp) + 9ef8: 0005303a rdctl r2,status + 9efc: e0bffe15 stw r2,-8(fp) + 9f00: e0fffe17 ldw r3,-8(fp) + 9f04: 00bfff84 movi r2,-2 + 9f08: 1884703a and r2,r3,r2 + 9f0c: 1001703a wrctl status,r2 + 9f10: e0bffe17 ldw r2,-8(fp) + 9f14: e0bffd15 stw r2,-12(fp) + 9f18: 00c00044 movi r3,1 + 9f1c: e0bfff17 ldw r2,-4(fp) + 9f20: 1884983a sll r2,r3,r2 + 9f24: 0084303a nor r2,zero,r2 + 9f28: 1007883a mov r3,r2 + 9f2c: 00800074 movhi r2,1 + 9f30: 10b07517 ldw r2,-15916(r2) + 9f34: 1886703a and r3,r3,r2 + 9f38: 00800074 movhi r2,1 + 9f3c: 10f07515 stw r3,-15916(r2) + 9f40: 00800074 movhi r2,1 + 9f44: 10b07517 ldw r2,-15916(r2) + 9f48: 100170fa wrctl ienable,r2 + 9f4c: e0bffd17 ldw r2,-12(fp) + 9f50: e0bffc15 stw r2,-16(fp) + 9f54: e0bffc17 ldw r2,-16(fp) + 9f58: 1001703a wrctl status,r2 + 9f5c: 0001883a nop + 9f60: 0005883a mov r2,zero + 9f64: e037883a mov sp,fp + 9f68: df000017 ldw fp,0(sp) + 9f6c: dec00104 addi sp,sp,4 + 9f70: f800283a ret + +00009f74 : + 9f74: defffc04 addi sp,sp,-16 + 9f78: df000315 stw fp,12(sp) + 9f7c: df000304 addi fp,sp,12 + 9f80: e13ffe15 stw r4,-8(fp) + 9f84: e17ffd15 stw r5,-12(fp) + 9f88: 000530fa rdctl r2,ienable + 9f8c: e0bfff15 stw r2,-4(fp) + 9f90: 00c00044 movi r3,1 + 9f94: e0bffd17 ldw r2,-12(fp) + 9f98: 1884983a sll r2,r3,r2 + 9f9c: 1007883a mov r3,r2 + 9fa0: e0bfff17 ldw r2,-4(fp) + 9fa4: 1884703a and r2,r3,r2 + 9fa8: 1004c03a cmpne r2,r2,zero + 9fac: 10803fcc andi r2,r2,255 + 9fb0: e037883a mov sp,fp + 9fb4: df000017 ldw fp,0(sp) + 9fb8: dec00104 addi sp,sp,4 + 9fbc: f800283a ret + +00009fc0 : + 9fc0: defff504 addi sp,sp,-44 + 9fc4: dfc00a15 stw ra,40(sp) + 9fc8: df000915 stw fp,36(sp) + 9fcc: df000904 addi fp,sp,36 + 9fd0: e13ffa15 stw r4,-24(fp) + 9fd4: e17ff915 stw r5,-28(fp) + 9fd8: e1bff815 stw r6,-32(fp) + 9fdc: e1fff715 stw r7,-36(fp) + 9fe0: 00bffa84 movi r2,-22 + 9fe4: e0bfff15 stw r2,-4(fp) + 9fe8: e0bff917 ldw r2,-28(fp) + 9fec: e0bffe15 stw r2,-8(fp) + 9ff0: e0bffe17 ldw r2,-8(fp) + 9ff4: 10800808 cmpgei r2,r2,32 + 9ff8: 1000251e bne r2,zero,a090 + 9ffc: 0005303a rdctl r2,status + a000: e0bffc15 stw r2,-16(fp) + a004: e0fffc17 ldw r3,-16(fp) + a008: 00bfff84 movi r2,-2 + a00c: 1884703a and r2,r3,r2 + a010: 1001703a wrctl status,r2 + a014: e0bffc17 ldw r2,-16(fp) + a018: e0bffd15 stw r2,-12(fp) + a01c: e0bffe17 ldw r2,-8(fp) + a020: 100890fa slli r4,r2,3 + a024: e0fff817 ldw r3,-32(fp) + a028: 00800074 movhi r2,1 + a02c: 2085883a add r2,r4,r2 + a030: 10f47815 stw r3,-11808(r2) + a034: e0bffe17 ldw r2,-8(fp) + a038: 100890fa slli r4,r2,3 + a03c: e0fff717 ldw r3,-36(fp) + a040: 00800074 movhi r2,1 + a044: 2085883a add r2,r4,r2 + a048: 10f47915 stw r3,-11804(r2) + a04c: e0bff817 ldw r2,-32(fp) + a050: 10000526 beq r2,zero,a068 + a054: e0bffe17 ldw r2,-8(fp) + a058: 100b883a mov r5,r2 + a05c: e13ffa17 ldw r4,-24(fp) + a060: 0009e480 call 9e48 + a064: 00000406 br a078 + a068: e0bffe17 ldw r2,-8(fp) + a06c: 100b883a mov r5,r2 + a070: e13ffa17 ldw r4,-24(fp) + a074: 0009edc0 call 9edc + a078: e0bfff15 stw r2,-4(fp) + a07c: e0bffd17 ldw r2,-12(fp) + a080: e0bffb15 stw r2,-20(fp) + a084: e0bffb17 ldw r2,-20(fp) + a088: 1001703a wrctl status,r2 + a08c: 0001883a nop + a090: e0bfff17 ldw r2,-4(fp) + a094: e037883a mov sp,fp + a098: dfc00117 ldw ra,4(sp) + a09c: df000017 ldw fp,0(sp) + a0a0: dec00204 addi sp,sp,8 + a0a4: f800283a ret + +0000a0a8 : + a0a8: defff904 addi sp,sp,-28 + a0ac: dfc00615 stw ra,24(sp) + a0b0: df000515 stw fp,20(sp) + a0b4: df000504 addi fp,sp,20 + a0b8: e13ffe15 stw r4,-8(fp) + a0bc: e17ffd15 stw r5,-12(fp) + a0c0: e1bffc15 stw r6,-16(fp) + a0c4: e1fffb15 stw r7,-20(fp) + a0c8: e1bffb17 ldw r6,-20(fp) + a0cc: e17ffc17 ldw r5,-16(fp) + a0d0: e13ffd17 ldw r4,-12(fp) + a0d4: 000a2d80 call a2d8 + a0d8: e0bfff15 stw r2,-4(fp) + a0dc: e0bfff17 ldw r2,-4(fp) + a0e0: 10001716 blt r2,zero,a140 + a0e4: e0bfff17 ldw r2,-4(fp) + a0e8: 10c00324 muli r3,r2,12 + a0ec: 00800074 movhi r2,1 + a0f0: 1885883a add r2,r3,r2 + a0f4: 10ef3317 ldw r3,-17204(r2) + a0f8: e0bffe17 ldw r2,-8(fp) + a0fc: 10c00015 stw r3,0(r2) + a100: e0bfff17 ldw r2,-4(fp) + a104: 10c00324 muli r3,r2,12 + a108: 00800074 movhi r2,1 + a10c: 1885883a add r2,r3,r2 + a110: 10ef3417 ldw r3,-17200(r2) + a114: e0bffe17 ldw r2,-8(fp) + a118: 10c00115 stw r3,4(r2) + a11c: e0bfff17 ldw r2,-4(fp) + a120: 10c00324 muli r3,r2,12 + a124: 00800074 movhi r2,1 + a128: 1885883a add r2,r3,r2 + a12c: 10ef3517 ldw r3,-17196(r2) + a130: e0bffe17 ldw r2,-8(fp) + a134: 10c00215 stw r3,8(r2) + a138: e13fff17 ldw r4,-4(fp) + a13c: 000a68c0 call a68c + a140: 0001883a nop + a144: e037883a mov sp,fp + a148: dfc00117 ldw ra,4(sp) + a14c: df000017 ldw fp,0(sp) + a150: dec00204 addi sp,sp,8 + a154: f800283a ret + +0000a158 : + a158: defffb04 addi sp,sp,-20 + a15c: dfc00415 stw ra,16(sp) + a160: df000315 stw fp,12(sp) + a164: df000304 addi fp,sp,12 + a168: e13fff15 stw r4,-4(fp) + a16c: e17ffe15 stw r5,-8(fp) + a170: e1bffd15 stw r6,-12(fp) + a174: 01c07fc4 movi r7,511 + a178: 01800044 movi r6,1 + a17c: e17fff17 ldw r5,-4(fp) + a180: 01000074 movhi r4,1 + a184: 212f3604 addi r4,r4,-17192 + a188: 000a0a80 call a0a8 + a18c: 01c07fc4 movi r7,511 + a190: 000d883a mov r6,zero + a194: e17ffe17 ldw r5,-8(fp) + a198: 01000074 movhi r4,1 + a19c: 212f3304 addi r4,r4,-17204 + a1a0: 000a0a80 call a0a8 + a1a4: 01c07fc4 movi r7,511 + a1a8: 01800044 movi r6,1 + a1ac: e17ffd17 ldw r5,-12(fp) + a1b0: 01000074 movhi r4,1 + a1b4: 212f3904 addi r4,r4,-17180 + a1b8: 000a0a80 call a0a8 + a1bc: 0001883a nop + a1c0: e037883a mov sp,fp + a1c4: dfc00117 ldw ra,4(sp) + a1c8: df000017 ldw fp,0(sp) + a1cc: dec00204 addi sp,sp,8 + a1d0: f800283a ret + +0000a1d4 : + a1d4: defffe04 addi sp,sp,-8 + a1d8: dfc00115 stw ra,4(sp) + a1dc: df000015 stw fp,0(sp) + a1e0: d839883a mov fp,sp + a1e4: 00800074 movhi r2,1 + a1e8: 10af9f17 ldw r2,-16772(r2) + a1ec: 10000426 beq r2,zero,a200 + a1f0: 00800074 movhi r2,1 + a1f4: 10af9f17 ldw r2,-16772(r2) + a1f8: 103ee83a callr r2 + a1fc: 00000206 br a208 + a200: 00800074 movhi r2,1 + a204: 10b06f04 addi r2,r2,-15940 + a208: e037883a mov sp,fp + a20c: dfc00117 ldw ra,4(sp) + a210: df000017 ldw fp,0(sp) + a214: dec00204 addi sp,sp,8 + a218: f800283a ret + +0000a21c : + a21c: defffd04 addi sp,sp,-12 + a220: df000215 stw fp,8(sp) + a224: df000204 addi fp,sp,8 + a228: e13ffe15 stw r4,-8(fp) + a22c: e0bffe17 ldw r2,-8(fp) + a230: 10800217 ldw r2,8(r2) + a234: 10d00034 orhi r3,r2,16384 + a238: e0bffe17 ldw r2,-8(fp) + a23c: 10c00215 stw r3,8(r2) + a240: e03fff15 stw zero,-4(fp) + a244: 00001a06 br a2b0 + a248: e0bfff17 ldw r2,-4(fp) + a24c: 10c00324 muli r3,r2,12 + a250: 00800074 movhi r2,1 + a254: 1885883a add r2,r3,r2 + a258: 10ef3317 ldw r3,-17204(r2) + a25c: e0bffe17 ldw r2,-8(fp) + a260: 10800017 ldw r2,0(r2) + a264: 18800f1e bne r3,r2,a2a4 + a268: e0bfff17 ldw r2,-4(fp) + a26c: 10c00324 muli r3,r2,12 + a270: 00800074 movhi r2,1 + a274: 1885883a add r2,r3,r2 + a278: 10af3517 ldw r2,-17196(r2) + a27c: 1000090e bge r2,zero,a2a4 + a280: e0bfff17 ldw r2,-4(fp) + a284: 10c00324 muli r3,r2,12 + a288: 00800074 movhi r2,1 + a28c: 10af3304 addi r2,r2,-17204 + a290: 1885883a add r2,r3,r2 + a294: e0fffe17 ldw r3,-8(fp) + a298: 18800226 beq r3,r2,a2a4 + a29c: 00bffcc4 movi r2,-13 + a2a0: 00000906 br a2c8 + a2a4: e0bfff17 ldw r2,-4(fp) + a2a8: 10800044 addi r2,r2,1 + a2ac: e0bfff15 stw r2,-4(fp) + a2b0: 00800074 movhi r2,1 + a2b4: 10af9e17 ldw r2,-16776(r2) + a2b8: 1007883a mov r3,r2 + a2bc: e0bfff17 ldw r2,-4(fp) + a2c0: 18bfe12e bgeu r3,r2,a248 + a2c4: 0005883a mov r2,zero + a2c8: e037883a mov sp,fp + a2cc: df000017 ldw fp,0(sp) + a2d0: dec00104 addi sp,sp,4 + a2d4: f800283a ret + +0000a2d8 : + a2d8: defff604 addi sp,sp,-40 + a2dc: dfc00915 stw ra,36(sp) + a2e0: df000815 stw fp,32(sp) + a2e4: df000804 addi fp,sp,32 + a2e8: e13ffa15 stw r4,-24(fp) + a2ec: e17ff915 stw r5,-28(fp) + a2f0: e1bff815 stw r6,-32(fp) + a2f4: 00bfffc4 movi r2,-1 + a2f8: e0bffe15 stw r2,-8(fp) + a2fc: 00bffb44 movi r2,-19 + a300: e0bffd15 stw r2,-12(fp) + a304: e03ffc15 stw zero,-16(fp) + a308: 01400074 movhi r5,1 + a30c: 296f9c04 addi r5,r5,-16784 + a310: e13ffa17 ldw r4,-24(fp) + a314: 0009d340 call 9d34 + a318: e0bfff15 stw r2,-4(fp) + a31c: e0bfff17 ldw r2,-4(fp) + a320: 1000051e bne r2,zero,a338 + a324: e13ffa17 ldw r4,-24(fp) + a328: 000a7080 call a708 + a32c: e0bfff15 stw r2,-4(fp) + a330: 00800044 movi r2,1 + a334: e0bffc15 stw r2,-16(fp) + a338: e0bfff17 ldw r2,-4(fp) + a33c: 10002926 beq r2,zero,a3e4 + a340: e13fff17 ldw r4,-4(fp) + a344: 000a8180 call a818 + a348: e0bffe15 stw r2,-8(fp) + a34c: e0bffe17 ldw r2,-8(fp) + a350: 1000030e bge r2,zero,a360 + a354: e0bffe17 ldw r2,-8(fp) + a358: e0bffd15 stw r2,-12(fp) + a35c: 00002306 br a3ec + a360: e0bffe17 ldw r2,-8(fp) + a364: 10c00324 muli r3,r2,12 + a368: 00800074 movhi r2,1 + a36c: 10af3304 addi r2,r2,-17204 + a370: 1885883a add r2,r3,r2 + a374: e0bffb15 stw r2,-20(fp) + a378: e0fff917 ldw r3,-28(fp) + a37c: 00900034 movhi r2,16384 + a380: 10bfffc4 addi r2,r2,-1 + a384: 1886703a and r3,r3,r2 + a388: e0bffb17 ldw r2,-20(fp) + a38c: 10c00215 stw r3,8(r2) + a390: e0bffc17 ldw r2,-16(fp) + a394: 1000051e bne r2,zero,a3ac + a398: e13ffb17 ldw r4,-20(fp) + a39c: 000a21c0 call a21c + a3a0: e0bffd15 stw r2,-12(fp) + a3a4: e0bffd17 ldw r2,-12(fp) + a3a8: 10001016 blt r2,zero,a3ec + a3ac: e0bfff17 ldw r2,-4(fp) + a3b0: 10800317 ldw r2,12(r2) + a3b4: 10000826 beq r2,zero,a3d8 + a3b8: e0bfff17 ldw r2,-4(fp) + a3bc: 10800317 ldw r2,12(r2) + a3c0: e1fff817 ldw r7,-32(fp) + a3c4: e1bff917 ldw r6,-28(fp) + a3c8: e17ffa17 ldw r5,-24(fp) + a3cc: e13ffb17 ldw r4,-20(fp) + a3d0: 103ee83a callr r2 + a3d4: 00000106 br a3dc + a3d8: 0005883a mov r2,zero + a3dc: e0bffd15 stw r2,-12(fp) + a3e0: 00000206 br a3ec + a3e4: 00bffb44 movi r2,-19 + a3e8: e0bffd15 stw r2,-12(fp) + a3ec: e0bffd17 ldw r2,-12(fp) + a3f0: 1000090e bge r2,zero,a418 + a3f4: e13ffe17 ldw r4,-8(fp) + a3f8: 000a68c0 call a68c + a3fc: 000a1d40 call a1d4 + a400: 1007883a mov r3,r2 + a404: e0bffd17 ldw r2,-12(fp) + a408: 0085c83a sub r2,zero,r2 + a40c: 18800015 stw r2,0(r3) + a410: 00bfffc4 movi r2,-1 + a414: 00000106 br a41c + a418: e0bffe17 ldw r2,-8(fp) + a41c: e037883a mov sp,fp + a420: dfc00117 ldw ra,4(sp) + a424: df000017 ldw fp,0(sp) + a428: dec00204 addi sp,sp,8 + a42c: f800283a ret + +0000a430 : + a430: defff204 addi sp,sp,-56 + a434: dfc00a15 stw ra,40(sp) + a438: df000915 stw fp,36(sp) + a43c: df000904 addi fp,sp,36 + a440: e13ff715 stw r4,-36(fp) + a444: e1400215 stw r5,8(fp) + a448: e1800315 stw r6,12(fp) + a44c: e1c00415 stw r7,16(fp) + a450: e0800204 addi r2,fp,8 + a454: e0bff815 stw r2,-32(fp) + a458: e0bff717 ldw r2,-36(fp) + a45c: e0bfff15 stw r2,-4(fp) + a460: 00006f06 br a620 + a464: e0bffec7 ldb r2,-5(fp) + a468: 10800960 cmpeqi r2,r2,37 + a46c: 1000041e bne r2,zero,a480 + a470: e0bffec7 ldb r2,-5(fp) + a474: 1009883a mov r4,r2 + a478: 000a65c0 call a65c + a47c: 00006806 br a620 + a480: e0bfff17 ldw r2,-4(fp) + a484: 10c00044 addi r3,r2,1 + a488: e0ffff15 stw r3,-4(fp) + a48c: 10800003 ldbu r2,0(r2) + a490: e0bffec5 stb r2,-5(fp) + a494: e0bffec7 ldb r2,-5(fp) + a498: 10006926 beq r2,zero,a640 + a49c: e0bffec7 ldb r2,-5(fp) + a4a0: 10800958 cmpnei r2,r2,37 + a4a4: 1000041e bne r2,zero,a4b8 + a4a8: e0bffec7 ldb r2,-5(fp) + a4ac: 1009883a mov r4,r2 + a4b0: 000a65c0 call a65c + a4b4: 00005a06 br a620 + a4b8: e0bffec7 ldb r2,-5(fp) + a4bc: 108018d8 cmpnei r2,r2,99 + a4c0: 1000081e bne r2,zero,a4e4 + a4c4: e0bff817 ldw r2,-32(fp) + a4c8: 10c00104 addi r3,r2,4 + a4cc: e0fff815 stw r3,-32(fp) + a4d0: 10800017 ldw r2,0(r2) + a4d4: e0bff915 stw r2,-28(fp) + a4d8: e13ff917 ldw r4,-28(fp) + a4dc: 000a65c0 call a65c + a4e0: 00004f06 br a620 + a4e4: e0bffec7 ldb r2,-5(fp) + a4e8: 10801e18 cmpnei r2,r2,120 + a4ec: 1000341e bne r2,zero,a5c0 + a4f0: e0bff817 ldw r2,-32(fp) + a4f4: 10c00104 addi r3,r2,4 + a4f8: e0fff815 stw r3,-32(fp) + a4fc: 10800017 ldw r2,0(r2) + a500: e0bffb15 stw r2,-20(fp) + a504: e0bffb17 ldw r2,-20(fp) + a508: 1000031e bne r2,zero,a518 + a50c: 01000c04 movi r4,48 + a510: 000a65c0 call a65c + a514: 00004206 br a620 + a518: 00800704 movi r2,28 + a51c: e0bffd15 stw r2,-12(fp) + a520: 00000306 br a530 + a524: e0bffd17 ldw r2,-12(fp) + a528: 10bfff04 addi r2,r2,-4 + a52c: e0bffd15 stw r2,-12(fp) + a530: 00c003c4 movi r3,15 + a534: e0bffd17 ldw r2,-12(fp) + a538: 1884983a sll r2,r3,r2 + a53c: 1007883a mov r3,r2 + a540: e0bffb17 ldw r2,-20(fp) + a544: 1884703a and r2,r3,r2 + a548: 103ff626 beq r2,zero,a524 + a54c: 00001906 br a5b4 + a550: 00c003c4 movi r3,15 + a554: e0bffd17 ldw r2,-12(fp) + a558: 1884983a sll r2,r3,r2 + a55c: 1007883a mov r3,r2 + a560: e0bffb17 ldw r2,-20(fp) + a564: 1886703a and r3,r3,r2 + a568: e0bffd17 ldw r2,-12(fp) + a56c: 1884d83a srl r2,r3,r2 + a570: e0bffa15 stw r2,-24(fp) + a574: e0bffa17 ldw r2,-24(fp) + a578: 108002a8 cmpgeui r2,r2,10 + a57c: 1000041e bne r2,zero,a590 + a580: e0bffa17 ldw r2,-24(fp) + a584: 10800c04 addi r2,r2,48 + a588: e0bffec5 stb r2,-5(fp) + a58c: 00000306 br a59c + a590: e0bffa17 ldw r2,-24(fp) + a594: 108015c4 addi r2,r2,87 + a598: e0bffec5 stb r2,-5(fp) + a59c: e0bffec7 ldb r2,-5(fp) + a5a0: 1009883a mov r4,r2 + a5a4: 000a65c0 call a65c + a5a8: e0bffd17 ldw r2,-12(fp) + a5ac: 10bfff04 addi r2,r2,-4 + a5b0: e0bffd15 stw r2,-12(fp) + a5b4: e0bffd17 ldw r2,-12(fp) + a5b8: 103fe50e bge r2,zero,a550 + a5bc: 00001806 br a620 + a5c0: e0bffec7 ldb r2,-5(fp) + a5c4: 10801cd8 cmpnei r2,r2,115 + a5c8: 1000151e bne r2,zero,a620 + a5cc: e0bff817 ldw r2,-32(fp) + a5d0: 10c00104 addi r3,r2,4 + a5d4: e0fff815 stw r3,-32(fp) + a5d8: 10800017 ldw r2,0(r2) + a5dc: e0bffc15 stw r2,-16(fp) + a5e0: 00000906 br a608 + a5e4: e0bffc17 ldw r2,-16(fp) + a5e8: 10c00044 addi r3,r2,1 + a5ec: e0fffc15 stw r3,-16(fp) + a5f0: 10800003 ldbu r2,0(r2) + a5f4: 10803fcc andi r2,r2,255 + a5f8: 1080201c xori r2,r2,128 + a5fc: 10bfe004 addi r2,r2,-128 + a600: 1009883a mov r4,r2 + a604: 000a65c0 call a65c + a608: e0bffc17 ldw r2,-16(fp) + a60c: 10800003 ldbu r2,0(r2) + a610: 10803fcc andi r2,r2,255 + a614: 1080201c xori r2,r2,128 + a618: 10bfe004 addi r2,r2,-128 + a61c: 103ff11e bne r2,zero,a5e4 + a620: e0bfff17 ldw r2,-4(fp) + a624: 10c00044 addi r3,r2,1 + a628: e0ffff15 stw r3,-4(fp) + a62c: 10800003 ldbu r2,0(r2) + a630: e0bffec5 stb r2,-5(fp) + a634: e0bffec7 ldb r2,-5(fp) + a638: 103f8a1e bne r2,zero,a464 + a63c: 00000106 br a644 + a640: 0001883a nop + a644: 0001883a nop + a648: e037883a mov sp,fp + a64c: dfc00117 ldw ra,4(sp) + a650: df000017 ldw fp,0(sp) + a654: dec00504 addi sp,sp,20 + a658: f800283a ret + +0000a65c : + a65c: defffd04 addi sp,sp,-12 + a660: dfc00215 stw ra,8(sp) + a664: df000115 stw fp,4(sp) + a668: df000104 addi fp,sp,4 + a66c: e13fff15 stw r4,-4(fp) + a670: e13fff17 ldw r4,-4(fp) + a674: 0006c180 call 6c18 + a678: e037883a mov sp,fp + a67c: dfc00117 ldw ra,4(sp) + a680: df000017 ldw fp,0(sp) + a684: dec00204 addi sp,sp,8 + a688: f800283a ret + +0000a68c : + a68c: defffe04 addi sp,sp,-8 + a690: df000115 stw fp,4(sp) + a694: df000104 addi fp,sp,4 + a698: e13fff15 stw r4,-4(fp) + a69c: e0bfff17 ldw r2,-4(fp) + a6a0: 108000d0 cmplti r2,r2,3 + a6a4: 10000a1e bne r2,zero,a6d0 + a6a8: e0bfff17 ldw r2,-4(fp) + a6ac: 10c00324 muli r3,r2,12 + a6b0: 00800074 movhi r2,1 + a6b4: 1885883a add r2,r3,r2 + a6b8: 102f3515 stw zero,-17196(r2) + a6bc: e0bfff17 ldw r2,-4(fp) + a6c0: 10c00324 muli r3,r2,12 + a6c4: 00800074 movhi r2,1 + a6c8: 1885883a add r2,r3,r2 + a6cc: 102f3315 stw zero,-17204(r2) + a6d0: 0001883a nop + a6d4: e037883a mov sp,fp + a6d8: df000017 ldw fp,0(sp) + a6dc: dec00104 addi sp,sp,4 + a6e0: f800283a ret + +0000a6e4 : + a6e4: deffff04 addi sp,sp,-4 + a6e8: df000015 stw fp,0(sp) + a6ec: d839883a mov fp,sp + a6f0: 000170fa wrctl ienable,zero + a6f4: 0001883a nop + a6f8: e037883a mov sp,fp + a6fc: df000017 ldw fp,0(sp) + a700: dec00104 addi sp,sp,4 + a704: f800283a ret + +0000a708 : + a708: defffb04 addi sp,sp,-20 + a70c: dfc00415 stw ra,16(sp) + a710: df000315 stw fp,12(sp) + a714: df000304 addi fp,sp,12 + a718: e13ffd15 stw r4,-12(fp) + a71c: 00800074 movhi r2,1 + a720: 10af9a17 ldw r2,-16792(r2) + a724: e0bfff15 stw r2,-4(fp) + a728: 00003106 br a7f0 + a72c: e0bfff17 ldw r2,-4(fp) + a730: 10800217 ldw r2,8(r2) + a734: 1009883a mov r4,r2 + a738: 0006cc00 call 6cc0 + a73c: e0bffe15 stw r2,-8(fp) + a740: e0bfff17 ldw r2,-4(fp) + a744: 10c00217 ldw r3,8(r2) + a748: e0bffe17 ldw r2,-8(fp) + a74c: 10bfffc4 addi r2,r2,-1 + a750: 1885883a add r2,r3,r2 + a754: 10800003 ldbu r2,0(r2) + a758: 10803fcc andi r2,r2,255 + a75c: 1080201c xori r2,r2,128 + a760: 10bfe004 addi r2,r2,-128 + a764: 10800bd8 cmpnei r2,r2,47 + a768: 1000031e bne r2,zero,a778 + a76c: e0bffe17 ldw r2,-8(fp) + a770: 10bfffc4 addi r2,r2,-1 + a774: e0bffe15 stw r2,-8(fp) + a778: e0bffe17 ldw r2,-8(fp) + a77c: e0fffd17 ldw r3,-12(fp) + a780: 1885883a add r2,r3,r2 + a784: 10800003 ldbu r2,0(r2) + a788: 10803fcc andi r2,r2,255 + a78c: 1080201c xori r2,r2,128 + a790: 10bfe004 addi r2,r2,-128 + a794: 10800be0 cmpeqi r2,r2,47 + a798: 1000081e bne r2,zero,a7bc + a79c: e0bffe17 ldw r2,-8(fp) + a7a0: e0fffd17 ldw r3,-12(fp) + a7a4: 1885883a add r2,r3,r2 + a7a8: 10800003 ldbu r2,0(r2) + a7ac: 10803fcc andi r2,r2,255 + a7b0: 1080201c xori r2,r2,128 + a7b4: 10bfe004 addi r2,r2,-128 + a7b8: 10000a1e bne r2,zero,a7e4 + a7bc: e0bfff17 ldw r2,-4(fp) + a7c0: 10800217 ldw r2,8(r2) + a7c4: e0fffe17 ldw r3,-8(fp) + a7c8: 180d883a mov r6,r3 + a7cc: e17ffd17 ldw r5,-12(fp) + a7d0: 1009883a mov r4,r2 + a7d4: 000aa1c0 call aa1c + a7d8: 1000021e bne r2,zero,a7e4 + a7dc: e0bfff17 ldw r2,-4(fp) + a7e0: 00000806 br a804 + a7e4: e0bfff17 ldw r2,-4(fp) + a7e8: 10800017 ldw r2,0(r2) + a7ec: e0bfff15 stw r2,-4(fp) + a7f0: e0ffff17 ldw r3,-4(fp) + a7f4: 00800074 movhi r2,1 + a7f8: 10af9a04 addi r2,r2,-16792 + a7fc: 18bfcb1e bne r3,r2,a72c + a800: 0005883a mov r2,zero + a804: e037883a mov sp,fp + a808: dfc00117 ldw ra,4(sp) + a80c: df000017 ldw fp,0(sp) + a810: dec00204 addi sp,sp,8 + a814: f800283a ret + +0000a818 : + a818: defffc04 addi sp,sp,-16 + a81c: df000315 stw fp,12(sp) + a820: df000304 addi fp,sp,12 + a824: e13ffd15 stw r4,-12(fp) + a828: 00bffa04 movi r2,-24 + a82c: e0bffe15 stw r2,-8(fp) + a830: e03fff15 stw zero,-4(fp) + a834: 00001906 br a89c + a838: e0bfff17 ldw r2,-4(fp) + a83c: 10c00324 muli r3,r2,12 + a840: 00800074 movhi r2,1 + a844: 1885883a add r2,r3,r2 + a848: 10af3317 ldw r2,-17204(r2) + a84c: 1000101e bne r2,zero,a890 + a850: e0bfff17 ldw r2,-4(fp) + a854: 11000324 muli r4,r2,12 + a858: e0fffd17 ldw r3,-12(fp) + a85c: 00800074 movhi r2,1 + a860: 2085883a add r2,r4,r2 + a864: 10ef3315 stw r3,-17204(r2) + a868: 00800074 movhi r2,1 + a86c: 10ef9e17 ldw r3,-16776(r2) + a870: e0bfff17 ldw r2,-4(fp) + a874: 1880030e bge r3,r2,a884 + a878: e0ffff17 ldw r3,-4(fp) + a87c: 00800074 movhi r2,1 + a880: 10ef9e15 stw r3,-16776(r2) + a884: e0bfff17 ldw r2,-4(fp) + a888: e0bffe15 stw r2,-8(fp) + a88c: 00000706 br a8ac + a890: e0bfff17 ldw r2,-4(fp) + a894: 10800044 addi r2,r2,1 + a898: e0bfff15 stw r2,-4(fp) + a89c: e0bfff17 ldw r2,-4(fp) + a8a0: 10800810 cmplti r2,r2,32 + a8a4: 103fe41e bne r2,zero,a838 + a8a8: 0001883a nop + a8ac: e0bffe17 ldw r2,-8(fp) + a8b0: e037883a mov sp,fp + a8b4: df000017 ldw fp,0(sp) + a8b8: dec00104 addi sp,sp,4 + a8bc: f800283a ret + +0000a8c0 : + a8c0: defffb04 addi sp,sp,-20 + a8c4: df000415 stw fp,16(sp) + a8c8: df000404 addi fp,sp,16 + a8cc: e13ffd15 stw r4,-12(fp) + a8d0: e17ffc15 stw r5,-16(fp) + a8d4: e0bffc17 ldw r2,-16(fp) + a8d8: 10840070 cmpltui r2,r2,4097 + a8dc: 1000021e bne r2,zero,a8e8 + a8e0: 00840004 movi r2,4096 + a8e4: e0bffc15 stw r2,-16(fp) + a8e8: e0fffd17 ldw r3,-12(fp) + a8ec: e0bffc17 ldw r2,-16(fp) + a8f0: 1885883a add r2,r3,r2 + a8f4: e0bffe15 stw r2,-8(fp) + a8f8: e0bffd17 ldw r2,-12(fp) + a8fc: e0bfff15 stw r2,-4(fp) + a900: 00000506 br a918 + a904: e0bfff17 ldw r2,-4(fp) + a908: 1000603a flushi r2 + a90c: e0bfff17 ldw r2,-4(fp) + a910: 10800804 addi r2,r2,32 + a914: e0bfff15 stw r2,-4(fp) + a918: e0ffff17 ldw r3,-4(fp) + a91c: e0bffe17 ldw r2,-8(fp) + a920: 18bff836 bltu r3,r2,a904 + a924: e0bffd17 ldw r2,-12(fp) + a928: 108007cc andi r2,r2,31 + a92c: 10000226 beq r2,zero,a938 + a930: e0bfff17 ldw r2,-4(fp) + a934: 1000603a flushi r2 + a938: 0000203a flushp + a93c: 0001883a nop + a940: e037883a mov sp,fp + a944: df000017 ldw fp,0(sp) + a948: dec00104 addi sp,sp,4 + a94c: f800283a ret + +0000a950 : + a950: defffe04 addi sp,sp,-8 + a954: df000115 stw fp,4(sp) + a958: df000104 addi fp,sp,4 + a95c: e13fff15 stw r4,-4(fp) + a960: e0bfff17 ldw r2,-4(fp) + a964: 10bffe84 addi r2,r2,-6 + a968: 10c00428 cmpgeui r3,r2,16 + a96c: 1800191e bne r3,zero,a9d4 + a970: 100690ba slli r3,r2,2 + a974: 00800074 movhi r2,1 + a978: 1885883a add r2,r3,r2 + a97c: 10aa6117 ldw r2,-22140(r2) + a980: 1000683a jmp r2 + a984: 0000a9c4 movi zero,679 + a988: 0000a9c4 movi zero,679 + a98c: 0000a9d4 movui zero,679 + a990: 0000a9d4 movui zero,679 + a994: 0000a9d4 movui zero,679 + a998: 0000a9c4 movi zero,679 + a99c: 0000a9cc andi zero,zero,679 + a9a0: 0000a9d4 movui zero,679 + a9a4: 0000a9c4 movi zero,679 + a9a8: 0000a9c4 movi zero,679 + a9ac: 0000a9d4 movui zero,679 + a9b0: 0000a9c4 movi zero,679 + a9b4: 0000a9cc andi zero,zero,679 + a9b8: 0000a9d4 movui zero,679 + a9bc: 0000a9d4 movui zero,679 + a9c0: 0000a9c4 movi zero,679 + a9c4: 00800044 movi r2,1 + a9c8: 00000306 br a9d8 + a9cc: 0005883a mov r2,zero + a9d0: 00000106 br a9d8 + a9d4: 0005883a mov r2,zero + a9d8: e037883a mov sp,fp + a9dc: df000017 ldw fp,0(sp) + a9e0: dec00104 addi sp,sp,4 + a9e4: f800283a ret + +0000a9e8 : + a9e8: 200b883a mov r5,r4 + a9ec: 000f883a mov r7,zero + a9f0: 000d883a mov r6,zero + a9f4: 0009883a mov r4,zero + a9f8: 000aa4c1 jmpi aa4c <__register_exitproc> + +0000a9fc : + a9fc: defffe04 addi sp,sp,-8 + aa00: 000b883a mov r5,zero + aa04: dc000015 stw r16,0(sp) + aa08: dfc00115 stw ra,4(sp) + aa0c: 2021883a mov r16,r4 + aa10: 000ab680 call ab68 <__call_exitprocs> + aa14: 8009883a mov r4,r16 + aa18: 000ac940 call ac94 <_exit> + +0000aa1c : + aa1c: 0007883a mov r3,zero + aa20: 30c0021e bne r6,r3,aa2c + aa24: 0005883a mov r2,zero + aa28: f800283a ret + aa2c: 20c5883a add r2,r4,r3 + aa30: 18c00044 addi r3,r3,1 + aa34: 28cf883a add r7,r5,r3 + aa38: 10800003 ldbu r2,0(r2) + aa3c: 39ffffc3 ldbu r7,-1(r7) + aa40: 11fff726 beq r2,r7,aa20 + aa44: 11c5c83a sub r2,r2,r7 + aa48: f800283a ret + +0000aa4c <__register_exitproc>: + aa4c: 00800074 movhi r2,1 + aa50: 10af9417 ldw r2,-16816(r2) + aa54: defff904 addi sp,sp,-28 + aa58: dc000015 stw r16,0(sp) + aa5c: 14000d17 ldw r16,52(r2) + aa60: dd400515 stw r21,20(sp) + aa64: dd000415 stw r20,16(sp) + aa68: dcc00315 stw r19,12(sp) + aa6c: dc800215 stw r18,8(sp) + aa70: dfc00615 stw ra,24(sp) + aa74: dc400115 stw r17,4(sp) + aa78: 2025883a mov r18,r4 + aa7c: 2827883a mov r19,r5 + aa80: 302b883a mov r21,r6 + aa84: 3829883a mov r20,r7 + aa88: 8000081e bne r16,zero,aaac <__register_exitproc+0x60> + aa8c: 14000e04 addi r16,r2,56 + aa90: 00c00034 movhi r3,0 + aa94: 14000d15 stw r16,52(r2) + aa98: 18c00004 addi r3,r3,0 + aa9c: 18000326 beq r3,zero,aaac <__register_exitproc+0x60> + aaa0: 00c00034 movhi r3,0 + aaa4: 18c00017 ldw r3,0(r3) + aaa8: 10c03015 stw r3,192(r2) + aaac: 84400117 ldw r17,4(r16) + aab0: 88800810 cmplti r2,r17,32 + aab4: 10000a1e bne r2,zero,aae0 <__register_exitproc+0x94> + aab8: 00bfffc4 movi r2,-1 + aabc: dfc00617 ldw ra,24(sp) + aac0: dd400517 ldw r21,20(sp) + aac4: dd000417 ldw r20,16(sp) + aac8: dcc00317 ldw r19,12(sp) + aacc: dc800217 ldw r18,8(sp) + aad0: dc400117 ldw r17,4(sp) + aad4: dc000017 ldw r16,0(sp) + aad8: dec00704 addi sp,sp,28 + aadc: f800283a ret + aae0: 90001926 beq r18,zero,ab48 <__register_exitproc+0xfc> + aae4: 80802217 ldw r2,136(r16) + aae8: 1000091e bne r2,zero,ab10 <__register_exitproc+0xc4> + aaec: 00800034 movhi r2,0 + aaf0: 10800004 addi r2,r2,0 + aaf4: 103ff026 beq r2,zero,aab8 <__register_exitproc+0x6c> + aaf8: 01004204 movi r4,264 + aafc: 00000000 call 0 <__alt_mem_onchip_memory2_0> + ab00: 103fed26 beq r2,zero,aab8 <__register_exitproc+0x6c> + ab04: 10004015 stw zero,256(r2) + ab08: 10004115 stw zero,260(r2) + ab0c: 80802215 stw r2,136(r16) + ab10: 880890ba slli r4,r17,2 + ab14: 00c00044 movi r3,1 + ab18: 1c46983a sll r3,r3,r17 + ab1c: 1109883a add r4,r2,r4 + ab20: 25400015 stw r21,0(r4) + ab24: 11404017 ldw r5,256(r2) + ab28: 94800098 cmpnei r18,r18,2 + ab2c: 28cab03a or r5,r5,r3 + ab30: 11404015 stw r5,256(r2) + ab34: 25002015 stw r20,128(r4) + ab38: 9000031e bne r18,zero,ab48 <__register_exitproc+0xfc> + ab3c: 11004117 ldw r4,260(r2) + ab40: 20c6b03a or r3,r4,r3 + ab44: 10c04115 stw r3,260(r2) + ab48: 88800044 addi r2,r17,1 + ab4c: 8c400084 addi r17,r17,2 + ab50: 882290ba slli r17,r17,2 + ab54: 80800115 stw r2,4(r16) + ab58: 0005883a mov r2,zero + ab5c: 8461883a add r16,r16,r17 + ab60: 84c00015 stw r19,0(r16) + ab64: 003fd506 br aabc <__register_exitproc+0x70> + +0000ab68 <__call_exitprocs>: + ab68: defff604 addi sp,sp,-40 + ab6c: 00800074 movhi r2,1 + ab70: dd800615 stw r22,24(sp) + ab74: 15af9417 ldw r22,-16816(r2) + ab78: dd400515 stw r21,20(sp) + ab7c: dd000415 stw r20,16(sp) + ab80: dfc00915 stw ra,36(sp) + ab84: df000815 stw fp,32(sp) + ab88: ddc00715 stw r23,28(sp) + ab8c: dcc00315 stw r19,12(sp) + ab90: dc800215 stw r18,8(sp) + ab94: dc400115 stw r17,4(sp) + ab98: dc000015 stw r16,0(sp) + ab9c: 202b883a mov r21,r4 + aba0: 2829883a mov r20,r5 + aba4: b4400d17 ldw r17,52(r22) + aba8: 88000726 beq r17,zero,abc8 <__call_exitprocs+0x60> + abac: 8c000117 ldw r16,4(r17) + abb0: 8cc02217 ldw r19,136(r17) + abb4: 84bfffc4 addi r18,r16,-1 + abb8: 802090ba slli r16,r16,2 + abbc: 9c2f883a add r23,r19,r16 + abc0: 8c21883a add r16,r17,r16 + abc4: 90000c0e bge r18,zero,abf8 <__call_exitprocs+0x90> + abc8: dfc00917 ldw ra,36(sp) + abcc: df000817 ldw fp,32(sp) + abd0: ddc00717 ldw r23,28(sp) + abd4: dd800617 ldw r22,24(sp) + abd8: dd400517 ldw r21,20(sp) + abdc: dd000417 ldw r20,16(sp) + abe0: dcc00317 ldw r19,12(sp) + abe4: dc800217 ldw r18,8(sp) + abe8: dc400117 ldw r17,4(sp) + abec: dc000017 ldw r16,0(sp) + abf0: dec00a04 addi sp,sp,40 + abf4: f800283a ret + abf8: a0000726 beq r20,zero,ac18 <__call_exitprocs+0xb0> + abfc: 9800041e bne r19,zero,ac10 <__call_exitprocs+0xa8> + ac00: 94bfffc4 addi r18,r18,-1 + ac04: bdffff04 addi r23,r23,-4 + ac08: 843fff04 addi r16,r16,-4 + ac0c: 003fed06 br abc4 <__call_exitprocs+0x5c> + ac10: b8c01f17 ldw r3,124(r23) + ac14: 1d3ffa1e bne r3,r20,ac00 <__call_exitprocs+0x98> + ac18: 89000117 ldw r4,4(r17) + ac1c: 80c00117 ldw r3,4(r16) + ac20: 213fffc4 addi r4,r4,-1 + ac24: 24800f1e bne r4,r18,ac64 <__call_exitprocs+0xfc> + ac28: 8c800115 stw r18,4(r17) + ac2c: 183ff426 beq r3,zero,ac00 <__call_exitprocs+0x98> + ac30: 8f000117 ldw fp,4(r17) + ac34: 98000526 beq r19,zero,ac4c <__call_exitprocs+0xe4> + ac38: 00800044 movi r2,1 + ac3c: 148c983a sll r6,r2,r18 + ac40: 99004017 ldw r4,256(r19) + ac44: 3108703a and r4,r6,r4 + ac48: 2000081e bne r4,zero,ac6c <__call_exitprocs+0x104> + ac4c: 183ee83a callr r3 + ac50: 89000117 ldw r4,4(r17) + ac54: b0c00d17 ldw r3,52(r22) + ac58: 273fd21e bne r4,fp,aba4 <__call_exitprocs+0x3c> + ac5c: 88ffe826 beq r17,r3,ac00 <__call_exitprocs+0x98> + ac60: 003fd006 br aba4 <__call_exitprocs+0x3c> + ac64: 80000115 stw zero,4(r16) + ac68: 003ff006 br ac2c <__call_exitprocs+0xc4> + ac6c: 99404117 ldw r5,260(r19) + ac70: b93fff17 ldw r4,-4(r23) + ac74: 314c703a and r6,r6,r5 + ac78: 3000041e bne r6,zero,ac8c <__call_exitprocs+0x124> + ac7c: 200b883a mov r5,r4 + ac80: a809883a mov r4,r21 + ac84: 183ee83a callr r3 + ac88: 003ff106 br ac50 <__call_exitprocs+0xe8> + ac8c: 183ee83a callr r3 + ac90: 003fef06 br ac50 <__call_exitprocs+0xe8> + +0000ac94 <_exit>: + ac94: defffd04 addi sp,sp,-12 + ac98: df000215 stw fp,8(sp) + ac9c: df000204 addi fp,sp,8 + aca0: e13ffe15 stw r4,-8(fp) + aca4: 0001883a nop + aca8: e0bffe17 ldw r2,-8(fp) + acac: e0bfff15 stw r2,-4(fp) + acb0: e0bfff17 ldw r2,-4(fp) + acb4: 10000226 beq r2,zero,acc0 <_exit+0x2c> + acb8: 002af070 cmpltui zero,zero,43969 + acbc: 00000106 br acc4 <_exit+0x30> + acc0: 002af0b0 cmpltui zero,zero,43970 + acc4: 0001883a nop + acc8: 003fff06 br acc8 <_exit+0x34> diff --git a/run_tests.sh b/run_tests.sh new file mode 100644 index 0000000..6beb8f5 --- /dev/null +++ b/run_tests.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# run_tests.sh +cd /mnt/c/Workspace/quartus/video_processing +export PYTHONPATH=$PYTHONPATH:$(pwd)/tests/cocotb +python3 -m pytest -s tests/ > test_summary.log 2>&1 diff --git a/sim_build/video_pipeline.vvp b/sim_build/video_pipeline.vvp new file mode 100644 index 0000000..703ffd7 --- /dev/null +++ b/sim_build/video_pipeline.vvp @@ -0,0 +1,1728 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi"; +S_0x6357d32a9240 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x6357d32c8880 .scope module, "video_pipeline" "video_pipeline" 3 3; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk_50"; + .port_info 1 /INPUT 1 "clk_hdmi"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "m_waitrequest"; + .port_info 4 /INPUT 32 "m_readdata"; + .port_info 5 /INPUT 1 "m_readdatavalid"; + .port_info 6 /OUTPUT 32 "m_address"; + .port_info 7 /OUTPUT 1 "m_read"; + .port_info 8 /OUTPUT 8 "m_burstcount"; + .port_info 9 /INPUT 3 "s_address"; + .port_info 10 /INPUT 1 "s_read"; + .port_info 11 /INPUT 1 "s_write"; + .port_info 12 /INPUT 32 "s_writedata"; + .port_info 13 /OUTPUT 32 "s_readdata"; + .port_info 14 /OUTPUT 1 "s_readdatavalid"; + .port_info 15 /OUTPUT 24 "hdmi_d"; + .port_info 16 /OUTPUT 1 "hdmi_de"; + .port_info 17 /OUTPUT 1 "hdmi_hs"; + .port_info 18 /OUTPUT 1 "hdmi_vs"; + .port_info 19 /OUTPUT 8 "debug_leds"; +L_0x6357d32d6740 .functor XOR 1, L_0x6357d3309940, L_0x6357d3309a40, C4<0>, C4<0>; +L_0x6357d32d7390 .functor XOR 1, L_0x6357d3309c50, L_0x6357d3309cf0, C4<0>, C4<0>; +L_0x6357d32d97f0 .functor XOR 1, L_0x6357d3309ff0, L_0x6357d330a0d0, C4<0>, C4<0>; +L_0x6357d3325100 .functor BUFZ 1, L_0x6357d32db310, C4<0>, C4<0>, C4<0>; +L_0x6357d3325170 .functor BUFZ 1, L_0x6357d3324e20, C4<0>, C4<0>, C4<0>; +L_0x6357d3325280 .functor BUFZ 1, L_0x6357d331adc0, C4<0>, C4<0>, C4<0>; +L_0x6357d3325330 .functor BUFZ 1, L_0x6357d32d7390, C4<0>, C4<0>, C4<0>; +L_0x6357d3325760 .functor BUFZ 1, L_0x6357d32d6740, C4<0>, C4<0>, C4<0>; +v0x6357d3306660_0 .net *"_ivl_1", 0 0, L_0x6357d3309940; 1 drivers +v0x6357d3306760_0 .net *"_ivl_15", 0 0, L_0x6357d3309ff0; 1 drivers +v0x6357d3306840_0 .net *"_ivl_17", 0 0, L_0x6357d330a0d0; 1 drivers +v0x6357d3306930_0 .net *"_ivl_25", 0 0, L_0x6357d3325100; 1 drivers +v0x6357d3306a10_0 .net *"_ivl_29", 0 0, L_0x6357d3325170; 1 drivers +v0x6357d3306af0_0 .net *"_ivl_3", 0 0, L_0x6357d3309a40; 1 drivers +v0x6357d3306bd0_0 .net *"_ivl_33", 0 0, L_0x6357d33251e0; 1 drivers +v0x6357d3306cb0_0 .net *"_ivl_37", 0 0, L_0x6357d3325280; 1 drivers +v0x6357d3306d90_0 .net *"_ivl_41", 0 0, L_0x6357d3325330; 1 drivers +v0x6357d3306e70_0 .net *"_ivl_45", 0 0, v0x6357d3307f50_0; 1 drivers +v0x6357d3306f50_0 .net *"_ivl_49", 0 0, v0x6357d3307ae0_0; 1 drivers +v0x6357d3307030_0 .net *"_ivl_54", 0 0, L_0x6357d3325760; 1 drivers +v0x6357d3307110_0 .net *"_ivl_7", 0 0, L_0x6357d3309c50; 1 drivers +v0x6357d33071f0_0 .net *"_ivl_9", 0 0, L_0x6357d3309cf0; 1 drivers +o0x7d66d379f048 .functor BUFZ 1, C4; HiZ drive +v0x6357d33072d0_0 .net "clk_50", 0 0, o0x7d66d379f048; 0 drivers +o0x7d66d37a1298 .functor BUFZ 1, C4; HiZ drive +v0x6357d3307370_0 .net "clk_hdmi", 0 0, o0x7d66d37a1298; 0 drivers +v0x6357d3307410_0 .net "debug_leds", 7 0, L_0x6357d33254d0; 1 drivers +v0x6357d3307600_0 .net "dma_busy", 0 0, L_0x6357d329fb20; 1 drivers +v0x6357d33076f0_0 .net "dma_cont_74", 0 0, L_0x6357d331b000; 1 drivers +v0x6357d3307790_0 .net "dma_cont_sync", 0 0, L_0x6357d3309f00; 1 drivers +v0x6357d3307830_0 .var "dma_cont_sync_50", 2 0; +v0x6357d33078d0_0 .net "dma_done_50", 0 0, v0x6357d329f0e0_0; 1 drivers +v0x6357d3307970_0 .net "dma_done_sync", 0 0, L_0x6357d32d97f0; 1 drivers +v0x6357d3307a40_0 .var "dma_done_sync_74", 2 0; +v0x6357d3307ae0_0 .var "dma_done_toggle_50", 0 0; +v0x6357d3307ba0_0 .net "dma_en", 0 0, L_0x6357d331af10; 1 drivers +v0x6357d3307c70_0 .net "dma_start_74", 0 0, L_0x6357d331b140; 1 drivers +v0x6357d3307d40_0 .var "dma_start_74_d", 0 0; +v0x6357d3307de0_0 .net "dma_start_sync", 0 0, L_0x6357d32d7390; 1 drivers +v0x6357d3307eb0_0 .var "dma_start_sync_50", 2 0; +v0x6357d3307f50_0 .var "dma_start_toggle_74", 0 0; +v0x6357d3308010_0 .net "fifo_empty", 0 0, L_0x6357d331adc0; 1 drivers +v0x6357d33080e0_0 .net "fifo_full", 0 0, L_0x6357d330a760; 1 drivers +v0x6357d33081b0_0 .net "fifo_rd_data", 31 0, v0x6357d3305680_0; 1 drivers +v0x6357d3308280_0 .net "fifo_rd_en", 0 0, L_0x6357d3324e20; 1 drivers +v0x6357d3308370_0 .net "fifo_used", 8 0, L_0x6357d331ac30; 1 drivers +v0x6357d3308460_0 .net "fifo_wr_data", 31 0, L_0x6357d329eeb0; 1 drivers +v0x6357d3308550_0 .net "fifo_wr_en", 0 0, L_0x6357d32db310; 1 drivers +v0x6357d3308640_0 .net "hdmi_d", 23 0, v0x6357d3302740_0; 1 drivers +v0x6357d3308700_0 .net "hdmi_de", 0 0, v0x6357d3302820_0; 1 drivers +v0x6357d33087a0_0 .net "hdmi_hs", 0 0, v0x6357d33028e0_0; 1 drivers +v0x6357d3308840_0 .net "hdmi_vs", 0 0, v0x6357d33029a0_0; 1 drivers +v0x6357d33088e0_0 .net "m_address", 31 0, v0x6357d32f7360_0; 1 drivers +L_0x7d66d3756018 .functor BUFT 1, C4<01000000>, C4<0>, C4<0>, C4<0>; +v0x6357d33089b0_0 .net "m_burstcount", 7 0, L_0x7d66d3756018; 1 drivers +v0x6357d3308a80_0 .net "m_read", 0 0, v0x6357d32f7520_0; 1 drivers +o0x7d66d379f2b8 .functor BUFZ 32, C4; HiZ drive +v0x6357d3308b50_0 .net "m_readdata", 31 0, o0x7d66d379f2b8; 0 drivers +o0x7d66d379f2e8 .functor BUFZ 1, C4; HiZ drive +v0x6357d3308c20_0 .net "m_readdatavalid", 0 0, o0x7d66d379f2e8; 0 drivers +o0x7d66d379f318 .functor BUFZ 1, C4; HiZ drive +v0x6357d3308cf0_0 .net "m_waitrequest", 0 0, o0x7d66d379f318; 0 drivers +v0x6357d3308dc0_0 .net "reg_mode", 31 0, L_0x6357d330a940; 1 drivers +o0x7d66d379f378 .functor BUFZ 1, C4; HiZ drive +v0x6357d3308e90_0 .net "reset_n", 0 0, o0x7d66d379f378; 0 drivers +o0x7d66d37a1088 .functor BUFZ 3, C4; HiZ drive +v0x6357d3308f80_0 .net "s_address", 2 0, o0x7d66d37a1088; 0 drivers +o0x7d66d37a10b8 .functor BUFZ 1, C4; HiZ drive +v0x6357d3309020_0 .net "s_read", 0 0, o0x7d66d37a10b8; 0 drivers +v0x6357d33090f0_0 .net "s_readdata", 31 0, L_0x6357d331b270; 1 drivers +v0x6357d33091c0_0 .net "s_readdatavalid", 0 0, v0x6357d3300ff0_0; 1 drivers +o0x7d66d37a1148 .functor BUFZ 1, C4; HiZ drive +v0x6357d3309290_0 .net "s_write", 0 0, o0x7d66d37a1148; 0 drivers +o0x7d66d37a1178 .functor BUFZ 32, C4; HiZ drive +v0x6357d3309360_0 .net "s_writedata", 31 0, o0x7d66d37a1178; 0 drivers +v0x6357d3309430_0 .net "shadow_ptr", 31 0, L_0x6357d331b200; 1 drivers +v0x6357d3309520_0 .net "vs_toggle_raw", 0 0, v0x6357d3303d60_0; 1 drivers +v0x6357d33095c0_0 .net "vsync_edge_sync", 0 0, L_0x6357d32d6740; 1 drivers +v0x6357d3309690_0 .var "vsync_toggle_sync_50", 2 0; +L_0x6357d3309940 .part v0x6357d3309690_0, 2, 1; +L_0x6357d3309a40 .part v0x6357d3309690_0, 1, 1; +L_0x6357d3309c50 .part v0x6357d3307eb0_0, 2, 1; +L_0x6357d3309cf0 .part v0x6357d3307eb0_0, 1, 1; +L_0x6357d3309f00 .part v0x6357d3307830_0, 1, 1; +L_0x6357d3309ff0 .part v0x6357d3307a40_0, 2, 1; +L_0x6357d330a0d0 .part v0x6357d3307a40_0, 1, 1; +L_0x6357d3324fc0 .part v0x6357d3305680_0, 0, 24; +L_0x6357d33251e0 .part L_0x6357d331ac30, 8, 1; +LS_0x6357d33254d0_0_0 .concat8 [ 1 1 1 1], L_0x6357d3325100, L_0x6357d3325170, L_0x6357d33251e0, L_0x6357d3325280; +LS_0x6357d33254d0_0_4 .concat8 [ 1 1 1 1], L_0x6357d3325330, v0x6357d3307f50_0, v0x6357d3307ae0_0, L_0x6357d3325760; +L_0x6357d33254d0 .concat8 [ 4 4 0 0], LS_0x6357d33254d0_0_0, LS_0x6357d33254d0_0_4; +S_0x6357d32a9590 .scope module, "u_dma_master" "video_dma_master" 3 115, 4 3 0, S_0x6357d32c8880; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /INPUT 32 "start_addr"; + .port_info 3 /INPUT 1 "dma_start"; + .port_info 4 /INPUT 1 "dma_cont_en"; + .port_info 5 /OUTPUT 1 "dma_done"; + .port_info 6 /OUTPUT 1 "busy"; + .port_info 7 /INPUT 1 "vsync_edge"; + .port_info 8 /INPUT 1 "m_waitrequest"; + .port_info 9 /INPUT 32 "m_readdata"; + .port_info 10 /INPUT 1 "m_readdatavalid"; + .port_info 11 /OUTPUT 32 "m_address"; + .port_info 12 /OUTPUT 1 "m_read"; + .port_info 13 /OUTPUT 8 "m_burstcount"; + .port_info 14 /INPUT 9 "fifo_used"; + .port_info 15 /OUTPUT 1 "fifo_wr_en"; + .port_info 16 /OUTPUT 32 "fifo_wr_data"; +P_0x6357d31fad60 .param/l "BURST_LEN" 0 4 30, C4<01000000>; +P_0x6357d31fada0 .param/l "CHECK_FIFO" 1 4 38, C4<01>; +P_0x6357d31fade0 .param/l "FIFO_DEPTH" 0 4 31, +C4<00000000000000000000001000000000>; +P_0x6357d31fae20 .param/l "FRAME_SIZE_WORDS" 0 4 34, +C4<0000000000000000000000000000000000000000000001111110100100000000>; +P_0x6357d31fae60 .param/l "H_RES" 0 4 32, +C4<00000000000000000000001111000000>; +P_0x6357d31faea0 .param/l "IDLE" 1 4 37, C4<00>; +P_0x6357d31faee0 .param/l "ISSUE_READ" 1 4 39, C4<10>; +P_0x6357d31faf20 .param/l "V_RES" 0 4 33, +C4<00000000000000000000001000011100>; +P_0x6357d31faf60 .param/l "WAIT_END" 1 4 40, C4<11>; +L_0x6357d32db310 .functor BUFZ 1, o0x7d66d379f2e8, C4<0>, C4<0>, C4<0>; +L_0x6357d329eeb0 .functor BUFZ 32, o0x7d66d379f2b8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6357d329fb20 .functor BUFZ 1, v0x6357d32f71e0_0, C4<0>, C4<0>, C4<0>; +v0x6357d32d99b0_0 .net "busy", 0 0, L_0x6357d329fb20; alias, 1 drivers +v0x6357d32dc040_0 .net "clk", 0 0, o0x7d66d379f048; alias, 0 drivers +v0x6357d32dc0e0_0 .var "current_read_addr", 31 0; +v0x6357d329f010_0 .net "dma_cont_en", 0 0, L_0x6357d3309f00; alias, 1 drivers +v0x6357d329f0e0_0 .var "dma_done", 0 0; +v0x6357d329fcc0_0 .net "dma_start", 0 0, L_0x6357d32d7390; alias, 1 drivers +v0x6357d329fd90_0 .net "fifo_used", 8 0, L_0x6357d331ac30; alias, 1 drivers +v0x6357d32f7040_0 .net "fifo_wr_data", 31 0, L_0x6357d329eeb0; alias, 1 drivers +v0x6357d32f7120_0 .net "fifo_wr_en", 0 0, L_0x6357d32db310; alias, 1 drivers +v0x6357d32f71e0_0 .var "frame_active", 0 0; +v0x6357d32f72a0_0 .var "is_cont_mode", 0 0; +v0x6357d32f7360_0 .var "m_address", 31 0; +v0x6357d32f7440_0 .net "m_burstcount", 7 0, L_0x7d66d3756018; alias, 1 drivers +v0x6357d32f7520_0 .var "m_read", 0 0; +v0x6357d32f75e0_0 .net "m_readdata", 31 0, o0x7d66d379f2b8; alias, 0 drivers +v0x6357d32f76c0_0 .net "m_readdatavalid", 0 0, o0x7d66d379f2e8; alias, 0 drivers +v0x6357d32f7780_0 .net "m_waitrequest", 0 0, o0x7d66d379f318; alias, 0 drivers +v0x6357d32f7950_0 .var "pending_bursts", 9 0; +v0x6357d32f7a30_0 .net "reset_n", 0 0, o0x7d66d379f378; alias, 0 drivers +v0x6357d32f7af0_0 .net "start_addr", 31 0, L_0x6357d331b200; alias, 1 drivers +v0x6357d32f7bd0_0 .var "state", 1 0; +v0x6357d32f7cb0_0 .net "vsync_edge", 0 0, L_0x6357d32d6740; alias, 1 drivers +v0x6357d32f7d70_0 .var "words_commanded", 31 0; +v0x6357d32f7e50_0 .var "words_received", 31 0; +E_0x6357d3258cf0/0 .event negedge, v0x6357d32f7a30_0; +E_0x6357d3258cf0/1 .event posedge, v0x6357d32dc040_0; +E_0x6357d3258cf0 .event/or E_0x6357d3258cf0/0, E_0x6357d3258cf0/1; +S_0x6357d32f8150 .scope module, "u_hdmi_sync" "hdmi_sync_gen" 3 153, 5 6 0, S_0x6357d32c8880; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "clk_pixel"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /OUTPUT 24 "hdmi_d"; + .port_info 4 /OUTPUT 1 "hdmi_de"; + .port_info 5 /OUTPUT 1 "hdmi_hs"; + .port_info 6 /OUTPUT 1 "hdmi_vs"; + .port_info 7 /INPUT 3 "avs_address"; + .port_info 8 /INPUT 1 "avs_read"; + .port_info 9 /INPUT 1 "avs_write"; + .port_info 10 /INPUT 32 "avs_writedata"; + .port_info 11 /OUTPUT 32 "avs_readdata"; + .port_info 12 /OUTPUT 1 "avs_readdatavalid"; + .port_info 13 /OUTPUT 32 "reg_mode_out"; + .port_info 14 /OUTPUT 1 "dma_enable_out"; + .port_info 15 /OUTPUT 32 "shadow_ptr_out"; + .port_info 16 /INPUT 24 "stream_data_in"; + .port_info 17 /OUTPUT 1 "stream_rd_en"; + .port_info 18 /INPUT 1 "dma_busy"; + .port_info 19 /INPUT 1 "dma_done_in"; + .port_info 20 /OUTPUT 1 "dma_start_out"; + .port_info 21 /OUTPUT 1 "dma_cont_en_out"; + .port_info 22 /OUTPUT 1 "vs_toggle"; +P_0x6357d32f8300 .param/l "H_BACK" 0 5 167, +C4<00000000000000000000000001010000>; +P_0x6357d32f8340 .param/l "H_FRONT" 0 5 165, +C4<00000000000000000000000000110000>; +P_0x6357d32f8380 .param/l "H_SYNC" 0 5 166, +C4<00000000000000000000000000100000>; +P_0x6357d32f83c0 .param/l "H_TOTAL" 0 5 168, +C4<00000000000000000000010001100000>; +P_0x6357d32f8400 .param/l "H_VISIBLE" 0 5 164, +C4<00000000000000000000001111000000>; +P_0x6357d32f8440 .param/l "V_BACK" 0 5 173, +C4<00000000000000000000000000001111>; +P_0x6357d32f8480 .param/l "V_FRONT" 0 5 171, +C4<00000000000000000000000000000011>; +P_0x6357d32f84c0 .param/l "V_SYNC" 0 5 172, +C4<00000000000000000000000000000101>; +P_0x6357d32f8500 .param/l "V_TOTAL" 0 5 174, +C4<00000000000000000000001000110011>; +P_0x6357d32f8540 .param/l "V_VISIBLE" 0 5 170, +C4<00000000000000000000001000011100>; +L_0x6357d330a940 .functor BUFZ 32, v0x6357d33033a0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6357d331b140 .functor BUFZ 1, v0x6357d3301de0_0, C4<0>, C4<0>, C4<0>; +L_0x6357d331b200 .functor BUFZ 32, v0x6357d3303630_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6357d331b270 .functor BUFZ 32, v0x6357d3302d80_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6357d331b880 .functor AND 1, L_0x6357d331b450, L_0x6357d331b700, C4<1>, C4<1>; +L_0x6357d331bea0 .functor AND 1, L_0x6357d331bad0, L_0x6357d331bd50, C4<1>, C4<1>; +L_0x6357d331c220 .functor AND 1, L_0x6357d331c0e0, L_0x6357d331c380, C4<1>, C4<1>; +L_0x6357d331c940 .functor BUFZ 8, L_0x6357d331c5e0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x6357d331cec0 .functor BUFZ 8, L_0x6357d331ca50, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x6357d331d270 .functor BUFZ 8, L_0x6357d331caf0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x6357d331e550 .functor AND 1, L_0x6357d331dfd0, L_0x6357d331e2c0, C4<1>, C4<1>; +L_0x6357d331f220 .functor OR 1, L_0x6357d331e430, L_0x6357d331ef90, C4<0>, C4<0>; +L_0x6357d331f3a0 .functor AND 1, L_0x6357d331e550, L_0x6357d331f220, C4<1>, C4<1>; +L_0x6357d3322ca0 .functor BUFZ 16, L_0x6357d3322850, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x6357d331f330 .functor AND 1, L_0x6357d331b880, L_0x6357d3324500, C4<1>, C4<1>; +L_0x6357d3324e20 .functor AND 1, L_0x6357d331f330, L_0x6357d3324a50, C4<1>, C4<1>; +L_0x7d66d3756528 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x6357d32f8d10_0 .net/2u *"_ivl_100", 31 0, L_0x7d66d3756528; 1 drivers +v0x6357d32f8e10_0 .net *"_ivl_102", 0 0, L_0x6357d331d500; 1 drivers +v0x6357d32f8ed0_0 .net *"_ivl_104", 31 0, L_0x6357d331d5f0; 1 drivers +L_0x7d66d3756570 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6357d32f8fc0_0 .net *"_ivl_107", 19 0, L_0x7d66d3756570; 1 drivers +L_0x7d66d37565b8 .functor BUFT 1, C4<00000000000000000000000011111111>, C4<0>, C4<0>, C4<0>; +v0x6357d32f90a0_0 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*"_ivl_73", 1 0, L_0x7d66d3756408; 1 drivers +v0x6357d32ffca0_0 .net *"_ivl_76", 7 0, L_0x6357d331ca50; 1 drivers +v0x6357d32ffd80_0 .net *"_ivl_79", 7 0, L_0x6357d331cb90; 1 drivers +v0x6357d32ffe60_0 .net *"_ivl_80", 9 0, L_0x6357d331cc80; 1 drivers +L_0x7d66d3756450 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x6357d32fff40_0 .net *"_ivl_83", 1 0, L_0x7d66d3756450; 1 drivers +v0x6357d3300020_0 .net *"_ivl_86", 7 0, L_0x6357d331caf0; 1 drivers +v0x6357d3300100_0 .net *"_ivl_89", 7 0, L_0x6357d331cf80; 1 drivers +v0x6357d33001e0_0 .net *"_ivl_90", 9 0, L_0x6357d331d0e0; 1 drivers +L_0x7d66d3756498 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x6357d3300ad0_0 .net *"_ivl_93", 1 0, L_0x7d66d3756498; 1 drivers +v0x6357d3300bb0_0 .net *"_ivl_96", 31 0, L_0x6357d331d390; 1 drivers +L_0x7d66d37564e0 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6357d3300c90_0 .net *"_ivl_99", 19 0, L_0x7d66d37564e0; 1 drivers +v0x6357d3300d70_0 .net "avs_address", 2 0, o0x7d66d37a1088; alias, 0 drivers +v0x6357d3300e50_0 .net "avs_read", 0 0, o0x7d66d37a10b8; alias, 0 drivers +v0x6357d3300f10_0 .net "avs_readdata", 31 0, L_0x6357d331b270; alias, 1 drivers +v0x6357d3300ff0_0 .var "avs_readdatavalid", 0 0; +v0x6357d33010b0_0 .net "avs_write", 0 0, o0x7d66d37a1148; alias, 0 drivers +v0x6357d3301170_0 .net "avs_writedata", 31 0, o0x7d66d37a1178; alias, 0 drivers +v0x6357d3301250_0 .net "bar_idx", 2 0, L_0x6357d3322030; 1 drivers +v0x6357d3301330 .array "char_bitmap", 15 0, 15 0; +v0x6357d33013f0_0 .net "char_col_idx", 3 0, L_0x6357d33225a0; 1 drivers +v0x6357d33014d0_0 .net "char_color", 23 0, L_0x6357d3324010; 1 drivers +v0x6357d33015b0_0 .net "char_pixel", 0 0, L_0x6357d3323290; 1 drivers +v0x6357d3301670_0 .net "char_row_idx", 3 0, L_0x6357d3322500; 1 drivers +v0x6357d3301750_0 .net "clk", 0 0, o0x7d66d379f048; alias, 0 drivers +v0x6357d33017f0_0 .net "clk_pixel", 0 0, o0x7d66d37a1298; alias, 0 drivers +v0x6357d3301890_0 .net "current_row_bits", 15 0, L_0x6357d3322ca0; 1 drivers +v0x6357d3301970_0 .net "dma_busy", 0 0, L_0x6357d329fb20; alias, 1 drivers +v0x6357d3301a40_0 .net "dma_cont_en_out", 0 0, L_0x6357d331b000; alias, 1 drivers +v0x6357d3301ae0_0 .net "dma_done_in", 0 0, L_0x6357d32d97f0; alias, 1 drivers +v0x6357d3301ba0_0 .var "dma_done_sticky", 0 0; +v0x6357d3301c60_0 .net "dma_enable_out", 0 0, L_0x6357d331af10; alias, 1 drivers +v0x6357d3301d20_0 .net "dma_start_out", 0 0, L_0x6357d331b140; alias, 1 drivers +v0x6357d3301de0_0 .var "dma_start_pulse", 0 0; +v0x6357d3301ea0_0 .net "fancy_b", 7 0, L_0x6357d3323b80; 1 drivers +v0x6357d3301f80_0 .net "fancy_g", 7 0, L_0x6357d3323ae0; 1 drivers +v0x6357d3302060_0 .net "fancy_r", 7 0, L_0x6357d3323750; 1 drivers +v0x6357d3302140_0 .net "gamma_b", 7 0, L_0x6357d331d270; 1 drivers +v0x6357d3302220_0 .net "gamma_g", 7 0, L_0x6357d331cec0; 1 drivers +v0x6357d3302300_0 .net "gamma_r", 7 0, L_0x6357d331c940; 1 drivers +v0x6357d33023e0_0 .net "gray", 7 0, L_0x6357d331dcf0; 1 drivers +v0x6357d33024c0_0 .net "gray8_val", 7 0, L_0x6357d33221c0; 1 drivers +v0x6357d33025a0_0 .net "grid_line", 0 0, L_0x6357d331f3a0; 1 drivers +v0x6357d3302660_0 .var "h_cnt", 11 0; +v0x6357d3302740_0 .var "hdmi_d", 23 0; +v0x6357d3302820_0 .var "hdmi_de", 0 0; +v0x6357d33028e0_0 .var "hdmi_hs", 0 0; +v0x6357d33029a0_0 .var "hdmi_vs", 0 0; +v0x6357d3302a60_0 .var "hs_d1", 0 0; +v0x6357d3302b20_0 .net "hs_wire", 0 0, L_0x6357d331bea0; 1 drivers +v0x6357d3302be0 .array "lut_mem", 255 0, 7 0; +v0x6357d3302ca0_0 .var "pre_gamma_d", 23 0; +v0x6357d3302d80_0 .var "read_data_mux", 31 0; +v0x6357d3302e60_0 .var "reg_bitmap_addr", 31 0; +v0x6357d3302f40_0 .var "reg_bitmap_data", 31 0; +v0x6357d3303020_0 .var "reg_frame_ptr", 31 0; +v0x6357d3303100_0 .var "reg_global_ctrl", 31 0; +v0x6357d33031e0_0 .var "reg_lut_addr", 31 0; +v0x6357d33032c0_0 .var "reg_lut_data", 31 0; +v0x6357d33033a0_0 .var "reg_mode", 31 0; +v0x6357d3303480_0 .net "reg_mode_out", 31 0, L_0x6357d330a940; alias, 1 drivers +v0x6357d3303560_0 .net "reset_n", 0 0, o0x7d66d379f378; alias, 0 drivers +v0x6357d3303630_0 .var "shadow_ptr", 31 0; +v0x6357d33036f0_0 .net "shadow_ptr_out", 31 0, L_0x6357d331b200; alias, 1 drivers +v0x6357d33037e0_0 .net "stream_data_in", 23 0, L_0x6357d3324fc0; 1 drivers +v0x6357d33038a0_0 .net "stream_rd_en", 0 0, L_0x6357d3324e20; alias, 1 drivers +v0x6357d3303960_0 .var "v_cnt", 11 0; +v0x6357d3303a40_0 .net "visible", 0 0, L_0x6357d331b880; 1 drivers +v0x6357d3303b00_0 .var "visible_d1", 0 0; +v0x6357d3303bc0_0 .var "vs_d1", 0 0; +v0x6357d3303c80_0 .var "vs_sync_sh", 2 0; +v0x6357d3303d60_0 .var "vs_toggle", 0 0; +v0x6357d3303e20_0 .net "vs_wire", 0 0, L_0x6357d331c220; 1 drivers +E_0x6357d326d690/0 .event edge, v0x6357d33033a0_0, v0x6357d33023e0_0, v0x6357d33025a0_0, v0x6357d33024c0_0; +E_0x6357d326d690/1 .event edge, v0x6357d33014d0_0; +E_0x6357d326d690 .event/or E_0x6357d326d690/0, E_0x6357d326d690/1; +E_0x6357d321f390/0 .event negedge, v0x6357d32f7a30_0; +E_0x6357d321f390/1 .event posedge, v0x6357d33017f0_0; +E_0x6357d321f390 .event/or E_0x6357d321f390/0, E_0x6357d321f390/1; +E_0x6357d32e13f0/0 .event edge, v0x6357d3300d70_0, v0x6357d33033a0_0, v0x6357d32d99b0_0, v0x6357d3301ba0_0; +E_0x6357d32e13f0/1 .event edge, v0x6357d3303100_0, v0x6357d33031e0_0, v0x6357d33032c0_0, v0x6357d3302e60_0; +E_0x6357d32e13f0/2 .event edge, v0x6357d3302f40_0, v0x6357d3303020_0; +E_0x6357d32e13f0 .event/or E_0x6357d32e13f0/0, E_0x6357d32e13f0/1, E_0x6357d32e13f0/2; +L_0x6357d331af10 .part v0x6357d3303100_0, 1, 1; +L_0x6357d331b000 .part v0x6357d3303100_0, 1, 1; +L_0x6357d331b330 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d37560a8; +L_0x6357d331b450 .cmp/gt 32, L_0x7d66d37560f0, L_0x6357d331b330; +L_0x6357d331b5c0 .concat [ 12 20 0 0], v0x6357d3303960_0, L_0x7d66d3756138; +L_0x6357d331b700 .cmp/gt 32, L_0x7d66d3756180, L_0x6357d331b5c0; +L_0x6357d331b990 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d37561c8; +L_0x6357d331bad0 .cmp/ge 32, L_0x6357d331b990, L_0x7d66d3756210; +L_0x6357d331bc60 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756258; +L_0x6357d331bd50 .cmp/gt 32, L_0x7d66d37562a0, L_0x6357d331bc60; +L_0x6357d331bfa0 .concat [ 12 20 0 0], v0x6357d3303960_0, L_0x7d66d37562e8; +L_0x6357d331c0e0 .cmp/ge 32, L_0x6357d331bfa0, L_0x7d66d3756330; +L_0x6357d331c290 .concat [ 12 20 0 0], v0x6357d3303960_0, L_0x7d66d3756378; +L_0x6357d331c380 .cmp/gt 32, L_0x7d66d37563c0, L_0x6357d331c290; +L_0x6357d331c5e0 .array/port v0x6357d3302be0, L_0x6357d331c7b0; +L_0x6357d331c680 .part v0x6357d3302ca0_0, 16, 8; +L_0x6357d331c7b0 .concat [ 8 2 0 0], L_0x6357d331c680, L_0x7d66d3756408; +L_0x6357d331ca50 .array/port v0x6357d3302be0, L_0x6357d331cc80; +L_0x6357d331cb90 .part v0x6357d3302ca0_0, 8, 8; +L_0x6357d331cc80 .concat [ 8 2 0 0], L_0x6357d331cb90, L_0x7d66d3756450; +L_0x6357d331caf0 .array/port v0x6357d3302be0, L_0x6357d331d0e0; +L_0x6357d331cf80 .part v0x6357d3302ca0_0, 0, 8; +L_0x6357d331d0e0 .concat [ 8 2 0 0], L_0x6357d331cf80, L_0x7d66d3756498; +L_0x6357d331d390 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d37564e0; +L_0x6357d331d500 .cmp/gt 32, L_0x7d66d3756528, L_0x6357d331d390; +L_0x6357d331d5f0 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756570; +L_0x6357d331d7c0 .arith/mult 32, L_0x6357d331d5f0, L_0x7d66d37565b8; +L_0x6357d331d930 .arith/div 32, L_0x6357d331d7c0, L_0x7d66d3756600; +L_0x6357d331db60 .functor MUXZ 32, L_0x7d66d3756648, L_0x6357d331d930, L_0x6357d331d500, C4<>; +L_0x6357d331dcf0 .part L_0x6357d331db60, 0, 8; +L_0x6357d331dee0 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756690; +L_0x6357d331dfd0 .cmp/gt 32, L_0x7d66d37566d8, L_0x6357d331dee0; +L_0x6357d331e220 .concat [ 12 20 0 0], v0x6357d3303960_0, L_0x7d66d3756720; +L_0x6357d331e2c0 .cmp/gt 32, L_0x7d66d3756768, L_0x6357d331e220; +L_0x6357d331e660 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d37567b0; +L_0x6357d331e750 .arith/mod 32, L_0x6357d331e660, L_0x7d66d37567f8; +L_0x6357d331e430 .cmp/eq 32, L_0x6357d331e750, L_0x7d66d3756840; +L_0x6357d331ea10 .concat [ 12 20 0 0], v0x6357d3303960_0, L_0x7d66d3756888; +L_0x6357d331ec40 .arith/mod 32, L_0x6357d331ea10, L_0x7d66d37568d0; +L_0x6357d331ef90 .cmp/eq 32, L_0x6357d331ec40, L_0x7d66d3756918; +L_0x6357d331f4b0 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756960; +L_0x6357d331f5a0 .cmp/gt 32, L_0x7d66d37569a8, L_0x6357d331f4b0; +L_0x6357d331f840 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756a38; +L_0x6357d331f930 .cmp/gt 32, L_0x7d66d3756a80, L_0x6357d331f840; +L_0x6357d331fc10 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756b10; +L_0x6357d331fd30 .cmp/gt 32, L_0x7d66d3756b58, L_0x6357d331fc10; +L_0x6357d3320020 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756be8; +L_0x6357d3320140 .cmp/gt 32, L_0x7d66d3756c30, L_0x6357d3320020; +L_0x6357d3320440 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756cc0; +L_0x6357d3320560 .cmp/gt 32, L_0x7d66d3756d08, L_0x6357d3320440; +L_0x6357d3320870 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756d98; +L_0x6357d3320990 .cmp/gt 32, L_0x7d66d3756de0, L_0x6357d3320870; +L_0x6357d3320cb0 .concat [ 12 20 0 0], v0x6357d3302660_0, L_0x7d66d3756e70; +L_0x6357d3320dd0 .cmp/gt 32, L_0x7d66d3756eb8, L_0x6357d3320cb0; +L_0x6357d3321100 .functor MUXZ 3, L_0x7d66d3756f48, L_0x7d66d3756f00, L_0x6357d3320dd0, C4<>; +L_0x6357d33212c0 .functor MUXZ 3, L_0x6357d3321100, L_0x7d66d3756e28, L_0x6357d3320990, C4<>; +L_0x6357d3321620 .functor MUXZ 3, L_0x6357d33212c0, L_0x7d66d3756d50, L_0x6357d3320560, C4<>; +L_0x6357d33217b0 .functor MUXZ 3, L_0x6357d3321620, L_0x7d66d3756c78, L_0x6357d3320140, C4<>; +L_0x6357d3321b20 .functor MUXZ 3, L_0x6357d33217b0, L_0x7d66d3756ba0, L_0x6357d331fd30, C4<>; +L_0x6357d3321cb0 .functor MUXZ 3, L_0x6357d3321b20, L_0x7d66d3756ac8, L_0x6357d331f930, C4<>; +L_0x6357d3322030 .functor MUXZ 3, L_0x6357d3321cb0, L_0x7d66d37569f0, L_0x6357d331f5a0, C4<>; +L_0x6357d33221c0 .concat [ 5 3 0 0], L_0x7d66d3756f90, L_0x6357d3322030; +L_0x6357d3322500 .part v0x6357d3303960_0, 2, 4; +L_0x6357d33225a0 .part v0x6357d3302660_0, 2, 4; +L_0x6357d3322850 .array/port v0x6357d3301330, L_0x6357d33228f0; +L_0x6357d33228f0 .concat [ 4 2 0 0], L_0x6357d3322500, L_0x7d66d3756fd8; +L_0x6357d3322de0 .concat [ 4 28 0 0], L_0x6357d33225a0, L_0x7d66d3757068; +L_0x6357d3322f20 .arith/sub 32, L_0x7d66d3757020, L_0x6357d3322de0; +L_0x6357d3323290 .part/v L_0x6357d3322ca0, L_0x6357d3322f20, 1; +L_0x6357d33233d0 .part v0x6357d3302660_0, 0, 8; +L_0x6357d33236b0 .part v0x6357d3303960_0, 0, 8; +L_0x6357d3323750 .arith/sum 8, L_0x6357d33233d0, L_0x6357d33236b0; +L_0x6357d3323ae0 .part v0x6357d3302660_0, 2, 8; +L_0x6357d3323b80 .part v0x6357d3303960_0, 2, 8; +L_0x6357d3323e80 .concat [ 8 8 8 0], L_0x6357d3323b80, L_0x6357d3323ae0, L_0x6357d3323750; +L_0x6357d3324010 .functor MUXZ 24, L_0x7d66d37570b0, L_0x6357d3323e80, L_0x6357d3323290, C4<>; +L_0x6357d3324410 .concat [ 12 20 0 0], v0x6357d3303960_0, L_0x7d66d37570f8; +L_0x6357d3324500 .cmp/gt 32, L_0x7d66d3757140, L_0x6357d3324410; +L_0x6357d3324960 .part v0x6357d33033a0_0, 0, 4; +L_0x6357d3324a50 .cmp/eq 4, L_0x6357d3324960, L_0x7d66d3757188; +S_0x6357d33041c0 .scope module, "u_simple_fifo" "simple_dcfifo" 3 139, 6 3 0, S_0x6357d32c8880; + .timescale -9 -12; + .port_info 0 /INPUT 1 "wrclk"; + .port_info 1 /INPUT 32 "data"; + .port_info 2 /INPUT 1 "wrreq"; + .port_info 3 /OUTPUT 9 "wrusedw"; + .port_info 4 /OUTPUT 1 "wrfull"; + .port_info 5 /INPUT 1 "rdclk"; + .port_info 6 /INPUT 1 "rdreq"; + .port_info 7 /OUTPUT 32 "q"; + .port_info 8 /OUTPUT 1 "rdempty"; +P_0x6357d32434d0 .param/l "ADDR_WIDTH" 0 6 5, +C4<00000000000000000000000000001001>; +P_0x6357d3243510 .param/l "DATA_WIDTH" 0 6 4, +C4<00000000000000000000000000100000>; +L_0x6357d31facf0 .functor NOT 2, L_0x6357d330a440, C4<00>, C4<00>, C4<00>; +v0x6357d3304e80_0 .net *"_ivl_15", 0 0, L_0x6357d330aa40; 1 drivers +L_0x7d66d3756060 .functor BUFT 1, C4<111111111>, C4<0>, C4<0>, C4<0>; +v0x6357d3304f80_0 .net/2u *"_ivl_16", 8 0, L_0x7d66d3756060; 1 drivers +v0x6357d3305060_0 .net *"_ivl_19", 8 0, L_0x6357d331ab40; 1 drivers +v0x6357d3305150_0 .net *"_ivl_3", 1 0, L_0x6357d330a440; 1 drivers +v0x6357d3305230_0 .net *"_ivl_4", 1 0, L_0x6357d31facf0; 1 drivers +v0x6357d3305360_0 .net *"_ivl_7", 7 0, L_0x6357d330a580; 1 drivers +v0x6357d3305440_0 .net *"_ivl_8", 9 0, L_0x6357d330a620; 1 drivers +v0x6357d3305520_0 .net "data", 31 0, L_0x6357d329eeb0; alias, 1 drivers +v0x6357d33055e0 .array "mem", 0 511, 31 0; +v0x6357d3305680_0 .var "q", 31 0; +v0x6357d3305760_0 .var "rd_ptr_bin", 9 0; +v0x6357d3305840_0 .net "rd_ptr_bin_sync", 9 0, L_0x6357d330a3a0; 1 drivers +v0x6357d3305920_0 .var "rd_ptr_gray", 9 0; +v0x6357d3305a00_0 .var "rd_ptr_gray_sync1", 9 0; +v0x6357d3305ae0_0 .var "rd_ptr_gray_sync2", 9 0; +v0x6357d3305bc0_0 .net "rdclk", 0 0, o0x7d66d37a1298; alias, 0 drivers +v0x6357d3305c90_0 .net "rdempty", 0 0, L_0x6357d331adc0; alias, 1 drivers +v0x6357d3305d30_0 .net "rdreq", 0 0, L_0x6357d3324e20; alias, 1 drivers +v0x6357d3305e00_0 .net "used_diff", 9 0, L_0x6357d330a8a0; 1 drivers +v0x6357d3305ec0_0 .var "wr_ptr_bin", 9 0; +v0x6357d3305fa0_0 .var "wr_ptr_gray", 9 0; +v0x6357d3306080_0 .var "wr_ptr_gray_sync1", 9 0; +v0x6357d3306160_0 .var "wr_ptr_gray_sync2", 9 0; +v0x6357d3306240_0 .net "wrclk", 0 0, o0x7d66d379f048; alias, 0 drivers +v0x6357d33062e0_0 .net "wrfull", 0 0, L_0x6357d330a760; alias, 1 drivers +v0x6357d33063a0_0 .net "wrreq", 0 0, L_0x6357d32db310; alias, 1 drivers +v0x6357d3306440_0 .net "wrusedw", 8 0, L_0x6357d331ac30; alias, 1 drivers +E_0x6357d32e17c0 .event posedge, v0x6357d33017f0_0; +E_0x6357d32e19f0 .event posedge, v0x6357d32dc040_0; +L_0x6357d330a3a0 .ufunc/vec4 TD_video_pipeline.u_simple_fifo.gray2bin, 10, v0x6357d3305ae0_0 (v0x6357d3304bd0_0) S_0x6357d33049d0; +L_0x6357d330a440 .part v0x6357d3305ae0_0, 8, 2; +L_0x6357d330a580 .part v0x6357d3305ae0_0, 0, 8; +L_0x6357d330a620 .concat [ 8 2 0 0], L_0x6357d330a580, L_0x6357d31facf0; +L_0x6357d330a760 .cmp/eq 10, v0x6357d3305fa0_0, L_0x6357d330a620; +L_0x6357d330a8a0 .arith/sub 10, v0x6357d3305ec0_0, L_0x6357d330a3a0; +L_0x6357d330aa40 .part L_0x6357d330a8a0, 9, 1; +L_0x6357d331ab40 .part L_0x6357d330a8a0, 0, 9; +L_0x6357d331ac30 .functor MUXZ 9, L_0x6357d331ab40, L_0x7d66d3756060, L_0x6357d330aa40, C4<>; +L_0x6357d331adc0 .cmp/eq 10, v0x6357d3305920_0, v0x6357d3306160_0; +S_0x6357d33045f0 .scope function.vec4.s10, "bin2gray" "bin2gray" 6 52, 6 52 0, S_0x6357d33041c0; + .timescale -9 -12; +v0x6357d33047f0_0 .var "bin", 9 0; +; Variable bin2gray is vec4 return value of scope S_0x6357d33045f0 +TD_video_pipeline.u_simple_fifo.bin2gray ; + %load/vec4 v0x6357d33047f0_0; + %load/vec4 v0x6357d33047f0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %xor; + %ret/vec4 0, 0, 10; Assign to bin2gray (store_vec4_to_lval) + %end; +S_0x6357d33049d0 .scope function.vec4.s10, "gray2bin" "gray2bin" 6 59, 6 59 0, S_0x6357d33041c0; + .timescale -9 -12; +v0x6357d3304bd0_0 .var "gray", 9 0; +; Variable gray2bin is vec4 return value of scope S_0x6357d33049d0 +v0x6357d3304d90_0 .var/i "i", 31 0; +TD_video_pipeline.u_simple_fifo.gray2bin ; + %load/vec4 v0x6357d3304bd0_0; + %parti/s 1, 9, 5; + %ix/load 4, 9, 0; + %flag_set/imm 4, 0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %pushi/vec4 8, 0, 32; + %store/vec4 v0x6357d3304d90_0, 0, 32; +T_1.0 ; + %load/vec4 v0x6357d3304d90_0; + %cmpi/s 0, 0, 32; + %flag_inv 5; GE is !LT + %jmp/0xz T_1.1, 5; + %retload/vec4 0; Load gray2bin (draw_signal_vec4) + %load/vec4 v0x6357d3304d90_0; + %addi 1, 0, 32; + %part/s 1; + %load/vec4 v0x6357d3304bd0_0; + %load/vec4 v0x6357d3304d90_0; + %part/s 1; + %xor; + %ix/getv/s 4, v0x6357d3304d90_0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %load/vec4 v0x6357d3304d90_0; + %subi 1, 0, 32; + %store/vec4 v0x6357d3304d90_0, 0, 32; + %jmp T_1.0; +T_1.1 ; + %end; + .scope S_0x6357d32a9590; +T_2 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d32f7a30_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x6357d32f7bd0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d32f7360_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f7520_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d32dc0e0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d32f7d70_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f72a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f71e0_0, 0; + %pushi/vec4 0, 0, 10; + %assign/vec4 v0x6357d32f7950_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x6357d32f7bd0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_2.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_2.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_2.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_2.5, 6; + %jmp T_2.6; +T_2.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f7520_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d32f7d70_0, 0; + %load/vec4 v0x6357d329fcc0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.7, 8; + %load/vec4 v0x6357d32f7af0_0; + %assign/vec4 v0x6357d32dc0e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f72a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d32f71e0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x6357d32f7bd0_0, 0; + %jmp T_2.8; +T_2.7 ; + %load/vec4 v0x6357d329f010_0; + %load/vec4 v0x6357d32f7cb0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.9, 8; + %load/vec4 v0x6357d32f7af0_0; + %assign/vec4 v0x6357d32dc0e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d32f72a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d32f71e0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x6357d32f7bd0_0, 0; + %jmp T_2.10; +T_2.9 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f71e0_0, 0; +T_2.10 ; +T_2.8 ; + %jmp T_2.6; +T_2.3 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f7520_0, 0; + %load/vec4 v0x6357d32f7d70_0; + %pad/u 64; + %cmpi/u 518400, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_2.11, 5; + %pushi/vec4 3, 0, 2; + %assign/vec4 v0x6357d32f7bd0_0, 0; + %jmp T_2.12; +T_2.11 ; + %load/vec4 v0x6357d329fd90_0; + %pad/u 32; + %load/vec4 v0x6357d32f7d70_0; + %load/vec4 v0x6357d32f7e50_0; + %sub; + %add; + %cmpi/u 446, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_2.13, 5; + %load/vec4 v0x6357d32dc0e0_0; + %assign/vec4 v0x6357d32f7360_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d32f7520_0, 0; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x6357d32f7bd0_0, 0; +T_2.13 ; +T_2.12 ; + %jmp T_2.6; +T_2.4 ; + %load/vec4 v0x6357d32f7780_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.15, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f7520_0, 0; + %load/vec4 v0x6357d32dc0e0_0; + %addi 256, 0, 32; + %assign/vec4 v0x6357d32dc0e0_0, 0; + %load/vec4 v0x6357d32f7d70_0; + %addi 64, 0, 32; + %assign/vec4 v0x6357d32f7d70_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x6357d32f7bd0_0, 0; +T_2.15 ; + %jmp T_2.6; +T_2.5 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f7520_0, 0; + %load/vec4 v0x6357d32f7e50_0; + %pad/u 64; + %cmpi/u 518400, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_2.17, 5; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x6357d32f7bd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f71e0_0, 0; +T_2.17 ; + %jmp T_2.6; +T_2.6 ; + %pop/vec4 1; + %load/vec4 v0x6357d32f72a0_0; + %load/vec4 v0x6357d329f010_0; + %nor/r; + %and; + %load/vec4 v0x6357d32f7bd0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.19, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d32f72a0_0, 0; +T_2.19 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x6357d32a9590; +T_3 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d32f7a30_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d32f7e50_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0x6357d32f7bd0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x6357d329fcc0_0; + %load/vec4 v0x6357d329f010_0; + %load/vec4 v0x6357d32f7cb0_0; + %and; + %or; + %and; + %flag_set/vec4 8; + %jmp/0xz T_3.2, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d32f7e50_0, 0; +T_3.2 ; + %load/vec4 v0x6357d32f76c0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.4, 8; + %load/vec4 v0x6357d32f7e50_0; + %addi 1, 0, 32; + %assign/vec4 v0x6357d32f7e50_0, 0; +T_3.4 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x6357d32a9590; +T_4 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d32f7a30_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d329f0e0_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x6357d32f76c0_0; + %load/vec4 v0x6357d32f7e50_0; + %pad/u 64; + %pushi/vec4 518399, 0, 64; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d329f0e0_0, 0; + %jmp T_4.3; +T_4.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d329f0e0_0, 0; +T_4.3 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x6357d33041c0; +T_5 ; + %wait E_0x6357d32e19f0; + %load/vec4 v0x6357d3305920_0; + %assign/vec4 v0x6357d3305a00_0, 0; + %load/vec4 v0x6357d3305a00_0; + %assign/vec4 v0x6357d3305ae0_0, 0; + %jmp T_5; + .thread T_5; + .scope S_0x6357d33041c0; +T_6 ; + %wait E_0x6357d32e17c0; + %load/vec4 v0x6357d3305fa0_0; + %assign/vec4 v0x6357d3306080_0, 0; + %load/vec4 v0x6357d3306080_0; + %assign/vec4 v0x6357d3306160_0, 0; + %jmp T_6; + .thread T_6; + .scope S_0x6357d33041c0; +T_7 ; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3305ec0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3305fa0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3305760_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3305920_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3306080_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3306160_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3305a00_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6357d3305ae0_0, 0, 10; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x6357d3305680_0, 0, 32; + %end; + .thread T_7; + .scope S_0x6357d33041c0; +T_8 ; + %wait E_0x6357d32e19f0; + %load/vec4 v0x6357d33063a0_0; + %load/vec4 v0x6357d33062e0_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x6357d3305520_0; + %load/vec4 v0x6357d3305ec0_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d33055e0, 0, 4; + %load/vec4 v0x6357d3305ec0_0; + %addi 1, 0, 10; + %assign/vec4 v0x6357d3305ec0_0, 0; + %load/vec4 v0x6357d3305ec0_0; + %addi 1, 0, 10; + %store/vec4 v0x6357d33047f0_0, 0, 10; + %callf/vec4 TD_video_pipeline.u_simple_fifo.bin2gray, S_0x6357d33045f0; + %assign/vec4 v0x6357d3305fa0_0, 0; +T_8.0 ; + %jmp T_8; + .thread T_8; + .scope S_0x6357d33041c0; +T_9 ; + %wait E_0x6357d32e17c0; + %load/vec4 v0x6357d3305d30_0; + %load/vec4 v0x6357d3305c90_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %load/vec4 v0x6357d3305760_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 4; + %load/vec4a v0x6357d33055e0, 4; + %assign/vec4 v0x6357d3305680_0, 0; + %load/vec4 v0x6357d3305760_0; + %addi 1, 0, 10; + %assign/vec4 v0x6357d3305760_0, 0; + %load/vec4 v0x6357d3305760_0; + %addi 1, 0, 10; + %store/vec4 v0x6357d33047f0_0, 0, 10; + %callf/vec4 TD_video_pipeline.u_simple_fifo.bin2gray, S_0x6357d33045f0; + %assign/vec4 v0x6357d3305920_0, 0; +T_9.0 ; + %jmp T_9; + .thread T_9; + .scope S_0x6357d32f8150; +T_10 ; + %pushi/vec4 0, 0, 12; + %store/vec4 v0x6357d3302660_0, 0, 12; + %pushi/vec4 0, 0, 12; + %store/vec4 v0x6357d3303960_0, 0, 12; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x6357d3303b00_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x6357d3302a60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x6357d3303bc0_0, 0, 1; + %pushi/vec4 0, 0, 24; + %store/vec4 v0x6357d3302740_0, 0, 24; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x6357d3302820_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x6357d33028e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x6357d33029a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x6357d3303d60_0, 0, 1; + %end; + .thread T_10; + .scope S_0x6357d32f8150; +T_11 ; + %wait E_0x6357d32e13f0; + %load/vec4 v0x6357d3300d70_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_11.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_11.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_11.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_11.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_11.6, 6; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.0 ; + %load/vec4 v0x6357d33033a0_0; + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.1 ; + %load/vec4 v0x6357d3301970_0; + %load/vec4 v0x6357d3301ba0_0; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 28; + %load/vec4 v0x6357d3303100_0; + %parti/s 1, 1, 2; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6357d3303100_0; + %parti/s 1, 0, 2; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.2 ; + %load/vec4 v0x6357d33031e0_0; + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.3 ; + %load/vec4 v0x6357d33032c0_0; + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.4 ; + %load/vec4 v0x6357d3302e60_0; + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.5 ; + %load/vec4 v0x6357d3302f40_0; + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.6 ; + %load/vec4 v0x6357d3303020_0; + %store/vec4 v0x6357d3302d80_0, 0, 32; + %jmp T_11.8; +T_11.8 ; + %pop/vec4 1; + %jmp T_11; + .thread T_11, $push; + .scope S_0x6357d32f8150; +T_12 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d3303560_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d33033a0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d3303100_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d33031e0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6357d33032c0_0, 0; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x6357d3303020_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3300ff0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3301de0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3301ba0_0, 0; + %pushi/vec4 0, 0, 16; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 4, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 5, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 6, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 7, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 8, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 9, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 10, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 11, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 12, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 13, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 14, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 15, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %jmp T_12.1; +T_12.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3301de0_0, 0; + %load/vec4 v0x6357d3301ae0_0; + %flag_set/vec4 8; + %jmp/0xz T_12.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d3301ba0_0, 0; +T_12.2 ; + %load/vec4 v0x6357d33010b0_0; + %flag_set/vec4 8; + %jmp/0xz T_12.4, 8; + %load/vec4 v0x6357d3300d70_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_12.6, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_12.7, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_12.8, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_12.9, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_12.10, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_12.11, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_12.12, 6; + %jmp T_12.14; +T_12.6 ; + %load/vec4 v0x6357d3301170_0; + %assign/vec4 v0x6357d33033a0_0, 0; + %jmp T_12.14; +T_12.7 ; + %load/vec4 v0x6357d3301170_0; + %parti/s 2, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x6357d3303100_0, 4, 5; + %load/vec4 v0x6357d3301170_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_12.15, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d3301de0_0, 0; +T_12.15 ; + %load/vec4 v0x6357d3301170_0; + %parti/s 1, 30, 6; + %flag_set/vec4 8; + %jmp/0xz T_12.17, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3301ba0_0, 0; +T_12.17 ; + %jmp T_12.14; +T_12.8 ; + %load/vec4 v0x6357d3301170_0; + %assign/vec4 v0x6357d33031e0_0, 0; + %jmp T_12.14; +T_12.9 ; + %load/vec4 v0x6357d3301170_0; + %assign/vec4 v0x6357d33032c0_0, 0; + %load/vec4 v0x6357d3301170_0; + %parti/s 8, 0, 2; + %load/vec4 v0x6357d33031e0_0; + %parti/s 8, 0, 2; + %pad/u 10; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3302be0, 0, 4; + %jmp T_12.14; +T_12.10 ; + %load/vec4 v0x6357d3301170_0; + %assign/vec4 v0x6357d3302e60_0, 0; + %jmp T_12.14; +T_12.11 ; + %load/vec4 v0x6357d3301170_0; + %assign/vec4 v0x6357d3302f40_0, 0; + %load/vec4 v0x6357d3301170_0; + %parti/s 16, 0, 2; + %load/vec4 v0x6357d3302e60_0; + %parti/s 4, 0, 2; + %pad/u 6; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6357d3301330, 0, 4; + %jmp T_12.14; +T_12.12 ; + %load/vec4 v0x6357d3301170_0; + %assign/vec4 v0x6357d3303020_0, 0; + %jmp T_12.14; +T_12.14 ; + %pop/vec4 1; +T_12.4 ; + %load/vec4 v0x6357d3300e50_0; + %assign/vec4 v0x6357d3300ff0_0, 0; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x6357d32f8150; +T_13 ; + %wait E_0x6357d321f390; + %load/vec4 v0x6357d3303560_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_13.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6357d3302660_0, 0; + %jmp T_13.1; +T_13.0 ; + %load/vec4 v0x6357d3302660_0; + %pad/u 32; + %cmpi/e 1119, 0, 32; + %jmp/0xz T_13.2, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6357d3302660_0, 0; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0x6357d3302660_0; + %addi 1, 0, 12; + %assign/vec4 v0x6357d3302660_0, 0; +T_13.3 ; +T_13.1 ; + %jmp T_13; + .thread T_13; + .scope S_0x6357d32f8150; +T_14 ; + %wait E_0x6357d321f390; + %load/vec4 v0x6357d3303560_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6357d3303960_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v0x6357d3302660_0; + %pad/u 32; + %cmpi/e 1119, 0, 32; + %jmp/0xz T_14.2, 4; + %load/vec4 v0x6357d3303960_0; + %pad/u 32; + %cmpi/e 562, 0, 32; + %jmp/0xz T_14.4, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6357d3303960_0, 0; + %jmp T_14.5; +T_14.4 ; + %load/vec4 v0x6357d3303960_0; + %addi 1, 0, 12; + %assign/vec4 v0x6357d3303960_0, 0; +T_14.5 ; +T_14.2 ; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x6357d32f8150; +T_15 ; + %wait E_0x6357d321f390; + %load/vec4 v0x6357d3303560_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_15.0, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d33028e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6357d33029a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3302820_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3303b00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3302a60_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3303bc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3303d60_0, 0; + %jmp T_15.1; +T_15.0 ; + %load/vec4 v0x6357d3303a40_0; + %assign/vec4 v0x6357d3303b00_0, 0; + %load/vec4 v0x6357d3302b20_0; + %assign/vec4 v0x6357d3302a60_0, 0; + %load/vec4 v0x6357d3303e20_0; + %assign/vec4 v0x6357d3303bc0_0, 0; + %load/vec4 v0x6357d3302a60_0; + %inv; + %assign/vec4 v0x6357d33028e0_0, 0; + %load/vec4 v0x6357d3303bc0_0; + %inv; + %assign/vec4 v0x6357d33029a0_0, 0; + %load/vec4 v0x6357d3303b00_0; + %assign/vec4 v0x6357d3302820_0, 0; + %load/vec4 v0x6357d3303e20_0; + %load/vec4 v0x6357d3303bc0_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_15.2, 8; + %load/vec4 v0x6357d3303d60_0; + %inv; + %assign/vec4 v0x6357d3303d60_0, 0; +T_15.2 ; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_0x6357d32f8150; +T_16 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d3303560_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_16.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6357d3303c80_0, 0; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x6357d3303630_0, 0; + %jmp T_16.1; +T_16.0 ; + %load/vec4 v0x6357d3303c80_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6357d3303e20_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6357d3303c80_0, 0; + %load/vec4 v0x6357d3303c80_0; + %parti/s 1, 1, 2; + %load/vec4 v0x6357d3303c80_0; + %parti/s 1, 2, 3; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_16.2, 8; + %load/vec4 v0x6357d3303020_0; + %assign/vec4 v0x6357d3303630_0, 0; +T_16.2 ; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_0x6357d32f8150; +T_17 ; + %wait E_0x6357d326d690; + %load/vec4 v0x6357d33033a0_0; + %parti/s 4, 0, 2; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_17.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_17.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_17.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_17.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_17.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_17.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_17.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_17.7, 6; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.0 ; + %pushi/vec4 16711680, 0, 24; + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.1 ; + %pushi/vec4 65280, 0, 24; + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.2 ; + %pushi/vec4 255, 0, 24; + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.3 ; + %load/vec4 v0x6357d33023e0_0; + %load/vec4 v0x6357d33023e0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6357d33023e0_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.4 ; + %load/vec4 v0x6357d33025a0_0; + %flag_set/vec4 8; + %jmp/0 T_17.10, 8; + %pushi/vec4 16777215, 0, 24; + %jmp/1 T_17.11, 8; +T_17.10 ; End of true expr. + %pushi/vec4 0, 0, 24; + %jmp/0 T_17.11, 8; + ; End of false expr. + %blend; +T_17.11; + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.5 ; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.6 ; + %load/vec4 v0x6357d33024c0_0; + %load/vec4 v0x6357d33024c0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6357d33024c0_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.7 ; + %load/vec4 v0x6357d33014d0_0; + %store/vec4 v0x6357d3302ca0_0, 0, 24; + %jmp T_17.9; +T_17.9 ; + %pop/vec4 1; + %jmp T_17; + .thread T_17, $push; + .scope S_0x6357d32f8150; +T_18 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d3303560_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_18.0, 8; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x6357d3302740_0, 0; + %jmp T_18.1; +T_18.0 ; + %load/vec4 v0x6357d3303b00_0; + %flag_set/vec4 8; + %jmp/0xz T_18.2, 8; + %load/vec4 v0x6357d3303100_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_18.4, 8; + %load/vec4 v0x6357d3302300_0; + %load/vec4 v0x6357d3302220_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6357d3302140_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6357d3302740_0, 0; + %jmp T_18.5; +T_18.4 ; + %load/vec4 v0x6357d33033a0_0; + %parti/s 4, 0, 2; + %cmpi/e 8, 0, 4; + %jmp/0xz T_18.6, 4; + %load/vec4 v0x6357d33037e0_0; + %assign/vec4 v0x6357d3302740_0, 0; + %jmp T_18.7; +T_18.6 ; + %load/vec4 v0x6357d3302ca0_0; + %assign/vec4 v0x6357d3302740_0, 0; +T_18.7 ; +T_18.5 ; + %jmp T_18.3; +T_18.2 ; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x6357d3302740_0, 0; +T_18.3 ; +T_18.1 ; + %jmp T_18; + .thread T_18; + .scope S_0x6357d32c8880; +T_19 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d3308e90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_19.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6357d3309690_0, 0; + %jmp T_19.1; +T_19.0 ; + %load/vec4 v0x6357d3309690_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6357d3309520_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6357d3309690_0, 0; +T_19.1 ; + %jmp T_19; + .thread T_19; + .scope S_0x6357d32c8880; +T_20 ; + %wait E_0x6357d321f390; + %load/vec4 v0x6357d3308e90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_20.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3307f50_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3307d40_0, 0; + %jmp T_20.1; +T_20.0 ; + %load/vec4 v0x6357d3307c70_0; + %assign/vec4 v0x6357d3307d40_0, 0; + %load/vec4 v0x6357d3307c70_0; + %load/vec4 v0x6357d3307d40_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_20.2, 8; + %load/vec4 v0x6357d3307f50_0; + %inv; + %assign/vec4 v0x6357d3307f50_0, 0; +T_20.2 ; +T_20.1 ; + %jmp T_20; + .thread T_20; + .scope S_0x6357d32c8880; +T_21 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d3308e90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_21.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6357d3307eb0_0, 0; + %jmp T_21.1; +T_21.0 ; + %load/vec4 v0x6357d3307eb0_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6357d3307f50_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6357d3307eb0_0, 0; +T_21.1 ; + %jmp T_21; + .thread T_21; + .scope S_0x6357d32c8880; +T_22 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d3308e90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_22.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6357d3307830_0, 0; + %jmp T_22.1; +T_22.0 ; + %load/vec4 v0x6357d3307830_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6357d33076f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6357d3307830_0, 0; +T_22.1 ; + %jmp T_22; + .thread T_22; + .scope S_0x6357d32c8880; +T_23 ; + %wait E_0x6357d3258cf0; + %load/vec4 v0x6357d3308e90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_23.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6357d3307ae0_0, 0; + %jmp T_23.1; +T_23.0 ; + %load/vec4 v0x6357d33078d0_0; + %flag_set/vec4 8; + %jmp/0xz T_23.2, 8; + %load/vec4 v0x6357d3307ae0_0; + %inv; + %assign/vec4 v0x6357d3307ae0_0, 0; +T_23.2 ; +T_23.1 ; + %jmp T_23; + .thread T_23; + .scope S_0x6357d32c8880; +T_24 ; + %wait E_0x6357d321f390; + %load/vec4 v0x6357d3308e90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_24.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6357d3307a40_0, 0; + %jmp T_24.1; +T_24.0 ; + %load/vec4 v0x6357d3307a40_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6357d3307ae0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6357d3307a40_0, 0; +T_24.1 ; + %jmp T_24; + .thread T_24; +# The file index is used to find the file name in the following table. +:file_names 7; + "N/A"; + ""; + "-"; + "/mnt/c/Workspace/quartus/video_processing/RTL/video_pipeline.v"; + "/mnt/c/Workspace/quartus/video_processing/RTL/video_dma_master.v"; + "/mnt/c/Workspace/quartus/video_processing/RTL/hdmi_sync_gen.v"; + "/mnt/c/Workspace/quartus/video_processing/RTL/simple_dcfifo.v"; diff --git a/soc_system.qsys b/soc_system.qsys index 6d744bd..f3e411c 100644 --- a/soc_system.qsys +++ b/soc_system.qsys @@ -1150,7 +1150,7 @@ - + @@ -1487,7 +1487,7 @@ - + @@ -1803,6 +1803,15 @@ + + + + + diff --git a/soc_system/soc_system_bb.v b/soc_system/soc_system_bb.v index b3c26ba..0fa6879 100644 --- a/soc_system/soc_system_bb.v +++ b/soc_system/soc_system_bb.v @@ -3,6 +3,16 @@ module soc_system ( button_pio_external_connection_export, clk_clk, dipsw_pio_external_connection_export, + hdmi_sync_master_waitrequest, + hdmi_sync_master_readdata, + hdmi_sync_master_readdatavalid, + hdmi_sync_master_burstcount, + hdmi_sync_master_writedata, + hdmi_sync_master_address, + hdmi_sync_master_write, + hdmi_sync_master_read, + hdmi_sync_master_byteenable, + hdmi_sync_master_debugaccess, hps_0_f2h_cold_reset_req_reset_n, hps_0_f2h_debug_reset_req_reset_n, hps_0_f2h_stm_hw_events_stm_hwevents, @@ -88,21 +98,21 @@ module soc_system ( video_dma_s_write, video_dma_s_read, video_dma_s_byteenable, - video_dma_s_debugaccess, - hdmi_sync_master_waitrequest, - hdmi_sync_master_readdata, - hdmi_sync_master_readdatavalid, - hdmi_sync_master_burstcount, - hdmi_sync_master_writedata, - hdmi_sync_master_address, - hdmi_sync_master_write, - hdmi_sync_master_read, - hdmi_sync_master_byteenable, - hdmi_sync_master_debugaccess); + video_dma_s_debugaccess); input [1:0] button_pio_external_connection_export; input clk_clk; input [3:0] dipsw_pio_external_connection_export; + input hdmi_sync_master_waitrequest; + input [31:0] hdmi_sync_master_readdata; + input hdmi_sync_master_readdatavalid; + output [0:0] hdmi_sync_master_burstcount; + output [31:0] hdmi_sync_master_writedata; + output [2:0] hdmi_sync_master_address; + output hdmi_sync_master_write; + output hdmi_sync_master_read; + output [3:0] hdmi_sync_master_byteenable; + output hdmi_sync_master_debugaccess; input hps_0_f2h_cold_reset_req_reset_n; input hps_0_f2h_debug_reset_req_reset_n; input [27:0] hps_0_f2h_stm_hw_events_stm_hwevents; @@ -189,14 +199,4 @@ module soc_system ( input video_dma_s_read; input [3:0] video_dma_s_byteenable; input video_dma_s_debugaccess; - input hdmi_sync_master_waitrequest; - input [31:0] hdmi_sync_master_readdata; - input hdmi_sync_master_readdatavalid; - output [0:0] hdmi_sync_master_burstcount; - output [31:0] hdmi_sync_master_writedata; - output [2:0] hdmi_sync_master_address; - output hdmi_sync_master_write; - output hdmi_sync_master_read; - output [3:0] hdmi_sync_master_byteenable; - output hdmi_sync_master_debugaccess; endmodule diff --git a/soc_system/soc_system_inst.v b/soc_system/soc_system_inst.v index b2a89ff..8ef5314 100644 --- a/soc_system/soc_system_inst.v +++ b/soc_system/soc_system_inst.v @@ -2,6 +2,16 @@ .button_pio_external_connection_export (), // button_pio_external_connection.export .clk_clk (), // clk.clk .dipsw_pio_external_connection_export (), // dipsw_pio_external_connection.export + .hdmi_sync_master_waitrequest (), // hdmi_sync_master.waitrequest + .hdmi_sync_master_readdata (), // .readdata + .hdmi_sync_master_readdatavalid (), // .readdatavalid + .hdmi_sync_master_burstcount (), // .burstcount + .hdmi_sync_master_writedata (), // .writedata + .hdmi_sync_master_address (), // .address + .hdmi_sync_master_write (), // .write + .hdmi_sync_master_read (), // .read + .hdmi_sync_master_byteenable (), // .byteenable + .hdmi_sync_master_debugaccess (), // .debugaccess .hps_0_f2h_cold_reset_req_reset_n (), // hps_0_f2h_cold_reset_req.reset_n .hps_0_f2h_debug_reset_req_reset_n (), // hps_0_f2h_debug_reset_req.reset_n .hps_0_f2h_stm_hw_events_stm_hwevents (), // hps_0_f2h_stm_hw_events.stm_hwevents @@ -87,16 +97,6 @@ .video_dma_s_write (), // .write .video_dma_s_read (), // .read .video_dma_s_byteenable (), // .byteenable - .video_dma_s_debugaccess (), // .debugaccess - .hdmi_sync_master_waitrequest (), // hdmi_sync_master.waitrequest - .hdmi_sync_master_readdata (), // .readdata - .hdmi_sync_master_readdatavalid (), // .readdatavalid - .hdmi_sync_master_burstcount (), // .burstcount - .hdmi_sync_master_writedata (), // .writedata - .hdmi_sync_master_address (), // .address - .hdmi_sync_master_write (), // .write - .hdmi_sync_master_read (), // .read - .hdmi_sync_master_byteenable (), // .byteenable - .hdmi_sync_master_debugaccess () // .debugaccess + .video_dma_s_debugaccess () // .debugaccess ); diff --git a/soc_system/soc_system_inst.vhd b/soc_system/soc_system_inst.vhd index b98744f..2280102 100644 --- a/soc_system/soc_system_inst.vhd +++ b/soc_system/soc_system_inst.vhd @@ -3,6 +3,16 @@ button_pio_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export clk_clk : in std_logic := 'X'; -- clk dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + hdmi_sync_master_waitrequest : in std_logic := 'X'; -- waitrequest + hdmi_sync_master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata + hdmi_sync_master_readdatavalid : in std_logic := 'X'; -- readdatavalid + hdmi_sync_master_burstcount : out std_logic_vector(0 downto 0); -- burstcount + hdmi_sync_master_writedata : out std_logic_vector(31 downto 0); -- writedata + hdmi_sync_master_address : out std_logic_vector(2 downto 0); -- address + hdmi_sync_master_write : out std_logic; -- write + hdmi_sync_master_read : out std_logic; -- read + hdmi_sync_master_byteenable : out std_logic_vector(3 downto 0); -- byteenable + hdmi_sync_master_debugaccess : out std_logic; -- debugaccess hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents @@ -88,17 +98,7 @@ video_dma_s_write : in std_logic := 'X'; -- write video_dma_s_read : in std_logic := 'X'; -- read video_dma_s_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable - video_dma_s_debugaccess : in std_logic := 'X'; -- debugaccess - hdmi_sync_master_waitrequest : in std_logic := 'X'; -- waitrequest - hdmi_sync_master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata - hdmi_sync_master_readdatavalid : in std_logic := 'X'; -- readdatavalid - hdmi_sync_master_burstcount : out std_logic_vector(0 downto 0); -- burstcount - hdmi_sync_master_writedata : out std_logic_vector(31 downto 0); -- writedata - hdmi_sync_master_address : out std_logic_vector(2 downto 0); -- address - hdmi_sync_master_write : out std_logic; -- write - hdmi_sync_master_read : out std_logic; -- read - hdmi_sync_master_byteenable : out std_logic_vector(3 downto 0); -- byteenable - hdmi_sync_master_debugaccess : out std_logic -- debugaccess + video_dma_s_debugaccess : in std_logic := 'X' -- debugaccess ); end component soc_system; @@ -107,6 +107,16 @@ button_pio_external_connection_export => CONNECTED_TO_button_pio_external_connection_export, -- button_pio_external_connection.export clk_clk => CONNECTED_TO_clk_clk, -- clk.clk dipsw_pio_external_connection_export => CONNECTED_TO_dipsw_pio_external_connection_export, -- dipsw_pio_external_connection.export + hdmi_sync_master_waitrequest => CONNECTED_TO_hdmi_sync_master_waitrequest, -- hdmi_sync_master.waitrequest + hdmi_sync_master_readdata => CONNECTED_TO_hdmi_sync_master_readdata, -- .readdata + hdmi_sync_master_readdatavalid => CONNECTED_TO_hdmi_sync_master_readdatavalid, -- .readdatavalid + hdmi_sync_master_burstcount => CONNECTED_TO_hdmi_sync_master_burstcount, -- .burstcount + hdmi_sync_master_writedata => CONNECTED_TO_hdmi_sync_master_writedata, -- .writedata + hdmi_sync_master_address => CONNECTED_TO_hdmi_sync_master_address, -- .address + hdmi_sync_master_write => CONNECTED_TO_hdmi_sync_master_write, -- .write + hdmi_sync_master_read => CONNECTED_TO_hdmi_sync_master_read, -- .read + hdmi_sync_master_byteenable => CONNECTED_TO_hdmi_sync_master_byteenable, -- .byteenable + hdmi_sync_master_debugaccess => CONNECTED_TO_hdmi_sync_master_debugaccess, -- .debugaccess hps_0_f2h_cold_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_cold_reset_req_reset_n, -- hps_0_f2h_cold_reset_req.reset_n hps_0_f2h_debug_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_debug_reset_req_reset_n, -- hps_0_f2h_debug_reset_req.reset_n hps_0_f2h_stm_hw_events_stm_hwevents => CONNECTED_TO_hps_0_f2h_stm_hw_events_stm_hwevents, -- hps_0_f2h_stm_hw_events.stm_hwevents @@ -192,16 +202,6 @@ video_dma_s_write => CONNECTED_TO_video_dma_s_write, -- .write video_dma_s_read => CONNECTED_TO_video_dma_s_read, -- .read video_dma_s_byteenable => CONNECTED_TO_video_dma_s_byteenable, -- .byteenable - video_dma_s_debugaccess => CONNECTED_TO_video_dma_s_debugaccess, -- .debugaccess - hdmi_sync_master_waitrequest => CONNECTED_TO_hdmi_sync_master_waitrequest, -- hdmi_sync_master.waitrequest - hdmi_sync_master_readdata => CONNECTED_TO_hdmi_sync_master_readdata, -- .readdata - hdmi_sync_master_readdatavalid => CONNECTED_TO_hdmi_sync_master_readdatavalid, -- .readdatavalid - hdmi_sync_master_burstcount => CONNECTED_TO_hdmi_sync_master_burstcount, -- .burstcount - hdmi_sync_master_writedata => CONNECTED_TO_hdmi_sync_master_writedata, -- .writedata - hdmi_sync_master_address => CONNECTED_TO_hdmi_sync_master_address, -- .address - hdmi_sync_master_write => CONNECTED_TO_hdmi_sync_master_write, -- .write - hdmi_sync_master_read => CONNECTED_TO_hdmi_sync_master_read, -- .read - hdmi_sync_master_byteenable => CONNECTED_TO_hdmi_sync_master_byteenable, -- .byteenable - hdmi_sync_master_debugaccess => CONNECTED_TO_hdmi_sync_master_debugaccess -- .debugaccess + video_dma_s_debugaccess => CONNECTED_TO_video_dma_s_debugaccess -- .debugaccess ); diff --git a/test_compile.vvp b/test_compile.vvp new file mode 100644 index 0000000..36195b9 --- /dev/null +++ b/test_compile.vvp @@ -0,0 +1,1602 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi"; +S_0x6467f9d49540 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x6467f9d49890 .scope module, "video_pipeline" "video_pipeline" 3 3; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk_50"; + .port_info 1 /INPUT 1 "clk_hdmi"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "m_waitrequest"; + .port_info 4 /INPUT 32 "m_readdata"; + .port_info 5 /INPUT 1 "m_readdatavalid"; + .port_info 6 /OUTPUT 32 "m_address"; + .port_info 7 /OUTPUT 1 "m_read"; + .port_info 8 /OUTPUT 8 "m_burstcount"; + .port_info 9 /INPUT 3 "s_address"; + .port_info 10 /INPUT 1 "s_read"; + .port_info 11 /INPUT 1 "s_write"; + .port_info 12 /INPUT 32 "s_writedata"; + .port_info 13 /OUTPUT 32 "s_readdata"; + .port_info 14 /OUTPUT 1 "s_readdatavalid"; + .port_info 15 /OUTPUT 24 "hdmi_d"; + .port_info 16 /OUTPUT 1 "hdmi_de"; + .port_info 17 /OUTPUT 1 "hdmi_hs"; + .port_info 18 /OUTPUT 1 "hdmi_vs"; + .port_info 19 /OUTPUT 8 "debug_leds"; +L_0x6467f9d6e0f0 .functor XOR 1, L_0x6467f9d9e910, L_0x6467f9d9ea10, C4<0>, C4<0>; +L_0x6467f9d6ed40 .functor XOR 1, L_0x6467f9d9ec20, L_0x6467f9d9ecc0, C4<0>, C4<0>; +L_0x6467f9d6fac0 .functor XOR 1, L_0x6467f9d9efc0, L_0x6467f9d9f0a0, C4<0>, C4<0>; +L_0x6467f9db2cc0 .functor BUFZ 1, L_0x6467f9d703e0, C4<0>, C4<0>, C4<0>; +L_0x6467f9db7ea0 .functor BUFZ 1, L_0x6467f9db66e0, C4<0>, C4<0>, C4<0>; +L_0x6467f9db8040 .functor BUFZ 1, L_0x6467f9dafd90, C4<0>, C4<0>, C4<0>; +L_0x6467f9db80f0 .functor BUFZ 1, L_0x6467f9d6ed40, C4<0>, C4<0>, C4<0>; +L_0x6467f9db8520 .functor BUFZ 1, L_0x6467f9d6e0f0, C4<0>, C4<0>, C4<0>; +v0x6467f9d9b610_0 .net *"_ivl_1", 0 0, L_0x6467f9d9e910; 1 drivers +v0x6467f9d9b710_0 .net *"_ivl_15", 0 0, L_0x6467f9d9efc0; 1 drivers +v0x6467f9d9b7f0_0 .net *"_ivl_17", 0 0, L_0x6467f9d9f0a0; 1 drivers +v0x6467f9d9b8e0_0 .net *"_ivl_25", 0 0, L_0x6467f9db2cc0; 1 drivers +v0x6467f9d9b9c0_0 .net *"_ivl_29", 0 0, L_0x6467f9db7ea0; 1 drivers +v0x6467f9d9baa0_0 .net *"_ivl_3", 0 0, L_0x6467f9d9ea10; 1 drivers +v0x6467f9d9bb80_0 .net *"_ivl_33", 0 0, L_0x6467f9db7f10; 1 drivers +v0x6467f9d9bc60_0 .net *"_ivl_37", 0 0, L_0x6467f9db8040; 1 drivers +v0x6467f9d9bd40_0 .net *"_ivl_41", 0 0, L_0x6467f9db80f0; 1 drivers +v0x6467f9d9be20_0 .net *"_ivl_45", 0 0, v0x6467f9d9cf20_0; 1 drivers +v0x6467f9d9bf00_0 .net *"_ivl_49", 0 0, v0x6467f9d9cab0_0; 1 drivers +v0x6467f9d9bfe0_0 .net *"_ivl_54", 0 0, L_0x6467f9db8520; 1 drivers +v0x6467f9d9c0c0_0 .net *"_ivl_7", 0 0, L_0x6467f9d9ec20; 1 drivers +v0x6467f9d9c1a0_0 .net *"_ivl_9", 0 0, L_0x6467f9d9ecc0; 1 drivers +o0x714ef55cf048 .functor BUFZ 1, C4; HiZ drive +v0x6467f9d9c280_0 .net "clk_50", 0 0, o0x714ef55cf048; 0 drivers +o0x714ef55d0c98 .functor BUFZ 1, C4; HiZ drive +v0x6467f9d9c320_0 .net "clk_hdmi", 0 0, o0x714ef55d0c98; 0 drivers +v0x6467f9d9c410_0 .net "debug_leds", 7 0, L_0x6467f9db8290; 1 drivers +v0x6467f9d9c600_0 .net "dma_busy", 0 0, L_0x6467f9d3fc40; 1 drivers +v0x6467f9d9c6f0_0 .net "dma_cont_74", 0 0, L_0x6467f9daffd0; 1 drivers +v0x6467f9d9c790_0 .net "dma_cont_sync", 0 0, L_0x6467f9d9eed0; 1 drivers +v0x6467f9d9c830_0 .var "dma_cont_sync_50", 2 0; +v0x6467f9d9c8d0_0 .net "dma_done_50", 0 0, v0x6467f9d3f200_0; 1 drivers +v0x6467f9d9c970_0 .net "dma_done_sync", 0 0, L_0x6467f9d6fac0; 1 drivers +v0x6467f9d9ca10_0 .var "dma_done_sync_74", 2 0; +v0x6467f9d9cab0_0 .var "dma_done_toggle_50", 0 0; +v0x6467f9d9cb70_0 .net "dma_en", 0 0, L_0x6467f9dafee0; 1 drivers +v0x6467f9d9cc40_0 .net "dma_start_74", 0 0, L_0x6467f9db0110; 1 drivers +v0x6467f9d9cd10_0 .var "dma_start_74_d", 0 0; +v0x6467f9d9cdb0_0 .net "dma_start_sync", 0 0, L_0x6467f9d6ed40; 1 drivers +v0x6467f9d9ce80_0 .var "dma_start_sync_50", 2 0; +v0x6467f9d9cf20_0 .var "dma_start_toggle_74", 0 0; +v0x6467f9d9cfe0_0 .net "fifo_empty", 0 0, L_0x6467f9dafd90; 1 drivers +v0x6467f9d9d0b0_0 .net "fifo_full", 0 0, L_0x6467f9d9f730; 1 drivers +v0x6467f9d9d180_0 .net "fifo_rd_data", 31 0, v0x6467f9d9a640_0; 1 drivers +v0x6467f9d9d250_0 .net "fifo_rd_en", 0 0, L_0x6467f9db66e0; 1 drivers +v0x6467f9d9d340_0 .net "fifo_used", 8 0, L_0x6467f9dafc00; 1 drivers +v0x6467f9d9d430_0 .net "fifo_wr_data", 31 0, L_0x6467f9d3efd0; 1 drivers +v0x6467f9d9d520_0 .net "fifo_wr_en", 0 0, L_0x6467f9d703e0; 1 drivers +v0x6467f9d9d610_0 .net "hdmi_d", 23 0, v0x6467f9d978c0_0; 1 drivers +v0x6467f9d9d6d0_0 .net "hdmi_de", 0 0, v0x6467f9d979a0_0; 1 drivers +v0x6467f9d9d770_0 .net "hdmi_hs", 0 0, v0x6467f9d97a60_0; 1 drivers +v0x6467f9d9d810_0 .net "hdmi_vs", 0 0, v0x6467f9d97b20_0; 1 drivers +v0x6467f9d9d8b0_0 .net "m_address", 31 0, v0x6467f9d8e270_0; 1 drivers +L_0x714ef5586018 .functor BUFT 1, C4<01000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d9d980_0 .net "m_burstcount", 7 0, L_0x714ef5586018; 1 drivers +v0x6467f9d9da50_0 .net "m_read", 0 0, v0x6467f9d8e430_0; 1 drivers +o0x714ef55cf2b8 .functor BUFZ 32, C4; HiZ drive +v0x6467f9d9db20_0 .net "m_readdata", 31 0, o0x714ef55cf2b8; 0 drivers +o0x714ef55cf2e8 .functor BUFZ 1, C4; HiZ drive +v0x6467f9d9dbf0_0 .net "m_readdatavalid", 0 0, o0x714ef55cf2e8; 0 drivers +o0x714ef55cf318 .functor BUFZ 1, C4; HiZ drive +v0x6467f9d9dcc0_0 .net "m_waitrequest", 0 0, o0x714ef55cf318; 0 drivers +v0x6467f9d9dd90_0 .net "reg_mode", 31 0, L_0x6467f9d9f910; 1 drivers +o0x714ef55cf378 .functor BUFZ 1, C4; HiZ drive +v0x6467f9d9de60_0 .net "reset_n", 0 0, o0x714ef55cf378; 0 drivers +o0x714ef55d0a88 .functor BUFZ 3, C4; HiZ drive +v0x6467f9d9df50_0 .net "s_address", 2 0, o0x714ef55d0a88; 0 drivers +o0x714ef55d0ab8 .functor BUFZ 1, C4; HiZ drive +v0x6467f9d9dff0_0 .net "s_read", 0 0, o0x714ef55d0ab8; 0 drivers +v0x6467f9d9e0c0_0 .net "s_readdata", 31 0, L_0x6467f9db0240; 1 drivers +v0x6467f9d9e190_0 .net "s_readdatavalid", 0 0, v0x6467f9d95a10_0; 1 drivers +o0x714ef55d0b48 .functor BUFZ 1, C4; HiZ drive +v0x6467f9d9e260_0 .net "s_write", 0 0, o0x714ef55d0b48; 0 drivers +o0x714ef55d0b78 .functor BUFZ 32, C4; HiZ drive +v0x6467f9d9e330_0 .net "s_writedata", 31 0, o0x714ef55d0b78; 0 drivers +v0x6467f9d9e400_0 .net "shadow_ptr", 31 0, L_0x6467f9db01d0; 1 drivers +v0x6467f9d9e4f0_0 .net "vs_toggle_raw", 0 0, v0x6467f9d98d40_0; 1 drivers +v0x6467f9d9e590_0 .net "vsync_edge_sync", 0 0, L_0x6467f9d6e0f0; 1 drivers +v0x6467f9d9e660_0 .var "vsync_toggle_sync_50", 2 0; +L_0x6467f9d9e910 .part v0x6467f9d9e660_0, 2, 1; +L_0x6467f9d9ea10 .part v0x6467f9d9e660_0, 1, 1; +L_0x6467f9d9ec20 .part v0x6467f9d9ce80_0, 2, 1; +L_0x6467f9d9ecc0 .part v0x6467f9d9ce80_0, 1, 1; +L_0x6467f9d9eed0 .part v0x6467f9d9c830_0, 1, 1; +L_0x6467f9d9efc0 .part v0x6467f9d9ca10_0, 2, 1; +L_0x6467f9d9f0a0 .part v0x6467f9d9ca10_0, 1, 1; +L_0x6467f9db7d60 .part v0x6467f9d9a640_0, 0, 24; +L_0x6467f9db7f10 .part L_0x6467f9dafc00, 8, 1; +LS_0x6467f9db8290_0_0 .concat8 [ 1 1 1 1], L_0x6467f9db2cc0, L_0x6467f9db7ea0, L_0x6467f9db7f10, L_0x6467f9db8040; +LS_0x6467f9db8290_0_4 .concat8 [ 1 1 1 1], L_0x6467f9db80f0, v0x6467f9d9cf20_0, v0x6467f9d9cab0_0, L_0x6467f9db8520; +L_0x6467f9db8290 .concat8 [ 4 4 0 0], LS_0x6467f9db8290_0_0, LS_0x6467f9db8290_0_4; +S_0x6467f9d621d0 .scope module, "u_dma_master" "video_dma_master" 3 112, 4 3 0, S_0x6467f9d49890; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /INPUT 32 "start_addr"; + .port_info 3 /INPUT 1 "dma_start"; + .port_info 4 /INPUT 1 "dma_cont_en"; + .port_info 5 /OUTPUT 1 "dma_done"; + .port_info 6 /OUTPUT 1 "busy"; + .port_info 7 /INPUT 1 "vsync_edge"; + .port_info 8 /INPUT 1 "m_waitrequest"; + .port_info 9 /INPUT 32 "m_readdata"; + .port_info 10 /INPUT 1 "m_readdatavalid"; + .port_info 11 /OUTPUT 32 "m_address"; + .port_info 12 /OUTPUT 1 "m_read"; + .port_info 13 /OUTPUT 8 "m_burstcount"; + .port_info 14 /INPUT 9 "fifo_used"; + .port_info 15 /OUTPUT 1 "fifo_wr_en"; + .port_info 16 /OUTPUT 32 "fifo_wr_data"; +P_0x6467f9c9fd60 .param/l "BURST_LEN" 0 4 30, C4<01000000>; +P_0x6467f9c9fda0 .param/l "CHECK_FIFO" 1 4 38, C4<01>; +P_0x6467f9c9fde0 .param/l "FIFO_DEPTH" 0 4 31, +C4<00000000000000000000001000000000>; +P_0x6467f9c9fe20 .param/l "FRAME_SIZE_WORDS" 0 4 34, +C4<0000000000000000000000000000000000000000000011100001000000000000>; +P_0x6467f9c9fe60 .param/l "H_RES" 0 4 32, +C4<00000000000000000000010100000000>; +P_0x6467f9c9fea0 .param/l "IDLE" 1 4 37, C4<00>; +P_0x6467f9c9fee0 .param/l "ISSUE_READ" 1 4 39, C4<10>; +P_0x6467f9c9ff20 .param/l "V_RES" 0 4 33, +C4<00000000000000000000001011010000>; +P_0x6467f9c9ff60 .param/l "WAIT_END" 1 4 40, C4<11>; +L_0x6467f9d703e0 .functor BUFZ 1, o0x714ef55cf2e8, C4<0>, C4<0>, C4<0>; +L_0x6467f9d3efd0 .functor BUFZ 32, o0x714ef55cf2b8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6467f9d3fc40 .functor BUFZ 1, v0x6467f9d8e0f0_0, C4<0>, C4<0>, C4<0>; +v0x6467f9d6fc80_0 .net "busy", 0 0, L_0x6467f9d3fc40; alias, 1 drivers +v0x6467f9d70540_0 .net "clk", 0 0, o0x714ef55cf048; alias, 0 drivers +v0x6467f9d70610_0 .var "current_read_addr", 31 0; +v0x6467f9d3f130_0 .net "dma_cont_en", 0 0, L_0x6467f9d9eed0; alias, 1 drivers +v0x6467f9d3f200_0 .var "dma_done", 0 0; +v0x6467f9d3fde0_0 .net "dma_start", 0 0, L_0x6467f9d6ed40; alias, 1 drivers +v0x6467f9d3feb0_0 .net "fifo_used", 8 0, L_0x6467f9dafc00; alias, 1 drivers +v0x6467f9d8df50_0 .net "fifo_wr_data", 31 0, L_0x6467f9d3efd0; alias, 1 drivers +v0x6467f9d8e030_0 .net "fifo_wr_en", 0 0, L_0x6467f9d703e0; alias, 1 drivers +v0x6467f9d8e0f0_0 .var "frame_active", 0 0; +v0x6467f9d8e1b0_0 .var "is_cont_mode", 0 0; +v0x6467f9d8e270_0 .var "m_address", 31 0; +v0x6467f9d8e350_0 .net "m_burstcount", 7 0, L_0x714ef5586018; alias, 1 drivers +v0x6467f9d8e430_0 .var "m_read", 0 0; +v0x6467f9d8e4f0_0 .net "m_readdata", 31 0, o0x714ef55cf2b8; alias, 0 drivers +v0x6467f9d8e5d0_0 .net "m_readdatavalid", 0 0, o0x714ef55cf2e8; alias, 0 drivers +v0x6467f9d8e690_0 .net "m_waitrequest", 0 0, o0x714ef55cf318; alias, 0 drivers +v0x6467f9d8e860_0 .var "pending_bursts", 9 0; +v0x6467f9d8e940_0 .net "reset_n", 0 0, o0x714ef55cf378; alias, 0 drivers +v0x6467f9d8ea00_0 .net "start_addr", 31 0, L_0x6467f9db01d0; alias, 1 drivers +v0x6467f9d8eae0_0 .var "state", 1 0; +v0x6467f9d8ebc0_0 .net "vsync_edge", 0 0, L_0x6467f9d6e0f0; alias, 1 drivers +v0x6467f9d8ec80_0 .var "words_commanded", 31 0; +v0x6467f9d8ed60_0 .var "words_received", 31 0; +E_0x6467f9cfd880/0 .event negedge, v0x6467f9d8e940_0; +E_0x6467f9cfd880/1 .event posedge, v0x6467f9d70540_0; +E_0x6467f9cfd880 .event/or E_0x6467f9cfd880/0, E_0x6467f9cfd880/1; +S_0x6467f9ccbe50 .scope module, "u_hdmi_sync" "hdmi_sync_gen" 3 150, 5 6 0, S_0x6467f9d49890; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /OUTPUT 24 "hdmi_d"; + .port_info 3 /OUTPUT 1 "hdmi_de"; + .port_info 4 /OUTPUT 1 "hdmi_hs"; + .port_info 5 /OUTPUT 1 "hdmi_vs"; + .port_info 6 /INPUT 3 "avs_address"; + .port_info 7 /INPUT 1 "avs_read"; + .port_info 8 /INPUT 1 "avs_write"; + .port_info 9 /INPUT 32 "avs_writedata"; + .port_info 10 /OUTPUT 32 "avs_readdata"; + .port_info 11 /OUTPUT 1 "avs_readdatavalid"; + .port_info 12 /OUTPUT 32 "reg_mode_out"; + .port_info 13 /OUTPUT 1 "dma_enable_out"; + .port_info 14 /OUTPUT 32 "shadow_ptr_out"; + .port_info 15 /INPUT 24 "stream_data_in"; + .port_info 16 /OUTPUT 1 "stream_rd_en"; + .port_info 17 /INPUT 1 "dma_busy"; + .port_info 18 /INPUT 1 "dma_done_in"; + .port_info 19 /OUTPUT 1 "dma_start_out"; + .port_info 20 /OUTPUT 1 "dma_cont_en_out"; + .port_info 21 /OUTPUT 1 "vs_toggle"; +P_0x6467f9d8f080 .param/l "H_BACK" 0 5 148, +C4<00000000000000000000000000001000>; +P_0x6467f9d8f0c0 .param/l "H_FRONT" 0 5 146, +C4<00000000000000000000000000001000>; +P_0x6467f9d8f100 .param/l "H_SYNC" 0 5 147, +C4<00000000000000000000000000001000>; +P_0x6467f9d8f140 .param/l "H_TOTAL" 0 5 149, +C4<00000000000000000000000000111000>; +P_0x6467f9d8f180 .param/l "H_VISIBLE" 0 5 145, +C4<00000000000000000000000000100000>; +P_0x6467f9d8f1c0 .param/l "V_BACK" 0 5 154, +C4<00000000000000000000000000000010>; +P_0x6467f9d8f200 .param/l "V_FRONT" 0 5 152, +C4<00000000000000000000000000000010>; +P_0x6467f9d8f240 .param/l "V_SYNC" 0 5 153, +C4<00000000000000000000000000000010>; +P_0x6467f9d8f280 .param/l "V_TOTAL" 0 5 155, +C4<00000000000000000000000000010110>; +P_0x6467f9d8f2c0 .param/l "V_VISIBLE" 0 5 151, +C4<00000000000000000000000000010000>; +L_0x6467f9d9f910 .functor BUFZ 32, v0x6467f9d98460_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6467f9db0110 .functor BUFZ 1, v0x6467f9d96750_0, C4<0>, C4<0>, C4<0>; +L_0x6467f9db01d0 .functor BUFZ 32, v0x6467f9d986f0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6467f9db0240 .functor BUFZ 32, v0x6467f9d97e40_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x6467f9db0850 .functor AND 1, L_0x6467f9db0420, L_0x6467f9db06d0, C4<1>, C4<1>; +L_0x6467f9db0e70 .functor AND 1, L_0x6467f9db0aa0, L_0x6467f9db0d20, C4<1>, C4<1>; +L_0x6467f9db11f0 .functor AND 1, L_0x6467f9db10b0, L_0x6467f9db1350, C4<1>, C4<1>; +L_0x6467f9db1650 .functor AND 1, L_0x6467f9db11f0, L_0x6467f9db15b0, C4<1>, C4<1>; +L_0x6467f9db1bb0 .functor BUFZ 8, L_0x6467f9db17b0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x6467f9db1fa0 .functor BUFZ 8, L_0x6467f9db1c70, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x6467f9db24d0 .functor BUFZ 8, L_0x6467f9db20c0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x6467f9db2bb0 .functor OR 1, L_0x6467f9db27e0, L_0x6467f9db2a90, C4<0>, C4<0>; +L_0x6467f9db6270 .functor BUFZ 16, L_0x6467f9db5e80, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x6467f9db66e0 .functor AND 1, L_0x6467f9db0850, L_0x6467f9db7b00, C4<1>, C4<1>; +v0x6467f9d8fa80_0 .net *"_ivl_103", 5 0, L_0x6467f9db2630; 1 drivers +L_0x714ef55864e0 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d8fb80_0 .net/2u *"_ivl_104", 5 0, L_0x714ef55864e0; 1 drivers +v0x6467f9d8fc60_0 .net *"_ivl_106", 0 0, L_0x6467f9db27e0; 1 drivers +v0x6467f9d8fd30_0 .net *"_ivl_109", 5 0, L_0x6467f9db2900; 1 drivers +L_0x714ef5586528 .functor BUFT 1, C4<000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d8fe10_0 .net/2u *"_ivl_110", 5 0, L_0x714ef5586528; 1 drivers +v0x6467f9d8ff40_0 .net *"_ivl_112", 0 0, L_0x6467f9db2a90; 1 drivers +v0x6467f9d90000_0 .net *"_ivl_116", 31 0, L_0x6467f9db2d30; 1 drivers +L_0x714ef5586570 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d900e0_0 .net *"_ivl_119", 19 0, L_0x714ef5586570; 1 drivers +v0x6467f9d901c0_0 .net *"_ivl_12", 31 0, L_0x6467f9db0300; 1 drivers +L_0x714ef55865b8 .functor BUFT 1, C4<00000000000000000000000010100000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d902a0_0 .net/2u *"_ivl_120", 31 0, L_0x714ef55865b8; 1 drivers +v0x6467f9d90380_0 .net *"_ivl_122", 0 0, L_0x6467f9db2f20; 1 drivers +L_0x714ef5586600 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; 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2 0, L_0x714ef5586888; 1 drivers +v0x6467f9d913d0_0 .net *"_ivl_156", 31 0, L_0x6467f9db3b60; 1 drivers +L_0x714ef55868d0 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d914b0_0 .net *"_ivl_159", 19 0, L_0x714ef55868d0; 1 drivers +L_0x714ef55860f0 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d91590_0 .net/2u *"_ivl_16", 31 0, L_0x714ef55860f0; 1 drivers +L_0x714ef5586918 .functor BUFT 1, C4<00000000000000000000001100100000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d91670_0 .net/2u *"_ivl_160", 31 0, L_0x714ef5586918; 1 drivers +v0x6467f9d91750_0 .net *"_ivl_162", 0 0, L_0x6467f9db3fd0; 1 drivers +L_0x714ef5586960 .functor BUFT 1, C4<100>, C4<0>, C4<0>, C4<0>; +v0x6467f9d91a20_0 .net/2u *"_ivl_164", 2 0, L_0x714ef5586960; 1 drivers +v0x6467f9d91b00_0 .net *"_ivl_166", 31 0, L_0x6467f9db4140; 1 drivers +L_0x714ef55869a8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d91be0_0 .net *"_ivl_169", 19 0, L_0x714ef55869a8; 1 drivers +L_0x714ef55869f0 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d91cc0_0 .net/2u *"_ivl_170", 31 0, L_0x714ef55869f0; 1 drivers +v0x6467f9d91da0_0 .net *"_ivl_172", 0 0, L_0x6467f9db43b0; 1 drivers +L_0x714ef5586a38 .functor BUFT 1, C4<101>, C4<0>, C4<0>, C4<0>; +v0x6467f9d91e60_0 .net/2u *"_ivl_174", 2 0, L_0x714ef5586a38; 1 drivers +v0x6467f9d91f40_0 .net *"_ivl_176", 31 0, L_0x6467f9db4520; 1 drivers +L_0x714ef5586a80 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d92020_0 .net *"_ivl_179", 19 0, L_0x714ef5586a80; 1 drivers +v0x6467f9d92100_0 .net *"_ivl_18", 0 0, L_0x6467f9db0420; 1 drivers +L_0x714ef5586ac8 .functor BUFT 1, C4<00000000000000000000010001100000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d921c0_0 .net/2u *"_ivl_180", 31 0, L_0x714ef5586ac8; 1 drivers +v0x6467f9d922a0_0 .net *"_ivl_182", 0 0, L_0x6467f9db47a0; 1 drivers +L_0x714ef5586b10 .functor BUFT 1, C4<110>, C4<0>, C4<0>, C4<0>; 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C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d939d0_0 .net/2u *"_ivl_24", 31 0, L_0x714ef5586180; 1 drivers +L_0x714ef5586cc0 .functor BUFT 1, C4<000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d93ab0_0 .net/2u *"_ivl_240", 23 0, L_0x714ef5586cc0; 1 drivers +v0x6467f9d93b90_0 .net *"_ivl_245", 3 0, L_0x6467f9db77f0; 1 drivers +L_0x714ef5586d08 .functor BUFT 1, C4<1000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d93c70_0 .net/2u *"_ivl_246", 3 0, L_0x714ef5586d08; 1 drivers +v0x6467f9d93d50_0 .net *"_ivl_248", 0 0, L_0x6467f9db7b00; 1 drivers +v0x6467f9d93e10_0 .net *"_ivl_26", 0 0, L_0x6467f9db06d0; 1 drivers +v0x6467f9d93ed0_0 .net *"_ivl_30", 31 0, L_0x6467f9db0960; 1 drivers +L_0x714ef55861c8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d93fb0_0 .net *"_ivl_33", 19 0, L_0x714ef55861c8; 1 drivers +L_0x714ef5586210 .functor BUFT 1, C4<00000000000000000000000000101000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d94090_0 .net/2u *"_ivl_34", 31 0, L_0x714ef5586210; 1 drivers +v0x6467f9d94170_0 .net *"_ivl_36", 0 0, L_0x6467f9db0aa0; 1 drivers +v0x6467f9d94230_0 .net *"_ivl_38", 31 0, L_0x6467f9db0c30; 1 drivers +L_0x714ef5586258 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d94310_0 .net *"_ivl_41", 19 0, L_0x714ef5586258; 1 drivers +L_0x714ef55862a0 .functor BUFT 1, C4<00000000000000000000000000110000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d943f0_0 .net/2u *"_ivl_42", 31 0, L_0x714ef55862a0; 1 drivers +v0x6467f9d944d0_0 .net *"_ivl_44", 0 0, L_0x6467f9db0d20; 1 drivers +v0x6467f9d94590_0 .net *"_ivl_48", 31 0, L_0x6467f9db0f70; 1 drivers +L_0x714ef55862e8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x6467f9d94670_0 .net *"_ivl_51", 19 0, L_0x714ef55862e8; 1 drivers +L_0x714ef5586330 .functor BUFT 1, C4<00000000000000000000000000010010>, C4<0>, C4<0>, C4<0>; +v0x6467f9d94750_0 .net/2u *"_ivl_52", 31 0, L_0x714ef5586330; 1 drivers +v0x6467f9d94830_0 .net *"_ivl_54", 0 0, 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L_0x6467f9db0110; alias, 1 drivers +v0x6467f9d96750_0 .var "dma_start_pulse", 0 0; +v0x6467f9d96810_0 .net "fancy_b", 7 0, L_0x6467f9db7220; 1 drivers +v0x6467f9d968f0_0 .net "fancy_g", 7 0, L_0x6467f9db6f80; 1 drivers +v0x6467f9d969d0_0 .net "fancy_r", 7 0, L_0x6467f9db6e40; 1 drivers +v0x6467f9d96ab0_0 .net "gamma_b", 7 0, L_0x6467f9db24d0; 1 drivers +v0x6467f9d96b90_0 .net "gamma_g", 7 0, L_0x6467f9db1fa0; 1 drivers +v0x6467f9d96c70_0 .net "gamma_r", 7 0, L_0x6467f9db1bb0; 1 drivers +v0x6467f9d96d50_0 .net "gray", 7 0, L_0x6467f9db2590; 1 drivers +v0x6467f9d96e30_0 .net "gray8_val", 7 0, L_0x6467f9db5a50; 1 drivers +v0x6467f9d97720_0 .net "grid_line", 0 0, L_0x6467f9db2bb0; 1 drivers +v0x6467f9d977e0_0 .var "h_cnt", 11 0; +v0x6467f9d978c0_0 .var "hdmi_d", 23 0; +v0x6467f9d979a0_0 .var "hdmi_de", 0 0; +v0x6467f9d97a60_0 .var "hdmi_hs", 0 0; +v0x6467f9d97b20_0 .var "hdmi_vs", 0 0; +v0x6467f9d97be0_0 .net "hs_wire", 0 0, L_0x6467f9db0e70; 1 drivers +v0x6467f9d97ca0 .array "lut_mem", 255 0, 7 0; +v0x6467f9d97d60_0 .var "pre_gamma_d", 23 0; +v0x6467f9d97e40_0 .var "read_data_mux", 31 0; +v0x6467f9d97f20_0 .var "reg_bitmap_addr", 31 0; +v0x6467f9d98000_0 .var "reg_bitmap_data", 31 0; +v0x6467f9d980e0_0 .var "reg_frame_ptr", 31 0; +v0x6467f9d981c0_0 .var "reg_global_ctrl", 31 0; +v0x6467f9d982a0_0 .var "reg_lut_addr", 31 0; +v0x6467f9d98380_0 .var "reg_lut_data", 31 0; +v0x6467f9d98460_0 .var "reg_mode", 31 0; +v0x6467f9d98540_0 .net "reg_mode_out", 31 0, L_0x6467f9d9f910; alias, 1 drivers +v0x6467f9d98620_0 .net "reset_n", 0 0, o0x714ef55cf378; alias, 0 drivers +v0x6467f9d986f0_0 .var "shadow_ptr", 31 0; +v0x6467f9d987b0_0 .net "shadow_ptr_out", 31 0, L_0x6467f9db01d0; alias, 1 drivers +v0x6467f9d988a0_0 .net "stream_data_in", 23 0, L_0x6467f9db7d60; 1 drivers +v0x6467f9d98960_0 .net "stream_rd_en", 0 0, L_0x6467f9db66e0; alias, 1 drivers +v0x6467f9d98a20_0 .var "v_cnt", 11 0; +v0x6467f9d98b00_0 .net "visible", 0 0, L_0x6467f9db0850; 1 drivers +v0x6467f9d98bc0_0 .net "vs_edge", 0 0, L_0x6467f9db1650; 1 drivers +v0x6467f9d98c80_0 .var "vs_prev", 0 0; +v0x6467f9d98d40_0 .var "vs_toggle", 0 0; +v0x6467f9d98e00_0 .net "vs_wire", 0 0, L_0x6467f9db11f0; 1 drivers +E_0x6467f9d104f0/0 .event negedge, v0x6467f9d8e940_0; +E_0x6467f9d104f0/1 .event posedge, v0x6467f9d96170_0; +E_0x6467f9d104f0 .event/or E_0x6467f9d104f0/0, E_0x6467f9d104f0/1; +E_0x6467f9cc4390/0 .event edge, v0x6467f9d98460_0, v0x6467f9d96d50_0, v0x6467f9d97720_0, v0x6467f9d96e30_0; +E_0x6467f9cc4390/1 .event edge, v0x6467f9d95ef0_0; +E_0x6467f9cc4390 .event/or E_0x6467f9cc4390/0, E_0x6467f9cc4390/1; +E_0x6467f9d77fe0/0 .event edge, v0x6467f9d95790_0, v0x6467f9d98460_0, v0x6467f9d6fc80_0, v0x6467f9d96510_0; +E_0x6467f9d77fe0/1 .event edge, v0x6467f9d981c0_0, v0x6467f9d982a0_0, v0x6467f9d98380_0, v0x6467f9d97f20_0; +E_0x6467f9d77fe0/2 .event edge, v0x6467f9d98000_0, v0x6467f9d980e0_0; +E_0x6467f9d77fe0 .event/or E_0x6467f9d77fe0/0, E_0x6467f9d77fe0/1, E_0x6467f9d77fe0/2; +L_0x6467f9dafee0 .part v0x6467f9d981c0_0, 1, 1; +L_0x6467f9daffd0 .part v0x6467f9d981c0_0, 1, 1; +L_0x6467f9db0300 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef55860a8; +L_0x6467f9db0420 .cmp/gt 32, L_0x714ef55860f0, L_0x6467f9db0300; +L_0x6467f9db0590 .concat [ 12 20 0 0], v0x6467f9d98a20_0, L_0x714ef5586138; +L_0x6467f9db06d0 .cmp/gt 32, L_0x714ef5586180, L_0x6467f9db0590; +L_0x6467f9db0960 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef55861c8; +L_0x6467f9db0aa0 .cmp/ge 32, L_0x6467f9db0960, L_0x714ef5586210; +L_0x6467f9db0c30 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef5586258; +L_0x6467f9db0d20 .cmp/gt 32, L_0x714ef55862a0, L_0x6467f9db0c30; +L_0x6467f9db0f70 .concat [ 12 20 0 0], v0x6467f9d98a20_0, L_0x714ef55862e8; +L_0x6467f9db10b0 .cmp/ge 32, L_0x6467f9db0f70, L_0x714ef5586330; +L_0x6467f9db1260 .concat [ 12 20 0 0], v0x6467f9d98a20_0, L_0x714ef5586378; +L_0x6467f9db1350 .cmp/gt 32, L_0x714ef55863c0, L_0x6467f9db1260; +L_0x6467f9db15b0 .reduce/nor v0x6467f9d98c80_0; +L_0x6467f9db17b0 .array/port v0x6467f9d97ca0, L_0x6467f9db1980; +L_0x6467f9db18e0 .part v0x6467f9d97d60_0, 16, 8; +L_0x6467f9db1980 .concat [ 8 2 0 0], L_0x6467f9db18e0, L_0x714ef5586408; +L_0x6467f9db1c70 .array/port v0x6467f9d97ca0, L_0x6467f9db1ac0; +L_0x6467f9db1d10 .part v0x6467f9d97d60_0, 8, 8; +L_0x6467f9db1ac0 .concat [ 8 2 0 0], L_0x6467f9db1d10, L_0x714ef5586450; +L_0x6467f9db20c0 .array/port v0x6467f9d97ca0, L_0x6467f9db22c0; +L_0x6467f9db2220 .part v0x6467f9d97d60_0, 0, 8; +L_0x6467f9db22c0 .concat [ 8 2 0 0], L_0x6467f9db2220, L_0x714ef5586498; +L_0x6467f9db2590 .part v0x6467f9d977e0_0, 0, 8; +L_0x6467f9db2630 .part v0x6467f9d977e0_0, 0, 6; +L_0x6467f9db27e0 .cmp/eq 6, L_0x6467f9db2630, L_0x714ef55864e0; +L_0x6467f9db2900 .part v0x6467f9d98a20_0, 0, 6; +L_0x6467f9db2a90 .cmp/eq 6, L_0x6467f9db2900, L_0x714ef5586528; +L_0x6467f9db2d30 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef5586570; +L_0x6467f9db2f20 .cmp/gt 32, L_0x714ef55865b8, L_0x6467f9db2d30; +L_0x6467f9db3060 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef5586648; +L_0x6467f9db3290 .cmp/gt 32, L_0x714ef5586690, L_0x6467f9db3060; +L_0x6467f9db3400 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef5586720; +L_0x6467f9db3750 .cmp/gt 32, L_0x714ef5586768, L_0x6467f9db3400; +L_0x6467f9db38c0 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef55867f8; +L_0x6467f9db3630 .cmp/gt 32, L_0x714ef5586840, L_0x6467f9db38c0; +L_0x6467f9db3b60 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef55868d0; +L_0x6467f9db3fd0 .cmp/gt 32, L_0x714ef5586918, L_0x6467f9db3b60; +L_0x6467f9db4140 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef55869a8; +L_0x6467f9db43b0 .cmp/gt 32, L_0x714ef55869f0, L_0x6467f9db4140; +L_0x6467f9db4520 .concat [ 12 20 0 0], v0x6467f9d977e0_0, L_0x714ef5586a80; +L_0x6467f9db47a0 .cmp/gt 32, L_0x714ef5586ac8, L_0x6467f9db4520; +L_0x6467f9db4910 .functor MUXZ 3, L_0x714ef5586b58, L_0x714ef5586b10, L_0x6467f9db47a0, C4<>; +L_0x6467f9db4c40 .functor MUXZ 3, L_0x6467f9db4910, L_0x714ef5586a38, L_0x6467f9db43b0, C4<>; +L_0x6467f9db4dd0 .functor MUXZ 3, L_0x6467f9db4c40, L_0x714ef5586960, L_0x6467f9db3fd0, C4<>; +L_0x6467f9db50e0 .functor MUXZ 3, L_0x6467f9db4dd0, L_0x714ef5586888, L_0x6467f9db3630, C4<>; +L_0x6467f9db5270 .functor MUXZ 3, L_0x6467f9db50e0, L_0x714ef55867b0, L_0x6467f9db3750, C4<>; +L_0x6467f9db5590 .functor MUXZ 3, L_0x6467f9db5270, L_0x714ef55866d8, L_0x6467f9db3290, C4<>; +L_0x6467f9db5720 .functor MUXZ 3, L_0x6467f9db5590, L_0x714ef5586600, L_0x6467f9db2f20, C4<>; +L_0x6467f9db5a50 .concat [ 5 3 0 0], L_0x714ef5586ba0, L_0x6467f9db5720; +L_0x6467f9db5b90 .part v0x6467f9d98a20_0, 2, 4; +L_0x6467f9db5de0 .part v0x6467f9d977e0_0, 2, 4; +L_0x6467f9db5e80 .array/port v0x6467f9d95d50, L_0x6467f9db60e0; +L_0x6467f9db60e0 .concat [ 4 2 0 0], L_0x6467f9db5b90, L_0x714ef5586be8; +L_0x6467f9db6330 .concat [ 4 28 0 0], L_0x6467f9db5de0, L_0x714ef5586c78; +L_0x6467f9db6640 .arith/sub 32, L_0x714ef5586c30, L_0x6467f9db6330; +L_0x6467f9db67f0 .part/v L_0x6467f9db6270, L_0x6467f9db6640, 1; +L_0x6467f9db6b10 .part v0x6467f9d977e0_0, 0, 8; +L_0x6467f9db6bb0 .part v0x6467f9d98a20_0, 0, 8; +L_0x6467f9db6e40 .arith/sum 8, L_0x6467f9db6b10, L_0x6467f9db6bb0; +L_0x6467f9db6f80 .part v0x6467f9d977e0_0, 2, 8; +L_0x6467f9db7220 .part v0x6467f9d98a20_0, 2, 8; +L_0x6467f9db72c0 .concat [ 8 8 8 0], L_0x6467f9db7220, L_0x6467f9db6f80, L_0x6467f9db6e40; +L_0x6467f9db7660 .functor MUXZ 24, L_0x714ef5586cc0, L_0x6467f9db72c0, L_0x6467f9db67f0, C4<>; +L_0x6467f9db77f0 .part v0x6467f9d98460_0, 0, 4; +L_0x6467f9db7b00 .cmp/eq 4, L_0x6467f9db77f0, L_0x714ef5586d08; +S_0x6467f9d99180 .scope module, "u_simple_fifo" "simple_dcfifo" 3 136, 6 3 0, S_0x6467f9d49890; + .timescale -9 -12; + .port_info 0 /INPUT 1 "wrclk"; + .port_info 1 /INPUT 32 "data"; + .port_info 2 /INPUT 1 "wrreq"; + .port_info 3 /OUTPUT 9 "wrusedw"; + .port_info 4 /OUTPUT 1 "wrfull"; + .port_info 5 /INPUT 1 "rdclk"; + .port_info 6 /INPUT 1 "rdreq"; + .port_info 7 /OUTPUT 32 "q"; + .port_info 8 /OUTPUT 1 "rdempty"; +P_0x6467f9ce82b0 .param/l "ADDR_WIDTH" 0 6 5, +C4<00000000000000000000000000001001>; +P_0x6467f9ce82f0 .param/l "DATA_WIDTH" 0 6 4, +C4<00000000000000000000000000100000>; +L_0x6467f9c9fcf0 .functor NOT 2, L_0x6467f9d9f410, C4<00>, C4<00>, C4<00>; +v0x6467f9d99e40_0 .net *"_ivl_15", 0 0, L_0x6467f9d9fa10; 1 drivers +L_0x714ef5586060 .functor BUFT 1, C4<111111111>, C4<0>, C4<0>, C4<0>; +v0x6467f9d99f40_0 .net/2u *"_ivl_16", 8 0, L_0x714ef5586060; 1 drivers +v0x6467f9d9a020_0 .net *"_ivl_19", 8 0, L_0x6467f9dafb10; 1 drivers +v0x6467f9d9a110_0 .net *"_ivl_3", 1 0, L_0x6467f9d9f410; 1 drivers +v0x6467f9d9a1f0_0 .net *"_ivl_4", 1 0, L_0x6467f9c9fcf0; 1 drivers +v0x6467f9d9a320_0 .net *"_ivl_7", 7 0, L_0x6467f9d9f550; 1 drivers +v0x6467f9d9a400_0 .net *"_ivl_8", 9 0, L_0x6467f9d9f5f0; 1 drivers +v0x6467f9d9a4e0_0 .net "data", 31 0, L_0x6467f9d3efd0; alias, 1 drivers +v0x6467f9d9a5a0 .array "mem", 0 511, 31 0; +v0x6467f9d9a640_0 .var "q", 31 0; +v0x6467f9d9a720_0 .var "rd_ptr_bin", 9 0; +v0x6467f9d9a800_0 .net "rd_ptr_bin_sync", 9 0, L_0x6467f9d9f370; 1 drivers +v0x6467f9d9a8e0_0 .var "rd_ptr_gray", 9 0; +v0x6467f9d9a9c0_0 .var "rd_ptr_gray_sync1", 9 0; +v0x6467f9d9aaa0_0 .var "rd_ptr_gray_sync2", 9 0; +v0x6467f9d9ab80_0 .net "rdclk", 0 0, o0x714ef55d0c98; alias, 0 drivers +v0x6467f9d9ac50_0 .net "rdempty", 0 0, L_0x6467f9dafd90; alias, 1 drivers +v0x6467f9d9acf0_0 .net "rdreq", 0 0, L_0x6467f9db66e0; alias, 1 drivers +v0x6467f9d9adc0_0 .net "used_diff", 9 0, L_0x6467f9d9f870; 1 drivers +v0x6467f9d9ae80_0 .var "wr_ptr_bin", 9 0; +v0x6467f9d9af60_0 .var "wr_ptr_gray", 9 0; +v0x6467f9d9b040_0 .var "wr_ptr_gray_sync1", 9 0; +v0x6467f9d9b120_0 .var "wr_ptr_gray_sync2", 9 0; +v0x6467f9d9b200_0 .net "wrclk", 0 0, o0x714ef55cf048; alias, 0 drivers +v0x6467f9d9b2d0_0 .net "wrfull", 0 0, L_0x6467f9d9f730; alias, 1 drivers +v0x6467f9d9b370_0 .net "wrreq", 0 0, L_0x6467f9d703e0; alias, 1 drivers +v0x6467f9d9b440_0 .net "wrusedw", 8 0, L_0x6467f9dafc00; alias, 1 drivers +E_0x6467f9d783b0 .event posedge, v0x6467f9d96170_0; +E_0x6467f9d785e0 .event posedge, v0x6467f9d70540_0; +L_0x6467f9d9f370 .ufunc/vec4 TD_video_pipeline.u_simple_fifo.gray2bin, 10, v0x6467f9d9aaa0_0 (v0x6467f9d99b90_0) S_0x6467f9d99990; +L_0x6467f9d9f410 .part v0x6467f9d9aaa0_0, 8, 2; +L_0x6467f9d9f550 .part v0x6467f9d9aaa0_0, 0, 8; +L_0x6467f9d9f5f0 .concat [ 8 2 0 0], L_0x6467f9d9f550, L_0x6467f9c9fcf0; +L_0x6467f9d9f730 .cmp/eq 10, v0x6467f9d9af60_0, L_0x6467f9d9f5f0; +L_0x6467f9d9f870 .arith/sub 10, v0x6467f9d9ae80_0, L_0x6467f9d9f370; +L_0x6467f9d9fa10 .part L_0x6467f9d9f870, 9, 1; +L_0x6467f9dafb10 .part L_0x6467f9d9f870, 0, 9; +L_0x6467f9dafc00 .functor MUXZ 9, L_0x6467f9dafb10, L_0x714ef5586060, L_0x6467f9d9fa10, C4<>; +L_0x6467f9dafd90 .cmp/eq 10, v0x6467f9d9a8e0_0, v0x6467f9d9b120_0; +S_0x6467f9d995b0 .scope function.vec4.s10, "bin2gray" "bin2gray" 6 52, 6 52 0, S_0x6467f9d99180; + .timescale -9 -12; +v0x6467f9d997b0_0 .var "bin", 9 0; +; Variable bin2gray is vec4 return value of scope S_0x6467f9d995b0 +TD_video_pipeline.u_simple_fifo.bin2gray ; + %load/vec4 v0x6467f9d997b0_0; + %load/vec4 v0x6467f9d997b0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %xor; + %ret/vec4 0, 0, 10; Assign to bin2gray (store_vec4_to_lval) + %end; +S_0x6467f9d99990 .scope function.vec4.s10, "gray2bin" "gray2bin" 6 59, 6 59 0, S_0x6467f9d99180; + .timescale -9 -12; +v0x6467f9d99b90_0 .var "gray", 9 0; +; Variable gray2bin is vec4 return value of scope S_0x6467f9d99990 +v0x6467f9d99d50_0 .var/i "i", 31 0; +TD_video_pipeline.u_simple_fifo.gray2bin ; + %load/vec4 v0x6467f9d99b90_0; + %parti/s 1, 9, 5; + %ix/load 4, 9, 0; + %flag_set/imm 4, 0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %pushi/vec4 8, 0, 32; + %store/vec4 v0x6467f9d99d50_0, 0, 32; +T_1.0 ; + %load/vec4 v0x6467f9d99d50_0; + %cmpi/s 0, 0, 32; + %flag_inv 5; GE is !LT + %jmp/0xz T_1.1, 5; + %retload/vec4 0; Load gray2bin (draw_signal_vec4) + %load/vec4 v0x6467f9d99d50_0; + %addi 1, 0, 32; + %part/s 1; + %load/vec4 v0x6467f9d99b90_0; + %load/vec4 v0x6467f9d99d50_0; + %part/s 1; + %xor; + %ix/getv/s 4, v0x6467f9d99d50_0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %load/vec4 v0x6467f9d99d50_0; + %subi 1, 0, 32; + %store/vec4 v0x6467f9d99d50_0, 0, 32; + %jmp T_1.0; +T_1.1 ; + %end; + .scope S_0x6467f9d621d0; +T_2 ; + %wait E_0x6467f9cfd880; + %load/vec4 v0x6467f9d8e940_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x6467f9d8eae0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d8e270_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e430_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d70610_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d8ec80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e1b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e0f0_0, 0; + %pushi/vec4 0, 0, 10; + %assign/vec4 v0x6467f9d8e860_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x6467f9d8eae0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_2.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_2.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_2.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_2.5, 6; + %jmp T_2.6; +T_2.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e430_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d8ec80_0, 0; + %load/vec4 v0x6467f9d3fde0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.7, 8; + %load/vec4 v0x6467f9d8ea00_0; + %assign/vec4 v0x6467f9d70610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e1b0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6467f9d8e0f0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x6467f9d8eae0_0, 0; + %jmp T_2.8; +T_2.7 ; + %load/vec4 v0x6467f9d3f130_0; + %load/vec4 v0x6467f9d8ebc0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.9, 8; + %load/vec4 v0x6467f9d8ea00_0; + %assign/vec4 v0x6467f9d70610_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6467f9d8e1b0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6467f9d8e0f0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x6467f9d8eae0_0, 0; + %jmp T_2.10; +T_2.9 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e0f0_0, 0; +T_2.10 ; +T_2.8 ; + %jmp T_2.6; +T_2.3 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e430_0, 0; + %load/vec4 v0x6467f9d8ec80_0; + %pad/u 64; + %cmpi/u 921600, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_2.11, 5; + %pushi/vec4 3, 0, 2; + %assign/vec4 v0x6467f9d8eae0_0, 0; + %jmp T_2.12; +T_2.11 ; + %load/vec4 v0x6467f9d3feb0_0; + %pad/u 32; + %load/vec4 v0x6467f9d8ec80_0; + %load/vec4 v0x6467f9d8ed60_0; + %sub; + %add; + %cmpi/u 446, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_2.13, 5; + %load/vec4 v0x6467f9d70610_0; + %assign/vec4 v0x6467f9d8e270_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6467f9d8e430_0, 0; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x6467f9d8eae0_0, 0; +T_2.13 ; +T_2.12 ; + %jmp T_2.6; +T_2.4 ; + %load/vec4 v0x6467f9d8e690_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.15, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e430_0, 0; + %load/vec4 v0x6467f9d70610_0; + %addi 256, 0, 32; + %assign/vec4 v0x6467f9d70610_0, 0; + %load/vec4 v0x6467f9d8ec80_0; + %addi 64, 0, 32; + %assign/vec4 v0x6467f9d8ec80_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x6467f9d8eae0_0, 0; +T_2.15 ; + %jmp T_2.6; +T_2.5 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e430_0, 0; + %load/vec4 v0x6467f9d8ed60_0; + %pad/u 64; + %cmpi/u 921600, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_2.17, 5; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x6467f9d8eae0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e0f0_0, 0; +T_2.17 ; + %jmp T_2.6; +T_2.6 ; + %pop/vec4 1; + %load/vec4 v0x6467f9d8e1b0_0; + %load/vec4 v0x6467f9d3f130_0; + %nor/r; + %and; + %load/vec4 v0x6467f9d8eae0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.19, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d8e1b0_0, 0; +T_2.19 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x6467f9d621d0; +T_3 ; + %wait E_0x6467f9cfd880; + %load/vec4 v0x6467f9d8e940_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d8ed60_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0x6467f9d8eae0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x6467f9d3fde0_0; + %load/vec4 v0x6467f9d3f130_0; + %load/vec4 v0x6467f9d8ebc0_0; + %and; + %or; + %and; + %flag_set/vec4 8; + %jmp/0xz T_3.2, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d8ed60_0, 0; +T_3.2 ; + %load/vec4 v0x6467f9d8e5d0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.4, 8; + %load/vec4 v0x6467f9d8ed60_0; + %addi 1, 0, 32; + %assign/vec4 v0x6467f9d8ed60_0, 0; +T_3.4 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x6467f9d621d0; +T_4 ; + %wait E_0x6467f9cfd880; + %load/vec4 v0x6467f9d8e940_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d3f200_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x6467f9d8e5d0_0; + %load/vec4 v0x6467f9d8ed60_0; + %pad/u 64; + %pushi/vec4 921599, 0, 64; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6467f9d3f200_0, 0; + %jmp T_4.3; +T_4.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d3f200_0, 0; +T_4.3 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x6467f9d99180; +T_5 ; + %wait E_0x6467f9d785e0; + %load/vec4 v0x6467f9d9a8e0_0; + %assign/vec4 v0x6467f9d9a9c0_0, 0; + %load/vec4 v0x6467f9d9a9c0_0; + %assign/vec4 v0x6467f9d9aaa0_0, 0; + %jmp T_5; + .thread T_5; + .scope S_0x6467f9d99180; +T_6 ; + %wait E_0x6467f9d783b0; + %load/vec4 v0x6467f9d9af60_0; + %assign/vec4 v0x6467f9d9b040_0, 0; + %load/vec4 v0x6467f9d9b040_0; + %assign/vec4 v0x6467f9d9b120_0, 0; + %jmp T_6; + .thread T_6; + .scope S_0x6467f9d99180; +T_7 ; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9ae80_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9af60_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9a720_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9a8e0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9b040_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9b120_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9a9c0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x6467f9d9aaa0_0, 0, 10; + %end; + .thread T_7; + .scope S_0x6467f9d99180; +T_8 ; + %wait E_0x6467f9d785e0; + %load/vec4 v0x6467f9d9b370_0; + %load/vec4 v0x6467f9d9b2d0_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x6467f9d9a4e0_0; + %load/vec4 v0x6467f9d9ae80_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d9a5a0, 0, 4; + %load/vec4 v0x6467f9d9ae80_0; + %addi 1, 0, 10; + %assign/vec4 v0x6467f9d9ae80_0, 0; + %load/vec4 v0x6467f9d9ae80_0; + %addi 1, 0, 10; + %store/vec4 v0x6467f9d997b0_0, 0, 10; + %callf/vec4 TD_video_pipeline.u_simple_fifo.bin2gray, S_0x6467f9d995b0; + %assign/vec4 v0x6467f9d9af60_0, 0; +T_8.0 ; + %jmp T_8; + .thread T_8; + .scope S_0x6467f9d99180; +T_9 ; + %wait E_0x6467f9d783b0; + %load/vec4 v0x6467f9d9acf0_0; + %load/vec4 v0x6467f9d9ac50_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %load/vec4 v0x6467f9d9a720_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 4; + %load/vec4a v0x6467f9d9a5a0, 4; + %assign/vec4 v0x6467f9d9a640_0, 0; + %load/vec4 v0x6467f9d9a720_0; + %addi 1, 0, 10; + %assign/vec4 v0x6467f9d9a720_0, 0; + %load/vec4 v0x6467f9d9a720_0; + %addi 1, 0, 10; + %store/vec4 v0x6467f9d997b0_0, 0, 10; + %callf/vec4 TD_video_pipeline.u_simple_fifo.bin2gray, S_0x6467f9d995b0; + %assign/vec4 v0x6467f9d9a8e0_0, 0; +T_9.0 ; + %jmp T_9; + .thread T_9; + .scope S_0x6467f9ccbe50; +T_10 ; + %wait E_0x6467f9d77fe0; + %load/vec4 v0x6467f9d95790_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_10.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_10.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_10.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_10.6, 6; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.0 ; + %load/vec4 v0x6467f9d98460_0; + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.1 ; + %load/vec4 v0x6467f9d96310_0; + %load/vec4 v0x6467f9d96510_0; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 28; + %load/vec4 v0x6467f9d981c0_0; + %parti/s 1, 1, 2; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6467f9d981c0_0; + %parti/s 1, 0, 2; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.2 ; + %load/vec4 v0x6467f9d982a0_0; + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.3 ; + %load/vec4 v0x6467f9d98380_0; + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.4 ; + %load/vec4 v0x6467f9d97f20_0; + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.5 ; + %load/vec4 v0x6467f9d98000_0; + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.6 ; + %load/vec4 v0x6467f9d980e0_0; + %store/vec4 v0x6467f9d97e40_0, 0, 32; + %jmp T_10.8; +T_10.8 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10, $push; + .scope S_0x6467f9ccbe50; +T_11 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d98620_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d98460_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d981c0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d982a0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x6467f9d98380_0, 0; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x6467f9d980e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d95a10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d96750_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d96510_0, 0; + %pushi/vec4 0, 0, 16; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 4, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 5, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 6, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 7, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 8, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 9, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 10, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 11, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 12, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 13, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 14, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 15, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %jmp T_11.1; +T_11.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d96750_0, 0; + %load/vec4 v0x6467f9d96450_0; + %flag_set/vec4 8; + %jmp/0xz T_11.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6467f9d96510_0, 0; +T_11.2 ; + %load/vec4 v0x6467f9d95ad0_0; + %flag_set/vec4 8; + %jmp/0xz T_11.4, 8; + %load/vec4 v0x6467f9d95790_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.6, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.7, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_11.8, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_11.9, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_11.10, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_11.11, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_11.12, 6; + %jmp T_11.14; +T_11.6 ; + %load/vec4 v0x6467f9d95b90_0; + %assign/vec4 v0x6467f9d98460_0, 0; + %jmp T_11.14; +T_11.7 ; + %load/vec4 v0x6467f9d95b90_0; + %assign/vec4 v0x6467f9d981c0_0, 0; + %load/vec4 v0x6467f9d95b90_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_11.15, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x6467f9d96750_0, 0; +T_11.15 ; + %load/vec4 v0x6467f9d95b90_0; + %parti/s 1, 30, 6; + %flag_set/vec4 8; + %jmp/0xz T_11.17, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d96510_0, 0; +T_11.17 ; + %jmp T_11.14; +T_11.8 ; + %load/vec4 v0x6467f9d95b90_0; + %assign/vec4 v0x6467f9d982a0_0, 0; + %jmp T_11.14; +T_11.9 ; + %load/vec4 v0x6467f9d95b90_0; + %assign/vec4 v0x6467f9d98380_0, 0; + %load/vec4 v0x6467f9d95b90_0; + %parti/s 8, 0, 2; + %load/vec4 v0x6467f9d982a0_0; + %parti/s 8, 0, 2; + %pad/u 10; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d97ca0, 0, 4; + %jmp T_11.14; +T_11.10 ; + %load/vec4 v0x6467f9d95b90_0; + %assign/vec4 v0x6467f9d97f20_0, 0; + %jmp T_11.14; +T_11.11 ; + %load/vec4 v0x6467f9d95b90_0; + %assign/vec4 v0x6467f9d98000_0, 0; + %load/vec4 v0x6467f9d95b90_0; + %parti/s 16, 0, 2; + %load/vec4 v0x6467f9d97f20_0; + %parti/s 4, 0, 2; + %pad/u 6; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x6467f9d95d50, 0, 4; + %jmp T_11.14; +T_11.12 ; + %load/vec4 v0x6467f9d95b90_0; + %assign/vec4 v0x6467f9d980e0_0, 0; + %jmp T_11.14; +T_11.14 ; + %pop/vec4 1; +T_11.4 ; + %load/vec4 v0x6467f9d95870_0; + %assign/vec4 v0x6467f9d95a10_0, 0; +T_11.1 ; + %jmp T_11; + .thread T_11; + .scope S_0x6467f9ccbe50; +T_12 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d98620_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6467f9d977e0_0, 0; + %jmp T_12.1; +T_12.0 ; + %load/vec4 v0x6467f9d977e0_0; + %pad/u 32; + %cmpi/e 55, 0, 32; + %jmp/0xz T_12.2, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6467f9d977e0_0, 0; + %jmp T_12.3; +T_12.2 ; + %load/vec4 v0x6467f9d977e0_0; + %addi 1, 0, 12; + %assign/vec4 v0x6467f9d977e0_0, 0; +T_12.3 ; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x6467f9ccbe50; +T_13 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d98620_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_13.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6467f9d98a20_0, 0; + %jmp T_13.1; +T_13.0 ; + %load/vec4 v0x6467f9d977e0_0; + %pad/u 32; + %cmpi/e 55, 0, 32; + %jmp/0xz T_13.2, 4; + %load/vec4 v0x6467f9d98a20_0; + %pad/u 32; + %cmpi/e 21, 0, 32; + %jmp/0xz T_13.4, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x6467f9d98a20_0, 0; + %jmp T_13.5; +T_13.4 ; + %load/vec4 v0x6467f9d98a20_0; + %addi 1, 0, 12; + %assign/vec4 v0x6467f9d98a20_0, 0; +T_13.5 ; +T_13.2 ; +T_13.1 ; + %jmp T_13; + .thread T_13; + .scope S_0x6467f9ccbe50; +T_14 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d98620_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d97a60_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d97b20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d979a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d98c80_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v0x6467f9d97be0_0; + %assign/vec4 v0x6467f9d97a60_0, 0; + %load/vec4 v0x6467f9d98e00_0; + %assign/vec4 v0x6467f9d97b20_0, 0; + %load/vec4 v0x6467f9d98b00_0; + %assign/vec4 v0x6467f9d979a0_0, 0; + %load/vec4 v0x6467f9d98e00_0; + %assign/vec4 v0x6467f9d98c80_0, 0; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x6467f9ccbe50; +T_15 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d98620_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_15.0, 8; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x6467f9d986f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d98d40_0, 0; + %jmp T_15.1; +T_15.0 ; + %load/vec4 v0x6467f9d98bc0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.2, 8; + %load/vec4 v0x6467f9d980e0_0; + %assign/vec4 v0x6467f9d986f0_0, 0; + %load/vec4 v0x6467f9d98d40_0; + %inv; + %assign/vec4 v0x6467f9d98d40_0, 0; +T_15.2 ; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_0x6467f9ccbe50; +T_16 ; + %wait E_0x6467f9cc4390; + %load/vec4 v0x6467f9d98460_0; + %parti/s 4, 0, 2; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_16.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_16.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_16.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_16.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_16.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_16.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_16.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_16.7, 6; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.0 ; + %pushi/vec4 16711680, 0, 24; + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.1 ; + %pushi/vec4 65280, 0, 24; + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.2 ; + %pushi/vec4 255, 0, 24; + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.3 ; + %load/vec4 v0x6467f9d96d50_0; + %load/vec4 v0x6467f9d96d50_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6467f9d96d50_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.4 ; + %load/vec4 v0x6467f9d97720_0; + %flag_set/vec4 8; + %jmp/0 T_16.10, 8; + %pushi/vec4 16777215, 0, 24; + %jmp/1 T_16.11, 8; +T_16.10 ; End of true expr. + %pushi/vec4 0, 0, 24; + %jmp/0 T_16.11, 8; + ; End of false expr. + %blend; +T_16.11; + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.5 ; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.6 ; + %load/vec4 v0x6467f9d96e30_0; + %load/vec4 v0x6467f9d96e30_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6467f9d96e30_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.7 ; + %load/vec4 v0x6467f9d95ef0_0; + %store/vec4 v0x6467f9d97d60_0, 0, 24; + %jmp T_16.9; +T_16.9 ; + %pop/vec4 1; + %jmp T_16; + .thread T_16, $push; + .scope S_0x6467f9ccbe50; +T_17 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d98620_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_17.0, 8; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x6467f9d978c0_0, 0; + %jmp T_17.1; +T_17.0 ; + %load/vec4 v0x6467f9d98b00_0; + %flag_set/vec4 8; + %jmp/0xz T_17.2, 8; + %load/vec4 v0x6467f9d981c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_17.4, 8; + %load/vec4 v0x6467f9d96c70_0; + %load/vec4 v0x6467f9d96b90_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x6467f9d96ab0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6467f9d978c0_0, 0; + %jmp T_17.5; +T_17.4 ; + %load/vec4 v0x6467f9d98460_0; + %parti/s 4, 0, 2; + %cmpi/e 8, 0, 4; + %jmp/0xz T_17.6, 4; + %load/vec4 v0x6467f9d988a0_0; + %assign/vec4 v0x6467f9d978c0_0, 0; + %jmp T_17.7; +T_17.6 ; + %load/vec4 v0x6467f9d97d60_0; + %assign/vec4 v0x6467f9d978c0_0, 0; +T_17.7 ; +T_17.5 ; + %jmp T_17.3; +T_17.2 ; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x6467f9d978c0_0, 0; +T_17.3 ; +T_17.1 ; + %jmp T_17; + .thread T_17; + .scope S_0x6467f9d49890; +T_18 ; + %wait E_0x6467f9cfd880; + %load/vec4 v0x6467f9d9de60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_18.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6467f9d9e660_0, 0; + %jmp T_18.1; +T_18.0 ; + %load/vec4 v0x6467f9d9e660_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6467f9d9e4f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6467f9d9e660_0, 0; +T_18.1 ; + %jmp T_18; + .thread T_18; + .scope S_0x6467f9d49890; +T_19 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d9de60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_19.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d9cf20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d9cd10_0, 0; + %jmp T_19.1; +T_19.0 ; + %load/vec4 v0x6467f9d9cc40_0; + %assign/vec4 v0x6467f9d9cd10_0, 0; + %load/vec4 v0x6467f9d9cc40_0; + %load/vec4 v0x6467f9d9cd10_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_19.2, 8; + %load/vec4 v0x6467f9d9cf20_0; + %inv; + %assign/vec4 v0x6467f9d9cf20_0, 0; +T_19.2 ; +T_19.1 ; + %jmp T_19; + .thread T_19; + .scope S_0x6467f9d49890; +T_20 ; + %wait E_0x6467f9cfd880; + %load/vec4 v0x6467f9d9de60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_20.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6467f9d9ce80_0, 0; + %jmp T_20.1; +T_20.0 ; + %load/vec4 v0x6467f9d9ce80_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6467f9d9cf20_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6467f9d9ce80_0, 0; +T_20.1 ; + %jmp T_20; + .thread T_20; + .scope S_0x6467f9d49890; +T_21 ; + %wait E_0x6467f9cfd880; + %load/vec4 v0x6467f9d9de60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_21.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6467f9d9c830_0, 0; + %jmp T_21.1; +T_21.0 ; + %load/vec4 v0x6467f9d9c830_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6467f9d9c6f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x6467f9d9c830_0, 0; +T_21.1 ; + %jmp T_21; + .thread T_21; + .scope S_0x6467f9d49890; +T_22 ; + %wait E_0x6467f9cfd880; + %load/vec4 v0x6467f9d9de60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_22.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x6467f9d9cab0_0, 0; + %jmp T_22.1; +T_22.0 ; + %load/vec4 v0x6467f9d9c8d0_0; + %flag_set/vec4 8; + %jmp/0xz T_22.2, 8; + %load/vec4 v0x6467f9d9cab0_0; + %inv; + %assign/vec4 v0x6467f9d9cab0_0, 0; +T_22.2 ; +T_22.1 ; + %jmp T_22; + .thread T_22; + .scope S_0x6467f9d49890; +T_23 ; + %wait E_0x6467f9d104f0; + %load/vec4 v0x6467f9d9de60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_23.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x6467f9d9ca10_0, 0; + %jmp T_23.1; +T_23.0 ; + %load/vec4 v0x6467f9d9ca10_0; + %parti/s 2, 0, 2; + %load/vec4 v0x6467f9d9cab0_0; + %concat/vec4; draw_concat_vec4 + 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found.") + return + + print(f"Reading {input_file}...") + with open(input_file, "rb") as f: + data = f.read() + + total_pixels = len(data) // 4 + # Unpack all data + all_pixels = struct.unpack(f"<{total_pixels}I", data) + + # Load Reference + if os.path.exists(ref_image_path): + print(f"Loading reference image: {ref_image_path}...") + with open(ref_image_path, "rb") as f: + ref_data = f.read() + ref_len = len(ref_data) // 4 + ref_pixels = struct.unpack(f"<{ref_len}I", ref_data) + print(f"Reference Image loaded: {len(ref_pixels)} pixels") + else: + print(f"Warning: Reference image {ref_image_path} not found. Skipping verification.") + ref_pixels = None + + FRAME_SIZE = 960 * 540 + + # Helper for verification + def verify_chunk(frame_name, pixels, start_offset_in_ref): + if ref_pixels is None: return + match = True + err_count = 0 + for i in range(len(pixels)): + ref_idx = (i + start_offset_in_ref) % len(ref_pixels) + if pixels[i] != ref_pixels[ref_idx]: + match = False + err_count += 1 + if err_count < 5: + print(f" [FAIL] Pixel {i}: Sim {pixels[i]:06X} != Ref {ref_pixels[ref_idx]:06X}") + + if match: + print(f" [PASS] {frame_name} Verified against Reference Image!") + else: + print(f" [FAIL] {frame_name} had {err_count} mismatches.") + + # Frame 0, 1, 2: All Full Frames + for f_idx in range(3): + start_px = f_idx * FRAME_SIZE + if total_pixels >= start_px + FRAME_SIZE: + print(f"Saving Frame {f_idx} (Full Frame)...") + chunk = all_pixels[start_px : start_px + FRAME_SIZE] + write_bmp(f"frame_{f_idx}_full.bmp", width, 540, chunk) + verify_chunk(f"Frame {f_idx}", chunk, 0) + + print("Done!") + +if __name__ == "__main__": + main() diff --git a/tests/cocotb/check_raw.py b/tests/cocotb/check_raw.py new file mode 100644 index 0000000..2a7b15f --- /dev/null +++ b/tests/cocotb/check_raw.py @@ -0,0 +1,17 @@ +import struct +import os + +raw_path = '../../linux_software/image_converter/image.raw' +if not os.path.exists(raw_path): + raw_path = 'linux_software/image_converter/image.raw' # alternate from root + +with open(raw_path, 'rb') as f: + data = f.read() + words = struct.unpack('<' + str(len(data)//4) + 'I', data) + print(f"Total Words: {len(words)}") + print(f"P0: {words[0]:06X}") + print(f"P1279: {words[1279]:06X}") + print(f"P1280: {words[1280]:06X}") + print(f"P1281: {words[1281]:06X}") + # Also check start of some later lines + print(f"P2560 (Line 2 Start): {words[2560]:06X}") diff --git a/tests/cocotb/hdmi_output.bin.old b/tests/cocotb/hdmi_output.bin.old new file mode 100644 index 0000000000000000000000000000000000000000..5ae8f654110c6a8eea83491c239cb95a7bf67113 GIT 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cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer, ReadOnly, Join +from cocotb.queue import Queue +import random + +class AvalonMemory: + def __init__(self, dut, size=1024*1024): + self.dut = dut + self.mem = {} + # Populate memory with pattern + for i in range(0, size, 4): + self.mem[i] = (i // 4) & 0xFFFFFFFF # Addr/4 pattern + + self.req_queue = Queue() + + async def run(self): + """Standard Avalon-MM Slave Responder""" + # Ensure outputs are driven + self.dut.m_waitrequest.value = 0 + self.dut.m_readdatavalid.value = 0 + self.dut.m_readdata.value = 0 + + # Fork response driver + cocotb.start_soon(self.response_driver()) + + while True: + await RisingEdge(self.dut.clk) + + # Default + # self.dut.m_readdatavalid.value = 0 # Driver handles this + + try: + read_req = int(self.dut.m_read.value) + wait_req = int(self.dut.m_waitrequest.value) + except ValueError: + read_req = 0 + wait_req = 0 + + if read_req and not wait_req: + try: + addr = int(self.dut.m_address.value) + burst = int(self.dut.m_burstcount.value) + except ValueError: + cocotb.log.warning("Avalon Master asserted Read with Undefined Address/Burst") + continue + + # Enqueue Request + self.req_queue.put_nowait((addr, burst)) + + async def response_driver(self): + while True: + # Get next request + addr, burst = await self.req_queue.get() + + # Latency (simulated memory access time) + latency = random.randint(5, 20) + for _ in range(latency): + await RisingEdge(self.dut.clk) + self.dut.m_readdatavalid.value = 0 + + # Send Burst + for i in range(burst): + await RisingEdge(self.dut.clk) + self.dut.m_readdatavalid.value = 1 + addr_cal = addr + (i * 4) + data = self.mem.get(addr_cal, 0xBADF00D) + self.dut.m_readdata.value = data + + # End Burst + await RisingEdge(self.dut.clk) + self.dut.m_readdatavalid.value = 0 + +@cocotb.test() +async def test_dma_basic_transfer(dut): + """Test DMA Single Frame Transfer""" + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + # Initialize ALL Inputs + dut.reset_n.value = 0 + dut.dma_start.value = 0 + dut.dma_cont_en.value = 0 + dut.fifo_used.value = 0 + dut.m_waitrequest.value = 0 + dut.m_readdata.value = 0 + dut.m_readdatavalid.value = 0 + dut.start_addr.value = 0 + dut.vsync_edge.value = 0 + + # Memory Model + mem_model = AvalonMemory(dut) + cocotb.start_soon(mem_model.run()) + + await Timer(50, units="ns") + dut.reset_n.value = 1 + await Timer(50, units="ns") + + # Start DMA + dut.start_addr.value = 0 + dut.dma_start.value = 1 + await RisingEdge(dut.clk) + dut.dma_start.value = 0 + + # Monitor FIFO Writes + expected_count = 0 + last_val = -1 + timeout_counter = 0 + + # Verify at least 512 words (8 bursts) to ensure multiple bursts work smoothly + while expected_count < 512: + await RisingEdge(dut.clk) + + if dut.fifo_wr_en.value == 1: + try: + val = int(dut.fifo_wr_data.value) + except ValueError: + val = -1 + + # dut._log.info(f"FIFO Write: {val} (Expected {expected_count})") + + if val != expected_count: + raise AssertionError(f"Data mismatch! Got {val}, expected {expected_count}") + + last_val = val + expected_count += 1 + timeout_counter = 0 + + timeout_counter += 1 + if timeout_counter > 10000: + raise TimeoutError(f"DMA did not write data. Current count: {expected_count}") + + dut._log.info(f"Verified {expected_count} words written to FIFO") + +@cocotb.test() +async def test_dma_fifo_backpressure(dut): + """Test DMA pauses when FIFO is full""" + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + # Initialize Inputs + dut.reset_n.value = 0 + dut.dma_start.value = 0 + dut.dma_cont_en.value = 0 + dut.start_addr.value = 0 + dut.vsync_edge.value = 0 + dut.fifo_used.value = 0 + + dut.m_waitrequest.value = 0 + dut.m_readdata.value = 0 + dut.m_readdatavalid.value = 0 + + mem_model = AvalonMemory(dut) + cocotb.start_soon(mem_model.run()) + + await Timer(50, units="ns") + dut.reset_n.value = 1 + + # Start DMA + dut.dma_start.value = 1 + await RisingEdge(dut.clk) + dut.dma_start.value = 0 + + # Let it run a bit + await Timer(500, units="ns") + + # Assert FIFO "Almost Full" + dut.fifo_used.value = 450 + + await Timer(2000, units="ns") + + # Monitor for silence on m_read + read_commands = 0 + for _ in range(200): + await RisingEdge(dut.clk) + if dut.m_read.value == 1: + read_commands += 1 + + assert read_commands == 0, "DMA issued read commands despite FIFO being almost full!" + + # Release backpressure + dut.fifo_used.value = 0 + await Timer(500, units="ns") + + # Should see reads again + read_commands = 0 + for _ in range(200): + await RisingEdge(dut.clk) + if dut.m_read.value == 1: + read_commands += 1 + + assert read_commands > 0, "DMA did not resume after FIFO space cleared" diff --git a/tests/cocotb/tb_fifo.py b/tests/cocotb/tb_fifo.py new file mode 100644 index 0000000..b15e688 --- /dev/null +++ b/tests/cocotb/tb_fifo.py @@ -0,0 +1,155 @@ +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, ReadOnly, Timer +from cocotb.queue import Queue +import random + +class FIFO_Driver: + def __init__(self, dut, name, clock): + self.dut = dut + self.name = name + self.clock = clock + self.queue = Queue() + + async def write(self, data): + while self.dut.wrfull.value: + await RisingEdge(self.clock) + self.dut.wrreq.value = 1 + self.dut.data.value = data + await RisingEdge(self.clock) + self.dut.wrreq.value = 0 + self.queue.put_nowait(data) + +@cocotb.test() +async def test_fifo_basic(dut): + """Basic Write and Read Test""" + cocotb.start_soon(Clock(dut.wrclk, 10, units="ns").start()) # 100MHz + cocotb.start_soon(Clock(dut.rdclk, 13.46, units="ns").start()) # ~74.25MHz + + dut.wrreq.value = 0 + dut.rdreq.value = 0 + + await Timer(50, units="ns") + + # Write 10 values + for i in range(10): + dut.data.value = i + dut.wrreq.value = 1 + await RisingEdge(dut.wrclk) + dut.wrreq.value = 0 + + await Timer(50, units="ns") + + # Read 10 values + for i in range(10): + # Wait until not empty + while dut.rdempty.value: + await RisingEdge(dut.rdclk) + + # Issue Read + dut.rdreq.value = 1 + await RisingEdge(dut.rdclk) + dut.rdreq.value = 0 + + # Wait for data (latency 1 cycle, already passed by RisingEdge above? + # Logic: q updates at posedge rdclk. + # At Time T (RisingEdge), we set rdreq=1. + # At Time T+1 (RisingEdge), q updates. + # So we need to wait ONE MORE edge? + # Code: always @(posedge rdclk) if (rdreq) q <= mem... + # Yes, q updates at the NEXT edge. + await RisingEdge(dut.rdclk) + + await ReadOnly() + read_val = int(dut.q.value) + assert read_val == i, f"Expected {i}, got {read_val}" + + # Correctly exit ReadOnly phase before next loop might drive signals + await RisingEdge(dut.rdclk) + +@cocotb.test() +async def test_fifo_flags(dut): + """Test Full and Empty Flags""" + cocotb.start_soon(Clock(dut.wrclk, 10, units="ns").start()) + cocotb.start_soon(Clock(dut.rdclk, 23, units="ns").start()) # Different freq + + dut.wrreq.value = 0 + dut.rdreq.value = 0 + + # Wait for initial sync + await Timer(100, units="ns") + + # Debug: Print pointers + dut._log.info(f"rdempty: {dut.rdempty.value}") + try: + dut._log.info(f"rd_ptr_gray: {dut.rd_ptr_gray.value}") + dut._log.info(f"wr_ptr_gray_sync2: {dut.wr_ptr_gray_sync2.value}") + except: + dut._log.info("Could not access internal signals directly") + + assert dut.rdempty.value == 1, "Should be empty initially" + assert dut.wrfull.value == 0, "Should not be full initially" + + # Write 1 + dut.data.value = 0xAA + dut.wrreq.value = 1 + await RisingEdge(dut.wrclk) + dut.wrreq.value = 0 + + # Wait for CDC (Writer -> Reader) + # wr_ptr changes -> sync1 -> sync2 -> rdempty clears + # At least 2-3 rdclk cycles + for _ in range(5): + await RisingEdge(dut.rdclk) + + assert dut.rdempty.value == 0, "Should not be empty after write" + + # Read 1 + dut.rdreq.value = 1 + await RisingEdge(dut.rdclk) + dut.rdreq.value = 0 + + # Check Empty again + # rd_ptr changes -> sync1 -> sync2 -> wrfull clears (not checked here) + # But rdempty is purely local to rdclk domain? + # assign rdempty = (rd_ptr_gray == wr_ptr_gray_sync2); + # rd_ptr_gray updates at rdclk. wr_ptr_gray_sync2 is stable (if no more writes). + # So rdempty should assert immediately at next rdclk edge? + await RisingEdge(dut.rdclk) + await ReadOnly() + assert dut.rdempty.value == 1, "Should be empty after reading all data" + +@cocotb.test() +async def test_fifo_overflow_protection(dut): + """Check wrusedw saturation mechanisms""" + cocotb.start_soon(Clock(dut.wrclk, 10, units="ns").start()) + cocotb.start_soon(Clock(dut.rdclk, 10, units="ns").start()) + + dut.wrreq.value = 0 + dut.rdreq.value = 0 + await Timer(100, units="ns") + + # Fill almost full + depth = 512 + for i in range(depth - 1): + dut.data.value = i + dut.wrreq.value = 1 + await RisingEdge(dut.wrclk) + dut.wrreq.value = 0 + + await RisingEdge(dut.wrclk) + + # Write one more to fill + dut.data.value = 0xFF + dut.wrreq.value = 1 + await RisingEdge(dut.wrclk) + dut.wrreq.value = 0 + + await RisingEdge(dut.wrclk) + await ReadOnly() + + assert dut.wrfull.value == 1, "Should be full" + + used = int(dut.wrusedw.value) + # 511 is the saturated max for 9-bit width (which is default ADDR_WIDTH=9) + assert used == 511, f"Used words should be saturated to 511, got {used}" diff --git a/tests/cocotb/tb_hdmi_sync_gen.py b/tests/cocotb/tb_hdmi_sync_gen.py new file mode 100644 index 0000000..628c2c2 --- /dev/null +++ b/tests/cocotb/tb_hdmi_sync_gen.py @@ -0,0 +1,78 @@ +import cocotb +from cocotb.triggers import RisingEdge, Timer +from cocotb.clock import Clock + +async def reset_dut(reset_n, duration_ns): + reset_n.value = 0 + await Timer(duration_ns, unit="ns") + reset_n.value = 1 + await Timer(duration_ns, unit="ns") + +@cocotb.test() +async def test_dma_control_registers(dut): + """Test DMA Control Register (REG_GLOBAL_CTRL) logic""" + + # 1. Start Clock (74.25 MHz -> approx 13468 ps) + cocotb.start_soon(Clock(dut.clk, 13468, unit="ps").start()) + + # 2. Reset + await reset_dut(dut.reset_n, 50) + await RisingEdge(dut.clk) + + # 3. Check Default values (Should be 0) + # Note: These ports will exist AFTER my RTL modification + # Currently they might cause 'attribute not found' or similar if simulator supports it + # But since I'm doing TDD, I expect failure. + + try: + dma_en = dut.dma_enable_out.value + dut._log.info(f"Initial DMA Enable: {dma_en}") + assert dma_en == 0, "DMA Enable should be 0 by default" + except AttributeError: + dut._log.error("Port 'dma_enable_out' NOT FOUND in DUT!") + raise AttributeError("Required port 'dma_enable_out' missing for DMA control test") + + # 4. Write to REG_GLOBAL_CTRL (Addr 1) + # Bit 0: Gamma En, Bit 1: DMA En + dut.avs_address.value = 1 + dut.avs_writedata.value = 0x02 # Enable DMA, Disable Gamma + dut.avs_write.value = 1 + await RisingEdge(dut.clk) + dut.avs_write.value = 0 + + await RisingEdge(dut.clk) + + # 5. Check dma_enable_out + assert dut.dma_enable_out.value == 1, "DMA Enable output should be 1 after writing 0x02 to Addr 1" + + # 6. Disable DMA + dut.avs_address.value = 1 + dut.avs_writedata.value = 0x01 # Disable DMA, Enable Gamma + dut.avs_write.value = 1 + await RisingEdge(dut.clk) + dut.avs_write.value = 0 + + await RisingEdge(dut.clk) + assert dut.dma_enable_out.value == 0, "DMA Enable output should be 0 after writing 0x01 to Addr 1" + dut._log.info("DMA Control Register Test PASSED") + +@cocotb.test() +async def test_mode_out_connection(dut): + """Test reg_mode_out port connection for video_pipeline synchronization""" + + cocotb.start_soon(Clock(dut.clk, 13468, unit="ps").start()) + await reset_dut(dut.reset_n, 50) + + try: + # Write mode 8 + dut.avs_address.value = 0 + dut.avs_writedata.value = 8 + dut.avs_write.value = 1 + await RisingEdge(dut.clk) + dut.avs_write.value = 0 + + await RisingEdge(dut.clk) + assert dut.reg_mode_out.value == 8, "reg_mode_out should reflect mode 8" + except AttributeError: + dut._log.error("Port 'reg_mode_out' NOT FOUND in DUT!") + raise AttributeError("Required port 'reg_mode_out' missing for pipeline sync test") diff --git a/tests/cocotb/tb_video_dma_master.py b/tests/cocotb/tb_video_dma_master.py new file mode 100644 index 0000000..e49e384 --- /dev/null +++ b/tests/cocotb/tb_video_dma_master.py @@ -0,0 +1,64 @@ +import cocotb +from cocotb.triggers import RisingEdge, Timer +from cocotb.clock import Clock + +async def reset_dut(reset_n, duration_ns): + reset_n.value = 0 + await Timer(duration_ns, unit="ns") + reset_n.value = 1 + await Timer(duration_ns, unit="ns") + +@cocotb.test() +async def test_dma_single_frame(dut): + """Test that DMA starts on start pulse and stops after one frame""" + + cocotb.start_soon(Clock(dut.clk, 20, unit="ns").start()) # 50MHz + await reset_dut(dut.reset_n, 100) + + # Setup + dut.dma_start.value = 0 + dut.dma_cont_en.value = 0 + dut.start_addr.value = 0x30000000 + dut.vsync_edge.value = 0 + dut.fifo_used.value = 0 + dut.m_waitrequest.value = 0 + dut.m_readdata.value = 0 + dut.m_readdatavalid.value = 0 + + # 1. Start Pulse + await RisingEdge(dut.clk) + dut.dma_start.value = 1 + await RisingEdge(dut.clk) + dut.dma_start.value = 0 + + # Wait for Busy + await RisingEdge(dut.clk) + assert dut.busy.value == 1, "DMA should be busy after start pulse" + + # 2. Simulate reading some data (just verify it stays busy) + for _ in range(100): + await RisingEdge(dut.clk) + if (dut.m_read.value == 1): + dut.m_readdatavalid.value = 1 + else: + dut.m_readdatavalid.value = 0 + + assert dut.busy.value == 1, "DMA should still be busy mid-frame" + dut._log.info("DMA successfully started and busy bit set") + +@cocotb.test() +async def test_dma_continuous_mode(dut): + """Test that DMA starts and restarts on V-Sync in continuous mode""" + + cocotb.start_soon(Clock(dut.clk, 20, unit="ns").start()) + await reset_dut(dut.reset_n, 100) + + dut.dma_start.value = 0 + dut.dma_cont_en.value = 1 + dut.vsync_edge.value = 1 + await RisingEdge(dut.clk) + dut.vsync_edge.value = 0 + + await RisingEdge(dut.clk) + assert dut.busy.value == 1, "DMA should start on V-Sync in continuous mode" + dut._log.info("DMA continuous mode started successfully") diff --git a/tests/cocotb/tb_video_integration.py b/tests/cocotb/tb_video_integration.py new file mode 100644 index 0000000..0614601 --- /dev/null +++ b/tests/cocotb/tb_video_integration.py @@ -0,0 +1,219 @@ +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer, ReadOnly, ClockCycles +import os +import struct +import random +from cocotb.queue import Queue + +class AvalonMemory: + def __init__(self, dut, size=1024*1024): + self.dut = dut + self.mem = {} + # Populate memory with pattern: 0x00RRGGBB + for i in range(0, size, 4): + val = (i // 4) & 0x00FFFFFF + self.mem[i] = val + + self.req_queue = Queue() + + async def run(self): + """Standard Avalon-MM Slave Responder""" + self.dut.m_waitrequest.value = 0 + self.dut.m_readdatavalid.value = 0 + self.dut.m_readdata.value = 0 + + cocotb.start_soon(self.response_driver()) + + while True: + await RisingEdge(self.dut.clk_50) + try: + read_req = int(self.dut.m_read.value) + wait_req = int(self.dut.m_waitrequest.value) + except ValueError: + read_req = 0 + wait_req = 0 + + if read_req and not wait_req: + try: + addr = int(self.dut.m_address.value) + burst = int(self.dut.m_burstcount.value) + except ValueError: + continue + self.req_queue.put_nowait((addr, burst)) + + async def response_driver(self): + while True: + addr, burst = await self.req_queue.get() + latency = random.randint(2, 10) + for _ in range(latency): + await RisingEdge(self.dut.clk_50) + self.dut.m_readdatavalid.value = 0 + + for i in range(burst): + await RisingEdge(self.dut.clk_50) + self.dut.m_readdatavalid.value = 1 + addr_cal = addr + (i * 4) + data = self.mem.get(addr_cal, 0x000000) + self.dut.m_readdata.value = data + + await RisingEdge(self.dut.clk_50) + self.dut.m_readdatavalid.value = 0 + +async def configure_pipeline(dut): + """Sets mode to DMA Stream through Nios II Slave interface""" + # Mode 8: DMA Stream + dut.s_address.value = 0 + dut.s_writedata.value = 8 + dut.s_write.value = 1 + await RisingEdge(dut.clk_50) + dut.s_write.value = 0 + + # Global Ctrl: Bit[1]=Continuous Enable + dut.s_address.value = 1 + dut.s_writedata.value = 0x00000002 + dut.s_write.value = 1 + await RisingEdge(dut.clk_50) + dut.s_write.value = 0 + + # Frame Pointer + dut.s_address.value = 6 + dut.s_writedata.value = 0x00000000 + dut.s_write.value = 1 + await RisingEdge(dut.clk_50) + dut.s_write.value = 0 + +@cocotb.test() +async def test_full_integration(dut): + """ + Verify DMA reads -> FIFO -> HDMI Output (960x540 qHD) + """ + cocotb.start_soon(Clock(dut.clk_50, 20, units="ns").start()) # 50 MHz + cocotb.start_soon(Clock(dut.clk_hdmi, 26.43, units="ns").start()) # ~37.83 MHz + + debug_log_file = os.path.join(os.path.dirname(__file__), "debug_timing.log") + if os.path.exists(debug_log_file): os.remove(debug_log_file) + + with open(debug_log_file, "a") as f: f.write("Testbench Start\n") + + # Initialize signals + dut.reset_n.value = 0 + dut.s_read.value = 0 + dut.s_write.value = 0 + dut.m_waitrequest.value = 0 + dut.m_readdata.value = 0 + dut.m_readdatavalid.value = 0 + + # Setup Memory Model + mem_model = AvalonMemory(dut) + image_path = os.path.join(os.path.dirname(os.path.dirname(os.path.dirname(__file__))), + "linux_software/image_converter/image.raw") + if os.path.exists(image_path): + try: + with open(image_path, "rb") as f_img: + raw_data = f_img.read() + words = struct.unpack('<' + str(len(raw_data)//4) + 'I', raw_data) + for i, word in enumerate(words): + mem_model.mem[i*4] = word + with open(debug_log_file, "a") as f: + f.write(f"Loaded {len(words)} words into Memory Model\n") + except Exception as e: + dut._log.error(f"Failed to load image: {e}") + + cocotb.start_soon(mem_model.run()) + + # Reset Sequence + await Timer(100, units="ns") + dut.reset_n.value = 1 + await ClockCycles(dut.clk_hdmi, 10) + + # 1. Configure Pipeline (Start DMA) + await configure_pipeline(dut) + + # 2. Wait for FIFO to prime + dut._log.info("Waiting for FIFO to prime...") + for _ in range(1000): + await RisingEdge(dut.clk_50) + try: + if int(dut.u_simple_fifo.wrusedw.value) > 32: + break + except: pass + + # 3. Fast-Forward to V-Sync start to avoid long wait + # v_cnt=542 is just before V-Sync (starts at 543) + dut._log.info("Fast-forwarding to V-Sync start...") + try: + dut.u_hdmi_sync.v_cnt.value = 542 + dut.u_hdmi_sync.h_cnt.value = 1110 + except: pass + + # 4. Wait for Frame Start (V-Sync Falling Edge) + dut._log.info("Waiting for first Frame Start (VSync Falling)...") + while True: + await RisingEdge(dut.clk_hdmi) + if int(dut.hdmi_vs.value) == 0: # VSync Active + break + + while True: + await RisingEdge(dut.clk_hdmi) + if int(dut.hdmi_vs.value) == 1: # VSync Inactive (Frame Start) + break + + dut._log.info("Frame Start detected! Starting 3-frame capture.") + + # Output file for HDMI data + output_bin_file = os.path.join(os.path.dirname(__file__), "hdmi_output.bin") + f_out = open(output_bin_file, "wb") + + pixel_count = 0 + frame_size = 960 * 540 + target_pixels = frame_size * 3 + + dut._log.info(f"Starting Capture. Target: {target_pixels} pixels") + + vs_prev = 0 + de_prev = 0 + last_dma_addr = -1 + + # Main simulation loop + for cycle in range(5000000): # 5M cycles timeout + await RisingEdge(dut.clk_hdmi) + await ReadOnly() # CRITICAL: Exact sampling + + de = int(dut.hdmi_de.value) + vs = int(dut.hdmi_vs.value) + data = int(dut.hdmi_d.value) + v_cnt = int(dut.u_hdmi_sync.v_cnt.value) + h_cnt = int(dut.u_hdmi_sync.h_cnt.value) + + # Monitor DMA (Reduced for speed) + # curr_dma_addr = int(dut.m_address.value) + # if curr_dma_addr != last_dma_addr: + # last_dma_addr = curr_dma_addr + + # Log DE Transitions (Reduced for speed) + if de != de_prev: + de_prev = de + if vs != vs_prev: + vs_prev = vs + + # Capture Data + if de == 1: + f_out.write(struct.pack("= 950 and px_in_f <= 970: + with open(debug_log_file, "a") as f: + f.write(f"[DEBUG] Fx {pixel_count // frame_size} Px {px_in_f}: {data:06X} (FIFO={int(dut.u_simple_fifo.wrusedw.value)})\n") + + pixel_count += 1 + if pixel_count >= target_pixels: + break + + # Heartbeat + if cycle % 500000 == 0: + dut._log.info(f"Cycles: {cycle}, Captured: {pixel_count}") + + f_out.close() + dut._log.info("Simulation Finished successfully.") diff --git a/tests/cocotb/tb_video_pipeline.py b/tests/cocotb/tb_video_pipeline.py new file mode 100644 index 0000000..cf4f9e7 --- /dev/null +++ b/tests/cocotb/tb_video_pipeline.py @@ -0,0 +1,60 @@ +import cocotb +from cocotb.triggers import RisingEdge, Timer +from cocotb.clock import Clock + +async def reset_pipeline(dut, duration_ns): + dut.reset_n.value = 0 + await Timer(duration_ns, unit="ns") + dut.reset_n.value = 1 + await Timer(duration_ns, unit="ns") + +@cocotb.test() +async def test_pipeline_dma_control(dut): + """Test DMA Start/Busy/Done/Stop through registers""" + + cocotb.start_soon(Clock(dut.clk_50, 20, unit="ns").start()) + cocotb.start_soon(Clock(dut.clk_hdmi, 13468, unit="ps").start()) + + await reset_pipeline(dut, 100) + + # 1. Switch to DMA Mode + dut.s_address.value = 0 + dut.s_writedata.value = 8 + dut.s_write.value = 1 + await RisingEdge(dut.clk_hdmi) + dut.s_write.value = 0 + + # 2. Check initial Busy=0 + dut.s_address.value = 1 + dut.s_read.value = 1 + await RisingEdge(dut.clk_hdmi) + await RisingEdge(dut.clk_hdmi) # Wait for valid + assert not (int(dut.s_readdata.value) & (1 << 31)), "DMA should not be busy initially" + dut.s_read.value = 0 + + # 3. Issue Start Pulse (Addr 1, Bit 2) + dut.s_address.value = 1 + dut.s_writedata.value = 0x04 + dut.s_write.value = 1 + await RisingEdge(dut.clk_hdmi) + dut.s_write.value = 0 + + # 4. Check for Busy bit (Wait for CDC) + for _ in range(20): + dut.s_address.value = 1 + dut.s_read.value = 1 + await RisingEdge(dut.clk_hdmi) + await RisingEdge(dut.clk_hdmi) + if (int(dut.s_readdata.value) & (1 << 31)): + break + assert (int(dut.s_readdata.value) & (1 << 31)), "Busy bit should be set after Start command" + dut._log.info("DMA Busy bit detected correctly") + + # 5. Continuous Mode (Addr 1, Bit 1) + dut.s_address.value = 1 + dut.s_writedata.value = 0x02 + dut.s_write.value = 1 + await RisingEdge(dut.clk_hdmi) + dut.s_write.value = 0 + + dut._log.info("DMA Control register test completed") diff --git a/tests/sim_build/hdmi_sync_gen.vvp b/tests/sim_build/hdmi_sync_gen.vvp new file mode 100644 index 0000000..e8f90d9 --- /dev/null +++ b/tests/sim_build/hdmi_sync_gen.vvp @@ -0,0 +1,1019 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi"; +S_0x63a68be9f240 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x63a68beeaac0 .scope module, "hdmi_sync_gen" "hdmi_sync_gen" 3 6; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "clk_pixel"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /OUTPUT 24 "hdmi_d"; + .port_info 4 /OUTPUT 1 "hdmi_de"; + .port_info 5 /OUTPUT 1 "hdmi_hs"; + .port_info 6 /OUTPUT 1 "hdmi_vs"; + .port_info 7 /INPUT 3 "avs_address"; + .port_info 8 /INPUT 1 "avs_read"; + .port_info 9 /INPUT 1 "avs_write"; + .port_info 10 /INPUT 32 "avs_writedata"; + .port_info 11 /OUTPUT 32 "avs_readdata"; + .port_info 12 /OUTPUT 1 "avs_readdatavalid"; + .port_info 13 /OUTPUT 32 "reg_mode_out"; + .port_info 14 /OUTPUT 1 "dma_enable_out"; + .port_info 15 /OUTPUT 32 "shadow_ptr_out"; + .port_info 16 /INPUT 24 "stream_data_in"; + .port_info 17 /OUTPUT 1 "stream_rd_en"; + .port_info 18 /INPUT 1 "dma_busy"; + .port_info 19 /INPUT 1 "dma_done_in"; + .port_info 20 /OUTPUT 1 "dma_start_out"; + .port_info 21 /OUTPUT 1 "dma_cont_en_out"; + .port_info 22 /OUTPUT 1 "vs_toggle"; +P_0x63a68be70d60 .param/l "H_BACK" 0 3 167, +C4<00000000000000000000000001010000>; +P_0x63a68be70da0 .param/l "H_FRONT" 0 3 165, +C4<00000000000000000000000000110000>; +P_0x63a68be70de0 .param/l "H_SYNC" 0 3 166, +C4<00000000000000000000000000100000>; +P_0x63a68be70e20 .param/l "H_TOTAL" 0 3 168, +C4<00000000000000000000010001100000>; +P_0x63a68be70e60 .param/l "H_VISIBLE" 0 3 164, +C4<00000000000000000000001111000000>; +P_0x63a68be70ea0 .param/l "V_BACK" 0 3 173, +C4<00000000000000000000000000001111>; +P_0x63a68be70ee0 .param/l "V_FRONT" 0 3 171, +C4<00000000000000000000000000000011>; +P_0x63a68be70f20 .param/l "V_SYNC" 0 3 172, +C4<00000000000000000000000000000101>; +P_0x63a68be70f60 .param/l "V_TOTAL" 0 3 174, +C4<00000000000000000000001000110011>; +P_0x63a68be70fa0 .param/l "V_VISIBLE" 0 3 170, +C4<00000000000000000000001000011100>; +L_0x63a68bef7e90 .functor BUFZ 32, v0x63a68bf24c10_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x63a68bef8980 .functor BUFZ 1, v0x63a68bf23650_0, C4<0>, C4<0>, C4<0>; +L_0x63a68bef95d0 .functor BUFZ 32, v0x63a68bf24e90_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x63a68befb9b0 .functor BUFZ 32, v0x63a68bf245f0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x63a68be70cf0 .functor AND 1, L_0x63a68bf35ef0, L_0x63a68bf361e0, C4<1>, C4<1>; +L_0x63a68bf369e0 .functor AND 1, L_0x63a68bf365c0, L_0x63a68bf36840, C4<1>, C4<1>; +L_0x63a68bf36d10 .functor AND 1, L_0x63a68bf36c20, L_0x63a68bf36e70, C4<1>, C4<1>; +L_0x63a68bf37430 .functor BUFZ 8, L_0x63a68bf370d0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x63a68bf379b0 .functor BUFZ 8, L_0x63a68bf37540, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x63a68bf37d60 .functor BUFZ 8, L_0x63a68bf375e0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x63a68bf39040 .functor AND 1, L_0x63a68bf38ac0, L_0x63a68bf38db0, C4<1>, C4<1>; +L_0x63a68bf39b00 .functor OR 1, L_0x63a68bf38f20, L_0x63a68bf39870, C4<0>, C4<0>; +L_0x63a68bf39c80 .functor AND 1, L_0x63a68bf39040, L_0x63a68bf39b00, C4<1>, C4<1>; +L_0x63a68bf3d580 .functor BUFZ 16, L_0x63a68bf3d130, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x63a68bf39c10 .functor AND 1, L_0x63a68be70cf0, L_0x63a68bf3ede0, C4<1>, C4<1>; +L_0x63a68bf3f700 .functor AND 1, L_0x63a68bf39c10, L_0x63a68bf3f330, C4<1>, C4<1>; +L_0x792b62445498 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bef8050_0 .net/2u *"_ivl_100", 31 0, L_0x792b62445498; 1 drivers +v0x63a68bef8b60_0 .net *"_ivl_102", 0 0, L_0x63a68bf37ff0; 1 drivers +v0x63a68bef8c00_0 .net *"_ivl_104", 31 0, L_0x63a68bf380e0; 1 drivers +L_0x792b624454e0 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bef97b0_0 .net *"_ivl_107", 19 0, L_0x792b624454e0; 1 drivers +L_0x792b62445528 .functor BUFT 1, C4<00000000000000000000000011111111>, C4<0>, C4<0>, C4<0>; +v0x63a68bef9850_0 .net/2u *"_ivl_108", 31 0, L_0x792b62445528; 1 drivers +v0x63a68befbad0_0 .net *"_ivl_111", 31 0, L_0x63a68bf382b0; 1 drivers +L_0x792b62445570 .functor BUFT 1, C4<00000000000000000000001110111111>, C4<0>, C4<0>, C4<0>; +v0x63a68befbb70_0 .net/2u *"_ivl_112", 31 0, L_0x792b62445570; 1 drivers +v0x63a68bf1abb0_0 .net *"_ivl_114", 31 0, L_0x63a68bf38420; 1 drivers +L_0x792b624455b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1ac90_0 .net/2u *"_ivl_116", 31 0, L_0x792b624455b8; 1 drivers +v0x63a68bf1ad70_0 .net *"_ivl_118", 31 0, L_0x63a68bf38650; 1 drivers +v0x63a68bf1ae50_0 .net *"_ivl_12", 31 0, L_0x63a68bf25d30; 1 drivers +v0x63a68bf1af30_0 .net *"_ivl_122", 31 0, L_0x63a68bf389d0; 1 drivers +L_0x792b62445600 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1b010_0 .net *"_ivl_125", 19 0, L_0x792b62445600; 1 drivers +L_0x792b62445648 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1b0f0_0 .net/2u *"_ivl_126", 31 0, L_0x792b62445648; 1 drivers +v0x63a68bf1b1d0_0 .net *"_ivl_128", 0 0, L_0x63a68bf38ac0; 1 drivers +v0x63a68bf1b290_0 .net *"_ivl_130", 31 0, L_0x63a68bf38d10; 1 drivers +L_0x792b62445690 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1b370_0 .net *"_ivl_133", 19 0, L_0x792b62445690; 1 drivers +L_0x792b624456d8 .functor BUFT 1, C4<00000000000000000000001000011100>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1b560_0 .net/2u *"_ivl_134", 31 0, L_0x792b624456d8; 1 drivers +v0x63a68bf1b640_0 .net *"_ivl_136", 0 0, L_0x63a68bf38db0; 1 drivers +v0x63a68bf1b700_0 .net *"_ivl_139", 0 0, L_0x63a68bf39040; 1 drivers +v0x63a68bf1b7c0_0 .net *"_ivl_140", 31 0, L_0x63a68bf39150; 1 drivers +L_0x792b62445720 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1b8a0_0 .net *"_ivl_143", 19 0, L_0x792b62445720; 1 drivers +L_0x792b62445768 .functor BUFT 1, C4<00000000000000000000000000111100>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1b980_0 .net/2u *"_ivl_144", 31 0, L_0x792b62445768; 1 drivers +v0x63a68bf1ba60_0 .net *"_ivl_146", 31 0, L_0x63a68bf39240; 1 drivers +L_0x792b624457b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1bb40_0 .net/2u *"_ivl_148", 31 0, L_0x792b624457b0; 1 drivers +L_0x792b62445018 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1bc20_0 .net *"_ivl_15", 19 0, L_0x792b62445018; 1 drivers +v0x63a68bf1bd00_0 .net *"_ivl_150", 0 0, L_0x63a68bf38f20; 1 drivers +v0x63a68bf1bdc0_0 .net *"_ivl_152", 31 0, L_0x63a68bf39500; 1 drivers +L_0x792b624457f8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1bea0_0 .net *"_ivl_155", 19 0, L_0x792b624457f8; 1 drivers +L_0x792b62445840 .functor BUFT 1, C4<00000000000000000000000000111100>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1bf80_0 .net/2u *"_ivl_156", 31 0, L_0x792b62445840; 1 drivers +v0x63a68bf1c060_0 .net *"_ivl_158", 31 0, L_0x63a68bf39730; 1 drivers +L_0x792b62445060 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1c140_0 .net/2u *"_ivl_16", 31 0, L_0x792b62445060; 1 drivers +L_0x792b62445888 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1c220_0 .net/2u *"_ivl_160", 31 0, L_0x792b62445888; 1 drivers +v0x63a68bf1c510_0 .net *"_ivl_162", 0 0, L_0x63a68bf39870; 1 drivers +v0x63a68bf1c5d0_0 .net *"_ivl_165", 0 0, L_0x63a68bf39b00; 1 drivers +v0x63a68bf1c690_0 .net *"_ivl_168", 31 0, L_0x63a68bf39d90; 1 drivers +L_0x792b624458d0 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1c770_0 .net *"_ivl_171", 19 0, L_0x792b624458d0; 1 drivers +L_0x792b62445918 .functor BUFT 1, C4<00000000000000000000000001111000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1c850_0 .net/2u *"_ivl_172", 31 0, L_0x792b62445918; 1 drivers +v0x63a68bf1c930_0 .net *"_ivl_174", 0 0, L_0x63a68bf39e80; 1 drivers +L_0x792b62445960 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1c9f0_0 .net/2u *"_ivl_176", 2 0, L_0x792b62445960; 1 drivers +v0x63a68bf1cad0_0 .net *"_ivl_178", 31 0, L_0x63a68bf3a120; 1 drivers +v0x63a68bf1cbb0_0 .net *"_ivl_18", 0 0, L_0x63a68bf35ef0; 1 drivers +L_0x792b624459a8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1cc70_0 .net *"_ivl_181", 19 0, L_0x792b624459a8; 1 drivers +L_0x792b624459f0 .functor BUFT 1, C4<00000000000000000000000011110000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1cd50_0 .net/2u *"_ivl_182", 31 0, L_0x792b624459f0; 1 drivers +v0x63a68bf1ce30_0 .net *"_ivl_184", 0 0, L_0x63a68bf3a210; 1 drivers +L_0x792b62445a38 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1cef0_0 .net/2u *"_ivl_186", 2 0, L_0x792b62445a38; 1 drivers +v0x63a68bf1cfd0_0 .net *"_ivl_188", 31 0, L_0x63a68bf3a4f0; 1 drivers +L_0x792b62445a80 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1d0b0_0 .net *"_ivl_191", 19 0, L_0x792b62445a80; 1 drivers +L_0x792b62445ac8 .functor BUFT 1, C4<00000000000000000000000101101000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1d190_0 .net/2u *"_ivl_192", 31 0, L_0x792b62445ac8; 1 drivers +v0x63a68bf1d270_0 .net *"_ivl_194", 0 0, L_0x63a68bf3a610; 1 drivers +L_0x792b62445b10 .functor BUFT 1, C4<010>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1d330_0 .net/2u *"_ivl_196", 2 0, L_0x792b62445b10; 1 drivers +v0x63a68bf1d410_0 .net *"_ivl_198", 31 0, L_0x63a68bf3a900; 1 drivers +v0x63a68bf1d4f0_0 .net *"_ivl_20", 31 0, L_0x63a68bf36090; 1 drivers +L_0x792b62445b58 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1d5d0_0 .net *"_ivl_201", 19 0, L_0x792b62445b58; 1 drivers +L_0x792b62445ba0 .functor BUFT 1, C4<00000000000000000000000111100000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1d6b0_0 .net/2u *"_ivl_202", 31 0, L_0x792b62445ba0; 1 drivers +v0x63a68bf1d790_0 .net *"_ivl_204", 0 0, L_0x63a68bf3aa20; 1 drivers +L_0x792b62445be8 .functor BUFT 1, C4<011>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1d850_0 .net/2u *"_ivl_206", 2 0, L_0x792b62445be8; 1 drivers +v0x63a68bf1d930_0 .net *"_ivl_208", 31 0, L_0x63a68bf3ad20; 1 drivers +L_0x792b62445c30 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1da10_0 .net *"_ivl_211", 19 0, L_0x792b62445c30; 1 drivers +L_0x792b62445c78 .functor BUFT 1, C4<00000000000000000000001001011000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1daf0_0 .net/2u *"_ivl_212", 31 0, L_0x792b62445c78; 1 drivers +v0x63a68bf1dbd0_0 .net *"_ivl_214", 0 0, L_0x63a68bf3ae40; 1 drivers +L_0x792b62445cc0 .functor BUFT 1, C4<100>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1dc90_0 .net/2u *"_ivl_216", 2 0, L_0x792b62445cc0; 1 drivers +v0x63a68bf1dd70_0 .net *"_ivl_218", 31 0, L_0x63a68bf3b150; 1 drivers +L_0x792b62445d08 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1de50_0 .net *"_ivl_221", 19 0, L_0x792b62445d08; 1 drivers +L_0x792b62445d50 .functor BUFT 1, C4<00000000000000000000001011010000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1df30_0 .net/2u *"_ivl_222", 31 0, L_0x792b62445d50; 1 drivers +v0x63a68bf1e420_0 .net *"_ivl_224", 0 0, L_0x63a68bf3b270; 1 drivers +L_0x792b62445d98 .functor BUFT 1, C4<101>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1e4e0_0 .net/2u *"_ivl_226", 2 0, L_0x792b62445d98; 1 drivers +v0x63a68bf1e5c0_0 .net *"_ivl_228", 31 0, L_0x63a68bf3b590; 1 drivers +L_0x792b624450a8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1e6a0_0 .net *"_ivl_23", 19 0, L_0x792b624450a8; 1 drivers +L_0x792b62445de0 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1e780_0 .net *"_ivl_231", 19 0, L_0x792b62445de0; 1 drivers +L_0x792b62445e28 .functor BUFT 1, C4<00000000000000000000001101001000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1e860_0 .net/2u *"_ivl_232", 31 0, L_0x792b62445e28; 1 drivers +v0x63a68bf1e940_0 .net *"_ivl_234", 0 0, L_0x63a68bf3b6b0; 1 drivers +L_0x792b62445e70 .functor BUFT 1, C4<110>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1ea00_0 .net/2u *"_ivl_236", 2 0, L_0x792b62445e70; 1 drivers +L_0x792b62445eb8 .functor BUFT 1, C4<111>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1eae0_0 .net/2u *"_ivl_238", 2 0, L_0x792b62445eb8; 1 drivers +L_0x792b624450f0 .functor BUFT 1, C4<00000000000000000000001000011100>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1ebc0_0 .net/2u *"_ivl_24", 31 0, L_0x792b624450f0; 1 drivers +v0x63a68bf1eca0_0 .net *"_ivl_240", 2 0, L_0x63a68bf3b9e0; 1 drivers +v0x63a68bf1ed80_0 .net *"_ivl_242", 2 0, L_0x63a68bf3bba0; 1 drivers +v0x63a68bf1ee60_0 .net *"_ivl_244", 2 0, L_0x63a68bf3bf00; 1 drivers +v0x63a68bf1ef40_0 .net *"_ivl_246", 2 0, L_0x63a68bf3c090; 1 drivers +v0x63a68bf1f020_0 .net *"_ivl_248", 2 0, L_0x63a68bf3c400; 1 drivers +v0x63a68bf1f100_0 .net *"_ivl_250", 2 0, L_0x63a68bf3c590; 1 drivers +L_0x792b62445f00 .functor BUFT 1, C4<00000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1f1e0_0 .net/2u *"_ivl_254", 4 0, L_0x792b62445f00; 1 drivers +v0x63a68bf1f2c0_0 .net *"_ivl_26", 0 0, L_0x63a68bf361e0; 1 drivers +v0x63a68bf1f380_0 .net *"_ivl_262", 15 0, L_0x63a68bf3d130; 1 drivers +v0x63a68bf1f460_0 .net *"_ivl_264", 5 0, L_0x63a68bf3d1d0; 1 drivers +L_0x792b62445f48 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1f540_0 .net *"_ivl_267", 1 0, L_0x792b62445f48; 1 drivers +L_0x792b62445f90 .functor BUFT 1, C4<00000000000000000000000000001111>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1f620_0 .net/2u *"_ivl_270", 31 0, L_0x792b62445f90; 1 drivers +v0x63a68bf1f700_0 .net *"_ivl_272", 31 0, L_0x63a68bf3d6c0; 1 drivers +L_0x792b62445fd8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1f7e0_0 .net *"_ivl_275", 27 0, L_0x792b62445fd8; 1 drivers +v0x63a68bf1f8c0_0 .net *"_ivl_276", 31 0, L_0x63a68bf3d800; 1 drivers +v0x63a68bf1f9a0_0 .net *"_ivl_281", 7 0, L_0x63a68bf3dcb0; 1 drivers +v0x63a68bf1fa80_0 .net *"_ivl_283", 7 0, L_0x63a68bf3df90; 1 drivers +v0x63a68bf1fb60_0 .net *"_ivl_290", 23 0, L_0x63a68bf3e760; 1 drivers +L_0x792b62446020 .functor BUFT 1, C4<000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1fc40_0 .net/2u *"_ivl_292", 23 0, L_0x792b62446020; 1 drivers +v0x63a68bf1fd20_0 .net *"_ivl_296", 31 0, L_0x63a68bf3ecf0; 1 drivers +L_0x792b62446068 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1fe00_0 .net *"_ivl_299", 19 0, L_0x792b62446068; 1 drivers +v0x63a68bf1fee0_0 .net *"_ivl_30", 31 0, L_0x63a68bf36430; 1 drivers +L_0x792b624460b0 .functor BUFT 1, C4<00000000000000000000001000011100>, C4<0>, C4<0>, C4<0>; +v0x63a68bf1ffc0_0 .net/2u *"_ivl_300", 31 0, L_0x792b624460b0; 1 drivers +v0x63a68bf200a0_0 .net *"_ivl_302", 0 0, L_0x63a68bf3ede0; 1 drivers +v0x63a68bf20160_0 .net *"_ivl_305", 0 0, L_0x63a68bf39c10; 1 drivers +v0x63a68bf20220_0 .net *"_ivl_307", 3 0, L_0x63a68bf3f240; 1 drivers +L_0x792b624460f8 .functor BUFT 1, C4<1000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf20300_0 .net/2u *"_ivl_308", 3 0, L_0x792b624460f8; 1 drivers +v0x63a68bf203e0_0 .net *"_ivl_310", 0 0, L_0x63a68bf3f330; 1 drivers +L_0x792b62445138 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf204a0_0 .net *"_ivl_33", 19 0, L_0x792b62445138; 1 drivers +L_0x792b62445180 .functor BUFT 1, C4<00000000000000000000001111110000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf20580_0 .net/2u *"_ivl_34", 31 0, L_0x792b62445180; 1 drivers +v0x63a68bf20660_0 .net *"_ivl_36", 0 0, L_0x63a68bf365c0; 1 drivers +v0x63a68bf20720_0 .net *"_ivl_38", 31 0, L_0x63a68bf36750; 1 drivers +L_0x792b624451c8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf20800_0 .net *"_ivl_41", 19 0, L_0x792b624451c8; 1 drivers +L_0x792b62445210 .functor BUFT 1, C4<00000000000000000000010000010000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf208e0_0 .net/2u *"_ivl_42", 31 0, L_0x792b62445210; 1 drivers +v0x63a68bf209c0_0 .net *"_ivl_44", 0 0, L_0x63a68bf36840; 1 drivers +v0x63a68bf20a80_0 .net *"_ivl_48", 31 0, L_0x63a68bf36ae0; 1 drivers +L_0x792b62445258 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf20b60_0 .net *"_ivl_51", 19 0, L_0x792b62445258; 1 drivers +L_0x792b624452a0 .functor BUFT 1, C4<00000000000000000000001000011111>, C4<0>, C4<0>, C4<0>; +v0x63a68bf20c40_0 .net/2u *"_ivl_52", 31 0, L_0x792b624452a0; 1 drivers +v0x63a68bf20d20_0 .net *"_ivl_54", 0 0, L_0x63a68bf36c20; 1 drivers +v0x63a68bf20de0_0 .net *"_ivl_56", 31 0, L_0x63a68bf36d80; 1 drivers +L_0x792b624452e8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf20ec0_0 .net *"_ivl_59", 19 0, L_0x792b624452e8; 1 drivers +L_0x792b62445330 .functor BUFT 1, C4<00000000000000000000001000100100>, C4<0>, C4<0>, C4<0>; +v0x63a68bf20fa0_0 .net/2u *"_ivl_60", 31 0, L_0x792b62445330; 1 drivers +v0x63a68bf21080_0 .net *"_ivl_62", 0 0, L_0x63a68bf36e70; 1 drivers +v0x63a68bf21140_0 .net *"_ivl_66", 7 0, L_0x63a68bf370d0; 1 drivers +v0x63a68bf21220_0 .net *"_ivl_69", 7 0, L_0x63a68bf37170; 1 drivers +v0x63a68bf21300_0 .net *"_ivl_70", 9 0, L_0x63a68bf372a0; 1 drivers +L_0x792b62445378 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x63a68bf213e0_0 .net *"_ivl_73", 1 0, L_0x792b62445378; 1 drivers +v0x63a68bf214c0_0 .net *"_ivl_76", 7 0, L_0x63a68bf37540; 1 drivers +v0x63a68bf215a0_0 .net *"_ivl_79", 7 0, L_0x63a68bf37680; 1 drivers +v0x63a68bf21680_0 .net *"_ivl_80", 9 0, L_0x63a68bf37770; 1 drivers +L_0x792b624453c0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x63a68bf21760_0 .net *"_ivl_83", 1 0, L_0x792b624453c0; 1 drivers +v0x63a68bf21840_0 .net *"_ivl_86", 7 0, L_0x63a68bf375e0; 1 drivers +v0x63a68bf21920_0 .net *"_ivl_89", 7 0, L_0x63a68bf37a70; 1 drivers +v0x63a68bf21a00_0 .net *"_ivl_90", 9 0, L_0x63a68bf37bd0; 1 drivers +L_0x792b62445408 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x63a68bf222f0_0 .net *"_ivl_93", 1 0, L_0x792b62445408; 1 drivers +v0x63a68bf223d0_0 .net *"_ivl_96", 31 0, L_0x63a68bf37e80; 1 drivers +L_0x792b62445450 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x63a68bf224b0_0 .net *"_ivl_99", 19 0, L_0x792b62445450; 1 drivers +o0x792b6248f8d8 .functor BUFZ 3, C4; HiZ drive +v0x63a68bf22590_0 .net "avs_address", 2 0, o0x792b6248f8d8; 0 drivers +o0x792b6248f908 .functor BUFZ 1, C4; HiZ drive +v0x63a68bf22670_0 .net "avs_read", 0 0, o0x792b6248f908; 0 drivers +v0x63a68bf22730_0 .net "avs_readdata", 31 0, L_0x63a68befb9b0; 1 drivers +v0x63a68bf22810_0 .var "avs_readdatavalid", 0 0; +o0x792b6248f998 .functor BUFZ 1, C4; HiZ drive +v0x63a68bf228d0_0 .net "avs_write", 0 0, o0x792b6248f998; 0 drivers +o0x792b6248f9c8 .functor BUFZ 32, C4; HiZ drive +v0x63a68bf22990_0 .net "avs_writedata", 31 0, o0x792b6248f9c8; 0 drivers +v0x63a68bf22a70_0 .net "bar_idx", 2 0, L_0x63a68bf3c910; 1 drivers +v0x63a68bf22b50 .array "char_bitmap", 15 0, 15 0; +v0x63a68bf22c10_0 .net "char_col_idx", 3 0, L_0x63a68bf3ce80; 1 drivers +v0x63a68bf22cf0_0 .net "char_color", 23 0, L_0x63a68bf3e8f0; 1 drivers +v0x63a68bf22dd0_0 .net "char_pixel", 0 0, L_0x63a68bf3db70; 1 drivers +v0x63a68bf22e90_0 .net "char_row_idx", 3 0, L_0x63a68bf3cde0; 1 drivers +o0x792b6248fae8 .functor BUFZ 1, C4; HiZ drive +v0x63a68bf22f70_0 .net "clk", 0 0, o0x792b6248fae8; 0 drivers +o0x792b6248fb18 .functor BUFZ 1, C4; HiZ drive +v0x63a68bf23030_0 .net "clk_pixel", 0 0, o0x792b6248fb18; 0 drivers +v0x63a68bf230f0_0 .net "current_row_bits", 15 0, L_0x63a68bf3d580; 1 drivers +o0x792b6248fb78 .functor BUFZ 1, C4; HiZ drive +v0x63a68bf231d0_0 .net "dma_busy", 0 0, o0x792b6248fb78; 0 drivers +v0x63a68bf23290_0 .net "dma_cont_en_out", 0 0, L_0x63a68bf25bd0; 1 drivers +o0x792b6248fbd8 .functor BUFZ 1, C4; HiZ drive +v0x63a68bf23350_0 .net "dma_done_in", 0 0, o0x792b6248fbd8; 0 drivers +v0x63a68bf23410_0 .var "dma_done_sticky", 0 0; +v0x63a68bf234d0_0 .net "dma_enable_out", 0 0, L_0x63a68bf25b30; 1 drivers +v0x63a68bf23590_0 .net "dma_start_out", 0 0, L_0x63a68bef8980; 1 drivers +v0x63a68bf23650_0 .var "dma_start_pulse", 0 0; +v0x63a68bf23710_0 .net "fancy_b", 7 0, L_0x63a68bf3e460; 1 drivers +v0x63a68bf237f0_0 .net "fancy_g", 7 0, L_0x63a68bf3e3c0; 1 drivers +v0x63a68bf238d0_0 .net "fancy_r", 7 0, L_0x63a68bf3e030; 1 drivers +v0x63a68bf239b0_0 .net "gamma_b", 7 0, L_0x63a68bf37d60; 1 drivers +v0x63a68bf23a90_0 .net "gamma_g", 7 0, L_0x63a68bf379b0; 1 drivers +v0x63a68bf23b70_0 .net "gamma_r", 7 0, L_0x63a68bf37430; 1 drivers +v0x63a68bf23c50_0 .net "gray", 7 0, L_0x63a68bf387e0; 1 drivers +v0x63a68bf23d30_0 .net "gray8_val", 7 0, L_0x63a68bf3caa0; 1 drivers +v0x63a68bf23e10_0 .net "grid_line", 0 0, L_0x63a68bf39c80; 1 drivers +v0x63a68bf23ed0_0 .var "h_cnt", 11 0; +v0x63a68bf23fb0_0 .var "hdmi_d", 23 0; +v0x63a68bf24090_0 .var "hdmi_de", 0 0; +v0x63a68bf24150_0 .var "hdmi_hs", 0 0; +v0x63a68bf24210_0 .var "hdmi_vs", 0 0; +v0x63a68bf242d0_0 .var "hs_d1", 0 0; +v0x63a68bf24390_0 .net "hs_wire", 0 0, L_0x63a68bf369e0; 1 drivers +v0x63a68bf24450 .array "lut_mem", 255 0, 7 0; +v0x63a68bf24510_0 .var "pre_gamma_d", 23 0; +v0x63a68bf245f0_0 .var "read_data_mux", 31 0; +v0x63a68bf246d0_0 .var "reg_bitmap_addr", 31 0; +v0x63a68bf247b0_0 .var "reg_bitmap_data", 31 0; +v0x63a68bf24890_0 .var "reg_frame_ptr", 31 0; +v0x63a68bf24970_0 .var "reg_global_ctrl", 31 0; +v0x63a68bf24a50_0 .var "reg_lut_addr", 31 0; +v0x63a68bf24b30_0 .var "reg_lut_data", 31 0; +v0x63a68bf24c10_0 .var "reg_mode", 31 0; +v0x63a68bf24cf0_0 .net "reg_mode_out", 31 0, L_0x63a68bef7e90; 1 drivers +o0x792b624901a8 .functor BUFZ 1, C4; HiZ drive +v0x63a68bf24dd0_0 .net "reset_n", 0 0, o0x792b624901a8; 0 drivers +v0x63a68bf24e90_0 .var "shadow_ptr", 31 0; +v0x63a68bf24f70_0 .net "shadow_ptr_out", 31 0, L_0x63a68bef95d0; 1 drivers +o0x792b62490238 .functor BUFZ 24, C4; HiZ drive +v0x63a68bf25050_0 .net "stream_data_in", 23 0, o0x792b62490238; 0 drivers +v0x63a68bf25130_0 .net "stream_rd_en", 0 0, L_0x63a68bf3f700; 1 drivers +v0x63a68bf251f0_0 .var "v_cnt", 11 0; +v0x63a68bf252d0_0 .net "visible", 0 0, L_0x63a68be70cf0; 1 drivers +v0x63a68bf25390_0 .var "visible_d1", 0 0; +v0x63a68bf25450_0 .var "vs_d1", 0 0; +v0x63a68bf25510_0 .var "vs_sync_sh", 2 0; +v0x63a68bf255f0_0 .var "vs_toggle", 0 0; +v0x63a68bf256b0_0 .net "vs_wire", 0 0, L_0x63a68bf36d10; 1 drivers +E_0x63a68beadda0/0 .event negedge, v0x63a68bf24dd0_0; +E_0x63a68beadda0/1 .event posedge, v0x63a68bf22f70_0; +E_0x63a68beadda0 .event/or E_0x63a68beadda0/0, E_0x63a68beadda0/1; +E_0x63a68bec24d0/0 .event edge, v0x63a68bf24c10_0, v0x63a68bf23c50_0, v0x63a68bf23e10_0, v0x63a68bf23d30_0; +E_0x63a68bec24d0/1 .event edge, v0x63a68bf22cf0_0; +E_0x63a68bec24d0 .event/or E_0x63a68bec24d0/0, E_0x63a68bec24d0/1; +E_0x63a68be95390/0 .event negedge, v0x63a68bf24dd0_0; +E_0x63a68be95390/1 .event posedge, v0x63a68bf23030_0; +E_0x63a68be95390 .event/or E_0x63a68be95390/0, E_0x63a68be95390/1; +E_0x63a68befdbe0/0 .event edge, v0x63a68bf22590_0, v0x63a68bf24c10_0, v0x63a68bf231d0_0, v0x63a68bf23410_0; +E_0x63a68befdbe0/1 .event edge, v0x63a68bf24970_0, v0x63a68bf24a50_0, v0x63a68bf24b30_0, v0x63a68bf246d0_0; +E_0x63a68befdbe0/2 .event edge, v0x63a68bf247b0_0, v0x63a68bf24890_0; +E_0x63a68befdbe0 .event/or E_0x63a68befdbe0/0, E_0x63a68befdbe0/1, E_0x63a68befdbe0/2; +L_0x63a68bf25b30 .part v0x63a68bf24970_0, 1, 1; +L_0x63a68bf25bd0 .part v0x63a68bf24970_0, 1, 1; +L_0x63a68bf25d30 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445018; +L_0x63a68bf35ef0 .cmp/gt 32, L_0x792b62445060, L_0x63a68bf25d30; +L_0x63a68bf36090 .concat [ 12 20 0 0], v0x63a68bf251f0_0, L_0x792b624450a8; +L_0x63a68bf361e0 .cmp/gt 32, L_0x792b624450f0, L_0x63a68bf36090; +L_0x63a68bf36430 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445138; +L_0x63a68bf365c0 .cmp/ge 32, L_0x63a68bf36430, L_0x792b62445180; +L_0x63a68bf36750 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b624451c8; +L_0x63a68bf36840 .cmp/gt 32, L_0x792b62445210, L_0x63a68bf36750; +L_0x63a68bf36ae0 .concat [ 12 20 0 0], v0x63a68bf251f0_0, L_0x792b62445258; +L_0x63a68bf36c20 .cmp/ge 32, L_0x63a68bf36ae0, L_0x792b624452a0; +L_0x63a68bf36d80 .concat [ 12 20 0 0], v0x63a68bf251f0_0, L_0x792b624452e8; +L_0x63a68bf36e70 .cmp/gt 32, L_0x792b62445330, L_0x63a68bf36d80; +L_0x63a68bf370d0 .array/port v0x63a68bf24450, L_0x63a68bf372a0; +L_0x63a68bf37170 .part v0x63a68bf24510_0, 16, 8; +L_0x63a68bf372a0 .concat [ 8 2 0 0], L_0x63a68bf37170, L_0x792b62445378; +L_0x63a68bf37540 .array/port v0x63a68bf24450, L_0x63a68bf37770; +L_0x63a68bf37680 .part v0x63a68bf24510_0, 8, 8; +L_0x63a68bf37770 .concat [ 8 2 0 0], L_0x63a68bf37680, L_0x792b624453c0; +L_0x63a68bf375e0 .array/port v0x63a68bf24450, L_0x63a68bf37bd0; +L_0x63a68bf37a70 .part v0x63a68bf24510_0, 0, 8; +L_0x63a68bf37bd0 .concat [ 8 2 0 0], L_0x63a68bf37a70, L_0x792b62445408; +L_0x63a68bf37e80 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445450; +L_0x63a68bf37ff0 .cmp/gt 32, L_0x792b62445498, L_0x63a68bf37e80; +L_0x63a68bf380e0 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b624454e0; +L_0x63a68bf382b0 .arith/mult 32, L_0x63a68bf380e0, L_0x792b62445528; +L_0x63a68bf38420 .arith/div 32, L_0x63a68bf382b0, L_0x792b62445570; +L_0x63a68bf38650 .functor MUXZ 32, L_0x792b624455b8, L_0x63a68bf38420, L_0x63a68bf37ff0, C4<>; +L_0x63a68bf387e0 .part L_0x63a68bf38650, 0, 8; +L_0x63a68bf389d0 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445600; +L_0x63a68bf38ac0 .cmp/gt 32, L_0x792b62445648, L_0x63a68bf389d0; +L_0x63a68bf38d10 .concat [ 12 20 0 0], v0x63a68bf251f0_0, L_0x792b62445690; +L_0x63a68bf38db0 .cmp/gt 32, L_0x792b624456d8, L_0x63a68bf38d10; +L_0x63a68bf39150 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445720; +L_0x63a68bf39240 .arith/mod 32, L_0x63a68bf39150, L_0x792b62445768; +L_0x63a68bf38f20 .cmp/eq 32, L_0x63a68bf39240, L_0x792b624457b0; +L_0x63a68bf39500 .concat [ 12 20 0 0], v0x63a68bf251f0_0, L_0x792b624457f8; +L_0x63a68bf39730 .arith/mod 32, L_0x63a68bf39500, L_0x792b62445840; +L_0x63a68bf39870 .cmp/eq 32, L_0x63a68bf39730, L_0x792b62445888; +L_0x63a68bf39d90 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b624458d0; +L_0x63a68bf39e80 .cmp/gt 32, L_0x792b62445918, L_0x63a68bf39d90; +L_0x63a68bf3a120 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b624459a8; +L_0x63a68bf3a210 .cmp/gt 32, L_0x792b624459f0, L_0x63a68bf3a120; +L_0x63a68bf3a4f0 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445a80; +L_0x63a68bf3a610 .cmp/gt 32, L_0x792b62445ac8, L_0x63a68bf3a4f0; +L_0x63a68bf3a900 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445b58; +L_0x63a68bf3aa20 .cmp/gt 32, L_0x792b62445ba0, L_0x63a68bf3a900; +L_0x63a68bf3ad20 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445c30; +L_0x63a68bf3ae40 .cmp/gt 32, L_0x792b62445c78, L_0x63a68bf3ad20; +L_0x63a68bf3b150 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445d08; +L_0x63a68bf3b270 .cmp/gt 32, L_0x792b62445d50, L_0x63a68bf3b150; +L_0x63a68bf3b590 .concat [ 12 20 0 0], v0x63a68bf23ed0_0, L_0x792b62445de0; +L_0x63a68bf3b6b0 .cmp/gt 32, L_0x792b62445e28, L_0x63a68bf3b590; +L_0x63a68bf3b9e0 .functor MUXZ 3, L_0x792b62445eb8, L_0x792b62445e70, L_0x63a68bf3b6b0, C4<>; +L_0x63a68bf3bba0 .functor MUXZ 3, L_0x63a68bf3b9e0, L_0x792b62445d98, L_0x63a68bf3b270, C4<>; +L_0x63a68bf3bf00 .functor MUXZ 3, L_0x63a68bf3bba0, L_0x792b62445cc0, L_0x63a68bf3ae40, C4<>; +L_0x63a68bf3c090 .functor MUXZ 3, L_0x63a68bf3bf00, L_0x792b62445be8, L_0x63a68bf3aa20, C4<>; +L_0x63a68bf3c400 .functor MUXZ 3, L_0x63a68bf3c090, L_0x792b62445b10, L_0x63a68bf3a610, C4<>; +L_0x63a68bf3c590 .functor MUXZ 3, L_0x63a68bf3c400, L_0x792b62445a38, L_0x63a68bf3a210, C4<>; +L_0x63a68bf3c910 .functor MUXZ 3, L_0x63a68bf3c590, L_0x792b62445960, L_0x63a68bf39e80, C4<>; +L_0x63a68bf3caa0 .concat [ 5 3 0 0], L_0x792b62445f00, L_0x63a68bf3c910; +L_0x63a68bf3cde0 .part v0x63a68bf251f0_0, 2, 4; +L_0x63a68bf3ce80 .part v0x63a68bf23ed0_0, 2, 4; +L_0x63a68bf3d130 .array/port v0x63a68bf22b50, L_0x63a68bf3d1d0; +L_0x63a68bf3d1d0 .concat [ 4 2 0 0], L_0x63a68bf3cde0, L_0x792b62445f48; +L_0x63a68bf3d6c0 .concat [ 4 28 0 0], L_0x63a68bf3ce80, L_0x792b62445fd8; +L_0x63a68bf3d800 .arith/sub 32, L_0x792b62445f90, L_0x63a68bf3d6c0; +L_0x63a68bf3db70 .part/v L_0x63a68bf3d580, L_0x63a68bf3d800, 1; +L_0x63a68bf3dcb0 .part v0x63a68bf23ed0_0, 0, 8; +L_0x63a68bf3df90 .part v0x63a68bf251f0_0, 0, 8; +L_0x63a68bf3e030 .arith/sum 8, L_0x63a68bf3dcb0, L_0x63a68bf3df90; +L_0x63a68bf3e3c0 .part v0x63a68bf23ed0_0, 2, 8; +L_0x63a68bf3e460 .part v0x63a68bf251f0_0, 2, 8; +L_0x63a68bf3e760 .concat [ 8 8 8 0], L_0x63a68bf3e460, L_0x63a68bf3e3c0, L_0x63a68bf3e030; +L_0x63a68bf3e8f0 .functor MUXZ 24, L_0x792b62446020, L_0x63a68bf3e760, L_0x63a68bf3db70, C4<>; +L_0x63a68bf3ecf0 .concat [ 12 20 0 0], v0x63a68bf251f0_0, L_0x792b62446068; +L_0x63a68bf3ede0 .cmp/gt 32, L_0x792b624460b0, L_0x63a68bf3ecf0; +L_0x63a68bf3f240 .part v0x63a68bf24c10_0, 0, 4; +L_0x63a68bf3f330 .cmp/eq 4, L_0x63a68bf3f240, L_0x792b624460f8; + .scope S_0x63a68beeaac0; +T_0 ; + %pushi/vec4 0, 0, 12; + %store/vec4 v0x63a68bf23ed0_0, 0, 12; + %pushi/vec4 0, 0, 12; + %store/vec4 v0x63a68bf251f0_0, 0, 12; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x63a68bf25390_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x63a68bf242d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x63a68bf25450_0, 0, 1; + %pushi/vec4 0, 0, 24; + %store/vec4 v0x63a68bf23fb0_0, 0, 24; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x63a68bf24090_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x63a68bf24150_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x63a68bf24210_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x63a68bf255f0_0, 0, 1; + %end; + .thread T_0; + .scope S_0x63a68beeaac0; +T_1 ; + %wait E_0x63a68befdbe0; + %load/vec4 v0x63a68bf22590_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_1.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_1.6, 6; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.0 ; + %load/vec4 v0x63a68bf24c10_0; + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.1 ; + %load/vec4 v0x63a68bf231d0_0; + %load/vec4 v0x63a68bf23410_0; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 28; + %load/vec4 v0x63a68bf24970_0; + %parti/s 1, 1, 2; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x63a68bf24970_0; + %parti/s 1, 0, 2; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.2 ; + %load/vec4 v0x63a68bf24a50_0; + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.3 ; + %load/vec4 v0x63a68bf24b30_0; + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.4 ; + %load/vec4 v0x63a68bf246d0_0; + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.5 ; + %load/vec4 v0x63a68bf247b0_0; + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.6 ; + %load/vec4 v0x63a68bf24890_0; + %store/vec4 v0x63a68bf245f0_0, 0, 32; + %jmp T_1.8; +T_1.8 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1, $push; + .scope S_0x63a68beeaac0; +T_2 ; + %wait E_0x63a68beadda0; + %load/vec4 v0x63a68bf24dd0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x63a68bf24c10_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x63a68bf24970_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x63a68bf24a50_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x63a68bf24b30_0, 0; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x63a68bf24890_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf22810_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf23650_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf23410_0, 0; + %pushi/vec4 0, 0, 16; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 4, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 5, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 6, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 7, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 8, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 9, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 10, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 11, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 12, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 13, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 14, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 15, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %jmp T_2.1; +T_2.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf23650_0, 0; + %load/vec4 v0x63a68bf23350_0; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x63a68bf23410_0, 0; +T_2.2 ; + %load/vec4 v0x63a68bf228d0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.4, 8; + %load/vec4 v0x63a68bf22590_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_2.6, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_2.7, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_2.8, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_2.9, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_2.10, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_2.11, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_2.12, 6; + %jmp T_2.14; +T_2.6 ; + %load/vec4 v0x63a68bf22990_0; + %assign/vec4 v0x63a68bf24c10_0, 0; + %jmp T_2.14; +T_2.7 ; + %load/vec4 v0x63a68bf22990_0; + %parti/s 2, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x63a68bf24970_0, 4, 5; + %load/vec4 v0x63a68bf22990_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_2.15, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x63a68bf23650_0, 0; +T_2.15 ; + %load/vec4 v0x63a68bf22990_0; + %parti/s 1, 30, 6; + %flag_set/vec4 8; + %jmp/0xz T_2.17, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf23410_0, 0; +T_2.17 ; + %jmp T_2.14; +T_2.8 ; + %load/vec4 v0x63a68bf22990_0; + %assign/vec4 v0x63a68bf24a50_0, 0; + %jmp T_2.14; +T_2.9 ; + %load/vec4 v0x63a68bf22990_0; + %assign/vec4 v0x63a68bf24b30_0, 0; + %load/vec4 v0x63a68bf22990_0; + %parti/s 8, 0, 2; + %load/vec4 v0x63a68bf24a50_0; + %parti/s 8, 0, 2; + %pad/u 10; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf24450, 0, 4; + %jmp T_2.14; +T_2.10 ; + %load/vec4 v0x63a68bf22990_0; + %assign/vec4 v0x63a68bf246d0_0, 0; + %jmp T_2.14; +T_2.11 ; + %load/vec4 v0x63a68bf22990_0; + %assign/vec4 v0x63a68bf247b0_0, 0; + %load/vec4 v0x63a68bf22990_0; + %parti/s 16, 0, 2; + %load/vec4 v0x63a68bf246d0_0; + %parti/s 4, 0, 2; + %pad/u 6; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x63a68bf22b50, 0, 4; + %jmp T_2.14; +T_2.12 ; + %load/vec4 v0x63a68bf22990_0; + %assign/vec4 v0x63a68bf24890_0, 0; + %jmp T_2.14; +T_2.14 ; + %pop/vec4 1; +T_2.4 ; + %load/vec4 v0x63a68bf22670_0; + %assign/vec4 v0x63a68bf22810_0, 0; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x63a68beeaac0; +T_3 ; + %wait E_0x63a68be95390; + %load/vec4 v0x63a68bf24dd0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x63a68bf23ed0_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0x63a68bf23ed0_0; + %pad/u 32; + %cmpi/e 1119, 0, 32; + %jmp/0xz T_3.2, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x63a68bf23ed0_0, 0; + %jmp T_3.3; +T_3.2 ; + %load/vec4 v0x63a68bf23ed0_0; + %addi 1, 0, 12; + %assign/vec4 v0x63a68bf23ed0_0, 0; +T_3.3 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x63a68beeaac0; +T_4 ; + %wait E_0x63a68be95390; + %load/vec4 v0x63a68bf24dd0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x63a68bf251f0_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x63a68bf23ed0_0; + %pad/u 32; + %cmpi/e 1119, 0, 32; + %jmp/0xz T_4.2, 4; + %load/vec4 v0x63a68bf251f0_0; + %pad/u 32; + %cmpi/e 562, 0, 32; + %jmp/0xz T_4.4, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x63a68bf251f0_0, 0; + %jmp T_4.5; +T_4.4 ; + %load/vec4 v0x63a68bf251f0_0; + %addi 1, 0, 12; + %assign/vec4 v0x63a68bf251f0_0, 0; +T_4.5 ; +T_4.2 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x63a68beeaac0; +T_5 ; + %wait E_0x63a68be95390; + %load/vec4 v0x63a68bf24dd0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x63a68bf24150_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x63a68bf24210_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf24090_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf25390_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x63a68bf242d0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x63a68bf25450_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x63a68bf255f0_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x63a68bf252d0_0; + %assign/vec4 v0x63a68bf25390_0, 0; + %load/vec4 v0x63a68bf24390_0; + %assign/vec4 v0x63a68bf242d0_0, 0; + %load/vec4 v0x63a68bf256b0_0; + %assign/vec4 v0x63a68bf25450_0, 0; + %load/vec4 v0x63a68bf242d0_0; + %assign/vec4 v0x63a68bf24150_0, 0; + %load/vec4 v0x63a68bf25450_0; + %assign/vec4 v0x63a68bf24210_0, 0; + %load/vec4 v0x63a68bf25390_0; + %assign/vec4 v0x63a68bf24090_0, 0; + %load/vec4 v0x63a68bf256b0_0; + %load/vec4 v0x63a68bf25450_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %load/vec4 v0x63a68bf255f0_0; + %inv; + %assign/vec4 v0x63a68bf255f0_0, 0; +T_5.2 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x63a68beeaac0; +T_6 ; + %wait E_0x63a68beadda0; + %load/vec4 v0x63a68bf24dd0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x63a68bf25510_0, 0; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x63a68bf24e90_0, 0; + %jmp T_6.1; +T_6.0 ; + %load/vec4 v0x63a68bf25510_0; + %parti/s 2, 0, 2; + %load/vec4 v0x63a68bf256b0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x63a68bf25510_0, 0; + %load/vec4 v0x63a68bf25510_0; + %parti/s 1, 1, 2; + %load/vec4 v0x63a68bf25510_0; + %parti/s 1, 2, 3; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_6.2, 8; + %load/vec4 v0x63a68bf24890_0; + %assign/vec4 v0x63a68bf24e90_0, 0; +T_6.2 ; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_0x63a68beeaac0; +T_7 ; + %wait E_0x63a68bec24d0; + %load/vec4 v0x63a68bf24c10_0; + %parti/s 4, 0, 2; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_7.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_7.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_7.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_7.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_7.7, 6; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.0 ; + %pushi/vec4 16711680, 0, 24; + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.1 ; + %pushi/vec4 65280, 0, 24; + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.2 ; + %pushi/vec4 255, 0, 24; + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.3 ; + %load/vec4 v0x63a68bf23c50_0; + %load/vec4 v0x63a68bf23c50_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x63a68bf23c50_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.4 ; + %load/vec4 v0x63a68bf23e10_0; + %flag_set/vec4 8; + %jmp/0 T_7.10, 8; + %pushi/vec4 16777215, 0, 24; + %jmp/1 T_7.11, 8; +T_7.10 ; End of true expr. + %pushi/vec4 0, 0, 24; + %jmp/0 T_7.11, 8; + ; End of false expr. + %blend; +T_7.11; + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.5 ; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.6 ; + %load/vec4 v0x63a68bf23d30_0; + %load/vec4 v0x63a68bf23d30_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x63a68bf23d30_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.7 ; + %load/vec4 v0x63a68bf22cf0_0; + %store/vec4 v0x63a68bf24510_0, 0, 24; + %jmp T_7.9; +T_7.9 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7, $push; + .scope S_0x63a68beeaac0; +T_8 ; + %wait E_0x63a68beadda0; + %load/vec4 v0x63a68bf24dd0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x63a68bf23fb0_0, 0; + %jmp T_8.1; +T_8.0 ; + %load/vec4 v0x63a68bf25390_0; + %flag_set/vec4 8; + %jmp/0xz T_8.2, 8; + %load/vec4 v0x63a68bf24970_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_8.4, 8; + %load/vec4 v0x63a68bf23b70_0; + %load/vec4 v0x63a68bf23a90_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x63a68bf239b0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x63a68bf23fb0_0, 0; + %jmp T_8.5; +T_8.4 ; + %load/vec4 v0x63a68bf24c10_0; + %parti/s 4, 0, 2; + %cmpi/e 8, 0, 4; + %jmp/0xz T_8.6, 4; + %load/vec4 v0x63a68bf25050_0; + %assign/vec4 v0x63a68bf23fb0_0, 0; + %jmp T_8.7; +T_8.6 ; + %load/vec4 v0x63a68bf24510_0; + %assign/vec4 v0x63a68bf23fb0_0, 0; +T_8.7 ; +T_8.5 ; + %jmp T_8.3; +T_8.2 ; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x63a68bf23fb0_0, 0; +T_8.3 ; +T_8.1 ; + %jmp T_8; + .thread T_8; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "-"; + "/mnt/c/Workspace/quartus/video_processing/RTL/hdmi_sync_gen.v"; diff --git a/tests/sim_build/simple_dcfifo.vvp b/tests/sim_build/simple_dcfifo.vvp new file mode 100644 index 0000000..9413683 --- /dev/null +++ b/tests/sim_build/simple_dcfifo.vvp @@ -0,0 +1,217 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi"; +S_0x5787e8037d90 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x5787e8037f20 .scope module, "simple_dcfifo" "simple_dcfifo" 3 3; + .timescale -9 -12; + .port_info 0 /INPUT 1 "wrclk"; + .port_info 1 /INPUT 32 "data"; + .port_info 2 /INPUT 1 "wrreq"; + .port_info 3 /OUTPUT 9 "wrusedw"; + .port_info 4 /OUTPUT 1 "wrfull"; + .port_info 5 /INPUT 1 "rdclk"; + .port_info 6 /INPUT 1 "rdreq"; + .port_info 7 /OUTPUT 32 "q"; + .port_info 8 /OUTPUT 1 "rdempty"; +P_0x5787e8067790 .param/l "ADDR_WIDTH" 0 3 5, +C4<00000000000000000000000000001001>; +P_0x5787e80677d0 .param/l "DATA_WIDTH" 0 3 4, +C4<00000000000000000000000000100000>; +L_0x5787e8063a40 .functor NOT 2, L_0x5787e8098150, C4<00>, C4<00>, C4<00>; +v0x5787e8096750_0 .net *"_ivl_15", 0 0, L_0x5787e8098700; 1 drivers +L_0x7d47c766f018 .functor BUFT 1, C4<111111111>, C4<0>, C4<0>, C4<0>; +v0x5787e8096850_0 .net/2u *"_ivl_16", 8 0, L_0x7d47c766f018; 1 drivers +v0x5787e8096930_0 .net *"_ivl_19", 8 0, L_0x5787e80a8800; 1 drivers +v0x5787e80969f0_0 .net *"_ivl_3", 1 0, L_0x5787e8098150; 1 drivers +v0x5787e8096ad0_0 .net *"_ivl_4", 1 0, L_0x5787e8063a40; 1 drivers +v0x5787e8096c00_0 .net *"_ivl_7", 7 0, L_0x5787e8098270; 1 drivers +v0x5787e8096ce0_0 .net *"_ivl_8", 9 0, L_0x5787e8098310; 1 drivers +o0x7d47c76b8258 .functor BUFZ 32, C4; HiZ drive +v0x5787e8096dc0_0 .net "data", 31 0, o0x7d47c76b8258; 0 drivers +v0x5787e8096ea0 .array "mem", 0 511, 31 0; +v0x5787e8096f60_0 .var "q", 31 0; +v0x5787e8097040_0 .var "rd_ptr_bin", 9 0; +v0x5787e8097120_0 .net "rd_ptr_bin_sync", 9 0, L_0x5787e8098090; 1 drivers +v0x5787e8097200_0 .var "rd_ptr_gray", 9 0; +v0x5787e80972e0_0 .var "rd_ptr_gray_sync1", 9 0; +v0x5787e80973c0_0 .var "rd_ptr_gray_sync2", 9 0; +o0x7d47c76b83a8 .functor BUFZ 1, C4; HiZ drive +v0x5787e80974a0_0 .net "rdclk", 0 0, o0x7d47c76b83a8; 0 drivers +v0x5787e8097560_0 .net "rdempty", 0 0, L_0x5787e80a8ab0; 1 drivers +o0x7d47c76b8408 .functor BUFZ 1, C4; HiZ drive +v0x5787e8097730_0 .net "rdreq", 0 0, o0x7d47c76b8408; 0 drivers +v0x5787e80977f0_0 .net "used_diff", 9 0, L_0x5787e80985a0; 1 drivers +v0x5787e80978d0_0 .var "wr_ptr_bin", 9 0; +v0x5787e80979b0_0 .var "wr_ptr_gray", 9 0; +v0x5787e8097a90_0 .var "wr_ptr_gray_sync1", 9 0; +v0x5787e8097b70_0 .var "wr_ptr_gray_sync2", 9 0; +o0x7d47c76b8528 .functor BUFZ 1, C4; HiZ drive +v0x5787e8097c50_0 .net "wrclk", 0 0, o0x7d47c76b8528; 0 drivers +v0x5787e8097d10_0 .net "wrfull", 0 0, L_0x5787e80984b0; 1 drivers +o0x7d47c76b8588 .functor BUFZ 1, C4; HiZ drive +v0x5787e8097dd0_0 .net "wrreq", 0 0, o0x7d47c76b8588; 0 drivers +v0x5787e8097e90_0 .net "wrusedw", 8 0, L_0x5787e80a88f0; 1 drivers +E_0x5787e8075bf0 .event posedge, v0x5787e80974a0_0; +E_0x5787e8076b40 .event posedge, v0x5787e8097c50_0; +L_0x5787e8098090 .ufunc/vec4 TD_simple_dcfifo.gray2bin, 10, v0x5787e80973c0_0 (v0x5787e80964d0_0) S_0x5787e80962d0; +L_0x5787e8098150 .part v0x5787e80973c0_0, 8, 2; +L_0x5787e8098270 .part v0x5787e80973c0_0, 0, 8; +L_0x5787e8098310 .concat [ 8 2 0 0], L_0x5787e8098270, L_0x5787e8063a40; +L_0x5787e80984b0 .cmp/eq 10, v0x5787e80979b0_0, L_0x5787e8098310; +L_0x5787e80985a0 .arith/sub 10, v0x5787e80978d0_0, L_0x5787e8098090; +L_0x5787e8098700 .part L_0x5787e80985a0, 9, 1; +L_0x5787e80a8800 .part L_0x5787e80985a0, 0, 9; +L_0x5787e80a88f0 .functor MUXZ 9, L_0x5787e80a8800, L_0x7d47c766f018, L_0x5787e8098700, C4<>; +L_0x5787e80a8ab0 .cmp/eq 10, v0x5787e8097200_0, v0x5787e8097b70_0; +S_0x5787e8068750 .scope function.vec4.s10, "bin2gray" "bin2gray" 3 52, 3 52 0, S_0x5787e8037f20; + .timescale -9 -12; +v0x5787e8065720_0 .var "bin", 9 0; +; Variable bin2gray is vec4 return value of scope S_0x5787e8068750 +TD_simple_dcfifo.bin2gray ; + %load/vec4 v0x5787e8065720_0; + %load/vec4 v0x5787e8065720_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %xor; + %ret/vec4 0, 0, 10; Assign to bin2gray (store_vec4_to_lval) + %end; +S_0x5787e80962d0 .scope function.vec4.s10, "gray2bin" "gray2bin" 3 59, 3 59 0, S_0x5787e8037f20; + .timescale -9 -12; +v0x5787e80964d0_0 .var "gray", 9 0; +; Variable gray2bin is vec4 return value of scope S_0x5787e80962d0 +v0x5787e8096690_0 .var/i "i", 31 0; +TD_simple_dcfifo.gray2bin ; + %load/vec4 v0x5787e80964d0_0; + %parti/s 1, 9, 5; + %ix/load 4, 9, 0; + %flag_set/imm 4, 0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %pushi/vec4 8, 0, 32; + %store/vec4 v0x5787e8096690_0, 0, 32; +T_1.0 ; + %load/vec4 v0x5787e8096690_0; + %cmpi/s 0, 0, 32; + %flag_inv 5; GE is !LT + %jmp/0xz T_1.1, 5; + %retload/vec4 0; Load gray2bin (draw_signal_vec4) + %load/vec4 v0x5787e8096690_0; + %addi 1, 0, 32; + %part/s 1; + %load/vec4 v0x5787e80964d0_0; + %load/vec4 v0x5787e8096690_0; + %part/s 1; + %xor; + %ix/getv/s 4, v0x5787e8096690_0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %load/vec4 v0x5787e8096690_0; + %subi 1, 0, 32; + %store/vec4 v0x5787e8096690_0, 0, 32; + %jmp T_1.0; +T_1.1 ; + %end; + .scope S_0x5787e8037f20; +T_2 ; + %wait E_0x5787e8076b40; + %load/vec4 v0x5787e8097200_0; + %assign/vec4 v0x5787e80972e0_0, 0; + %load/vec4 v0x5787e80972e0_0; + %assign/vec4 v0x5787e80973c0_0, 0; + %jmp T_2; + .thread T_2; + .scope S_0x5787e8037f20; +T_3 ; + %wait E_0x5787e8075bf0; + %load/vec4 v0x5787e80979b0_0; + %assign/vec4 v0x5787e8097a90_0, 0; + %load/vec4 v0x5787e8097a90_0; + %assign/vec4 v0x5787e8097b70_0, 0; + %jmp T_3; + .thread T_3; + .scope S_0x5787e8037f20; +T_4 ; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e80978d0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e80979b0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e8097040_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e8097200_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e8097a90_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e8097b70_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e80972e0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x5787e80973c0_0, 0, 10; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x5787e8096f60_0, 0, 32; + %end; + .thread T_4; + .scope S_0x5787e8037f20; +T_5 ; + %wait E_0x5787e8076b40; + %load/vec4 v0x5787e8097dd0_0; + %load/vec4 v0x5787e8097d10_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %load/vec4 v0x5787e8096dc0_0; + %load/vec4 v0x5787e80978d0_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x5787e8096ea0, 0, 4; + %load/vec4 v0x5787e80978d0_0; + %addi 1, 0, 10; + %assign/vec4 v0x5787e80978d0_0, 0; + %load/vec4 v0x5787e80978d0_0; + %addi 1, 0, 10; + %store/vec4 v0x5787e8065720_0, 0, 10; + %callf/vec4 TD_simple_dcfifo.bin2gray, S_0x5787e8068750; + %assign/vec4 v0x5787e80979b0_0, 0; +T_5.0 ; + %jmp T_5; + .thread T_5; + .scope S_0x5787e8037f20; +T_6 ; + %wait E_0x5787e8075bf0; + %load/vec4 v0x5787e8097730_0; + %load/vec4 v0x5787e8097560_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %load/vec4 v0x5787e8097040_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 4; + %load/vec4a v0x5787e8096ea0, 4; + %assign/vec4 v0x5787e8096f60_0, 0; + %load/vec4 v0x5787e8097040_0; + %addi 1, 0, 10; + %assign/vec4 v0x5787e8097040_0, 0; + %load/vec4 v0x5787e8097040_0; + %addi 1, 0, 10; + %store/vec4 v0x5787e8065720_0, 0, 10; + %callf/vec4 TD_simple_dcfifo.bin2gray, S_0x5787e8068750; + %assign/vec4 v0x5787e8097200_0, 0; +T_6.0 ; + %jmp T_6; + .thread T_6; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "-"; + "/mnt/c/Workspace/quartus/video_processing/RTL/simple_dcfifo.v"; diff --git a/tests/sim_build/video_dma_master.vvp b/tests/sim_build/video_dma_master.vvp new file mode 100644 index 0000000..7620397 --- /dev/null +++ b/tests/sim_build/video_dma_master.vvp @@ -0,0 +1,314 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi"; +S_0x61c51c37dcf0 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x61c51c37de80 .scope module, "video_dma_master" "video_dma_master" 3 3; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /INPUT 32 "start_addr"; + .port_info 3 /INPUT 1 "dma_start"; + .port_info 4 /INPUT 1 "dma_cont_en"; + .port_info 5 /OUTPUT 1 "dma_done"; + .port_info 6 /OUTPUT 1 "busy"; + .port_info 7 /INPUT 1 "vsync_edge"; + .port_info 8 /INPUT 1 "m_waitrequest"; + .port_info 9 /INPUT 32 "m_readdata"; + .port_info 10 /INPUT 1 "m_readdatavalid"; + .port_info 11 /OUTPUT 32 "m_address"; + .port_info 12 /OUTPUT 1 "m_read"; + .port_info 13 /OUTPUT 8 "m_burstcount"; + .port_info 14 /INPUT 9 "fifo_used"; + .port_info 15 /OUTPUT 1 "fifo_wr_en"; + .port_info 16 /OUTPUT 32 "fifo_wr_data"; +P_0x61c51c3ad8f0 .param/l "BURST_LEN" 0 3 30, C4<01000000>; +P_0x61c51c3ad930 .param/l "CHECK_FIFO" 1 3 38, C4<01>; +P_0x61c51c3ad970 .param/l "FIFO_DEPTH" 0 3 31, +C4<00000000000000000000001000000000>; +P_0x61c51c3ad9b0 .param/l "FRAME_SIZE_WORDS" 0 3 34, +C4<0000000000000000000000000000000000000000000011100001000000000000>; +P_0x61c51c3ad9f0 .param/l "H_RES" 0 3 32, +C4<00000000000000000000010100000000>; +P_0x61c51c3ada30 .param/l "IDLE" 1 3 37, C4<00>; +P_0x61c51c3ada70 .param/l "ISSUE_READ" 1 3 39, C4<10>; +P_0x61c51c3adab0 .param/l "V_RES" 0 3 33, +C4<00000000000000000000001011010000>; +P_0x61c51c3adaf0 .param/l "WAIT_END" 1 3 40, C4<11>; +o0x7af4b7b9f2e8 .functor BUFZ 1, C4; HiZ drive +L_0x61c51c3ab1d0 .functor BUFZ 1, o0x7af4b7b9f2e8, C4<0>, C4<0>, C4<0>; +o0x7af4b7b9f2b8 .functor BUFZ 32, C4; HiZ drive +L_0x61c51c3abe40 .functor BUFZ 32, o0x7af4b7b9f2b8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x61c51c3e08d0 .functor BUFZ 1, v0x61c51c3df9c0_0, C4<0>, C4<0>, C4<0>; +v0x61c51c3ab330_0 .net "busy", 0 0, L_0x61c51c3e08d0; 1 drivers +o0x7af4b7b9f048 .functor BUFZ 1, C4; HiZ drive +v0x61c51c3ab400_0 .net "clk", 0 0, o0x7af4b7b9f048; 0 drivers +v0x61c51c3abfe0_0 .var "current_read_addr", 31 0; +o0x7af4b7b9f0a8 .functor BUFZ 1, C4; HiZ drive +v0x61c51c3ac0b0_0 .net "dma_cont_en", 0 0, o0x7af4b7b9f0a8; 0 drivers +v0x61c51c3df570_0 .var "dma_done", 0 0; +o0x7af4b7b9f108 .functor BUFZ 1, C4; HiZ drive +v0x61c51c3df680_0 .net "dma_start", 0 0, o0x7af4b7b9f108; 0 drivers +o0x7af4b7b9f138 .functor BUFZ 9, C4; HiZ drive +v0x61c51c3df740_0 .net "fifo_used", 8 0, o0x7af4b7b9f138; 0 drivers +v0x61c51c3df820_0 .net "fifo_wr_data", 31 0, L_0x61c51c3abe40; 1 drivers +v0x61c51c3df900_0 .net "fifo_wr_en", 0 0, L_0x61c51c3ab1d0; 1 drivers +v0x61c51c3df9c0_0 .var "frame_active", 0 0; +v0x61c51c3dfa80_0 .var "is_cont_mode", 0 0; +v0x61c51c3dfb40_0 .var "m_address", 31 0; +L_0x7af4b7b56018 .functor BUFT 1, C4<01000000>, C4<0>, C4<0>, C4<0>; +v0x61c51c3dfc20_0 .net "m_burstcount", 7 0, L_0x7af4b7b56018; 1 drivers +v0x61c51c3dfd00_0 .var "m_read", 0 0; +v0x61c51c3dfdc0_0 .net "m_readdata", 31 0, o0x7af4b7b9f2b8; 0 drivers +v0x61c51c3dfea0_0 .net "m_readdatavalid", 0 0, o0x7af4b7b9f2e8; 0 drivers +o0x7af4b7b9f318 .functor BUFZ 1, C4; HiZ drive +v0x61c51c3dff60_0 .net "m_waitrequest", 0 0, o0x7af4b7b9f318; 0 drivers +v0x61c51c3e0020_0 .var "pending_bursts", 9 0; +o0x7af4b7b9f378 .functor BUFZ 1, C4; HiZ drive +v0x61c51c3e0100_0 .net "reset_n", 0 0, o0x7af4b7b9f378; 0 drivers +o0x7af4b7b9f3a8 .functor BUFZ 32, C4; HiZ drive +v0x61c51c3e01c0_0 .net "start_addr", 31 0, o0x7af4b7b9f3a8; 0 drivers +v0x61c51c3e02a0_0 .var "state", 1 0; +o0x7af4b7b9f408 .functor BUFZ 1, C4; HiZ drive +v0x61c51c3e0380_0 .net "vsync_edge", 0 0, o0x7af4b7b9f408; 0 drivers +v0x61c51c3e0440_0 .var "words_commanded", 31 0; +v0x61c51c3e0520_0 .var "words_received", 31 0; +E_0x61c51c3bb460/0 .event negedge, v0x61c51c3e0100_0; +E_0x61c51c3bb460/1 .event posedge, v0x61c51c3ab400_0; +E_0x61c51c3bb460 .event/or E_0x61c51c3bb460/0, E_0x61c51c3bb460/1; + .scope S_0x61c51c37de80; +T_0 ; + %wait E_0x61c51c3bb460; + %load/vec4 v0x61c51c3e0100_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_0.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x61c51c3e02a0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x61c51c3dfb40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfd00_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x61c51c3abfe0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x61c51c3e0440_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfa80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3df9c0_0, 0; + %pushi/vec4 0, 0, 10; + %assign/vec4 v0x61c51c3e0020_0, 0; + %jmp T_0.1; +T_0.0 ; + %load/vec4 v0x61c51c3e02a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_0.5, 6; + %jmp T_0.6; +T_0.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfd00_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x61c51c3e0440_0, 0; + %load/vec4 v0x61c51c3df680_0; + %flag_set/vec4 8; + %jmp/0xz T_0.7, 8; + %load/vec4 v0x61c51c3e01c0_0; + %assign/vec4 v0x61c51c3abfe0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfa80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x61c51c3df9c0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x61c51c3e02a0_0, 0; + %jmp T_0.8; +T_0.7 ; + %load/vec4 v0x61c51c3ac0b0_0; + %load/vec4 v0x61c51c3e0380_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_0.9, 8; + %load/vec4 v0x61c51c3e01c0_0; + %assign/vec4 v0x61c51c3abfe0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x61c51c3dfa80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x61c51c3df9c0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x61c51c3e02a0_0, 0; + %jmp T_0.10; +T_0.9 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3df9c0_0, 0; +T_0.10 ; +T_0.8 ; + %jmp T_0.6; +T_0.3 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfd00_0, 0; + %load/vec4 v0x61c51c3e0440_0; + %pad/u 64; + %cmpi/u 921600, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_0.11, 5; + %pushi/vec4 3, 0, 2; + %assign/vec4 v0x61c51c3e02a0_0, 0; + %jmp T_0.12; +T_0.11 ; + %load/vec4 v0x61c51c3df740_0; + %pad/u 32; + %load/vec4 v0x61c51c3e0440_0; + %load/vec4 v0x61c51c3e0520_0; + %sub; + %add; + %cmpi/u 446, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_0.13, 5; + %load/vec4 v0x61c51c3abfe0_0; + %assign/vec4 v0x61c51c3dfb40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x61c51c3dfd00_0, 0; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x61c51c3e02a0_0, 0; +T_0.13 ; +T_0.12 ; + %jmp T_0.6; +T_0.4 ; + %load/vec4 v0x61c51c3dff60_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_0.15, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfd00_0, 0; + %load/vec4 v0x61c51c3abfe0_0; + %addi 256, 0, 32; + %assign/vec4 v0x61c51c3abfe0_0, 0; + %load/vec4 v0x61c51c3e0440_0; + %addi 64, 0, 32; + %assign/vec4 v0x61c51c3e0440_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x61c51c3e02a0_0, 0; +T_0.15 ; + %jmp T_0.6; +T_0.5 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfd00_0, 0; + %load/vec4 v0x61c51c3e0520_0; + %pad/u 64; + %cmpi/u 921600, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_0.17, 5; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x61c51c3e02a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3df9c0_0, 0; +T_0.17 ; + %jmp T_0.6; +T_0.6 ; + %pop/vec4 1; + %load/vec4 v0x61c51c3dfa80_0; + %load/vec4 v0x61c51c3ac0b0_0; + %nor/r; + %and; + %load/vec4 v0x61c51c3e02a0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_0.19, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3dfa80_0, 0; +T_0.19 ; +T_0.1 ; + %jmp T_0; + .thread T_0; + .scope S_0x61c51c37de80; +T_1 ; + %wait E_0x61c51c3bb460; + %load/vec4 v0x61c51c3e0100_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x61c51c3e0520_0, 0; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0x61c51c3e02a0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x61c51c3df680_0; + %load/vec4 v0x61c51c3ac0b0_0; + %load/vec4 v0x61c51c3e0380_0; + %and; + %or; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.2, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x61c51c3e0520_0, 0; +T_1.2 ; + %load/vec4 v0x61c51c3dfea0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x61c51c3e0520_0; + %addi 1, 0, 32; + %assign/vec4 v0x61c51c3e0520_0, 0; +T_1.4 ; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x61c51c37de80; +T_2 ; + %wait E_0x61c51c3bb460; + %load/vec4 v0x61c51c3e0100_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3df570_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x61c51c3dfea0_0; + %load/vec4 v0x61c51c3e0520_0; + %pad/u 64; + %pushi/vec4 921599, 0, 64; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x61c51c3df570_0, 0; + %jmp T_2.3; +T_2.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x61c51c3df570_0, 0; +T_2.3 ; +T_2.1 ; + %jmp T_2; + .thread T_2; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "-"; + "/mnt/c/Workspace/quartus/video_processing/RTL/video_dma_master.v"; diff --git a/tests/sim_build/video_pipeline.vvp b/tests/sim_build/video_pipeline.vvp new file mode 100644 index 0000000..194304c --- /dev/null +++ b/tests/sim_build/video_pipeline.vvp @@ -0,0 +1,1726 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi"; +S_0x62b71838b1c0 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x62b7183aa800 .scope module, "video_pipeline" "video_pipeline" 3 3; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk_50"; + .port_info 1 /INPUT 1 "clk_hdmi"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /INPUT 1 "m_waitrequest"; + .port_info 4 /INPUT 32 "m_readdata"; + .port_info 5 /INPUT 1 "m_readdatavalid"; + .port_info 6 /OUTPUT 32 "m_address"; + .port_info 7 /OUTPUT 1 "m_read"; + .port_info 8 /OUTPUT 8 "m_burstcount"; + .port_info 9 /INPUT 3 "s_address"; + .port_info 10 /INPUT 1 "s_read"; + .port_info 11 /INPUT 1 "s_write"; + .port_info 12 /INPUT 32 "s_writedata"; + .port_info 13 /OUTPUT 32 "s_readdata"; + .port_info 14 /OUTPUT 1 "s_readdatavalid"; + .port_info 15 /OUTPUT 24 "hdmi_d"; + .port_info 16 /OUTPUT 1 "hdmi_de"; + .port_info 17 /OUTPUT 1 "hdmi_hs"; + .port_info 18 /OUTPUT 1 "hdmi_vs"; + .port_info 19 /OUTPUT 8 "debug_leds"; +L_0x62b7183b86c0 .functor XOR 1, L_0x62b7183eb840, L_0x62b7183eb940, C4<0>, C4<0>; +L_0x62b7183b9310 .functor XOR 1, L_0x62b7183ebb50, L_0x62b7183ebbf0, C4<0>, C4<0>; +L_0x62b7183bb6f0 .functor XOR 1, L_0x62b7183ebef0, L_0x62b7183ebfd0, C4<0>, C4<0>; +L_0x62b718407000 .functor BUFZ 1, L_0x62b7183bd210, C4<0>, C4<0>, C4<0>; +L_0x62b718407070 .functor BUFZ 1, L_0x62b718406d20, C4<0>, C4<0>, C4<0>; +L_0x62b718407180 .functor BUFZ 1, L_0x62b7183fccc0, C4<0>, C4<0>, C4<0>; +L_0x62b718407230 .functor BUFZ 1, L_0x62b7183b9310, C4<0>, C4<0>, C4<0>; +L_0x62b718407660 .functor BUFZ 1, L_0x62b7183b86c0, C4<0>, C4<0>, C4<0>; +v0x62b7183e8560_0 .net *"_ivl_1", 0 0, L_0x62b7183eb840; 1 drivers +v0x62b7183e8660_0 .net *"_ivl_15", 0 0, L_0x62b7183ebef0; 1 drivers +v0x62b7183e8740_0 .net *"_ivl_17", 0 0, L_0x62b7183ebfd0; 1 drivers +v0x62b7183e8830_0 .net *"_ivl_25", 0 0, L_0x62b718407000; 1 drivers +v0x62b7183e8910_0 .net *"_ivl_29", 0 0, L_0x62b718407070; 1 drivers +v0x62b7183e89f0_0 .net *"_ivl_3", 0 0, L_0x62b7183eb940; 1 drivers +v0x62b7183e8ad0_0 .net *"_ivl_33", 0 0, L_0x62b7184070e0; 1 drivers +v0x62b7183e8bb0_0 .net *"_ivl_37", 0 0, L_0x62b718407180; 1 drivers +v0x62b7183e8c90_0 .net *"_ivl_41", 0 0, L_0x62b718407230; 1 drivers +v0x62b7183e8d70_0 .net *"_ivl_45", 0 0, v0x62b7183e9e50_0; 1 drivers +v0x62b7183e8e50_0 .net *"_ivl_49", 0 0, v0x62b7183e99e0_0; 1 drivers +v0x62b7183e8f30_0 .net *"_ivl_54", 0 0, L_0x62b718407660; 1 drivers +v0x62b7183e9010_0 .net *"_ivl_7", 0 0, L_0x62b7183ebb50; 1 drivers +v0x62b7183e90f0_0 .net *"_ivl_9", 0 0, L_0x62b7183ebbf0; 1 drivers +o0x7feda3498048 .functor BUFZ 1, C4; HiZ drive +v0x62b7183e91d0_0 .net "clk_50", 0 0, o0x7feda3498048; 0 drivers +o0x7feda349a298 .functor BUFZ 1, C4; HiZ drive +v0x62b7183e9270_0 .net "clk_hdmi", 0 0, o0x7feda349a298; 0 drivers +v0x62b7183e9310_0 .net "debug_leds", 7 0, L_0x62b7184073d0; 1 drivers +v0x62b7183e9500_0 .net "dma_busy", 0 0, L_0x62b718381aa0; 1 drivers +v0x62b7183e95f0_0 .net "dma_cont_74", 0 0, L_0x62b7183fcf00; 1 drivers +v0x62b7183e9690_0 .net "dma_cont_sync", 0 0, L_0x62b7183ebe00; 1 drivers +v0x62b7183e9730_0 .var "dma_cont_sync_50", 2 0; +v0x62b7183e97d0_0 .net "dma_done_50", 0 0, v0x62b718381060_0; 1 drivers +v0x62b7183e9870_0 .net "dma_done_sync", 0 0, L_0x62b7183bb6f0; 1 drivers +v0x62b7183e9940_0 .var "dma_done_sync_74", 2 0; +v0x62b7183e99e0_0 .var "dma_done_toggle_50", 0 0; +v0x62b7183e9aa0_0 .net "dma_en", 0 0, L_0x62b7183fce10; 1 drivers +v0x62b7183e9b70_0 .net "dma_start_74", 0 0, L_0x62b7183fd040; 1 drivers +v0x62b7183e9c40_0 .var "dma_start_74_d", 0 0; +v0x62b7183e9ce0_0 .net "dma_start_sync", 0 0, L_0x62b7183b9310; 1 drivers +v0x62b7183e9db0_0 .var "dma_start_sync_50", 2 0; +v0x62b7183e9e50_0 .var "dma_start_toggle_74", 0 0; +v0x62b7183e9f10_0 .net "fifo_empty", 0 0, L_0x62b7183fccc0; 1 drivers +v0x62b7183e9fe0_0 .net "fifo_full", 0 0, L_0x62b7183ec660; 1 drivers +v0x62b7183ea0b0_0 .net "fifo_rd_data", 31 0, v0x62b7183e7580_0; 1 drivers +v0x62b7183ea180_0 .net "fifo_rd_en", 0 0, L_0x62b718406d20; 1 drivers +v0x62b7183ea270_0 .net "fifo_used", 8 0, L_0x62b7183fcb30; 1 drivers +v0x62b7183ea360_0 .net "fifo_wr_data", 31 0, L_0x62b718380e30; 1 drivers +v0x62b7183ea450_0 .net "fifo_wr_en", 0 0, L_0x62b7183bd210; 1 drivers +v0x62b7183ea540_0 .net "hdmi_d", 23 0, v0x62b7183e4640_0; 1 drivers +v0x62b7183ea600_0 .net "hdmi_de", 0 0, v0x62b7183e4720_0; 1 drivers +v0x62b7183ea6a0_0 .net "hdmi_hs", 0 0, v0x62b7183e47e0_0; 1 drivers +v0x62b7183ea740_0 .net "hdmi_vs", 0 0, v0x62b7183e48a0_0; 1 drivers +v0x62b7183ea7e0_0 .net "m_address", 31 0, v0x62b7183d9260_0; 1 drivers +L_0x7feda344f018 .functor BUFT 1, C4<01000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183ea8b0_0 .net "m_burstcount", 7 0, L_0x7feda344f018; 1 drivers +v0x62b7183ea980_0 .net "m_read", 0 0, v0x62b7183d9420_0; 1 drivers +o0x7feda34982b8 .functor BUFZ 32, C4; HiZ drive +v0x62b7183eaa50_0 .net "m_readdata", 31 0, o0x7feda34982b8; 0 drivers +o0x7feda34982e8 .functor BUFZ 1, C4; HiZ drive +v0x62b7183eab20_0 .net "m_readdatavalid", 0 0, o0x7feda34982e8; 0 drivers +o0x7feda3498318 .functor BUFZ 1, C4; HiZ drive +v0x62b7183eabf0_0 .net "m_waitrequest", 0 0, o0x7feda3498318; 0 drivers +v0x62b7183eacc0_0 .net "reg_mode", 31 0, L_0x62b7183ec840; 1 drivers +o0x7feda3498378 .functor BUFZ 1, C4; HiZ drive +v0x62b7183ead90_0 .net "reset_n", 0 0, o0x7feda3498378; 0 drivers +o0x7feda349a088 .functor BUFZ 3, C4; HiZ drive +v0x62b7183eae80_0 .net "s_address", 2 0, o0x7feda349a088; 0 drivers +o0x7feda349a0b8 .functor BUFZ 1, C4; HiZ drive +v0x62b7183eaf20_0 .net "s_read", 0 0, o0x7feda349a0b8; 0 drivers +v0x62b7183eaff0_0 .net "s_readdata", 31 0, L_0x62b7183fd170; 1 drivers +v0x62b7183eb0c0_0 .net "s_readdatavalid", 0 0, v0x62b7183e2ef0_0; 1 drivers +o0x7feda349a148 .functor BUFZ 1, C4; HiZ drive +v0x62b7183eb190_0 .net "s_write", 0 0, o0x7feda349a148; 0 drivers +o0x7feda349a178 .functor BUFZ 32, C4; HiZ drive +v0x62b7183eb260_0 .net "s_writedata", 31 0, o0x7feda349a178; 0 drivers +v0x62b7183eb330_0 .net "shadow_ptr", 31 0, L_0x62b7183fd100; 1 drivers +v0x62b7183eb420_0 .net "vs_toggle_raw", 0 0, v0x62b7183e5c60_0; 1 drivers +v0x62b7183eb4c0_0 .net "vsync_edge_sync", 0 0, L_0x62b7183b86c0; 1 drivers +v0x62b7183eb590_0 .var "vsync_toggle_sync_50", 2 0; +L_0x62b7183eb840 .part v0x62b7183eb590_0, 2, 1; +L_0x62b7183eb940 .part v0x62b7183eb590_0, 1, 1; +L_0x62b7183ebb50 .part v0x62b7183e9db0_0, 2, 1; +L_0x62b7183ebbf0 .part v0x62b7183e9db0_0, 1, 1; +L_0x62b7183ebe00 .part v0x62b7183e9730_0, 1, 1; +L_0x62b7183ebef0 .part v0x62b7183e9940_0, 2, 1; +L_0x62b7183ebfd0 .part v0x62b7183e9940_0, 1, 1; +L_0x62b718406ec0 .part v0x62b7183e7580_0, 0, 24; +L_0x62b7184070e0 .part L_0x62b7183fcb30, 8, 1; +LS_0x62b7184073d0_0_0 .concat8 [ 1 1 1 1], L_0x62b718407000, L_0x62b718407070, L_0x62b7184070e0, L_0x62b718407180; +LS_0x62b7184073d0_0_4 .concat8 [ 1 1 1 1], L_0x62b718407230, v0x62b7183e9e50_0, v0x62b7183e99e0_0, L_0x62b718407660; +L_0x62b7184073d0 .concat8 [ 4 4 0 0], LS_0x62b7184073d0_0_0, LS_0x62b7184073d0_0_4; +S_0x62b71838b510 .scope module, "u_dma_master" "video_dma_master" 3 115, 4 3 0, S_0x62b7183aa800; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "reset_n"; + .port_info 2 /INPUT 32 "start_addr"; + .port_info 3 /INPUT 1 "dma_start"; + .port_info 4 /INPUT 1 "dma_cont_en"; + .port_info 5 /OUTPUT 1 "dma_done"; + .port_info 6 /OUTPUT 1 "busy"; + .port_info 7 /INPUT 1 "vsync_edge"; + .port_info 8 /INPUT 1 "m_waitrequest"; + .port_info 9 /INPUT 32 "m_readdata"; + .port_info 10 /INPUT 1 "m_readdatavalid"; + .port_info 11 /OUTPUT 32 "m_address"; + .port_info 12 /OUTPUT 1 "m_read"; + .port_info 13 /OUTPUT 8 "m_burstcount"; + .port_info 14 /INPUT 9 "fifo_used"; + .port_info 15 /OUTPUT 1 "fifo_wr_en"; + .port_info 16 /OUTPUT 32 "fifo_wr_data"; +P_0x62b7182dcd60 .param/l "BURST_LEN" 0 4 30, C4<01000000>; +P_0x62b7182dcda0 .param/l "CHECK_FIFO" 1 4 38, C4<01>; +P_0x62b7182dcde0 .param/l "FIFO_DEPTH" 0 4 31, +C4<00000000000000000000001000000000>; +P_0x62b7182dce20 .param/l "FRAME_SIZE_WORDS" 0 4 34, +C4<0000000000000000000000000000000000000000000001111110100100000000>; +P_0x62b7182dce60 .param/l "H_RES" 0 4 32, +C4<00000000000000000000001111000000>; +P_0x62b7182dcea0 .param/l "IDLE" 1 4 37, C4<00>; +P_0x62b7182dcee0 .param/l "ISSUE_READ" 1 4 39, C4<10>; +P_0x62b7182dcf20 .param/l "V_RES" 0 4 33, +C4<00000000000000000000001000011100>; +P_0x62b7182dcf60 .param/l "WAIT_END" 1 4 40, C4<11>; +L_0x62b7183bd210 .functor BUFZ 1, o0x7feda34982e8, C4<0>, C4<0>, C4<0>; +L_0x62b718380e30 .functor BUFZ 32, o0x7feda34982b8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x62b718381aa0 .functor BUFZ 1, v0x62b7183d90e0_0, C4<0>, C4<0>, C4<0>; +v0x62b7183bb8b0_0 .net "busy", 0 0, L_0x62b718381aa0; alias, 1 drivers +v0x62b7183bdf40_0 .net "clk", 0 0, o0x7feda3498048; alias, 0 drivers +v0x62b7183bdfe0_0 .var "current_read_addr", 31 0; +v0x62b718380f90_0 .net "dma_cont_en", 0 0, L_0x62b7183ebe00; alias, 1 drivers +v0x62b718381060_0 .var "dma_done", 0 0; +v0x62b718381c40_0 .net "dma_start", 0 0, L_0x62b7183b9310; alias, 1 drivers +v0x62b718381d10_0 .net "fifo_used", 8 0, L_0x62b7183fcb30; alias, 1 drivers +v0x62b7183d8f40_0 .net "fifo_wr_data", 31 0, L_0x62b718380e30; alias, 1 drivers +v0x62b7183d9020_0 .net "fifo_wr_en", 0 0, L_0x62b7183bd210; alias, 1 drivers +v0x62b7183d90e0_0 .var "frame_active", 0 0; +v0x62b7183d91a0_0 .var "is_cont_mode", 0 0; +v0x62b7183d9260_0 .var "m_address", 31 0; +v0x62b7183d9340_0 .net "m_burstcount", 7 0, L_0x7feda344f018; alias, 1 drivers +v0x62b7183d9420_0 .var "m_read", 0 0; +v0x62b7183d94e0_0 .net "m_readdata", 31 0, o0x7feda34982b8; alias, 0 drivers +v0x62b7183d95c0_0 .net "m_readdatavalid", 0 0, o0x7feda34982e8; alias, 0 drivers +v0x62b7183d9680_0 .net "m_waitrequest", 0 0, o0x7feda3498318; alias, 0 drivers +v0x62b7183d9850_0 .var "pending_bursts", 9 0; +v0x62b7183d9930_0 .net "reset_n", 0 0, o0x7feda3498378; alias, 0 drivers +v0x62b7183d99f0_0 .net "start_addr", 31 0, L_0x62b7183fd100; alias, 1 drivers +v0x62b7183d9ad0_0 .var "state", 1 0; +v0x62b7183d9bb0_0 .net "vsync_edge", 0 0, L_0x62b7183b86c0; alias, 1 drivers +v0x62b7183d9c70_0 .var "words_commanded", 31 0; +v0x62b7183d9d50_0 .var "words_received", 31 0; +E_0x62b71833acf0/0 .event negedge, v0x62b7183d9930_0; +E_0x62b71833acf0/1 .event posedge, v0x62b7183bdf40_0; +E_0x62b71833acf0 .event/or E_0x62b71833acf0/0, E_0x62b71833acf0/1; +S_0x62b7183da050 .scope module, "u_hdmi_sync" "hdmi_sync_gen" 3 153, 5 6 0, S_0x62b7183aa800; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "clk_pixel"; + .port_info 2 /INPUT 1 "reset_n"; + .port_info 3 /OUTPUT 24 "hdmi_d"; + .port_info 4 /OUTPUT 1 "hdmi_de"; + .port_info 5 /OUTPUT 1 "hdmi_hs"; + .port_info 6 /OUTPUT 1 "hdmi_vs"; + .port_info 7 /INPUT 3 "avs_address"; + .port_info 8 /INPUT 1 "avs_read"; + .port_info 9 /INPUT 1 "avs_write"; + .port_info 10 /INPUT 32 "avs_writedata"; + .port_info 11 /OUTPUT 32 "avs_readdata"; + .port_info 12 /OUTPUT 1 "avs_readdatavalid"; + .port_info 13 /OUTPUT 32 "reg_mode_out"; + .port_info 14 /OUTPUT 1 "dma_enable_out"; + .port_info 15 /OUTPUT 32 "shadow_ptr_out"; + .port_info 16 /INPUT 24 "stream_data_in"; + .port_info 17 /OUTPUT 1 "stream_rd_en"; + .port_info 18 /INPUT 1 "dma_busy"; + .port_info 19 /INPUT 1 "dma_done_in"; + .port_info 20 /OUTPUT 1 "dma_start_out"; + .port_info 21 /OUTPUT 1 "dma_cont_en_out"; + .port_info 22 /OUTPUT 1 "vs_toggle"; +P_0x62b7183da200 .param/l "H_BACK" 0 5 167, +C4<00000000000000000000000001010000>; +P_0x62b7183da240 .param/l "H_FRONT" 0 5 165, +C4<00000000000000000000000000110000>; +P_0x62b7183da280 .param/l "H_SYNC" 0 5 166, +C4<00000000000000000000000000100000>; +P_0x62b7183da2c0 .param/l "H_TOTAL" 0 5 168, +C4<00000000000000000000010001100000>; +P_0x62b7183da300 .param/l "H_VISIBLE" 0 5 164, +C4<00000000000000000000001111000000>; +P_0x62b7183da340 .param/l "V_BACK" 0 5 173, +C4<00000000000000000000000000001111>; +P_0x62b7183da380 .param/l "V_FRONT" 0 5 171, +C4<00000000000000000000000000000011>; +P_0x62b7183da3c0 .param/l "V_SYNC" 0 5 172, +C4<00000000000000000000000000000101>; +P_0x62b7183da400 .param/l "V_TOTAL" 0 5 174, +C4<00000000000000000000001000110011>; +P_0x62b7183da440 .param/l "V_VISIBLE" 0 5 170, +C4<00000000000000000000001000011100>; +L_0x62b7183ec840 .functor BUFZ 32, v0x62b7183e52a0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x62b7183fd040 .functor BUFZ 1, v0x62b7183e3ce0_0, C4<0>, C4<0>, C4<0>; +L_0x62b7183fd100 .functor BUFZ 32, v0x62b7183e5530_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x62b7183fd170 .functor BUFZ 32, v0x62b7183e4c80_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x62b7183fd780 .functor AND 1, L_0x62b7183fd350, L_0x62b7183fd600, C4<1>, C4<1>; +L_0x62b7183fdda0 .functor AND 1, L_0x62b7183fd9d0, L_0x62b7183fdc50, C4<1>, C4<1>; +L_0x62b7183fe120 .functor AND 1, L_0x62b7183fdfe0, L_0x62b7183fe280, C4<1>, C4<1>; +L_0x62b7183fe840 .functor BUFZ 8, L_0x62b7183fe4e0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x62b7183fedc0 .functor BUFZ 8, L_0x62b7183fe950, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x62b7183ff170 .functor BUFZ 8, L_0x62b7183fe9f0, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x62b718400450 .functor AND 1, L_0x62b7183ffed0, L_0x62b7184001c0, C4<1>, C4<1>; +L_0x62b718401120 .functor OR 1, L_0x62b718400330, L_0x62b718400e90, C4<0>, C4<0>; +L_0x62b7184012a0 .functor AND 1, L_0x62b718400450, L_0x62b718401120, C4<1>, C4<1>; +L_0x62b718404ba0 .functor BUFZ 16, L_0x62b718404750, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x62b718401230 .functor AND 1, L_0x62b7183fd780, L_0x62b718406400, C4<1>, C4<1>; +L_0x62b718406d20 .functor AND 1, L_0x62b718401230, L_0x62b718406950, C4<1>, C4<1>; +L_0x7feda344f528 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dac10_0 .net/2u *"_ivl_100", 31 0, L_0x7feda344f528; 1 drivers +v0x62b7183dad10_0 .net *"_ivl_102", 0 0, L_0x62b7183ff400; 1 drivers +v0x62b7183dadd0_0 .net *"_ivl_104", 31 0, L_0x62b7183ff4f0; 1 drivers +L_0x7feda344f570 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183daec0_0 .net *"_ivl_107", 19 0, L_0x7feda344f570; 1 drivers +L_0x7feda344f5b8 .functor BUFT 1, C4<00000000000000000000000011111111>, C4<0>, C4<0>, C4<0>; +v0x62b7183dafa0_0 .net/2u *"_ivl_108", 31 0, L_0x7feda344f5b8; 1 drivers +v0x62b7183db0d0_0 .net *"_ivl_111", 31 0, L_0x62b7183ff6c0; 1 drivers +L_0x7feda344f600 .functor BUFT 1, C4<00000000000000000000001110111111>, C4<0>, C4<0>, C4<0>; +v0x62b7183db1b0_0 .net/2u *"_ivl_112", 31 0, L_0x7feda344f600; 1 drivers +v0x62b7183db290_0 .net *"_ivl_114", 31 0, L_0x62b7183ff830; 1 drivers +L_0x7feda344f648 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183db370_0 .net/2u *"_ivl_116", 31 0, L_0x7feda344f648; 1 drivers +v0x62b7183db450_0 .net *"_ivl_118", 31 0, L_0x62b7183ffa60; 1 drivers +v0x62b7183db530_0 .net *"_ivl_12", 31 0, L_0x62b7183fd230; 1 drivers +v0x62b7183db610_0 .net *"_ivl_122", 31 0, L_0x62b7183ffde0; 1 drivers +L_0x7feda344f690 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183db6f0_0 .net *"_ivl_125", 19 0, L_0x7feda344f690; 1 drivers +L_0x7feda344f6d8 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183db7d0_0 .net/2u *"_ivl_126", 31 0, L_0x7feda344f6d8; 1 drivers +v0x62b7183db8b0_0 .net *"_ivl_128", 0 0, L_0x62b7183ffed0; 1 drivers +v0x62b7183db970_0 .net *"_ivl_130", 31 0, L_0x62b718400120; 1 drivers +L_0x7feda344f720 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dba50_0 .net *"_ivl_133", 19 0, L_0x7feda344f720; 1 drivers +L_0x7feda344f768 .functor BUFT 1, C4<00000000000000000000001000011100>, C4<0>, C4<0>, C4<0>; +v0x62b7183dbc40_0 .net/2u *"_ivl_134", 31 0, L_0x7feda344f768; 1 drivers +v0x62b7183dbd20_0 .net *"_ivl_136", 0 0, L_0x62b7184001c0; 1 drivers +v0x62b7183dbde0_0 .net *"_ivl_139", 0 0, L_0x62b718400450; 1 drivers +v0x62b7183dbea0_0 .net *"_ivl_140", 31 0, L_0x62b718400560; 1 drivers +L_0x7feda344f7b0 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dbf80_0 .net *"_ivl_143", 19 0, L_0x7feda344f7b0; 1 drivers +L_0x7feda344f7f8 .functor BUFT 1, C4<00000000000000000000000000111100>, C4<0>, C4<0>, C4<0>; +v0x62b7183dc060_0 .net/2u *"_ivl_144", 31 0, L_0x7feda344f7f8; 1 drivers +v0x62b7183dc140_0 .net *"_ivl_146", 31 0, L_0x62b718400650; 1 drivers +L_0x7feda344f840 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dc220_0 .net/2u *"_ivl_148", 31 0, L_0x7feda344f840; 1 drivers +L_0x7feda344f0a8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dc300_0 .net *"_ivl_15", 19 0, L_0x7feda344f0a8; 1 drivers +v0x62b7183dc3e0_0 .net *"_ivl_150", 0 0, L_0x62b718400330; 1 drivers +v0x62b7183dc4a0_0 .net *"_ivl_152", 31 0, L_0x62b718400910; 1 drivers +L_0x7feda344f888 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dc580_0 .net *"_ivl_155", 19 0, L_0x7feda344f888; 1 drivers +L_0x7feda344f8d0 .functor BUFT 1, C4<00000000000000000000000000111100>, C4<0>, C4<0>, C4<0>; +v0x62b7183dc660_0 .net/2u *"_ivl_156", 31 0, L_0x7feda344f8d0; 1 drivers +v0x62b7183dc740_0 .net *"_ivl_158", 31 0, L_0x62b718400b40; 1 drivers +L_0x7feda344f0f0 .functor BUFT 1, C4<00000000000000000000001111000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dc820_0 .net/2u *"_ivl_16", 31 0, L_0x7feda344f0f0; 1 drivers +L_0x7feda344f918 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dc900_0 .net/2u *"_ivl_160", 31 0, L_0x7feda344f918; 1 drivers +v0x62b7183dcbf0_0 .net *"_ivl_162", 0 0, L_0x62b718400e90; 1 drivers +v0x62b7183dccb0_0 .net *"_ivl_165", 0 0, L_0x62b718401120; 1 drivers +v0x62b7183dcd70_0 .net *"_ivl_168", 31 0, L_0x62b7184013b0; 1 drivers +L_0x7feda344f960 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dce50_0 .net *"_ivl_171", 19 0, L_0x7feda344f960; 1 drivers +L_0x7feda344f9a8 .functor BUFT 1, C4<00000000000000000000000001111000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dcf30_0 .net/2u *"_ivl_172", 31 0, L_0x7feda344f9a8; 1 drivers +v0x62b7183dd010_0 .net *"_ivl_174", 0 0, L_0x62b7184014a0; 1 drivers +L_0x7feda344f9f0 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dd0d0_0 .net/2u *"_ivl_176", 2 0, L_0x7feda344f9f0; 1 drivers +v0x62b7183dd1b0_0 .net *"_ivl_178", 31 0, L_0x62b718401740; 1 drivers +v0x62b7183dd290_0 .net *"_ivl_18", 0 0, L_0x62b7183fd350; 1 drivers +L_0x7feda344fa38 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dd350_0 .net *"_ivl_181", 19 0, L_0x7feda344fa38; 1 drivers +L_0x7feda344fa80 .functor BUFT 1, C4<00000000000000000000000011110000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dd430_0 .net/2u *"_ivl_182", 31 0, L_0x7feda344fa80; 1 drivers +v0x62b7183dd510_0 .net *"_ivl_184", 0 0, L_0x62b718401830; 1 drivers +L_0x7feda344fac8 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>; +v0x62b7183dd5d0_0 .net/2u *"_ivl_186", 2 0, L_0x7feda344fac8; 1 drivers +v0x62b7183dd6b0_0 .net *"_ivl_188", 31 0, L_0x62b718401b10; 1 drivers +L_0x7feda344fb10 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dd790_0 .net *"_ivl_191", 19 0, L_0x7feda344fb10; 1 drivers +L_0x7feda344fb58 .functor BUFT 1, C4<00000000000000000000000101101000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dd870_0 .net/2u *"_ivl_192", 31 0, L_0x7feda344fb58; 1 drivers +v0x62b7183dd950_0 .net *"_ivl_194", 0 0, L_0x62b718401c30; 1 drivers +L_0x7feda344fba0 .functor BUFT 1, C4<010>, C4<0>, C4<0>, C4<0>; +v0x62b7183dda10_0 .net/2u *"_ivl_196", 2 0, L_0x7feda344fba0; 1 drivers +v0x62b7183ddaf0_0 .net *"_ivl_198", 31 0, L_0x62b718401f20; 1 drivers +v0x62b7183ddbd0_0 .net *"_ivl_20", 31 0, L_0x62b7183fd4c0; 1 drivers +L_0x7feda344fbe8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183ddcb0_0 .net *"_ivl_201", 19 0, L_0x7feda344fbe8; 1 drivers +L_0x7feda344fc30 .functor BUFT 1, C4<00000000000000000000000111100000>, C4<0>, C4<0>, C4<0>; +v0x62b7183ddd90_0 .net/2u *"_ivl_202", 31 0, L_0x7feda344fc30; 1 drivers +v0x62b7183dde70_0 .net *"_ivl_204", 0 0, L_0x62b718402040; 1 drivers +L_0x7feda344fc78 .functor BUFT 1, C4<011>, C4<0>, C4<0>, C4<0>; +v0x62b7183ddf30_0 .net/2u *"_ivl_206", 2 0, L_0x7feda344fc78; 1 drivers +v0x62b7183de010_0 .net *"_ivl_208", 31 0, L_0x62b718402340; 1 drivers +L_0x7feda344fcc0 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183de0f0_0 .net *"_ivl_211", 19 0, L_0x7feda344fcc0; 1 drivers +L_0x7feda344fd08 .functor BUFT 1, C4<00000000000000000000001001011000>, C4<0>, C4<0>, C4<0>; +v0x62b7183de1d0_0 .net/2u *"_ivl_212", 31 0, L_0x7feda344fd08; 1 drivers +v0x62b7183de2b0_0 .net *"_ivl_214", 0 0, L_0x62b718402460; 1 drivers +L_0x7feda344fd50 .functor BUFT 1, C4<100>, C4<0>, C4<0>, C4<0>; +v0x62b7183de370_0 .net/2u *"_ivl_216", 2 0, L_0x7feda344fd50; 1 drivers +v0x62b7183de450_0 .net *"_ivl_218", 31 0, L_0x62b718402770; 1 drivers +L_0x7feda344fd98 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183de530_0 .net *"_ivl_221", 19 0, L_0x7feda344fd98; 1 drivers +L_0x7feda344fde0 .functor BUFT 1, C4<00000000000000000000001011010000>, C4<0>, C4<0>, C4<0>; +v0x62b7183de610_0 .net/2u *"_ivl_222", 31 0, L_0x7feda344fde0; 1 drivers +v0x62b7183deb00_0 .net *"_ivl_224", 0 0, L_0x62b718402890; 1 drivers +L_0x7feda344fe28 .functor BUFT 1, C4<101>, C4<0>, C4<0>, C4<0>; +v0x62b7183debc0_0 .net/2u *"_ivl_226", 2 0, L_0x7feda344fe28; 1 drivers +v0x62b7183deca0_0 .net *"_ivl_228", 31 0, L_0x62b718402bb0; 1 drivers +L_0x7feda344f138 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183ded80_0 .net *"_ivl_23", 19 0, L_0x7feda344f138; 1 drivers +L_0x7feda344fe70 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dee60_0 .net *"_ivl_231", 19 0, L_0x7feda344fe70; 1 drivers +L_0x7feda344feb8 .functor BUFT 1, C4<00000000000000000000001101001000>, C4<0>, C4<0>, C4<0>; +v0x62b7183def40_0 .net/2u *"_ivl_232", 31 0, L_0x7feda344feb8; 1 drivers +v0x62b7183df020_0 .net *"_ivl_234", 0 0, L_0x62b718402cd0; 1 drivers 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drivers +v0x62b7183df9a0_0 .net *"_ivl_26", 0 0, L_0x62b7183fd600; 1 drivers +v0x62b7183dfa60_0 .net *"_ivl_262", 15 0, L_0x62b718404750; 1 drivers +v0x62b7183dfb40_0 .net *"_ivl_264", 5 0, L_0x62b7184047f0; 1 drivers +L_0x7feda344ffd8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x62b7183dfc20_0 .net *"_ivl_267", 1 0, L_0x7feda344ffd8; 1 drivers +L_0x7feda3450020 .functor BUFT 1, C4<00000000000000000000000000001111>, C4<0>, C4<0>, C4<0>; +v0x62b7183dfd00_0 .net/2u *"_ivl_270", 31 0, L_0x7feda3450020; 1 drivers +v0x62b7183dfde0_0 .net *"_ivl_272", 31 0, L_0x62b718404ce0; 1 drivers +L_0x7feda3450068 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183dfec0_0 .net *"_ivl_275", 27 0, L_0x7feda3450068; 1 drivers +v0x62b7183dffa0_0 .net *"_ivl_276", 31 0, L_0x62b718404e20; 1 drivers +v0x62b7183e0080_0 .net *"_ivl_281", 7 0, L_0x62b7184052d0; 1 drivers +v0x62b7183e0160_0 .net *"_ivl_283", 7 0, L_0x62b7184055b0; 1 drivers +v0x62b7183e0240_0 .net *"_ivl_290", 23 0, L_0x62b718405d80; 1 drivers +L_0x7feda34500b0 .functor BUFT 1, C4<000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e0320_0 .net/2u *"_ivl_292", 23 0, L_0x7feda34500b0; 1 drivers +v0x62b7183e0400_0 .net *"_ivl_296", 31 0, L_0x62b718406310; 1 drivers +L_0x7feda34500f8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e04e0_0 .net *"_ivl_299", 19 0, L_0x7feda34500f8; 1 drivers +v0x62b7183e05c0_0 .net *"_ivl_30", 31 0, L_0x62b7183fd890; 1 drivers +L_0x7feda3450140 .functor BUFT 1, C4<00000000000000000000001000011100>, C4<0>, C4<0>, C4<0>; +v0x62b7183e06a0_0 .net/2u *"_ivl_300", 31 0, L_0x7feda3450140; 1 drivers +v0x62b7183e0780_0 .net *"_ivl_302", 0 0, L_0x62b718406400; 1 drivers +v0x62b7183e0840_0 .net *"_ivl_305", 0 0, L_0x62b718401230; 1 drivers +v0x62b7183e0900_0 .net *"_ivl_307", 3 0, L_0x62b718406860; 1 drivers +L_0x7feda3450188 .functor BUFT 1, C4<1000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e09e0_0 .net/2u *"_ivl_308", 3 0, L_0x7feda3450188; 1 drivers +v0x62b7183e0ac0_0 .net *"_ivl_310", 0 0, L_0x62b718406950; 1 drivers +L_0x7feda344f1c8 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e0b80_0 .net *"_ivl_33", 19 0, L_0x7feda344f1c8; 1 drivers +L_0x7feda344f210 .functor BUFT 1, C4<00000000000000000000001111110000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e0c60_0 .net/2u *"_ivl_34", 31 0, L_0x7feda344f210; 1 drivers +v0x62b7183e0d40_0 .net *"_ivl_36", 0 0, L_0x62b7183fd9d0; 1 drivers +v0x62b7183e0e00_0 .net *"_ivl_38", 31 0, L_0x62b7183fdb60; 1 drivers +L_0x7feda344f258 .functor BUFT 1, C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e0ee0_0 .net *"_ivl_41", 19 0, L_0x7feda344f258; 1 drivers +L_0x7feda344f2a0 .functor BUFT 1, C4<00000000000000000000010000010000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e0fc0_0 .net/2u *"_ivl_42", 31 0, L_0x7feda344f2a0; 1 drivers +v0x62b7183e10a0_0 .net *"_ivl_44", 0 0, L_0x62b7183fdc50; 1 drivers +v0x62b7183e1160_0 .net *"_ivl_48", 31 0, L_0x62b7183fdea0; 1 drivers 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C4<00000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x62b7183e2b90_0 .net *"_ivl_99", 19 0, L_0x7feda344f4e0; 1 drivers +v0x62b7183e2c70_0 .net "avs_address", 2 0, o0x7feda349a088; alias, 0 drivers +v0x62b7183e2d50_0 .net "avs_read", 0 0, o0x7feda349a0b8; alias, 0 drivers +v0x62b7183e2e10_0 .net "avs_readdata", 31 0, L_0x62b7183fd170; alias, 1 drivers +v0x62b7183e2ef0_0 .var "avs_readdatavalid", 0 0; +v0x62b7183e2fb0_0 .net "avs_write", 0 0, o0x7feda349a148; alias, 0 drivers +v0x62b7183e3070_0 .net "avs_writedata", 31 0, o0x7feda349a178; alias, 0 drivers +v0x62b7183e3150_0 .net "bar_idx", 2 0, L_0x62b718403f30; 1 drivers +v0x62b7183e3230 .array "char_bitmap", 15 0, 15 0; +v0x62b7183e32f0_0 .net "char_col_idx", 3 0, L_0x62b7184044a0; 1 drivers +v0x62b7183e33d0_0 .net "char_color", 23 0, L_0x62b718405f10; 1 drivers +v0x62b7183e34b0_0 .net "char_pixel", 0 0, L_0x62b718405190; 1 drivers +v0x62b7183e3570_0 .net "char_row_idx", 3 0, L_0x62b718404400; 1 drivers +v0x62b7183e3650_0 .net "clk", 0 0, o0x7feda3498048; alias, 0 drivers +v0x62b7183e36f0_0 .net "clk_pixel", 0 0, o0x7feda349a298; alias, 0 drivers +v0x62b7183e3790_0 .net "current_row_bits", 15 0, L_0x62b718404ba0; 1 drivers +v0x62b7183e3870_0 .net "dma_busy", 0 0, L_0x62b718381aa0; alias, 1 drivers +v0x62b7183e3940_0 .net "dma_cont_en_out", 0 0, L_0x62b7183fcf00; alias, 1 drivers +v0x62b7183e39e0_0 .net "dma_done_in", 0 0, L_0x62b7183bb6f0; alias, 1 drivers +v0x62b7183e3aa0_0 .var "dma_done_sticky", 0 0; +v0x62b7183e3b60_0 .net "dma_enable_out", 0 0, L_0x62b7183fce10; alias, 1 drivers +v0x62b7183e3c20_0 .net "dma_start_out", 0 0, L_0x62b7183fd040; alias, 1 drivers +v0x62b7183e3ce0_0 .var "dma_start_pulse", 0 0; +v0x62b7183e3da0_0 .net "fancy_b", 7 0, L_0x62b718405a80; 1 drivers +v0x62b7183e3e80_0 .net "fancy_g", 7 0, L_0x62b7184059e0; 1 drivers +v0x62b7183e3f60_0 .net "fancy_r", 7 0, L_0x62b718405650; 1 drivers +v0x62b7183e4040_0 .net "gamma_b", 7 0, L_0x62b7183ff170; 1 drivers +v0x62b7183e4120_0 .net "gamma_g", 7 0, L_0x62b7183fedc0; 1 drivers +v0x62b7183e4200_0 .net "gamma_r", 7 0, L_0x62b7183fe840; 1 drivers +v0x62b7183e42e0_0 .net "gray", 7 0, L_0x62b7183ffbf0; 1 drivers +v0x62b7183e43c0_0 .net "gray8_val", 7 0, L_0x62b7184040c0; 1 drivers +v0x62b7183e44a0_0 .net "grid_line", 0 0, L_0x62b7184012a0; 1 drivers +v0x62b7183e4560_0 .var "h_cnt", 11 0; +v0x62b7183e4640_0 .var "hdmi_d", 23 0; +v0x62b7183e4720_0 .var "hdmi_de", 0 0; +v0x62b7183e47e0_0 .var "hdmi_hs", 0 0; +v0x62b7183e48a0_0 .var "hdmi_vs", 0 0; +v0x62b7183e4960_0 .var "hs_d1", 0 0; +v0x62b7183e4a20_0 .net "hs_wire", 0 0, L_0x62b7183fdda0; 1 drivers +v0x62b7183e4ae0 .array "lut_mem", 255 0, 7 0; +v0x62b7183e4ba0_0 .var "pre_gamma_d", 23 0; +v0x62b7183e4c80_0 .var "read_data_mux", 31 0; +v0x62b7183e4d60_0 .var "reg_bitmap_addr", 31 0; +v0x62b7183e4e40_0 .var "reg_bitmap_data", 31 0; +v0x62b7183e4f20_0 .var "reg_frame_ptr", 31 0; +v0x62b7183e5000_0 .var "reg_global_ctrl", 31 0; +v0x62b7183e50e0_0 .var "reg_lut_addr", 31 0; +v0x62b7183e51c0_0 .var "reg_lut_data", 31 0; +v0x62b7183e52a0_0 .var "reg_mode", 31 0; +v0x62b7183e5380_0 .net "reg_mode_out", 31 0, L_0x62b7183ec840; alias, 1 drivers +v0x62b7183e5460_0 .net "reset_n", 0 0, o0x7feda3498378; alias, 0 drivers +v0x62b7183e5530_0 .var "shadow_ptr", 31 0; +v0x62b7183e55f0_0 .net "shadow_ptr_out", 31 0, L_0x62b7183fd100; alias, 1 drivers +v0x62b7183e56e0_0 .net "stream_data_in", 23 0, L_0x62b718406ec0; 1 drivers +v0x62b7183e57a0_0 .net "stream_rd_en", 0 0, L_0x62b718406d20; alias, 1 drivers +v0x62b7183e5860_0 .var "v_cnt", 11 0; +v0x62b7183e5940_0 .net "visible", 0 0, L_0x62b7183fd780; 1 drivers +v0x62b7183e5a00_0 .var "visible_d1", 0 0; +v0x62b7183e5ac0_0 .var "vs_d1", 0 0; +v0x62b7183e5b80_0 .var "vs_sync_sh", 2 0; +v0x62b7183e5c60_0 .var "vs_toggle", 0 0; +v0x62b7183e5d20_0 .net "vs_wire", 0 0, L_0x62b7183fe120; 1 drivers +E_0x62b71834f690/0 .event edge, v0x62b7183e52a0_0, v0x62b7183e42e0_0, v0x62b7183e44a0_0, v0x62b7183e43c0_0; +E_0x62b71834f690/1 .event edge, v0x62b7183e33d0_0; +E_0x62b71834f690 .event/or E_0x62b71834f690/0, E_0x62b71834f690/1; +E_0x62b718301390/0 .event negedge, v0x62b7183d9930_0; +E_0x62b718301390/1 .event posedge, v0x62b7183e36f0_0; +E_0x62b718301390 .event/or E_0x62b718301390/0, E_0x62b718301390/1; +E_0x62b7183c32f0/0 .event edge, v0x62b7183e2c70_0, v0x62b7183e52a0_0, v0x62b7183bb8b0_0, v0x62b7183e3aa0_0; +E_0x62b7183c32f0/1 .event edge, v0x62b7183e5000_0, v0x62b7183e50e0_0, v0x62b7183e51c0_0, v0x62b7183e4d60_0; +E_0x62b7183c32f0/2 .event edge, v0x62b7183e4e40_0, v0x62b7183e4f20_0; +E_0x62b7183c32f0 .event/or E_0x62b7183c32f0/0, E_0x62b7183c32f0/1, E_0x62b7183c32f0/2; +L_0x62b7183fce10 .part v0x62b7183e5000_0, 1, 1; +L_0x62b7183fcf00 .part v0x62b7183e5000_0, 1, 1; +L_0x62b7183fd230 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f0a8; +L_0x62b7183fd350 .cmp/gt 32, L_0x7feda344f0f0, L_0x62b7183fd230; +L_0x62b7183fd4c0 .concat [ 12 20 0 0], v0x62b7183e5860_0, L_0x7feda344f138; +L_0x62b7183fd600 .cmp/gt 32, L_0x7feda344f180, L_0x62b7183fd4c0; +L_0x62b7183fd890 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f1c8; +L_0x62b7183fd9d0 .cmp/ge 32, L_0x62b7183fd890, L_0x7feda344f210; +L_0x62b7183fdb60 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f258; +L_0x62b7183fdc50 .cmp/gt 32, L_0x7feda344f2a0, L_0x62b7183fdb60; +L_0x62b7183fdea0 .concat [ 12 20 0 0], v0x62b7183e5860_0, L_0x7feda344f2e8; +L_0x62b7183fdfe0 .cmp/ge 32, L_0x62b7183fdea0, L_0x7feda344f330; +L_0x62b7183fe190 .concat [ 12 20 0 0], v0x62b7183e5860_0, L_0x7feda344f378; +L_0x62b7183fe280 .cmp/gt 32, L_0x7feda344f3c0, L_0x62b7183fe190; +L_0x62b7183fe4e0 .array/port v0x62b7183e4ae0, L_0x62b7183fe6b0; +L_0x62b7183fe580 .part v0x62b7183e4ba0_0, 16, 8; +L_0x62b7183fe6b0 .concat [ 8 2 0 0], L_0x62b7183fe580, L_0x7feda344f408; +L_0x62b7183fe950 .array/port v0x62b7183e4ae0, L_0x62b7183feb80; +L_0x62b7183fea90 .part v0x62b7183e4ba0_0, 8, 8; +L_0x62b7183feb80 .concat [ 8 2 0 0], L_0x62b7183fea90, L_0x7feda344f450; +L_0x62b7183fe9f0 .array/port v0x62b7183e4ae0, L_0x62b7183fefe0; +L_0x62b7183fee80 .part v0x62b7183e4ba0_0, 0, 8; +L_0x62b7183fefe0 .concat [ 8 2 0 0], L_0x62b7183fee80, L_0x7feda344f498; +L_0x62b7183ff290 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f4e0; +L_0x62b7183ff400 .cmp/gt 32, L_0x7feda344f528, L_0x62b7183ff290; +L_0x62b7183ff4f0 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f570; +L_0x62b7183ff6c0 .arith/mult 32, L_0x62b7183ff4f0, L_0x7feda344f5b8; +L_0x62b7183ff830 .arith/div 32, L_0x62b7183ff6c0, L_0x7feda344f600; +L_0x62b7183ffa60 .functor MUXZ 32, L_0x7feda344f648, L_0x62b7183ff830, L_0x62b7183ff400, C4<>; +L_0x62b7183ffbf0 .part L_0x62b7183ffa60, 0, 8; +L_0x62b7183ffde0 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f690; +L_0x62b7183ffed0 .cmp/gt 32, L_0x7feda344f6d8, L_0x62b7183ffde0; +L_0x62b718400120 .concat [ 12 20 0 0], v0x62b7183e5860_0, L_0x7feda344f720; +L_0x62b7184001c0 .cmp/gt 32, L_0x7feda344f768, L_0x62b718400120; +L_0x62b718400560 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f7b0; +L_0x62b718400650 .arith/mod 32, L_0x62b718400560, L_0x7feda344f7f8; +L_0x62b718400330 .cmp/eq 32, L_0x62b718400650, L_0x7feda344f840; +L_0x62b718400910 .concat [ 12 20 0 0], v0x62b7183e5860_0, L_0x7feda344f888; +L_0x62b718400b40 .arith/mod 32, L_0x62b718400910, L_0x7feda344f8d0; +L_0x62b718400e90 .cmp/eq 32, L_0x62b718400b40, L_0x7feda344f918; +L_0x62b7184013b0 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344f960; +L_0x62b7184014a0 .cmp/gt 32, L_0x7feda344f9a8, L_0x62b7184013b0; +L_0x62b718401740 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344fa38; +L_0x62b718401830 .cmp/gt 32, L_0x7feda344fa80, L_0x62b718401740; +L_0x62b718401b10 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344fb10; +L_0x62b718401c30 .cmp/gt 32, L_0x7feda344fb58, L_0x62b718401b10; +L_0x62b718401f20 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344fbe8; +L_0x62b718402040 .cmp/gt 32, L_0x7feda344fc30, L_0x62b718401f20; +L_0x62b718402340 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344fcc0; +L_0x62b718402460 .cmp/gt 32, L_0x7feda344fd08, L_0x62b718402340; +L_0x62b718402770 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344fd98; +L_0x62b718402890 .cmp/gt 32, L_0x7feda344fde0, L_0x62b718402770; +L_0x62b718402bb0 .concat [ 12 20 0 0], v0x62b7183e4560_0, L_0x7feda344fe70; +L_0x62b718402cd0 .cmp/gt 32, L_0x7feda344feb8, L_0x62b718402bb0; +L_0x62b718403000 .functor MUXZ 3, L_0x7feda344ff48, L_0x7feda344ff00, L_0x62b718402cd0, C4<>; +L_0x62b7184031c0 .functor MUXZ 3, L_0x62b718403000, L_0x7feda344fe28, L_0x62b718402890, C4<>; +L_0x62b718403520 .functor MUXZ 3, L_0x62b7184031c0, L_0x7feda344fd50, L_0x62b718402460, C4<>; +L_0x62b7184036b0 .functor MUXZ 3, L_0x62b718403520, L_0x7feda344fc78, L_0x62b718402040, C4<>; +L_0x62b718403a20 .functor MUXZ 3, L_0x62b7184036b0, L_0x7feda344fba0, L_0x62b718401c30, C4<>; +L_0x62b718403bb0 .functor MUXZ 3, L_0x62b718403a20, L_0x7feda344fac8, L_0x62b718401830, C4<>; +L_0x62b718403f30 .functor MUXZ 3, L_0x62b718403bb0, L_0x7feda344f9f0, L_0x62b7184014a0, C4<>; +L_0x62b7184040c0 .concat [ 5 3 0 0], L_0x7feda344ff90, L_0x62b718403f30; +L_0x62b718404400 .part v0x62b7183e5860_0, 2, 4; +L_0x62b7184044a0 .part v0x62b7183e4560_0, 2, 4; +L_0x62b718404750 .array/port v0x62b7183e3230, L_0x62b7184047f0; +L_0x62b7184047f0 .concat [ 4 2 0 0], L_0x62b718404400, L_0x7feda344ffd8; +L_0x62b718404ce0 .concat [ 4 28 0 0], L_0x62b7184044a0, L_0x7feda3450068; +L_0x62b718404e20 .arith/sub 32, L_0x7feda3450020, L_0x62b718404ce0; +L_0x62b718405190 .part/v L_0x62b718404ba0, L_0x62b718404e20, 1; +L_0x62b7184052d0 .part v0x62b7183e4560_0, 0, 8; +L_0x62b7184055b0 .part v0x62b7183e5860_0, 0, 8; +L_0x62b718405650 .arith/sum 8, L_0x62b7184052d0, L_0x62b7184055b0; +L_0x62b7184059e0 .part v0x62b7183e4560_0, 2, 8; +L_0x62b718405a80 .part v0x62b7183e5860_0, 2, 8; +L_0x62b718405d80 .concat [ 8 8 8 0], L_0x62b718405a80, L_0x62b7184059e0, L_0x62b718405650; +L_0x62b718405f10 .functor MUXZ 24, L_0x7feda34500b0, L_0x62b718405d80, L_0x62b718405190, C4<>; +L_0x62b718406310 .concat [ 12 20 0 0], v0x62b7183e5860_0, L_0x7feda34500f8; +L_0x62b718406400 .cmp/gt 32, L_0x7feda3450140, L_0x62b718406310; +L_0x62b718406860 .part v0x62b7183e52a0_0, 0, 4; +L_0x62b718406950 .cmp/eq 4, L_0x62b718406860, L_0x7feda3450188; +S_0x62b7183e60c0 .scope module, "u_simple_fifo" "simple_dcfifo" 3 139, 6 3 0, S_0x62b7183aa800; + .timescale -9 -12; + .port_info 0 /INPUT 1 "wrclk"; + .port_info 1 /INPUT 32 "data"; + .port_info 2 /INPUT 1 "wrreq"; + .port_info 3 /OUTPUT 9 "wrusedw"; + .port_info 4 /OUTPUT 1 "wrfull"; + .port_info 5 /INPUT 1 "rdclk"; + .port_info 6 /INPUT 1 "rdreq"; + .port_info 7 /OUTPUT 32 "q"; + .port_info 8 /OUTPUT 1 "rdempty"; +P_0x62b7183254d0 .param/l "ADDR_WIDTH" 0 6 5, +C4<00000000000000000000000000001001>; +P_0x62b718325510 .param/l "DATA_WIDTH" 0 6 4, +C4<00000000000000000000000000100000>; +L_0x62b7182dccf0 .functor NOT 2, L_0x62b7183ec340, C4<00>, C4<00>, C4<00>; +v0x62b7183e6d80_0 .net *"_ivl_15", 0 0, L_0x62b7183ec940; 1 drivers +L_0x7feda344f060 .functor BUFT 1, C4<111111111>, C4<0>, C4<0>, C4<0>; +v0x62b7183e6e80_0 .net/2u *"_ivl_16", 8 0, L_0x7feda344f060; 1 drivers +v0x62b7183e6f60_0 .net *"_ivl_19", 8 0, L_0x62b7183fca40; 1 drivers +v0x62b7183e7050_0 .net *"_ivl_3", 1 0, L_0x62b7183ec340; 1 drivers +v0x62b7183e7130_0 .net *"_ivl_4", 1 0, L_0x62b7182dccf0; 1 drivers +v0x62b7183e7260_0 .net *"_ivl_7", 7 0, L_0x62b7183ec480; 1 drivers +v0x62b7183e7340_0 .net *"_ivl_8", 9 0, L_0x62b7183ec520; 1 drivers +v0x62b7183e7420_0 .net "data", 31 0, L_0x62b718380e30; alias, 1 drivers +v0x62b7183e74e0 .array "mem", 0 511, 31 0; +v0x62b7183e7580_0 .var "q", 31 0; +v0x62b7183e7660_0 .var "rd_ptr_bin", 9 0; +v0x62b7183e7740_0 .net "rd_ptr_bin_sync", 9 0, L_0x62b7183ec2a0; 1 drivers +v0x62b7183e7820_0 .var "rd_ptr_gray", 9 0; +v0x62b7183e7900_0 .var "rd_ptr_gray_sync1", 9 0; +v0x62b7183e79e0_0 .var "rd_ptr_gray_sync2", 9 0; +v0x62b7183e7ac0_0 .net "rdclk", 0 0, o0x7feda349a298; alias, 0 drivers +v0x62b7183e7b90_0 .net "rdempty", 0 0, L_0x62b7183fccc0; alias, 1 drivers +v0x62b7183e7c30_0 .net "rdreq", 0 0, L_0x62b718406d20; alias, 1 drivers +v0x62b7183e7d00_0 .net "used_diff", 9 0, L_0x62b7183ec7a0; 1 drivers +v0x62b7183e7dc0_0 .var "wr_ptr_bin", 9 0; +v0x62b7183e7ea0_0 .var "wr_ptr_gray", 9 0; +v0x62b7183e7f80_0 .var "wr_ptr_gray_sync1", 9 0; +v0x62b7183e8060_0 .var "wr_ptr_gray_sync2", 9 0; +v0x62b7183e8140_0 .net "wrclk", 0 0, o0x7feda3498048; alias, 0 drivers +v0x62b7183e81e0_0 .net "wrfull", 0 0, L_0x62b7183ec660; alias, 1 drivers +v0x62b7183e82a0_0 .net "wrreq", 0 0, L_0x62b7183bd210; alias, 1 drivers +v0x62b7183e8340_0 .net "wrusedw", 8 0, L_0x62b7183fcb30; alias, 1 drivers +E_0x62b7183c36c0 .event posedge, v0x62b7183e36f0_0; +E_0x62b7183c38f0 .event posedge, v0x62b7183bdf40_0; +L_0x62b7183ec2a0 .ufunc/vec4 TD_video_pipeline.u_simple_fifo.gray2bin, 10, v0x62b7183e79e0_0 (v0x62b7183e6ad0_0) S_0x62b7183e68d0; +L_0x62b7183ec340 .part v0x62b7183e79e0_0, 8, 2; +L_0x62b7183ec480 .part v0x62b7183e79e0_0, 0, 8; +L_0x62b7183ec520 .concat [ 8 2 0 0], L_0x62b7183ec480, L_0x62b7182dccf0; +L_0x62b7183ec660 .cmp/eq 10, v0x62b7183e7ea0_0, L_0x62b7183ec520; +L_0x62b7183ec7a0 .arith/sub 10, v0x62b7183e7dc0_0, L_0x62b7183ec2a0; +L_0x62b7183ec940 .part L_0x62b7183ec7a0, 9, 1; +L_0x62b7183fca40 .part L_0x62b7183ec7a0, 0, 9; +L_0x62b7183fcb30 .functor MUXZ 9, L_0x62b7183fca40, L_0x7feda344f060, L_0x62b7183ec940, C4<>; +L_0x62b7183fccc0 .cmp/eq 10, v0x62b7183e7820_0, v0x62b7183e8060_0; +S_0x62b7183e64f0 .scope function.vec4.s10, "bin2gray" "bin2gray" 6 52, 6 52 0, S_0x62b7183e60c0; + .timescale -9 -12; +v0x62b7183e66f0_0 .var "bin", 9 0; +; Variable bin2gray is vec4 return value of scope S_0x62b7183e64f0 +TD_video_pipeline.u_simple_fifo.bin2gray ; + %load/vec4 v0x62b7183e66f0_0; + %load/vec4 v0x62b7183e66f0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %xor; + %ret/vec4 0, 0, 10; Assign to bin2gray (store_vec4_to_lval) + %end; +S_0x62b7183e68d0 .scope function.vec4.s10, "gray2bin" "gray2bin" 6 59, 6 59 0, S_0x62b7183e60c0; + .timescale -9 -12; +v0x62b7183e6ad0_0 .var "gray", 9 0; +; Variable gray2bin is vec4 return value of scope S_0x62b7183e68d0 +v0x62b7183e6c90_0 .var/i "i", 31 0; +TD_video_pipeline.u_simple_fifo.gray2bin ; + %load/vec4 v0x62b7183e6ad0_0; + %parti/s 1, 9, 5; + %ix/load 4, 9, 0; + %flag_set/imm 4, 0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %pushi/vec4 8, 0, 32; + %store/vec4 v0x62b7183e6c90_0, 0, 32; +T_1.0 ; + %load/vec4 v0x62b7183e6c90_0; + %cmpi/s 0, 0, 32; + %flag_inv 5; GE is !LT + %jmp/0xz T_1.1, 5; + %retload/vec4 0; Load gray2bin (draw_signal_vec4) + %load/vec4 v0x62b7183e6c90_0; + %addi 1, 0, 32; + %part/s 1; + %load/vec4 v0x62b7183e6ad0_0; + %load/vec4 v0x62b7183e6c90_0; + %part/s 1; + %xor; + %ix/getv/s 4, v0x62b7183e6c90_0; + %ret/vec4 0, 4, 1; Assign to gray2bin (store_vec4_to_lval) + %load/vec4 v0x62b7183e6c90_0; + %subi 1, 0, 32; + %store/vec4 v0x62b7183e6c90_0, 0, 32; + %jmp T_1.0; +T_1.1 ; + %end; + .scope S_0x62b71838b510; +T_2 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183d9930_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x62b7183d9ad0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183d9260_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d9420_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183bdfe0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183d9c70_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d91a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d90e0_0, 0; + %pushi/vec4 0, 0, 10; + %assign/vec4 v0x62b7183d9850_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x62b7183d9ad0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_2.2, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_2.3, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_2.4, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_2.5, 6; + %jmp T_2.6; +T_2.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d9420_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183d9c70_0, 0; + %load/vec4 v0x62b718381c40_0; + %flag_set/vec4 8; + %jmp/0xz T_2.7, 8; + %load/vec4 v0x62b7183d99f0_0; + %assign/vec4 v0x62b7183bdfe0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d91a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183d90e0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x62b7183d9ad0_0, 0; + %jmp T_2.8; +T_2.7 ; + %load/vec4 v0x62b718380f90_0; + %load/vec4 v0x62b7183d9bb0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.9, 8; + %load/vec4 v0x62b7183d99f0_0; + %assign/vec4 v0x62b7183bdfe0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183d91a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183d90e0_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x62b7183d9ad0_0, 0; + %jmp T_2.10; +T_2.9 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d90e0_0, 0; +T_2.10 ; +T_2.8 ; + %jmp T_2.6; +T_2.3 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d9420_0, 0; + %load/vec4 v0x62b7183d9c70_0; + %pad/u 64; + %cmpi/u 518400, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_2.11, 5; + %pushi/vec4 3, 0, 2; + %assign/vec4 v0x62b7183d9ad0_0, 0; + %jmp T_2.12; +T_2.11 ; + %load/vec4 v0x62b718381d10_0; + %pad/u 32; + %load/vec4 v0x62b7183d9c70_0; + %load/vec4 v0x62b7183d9d50_0; + %sub; + %add; + %cmpi/u 446, 0, 32; + %flag_or 5, 4; + %jmp/0xz T_2.13, 5; + %load/vec4 v0x62b7183bdfe0_0; + %assign/vec4 v0x62b7183d9260_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183d9420_0, 0; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x62b7183d9ad0_0, 0; +T_2.13 ; +T_2.12 ; + %jmp T_2.6; +T_2.4 ; + %load/vec4 v0x62b7183d9680_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.15, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d9420_0, 0; + %load/vec4 v0x62b7183bdfe0_0; + %addi 256, 0, 32; + %assign/vec4 v0x62b7183bdfe0_0, 0; + %load/vec4 v0x62b7183d9c70_0; + %addi 64, 0, 32; + %assign/vec4 v0x62b7183d9c70_0, 0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x62b7183d9ad0_0, 0; +T_2.15 ; + %jmp T_2.6; +T_2.5 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d9420_0, 0; + %load/vec4 v0x62b7183d9d50_0; + %pad/u 64; + %cmpi/u 518400, 0, 64; + %flag_inv 5; GE is !LT + %jmp/0xz T_2.17, 5; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x62b7183d9ad0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d90e0_0, 0; +T_2.17 ; + %jmp T_2.6; +T_2.6 ; + %pop/vec4 1; + %load/vec4 v0x62b7183d91a0_0; + %load/vec4 v0x62b718380f90_0; + %nor/r; + %and; + %load/vec4 v0x62b7183d9ad0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.19, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183d91a0_0, 0; +T_2.19 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x62b71838b510; +T_3 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183d9930_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183d9d50_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0x62b7183d9ad0_0; + %pushi/vec4 0, 0, 2; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x62b718381c40_0; + %load/vec4 v0x62b718380f90_0; + %load/vec4 v0x62b7183d9bb0_0; + %and; + %or; + %and; + %flag_set/vec4 8; + %jmp/0xz T_3.2, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183d9d50_0, 0; +T_3.2 ; + %load/vec4 v0x62b7183d95c0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.4, 8; + %load/vec4 v0x62b7183d9d50_0; + %addi 1, 0, 32; + %assign/vec4 v0x62b7183d9d50_0, 0; +T_3.4 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x62b71838b510; +T_4 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183d9930_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b718381060_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x62b7183d95c0_0; + %load/vec4 v0x62b7183d9d50_0; + %pad/u 64; + %pushi/vec4 518399, 0, 64; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b718381060_0, 0; + %jmp T_4.3; +T_4.2 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b718381060_0, 0; +T_4.3 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x62b7183e60c0; +T_5 ; + %wait E_0x62b7183c38f0; + %load/vec4 v0x62b7183e7820_0; + %assign/vec4 v0x62b7183e7900_0, 0; + %load/vec4 v0x62b7183e7900_0; + %assign/vec4 v0x62b7183e79e0_0, 0; + %jmp T_5; + .thread T_5; + .scope S_0x62b7183e60c0; +T_6 ; + %wait E_0x62b7183c36c0; + %load/vec4 v0x62b7183e7ea0_0; + %assign/vec4 v0x62b7183e7f80_0, 0; + %load/vec4 v0x62b7183e7f80_0; + %assign/vec4 v0x62b7183e8060_0, 0; + %jmp T_6; + .thread T_6; + .scope S_0x62b7183e60c0; +T_7 ; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e7dc0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e7ea0_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e7660_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e7820_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e7f80_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e8060_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e7900_0, 0, 10; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x62b7183e79e0_0, 0, 10; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x62b7183e7580_0, 0, 32; + %end; + .thread T_7; + .scope S_0x62b7183e60c0; +T_8 ; + %wait E_0x62b7183c38f0; + %load/vec4 v0x62b7183e82a0_0; + %load/vec4 v0x62b7183e81e0_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x62b7183e7420_0; + %load/vec4 v0x62b7183e7dc0_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e74e0, 0, 4; + %load/vec4 v0x62b7183e7dc0_0; + %addi 1, 0, 10; + %assign/vec4 v0x62b7183e7dc0_0, 0; + %load/vec4 v0x62b7183e7dc0_0; + %addi 1, 0, 10; + %store/vec4 v0x62b7183e66f0_0, 0, 10; + %callf/vec4 TD_video_pipeline.u_simple_fifo.bin2gray, S_0x62b7183e64f0; + %assign/vec4 v0x62b7183e7ea0_0, 0; +T_8.0 ; + %jmp T_8; + .thread T_8; + .scope S_0x62b7183e60c0; +T_9 ; + %wait E_0x62b7183c36c0; + %load/vec4 v0x62b7183e7c30_0; + %load/vec4 v0x62b7183e7b90_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %load/vec4 v0x62b7183e7660_0; + %parti/s 9, 0, 2; + %pad/u 11; + %ix/vec4 4; + %load/vec4a v0x62b7183e74e0, 4; + %assign/vec4 v0x62b7183e7580_0, 0; + %load/vec4 v0x62b7183e7660_0; + %addi 1, 0, 10; + %assign/vec4 v0x62b7183e7660_0, 0; + %load/vec4 v0x62b7183e7660_0; + %addi 1, 0, 10; + %store/vec4 v0x62b7183e66f0_0, 0, 10; + %callf/vec4 TD_video_pipeline.u_simple_fifo.bin2gray, S_0x62b7183e64f0; + %assign/vec4 v0x62b7183e7820_0, 0; +T_9.0 ; + %jmp T_9; + .thread T_9; + .scope S_0x62b7183da050; +T_10 ; + %pushi/vec4 0, 0, 12; + %store/vec4 v0x62b7183e4560_0, 0, 12; + %pushi/vec4 0, 0, 12; + %store/vec4 v0x62b7183e5860_0, 0, 12; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x62b7183e5a00_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x62b7183e4960_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x62b7183e5ac0_0, 0, 1; + %pushi/vec4 0, 0, 24; + %store/vec4 v0x62b7183e4640_0, 0, 24; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x62b7183e4720_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x62b7183e47e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x62b7183e48a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x62b7183e5c60_0, 0, 1; + %end; + .thread T_10; + .scope S_0x62b7183da050; +T_11 ; + %wait E_0x62b7183c32f0; + %load/vec4 v0x62b7183e2c70_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_11.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_11.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_11.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_11.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_11.6, 6; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.0 ; + %load/vec4 v0x62b7183e52a0_0; + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.1 ; + %load/vec4 v0x62b7183e3870_0; + %load/vec4 v0x62b7183e3aa0_0; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 28; + %load/vec4 v0x62b7183e5000_0; + %parti/s 1, 1, 2; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x62b7183e5000_0; + %parti/s 1, 0, 2; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.2 ; + %load/vec4 v0x62b7183e50e0_0; + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.3 ; + %load/vec4 v0x62b7183e51c0_0; + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.4 ; + %load/vec4 v0x62b7183e4d60_0; + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.5 ; + %load/vec4 v0x62b7183e4e40_0; + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.6 ; + %load/vec4 v0x62b7183e4f20_0; + %store/vec4 v0x62b7183e4c80_0, 0, 32; + %jmp T_11.8; +T_11.8 ; + %pop/vec4 1; + %jmp T_11; + .thread T_11, $push; + .scope S_0x62b7183da050; +T_12 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183e5460_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183e52a0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183e5000_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183e50e0_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x62b7183e51c0_0, 0; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x62b7183e4f20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e2ef0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e3ce0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e3aa0_0, 0; + %pushi/vec4 0, 0, 16; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 4, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 5, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 6, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 7, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 8, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 9, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 10, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 11, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 12, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 13, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 14, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %pushi/vec4 0, 0, 16; + %ix/load 3, 15, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %jmp T_12.1; +T_12.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e3ce0_0, 0; + %load/vec4 v0x62b7183e39e0_0; + %flag_set/vec4 8; + %jmp/0xz T_12.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183e3aa0_0, 0; +T_12.2 ; + %load/vec4 v0x62b7183e2fb0_0; + %flag_set/vec4 8; + %jmp/0xz T_12.4, 8; + %load/vec4 v0x62b7183e2c70_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_12.6, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_12.7, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_12.8, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_12.9, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_12.10, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_12.11, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_12.12, 6; + %jmp T_12.14; +T_12.6 ; + %load/vec4 v0x62b7183e3070_0; + %assign/vec4 v0x62b7183e52a0_0, 0; + %jmp T_12.14; +T_12.7 ; + %load/vec4 v0x62b7183e3070_0; + %parti/s 2, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x62b7183e5000_0, 4, 5; + %load/vec4 v0x62b7183e3070_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_12.15, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183e3ce0_0, 0; +T_12.15 ; + %load/vec4 v0x62b7183e3070_0; + %parti/s 1, 30, 6; + %flag_set/vec4 8; + %jmp/0xz T_12.17, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e3aa0_0, 0; +T_12.17 ; + %jmp T_12.14; +T_12.8 ; + %load/vec4 v0x62b7183e3070_0; + %assign/vec4 v0x62b7183e50e0_0, 0; + %jmp T_12.14; +T_12.9 ; + %load/vec4 v0x62b7183e3070_0; + %assign/vec4 v0x62b7183e51c0_0, 0; + %load/vec4 v0x62b7183e3070_0; + %parti/s 8, 0, 2; + %load/vec4 v0x62b7183e50e0_0; + %parti/s 8, 0, 2; + %pad/u 10; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e4ae0, 0, 4; + %jmp T_12.14; +T_12.10 ; + %load/vec4 v0x62b7183e3070_0; + %assign/vec4 v0x62b7183e4d60_0, 0; + %jmp T_12.14; +T_12.11 ; + %load/vec4 v0x62b7183e3070_0; + %assign/vec4 v0x62b7183e4e40_0, 0; + %load/vec4 v0x62b7183e3070_0; + %parti/s 16, 0, 2; + %load/vec4 v0x62b7183e4d60_0; + %parti/s 4, 0, 2; + %pad/u 6; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x62b7183e3230, 0, 4; + %jmp T_12.14; +T_12.12 ; + %load/vec4 v0x62b7183e3070_0; + %assign/vec4 v0x62b7183e4f20_0, 0; + %jmp T_12.14; +T_12.14 ; + %pop/vec4 1; +T_12.4 ; + %load/vec4 v0x62b7183e2d50_0; + %assign/vec4 v0x62b7183e2ef0_0, 0; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x62b7183da050; +T_13 ; + %wait E_0x62b718301390; + %load/vec4 v0x62b7183e5460_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_13.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x62b7183e4560_0, 0; + %jmp T_13.1; +T_13.0 ; + %load/vec4 v0x62b7183e4560_0; + %pad/u 32; + %cmpi/e 1119, 0, 32; + %jmp/0xz T_13.2, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x62b7183e4560_0, 0; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0x62b7183e4560_0; + %addi 1, 0, 12; + %assign/vec4 v0x62b7183e4560_0, 0; +T_13.3 ; +T_13.1 ; + %jmp T_13; + .thread T_13; + .scope S_0x62b7183da050; +T_14 ; + %wait E_0x62b718301390; + %load/vec4 v0x62b7183e5460_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x62b7183e5860_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v0x62b7183e4560_0; + %pad/u 32; + %cmpi/e 1119, 0, 32; + %jmp/0xz T_14.2, 4; + %load/vec4 v0x62b7183e5860_0; + %pad/u 32; + %cmpi/e 562, 0, 32; + %jmp/0xz T_14.4, 4; + %pushi/vec4 0, 0, 12; + %assign/vec4 v0x62b7183e5860_0, 0; + %jmp T_14.5; +T_14.4 ; + %load/vec4 v0x62b7183e5860_0; + %addi 1, 0, 12; + %assign/vec4 v0x62b7183e5860_0, 0; +T_14.5 ; +T_14.2 ; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x62b7183da050; +T_15 ; + %wait E_0x62b718301390; + %load/vec4 v0x62b7183e5460_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_15.0, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183e47e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183e48a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e4720_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e5a00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183e4960_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x62b7183e5ac0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e5c60_0, 0; + %jmp T_15.1; +T_15.0 ; + %load/vec4 v0x62b7183e5940_0; + %assign/vec4 v0x62b7183e5a00_0, 0; + %load/vec4 v0x62b7183e4a20_0; + %assign/vec4 v0x62b7183e4960_0, 0; + %load/vec4 v0x62b7183e5d20_0; + %assign/vec4 v0x62b7183e5ac0_0, 0; + %load/vec4 v0x62b7183e4960_0; + %assign/vec4 v0x62b7183e47e0_0, 0; + %load/vec4 v0x62b7183e5ac0_0; + %assign/vec4 v0x62b7183e48a0_0, 0; + %load/vec4 v0x62b7183e5a00_0; + %assign/vec4 v0x62b7183e4720_0, 0; + %load/vec4 v0x62b7183e5d20_0; + %load/vec4 v0x62b7183e5ac0_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_15.2, 8; + %load/vec4 v0x62b7183e5c60_0; + %inv; + %assign/vec4 v0x62b7183e5c60_0, 0; +T_15.2 ; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_0x62b7183da050; +T_16 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183e5460_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_16.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x62b7183e5b80_0, 0; + %pushi/vec4 805306368, 0, 32; + %assign/vec4 v0x62b7183e5530_0, 0; + %jmp T_16.1; +T_16.0 ; + %load/vec4 v0x62b7183e5b80_0; + %parti/s 2, 0, 2; + %load/vec4 v0x62b7183e5d20_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x62b7183e5b80_0, 0; + %load/vec4 v0x62b7183e5b80_0; + %parti/s 1, 1, 2; + %load/vec4 v0x62b7183e5b80_0; + %parti/s 1, 2, 3; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_16.2, 8; + %load/vec4 v0x62b7183e4f20_0; + %assign/vec4 v0x62b7183e5530_0, 0; +T_16.2 ; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_0x62b7183da050; +T_17 ; + %wait E_0x62b71834f690; + %load/vec4 v0x62b7183e52a0_0; + %parti/s 4, 0, 2; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_17.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_17.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_17.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_17.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_17.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_17.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_17.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_17.7, 6; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.0 ; + %pushi/vec4 16711680, 0, 24; + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.1 ; + %pushi/vec4 65280, 0, 24; + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.2 ; + %pushi/vec4 255, 0, 24; + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.3 ; + %load/vec4 v0x62b7183e42e0_0; + %load/vec4 v0x62b7183e42e0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x62b7183e42e0_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.4 ; + %load/vec4 v0x62b7183e44a0_0; + %flag_set/vec4 8; + %jmp/0 T_17.10, 8; + %pushi/vec4 16777215, 0, 24; + %jmp/1 T_17.11, 8; +T_17.10 ; End of true expr. + %pushi/vec4 0, 0, 24; + %jmp/0 T_17.11, 8; + ; End of false expr. + %blend; +T_17.11; + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.5 ; + %pushi/vec4 16777215, 0, 24; + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.6 ; + %load/vec4 v0x62b7183e43c0_0; + %load/vec4 v0x62b7183e43c0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x62b7183e43c0_0; + %concat/vec4; draw_concat_vec4 + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.7 ; + %load/vec4 v0x62b7183e33d0_0; + %store/vec4 v0x62b7183e4ba0_0, 0, 24; + %jmp T_17.9; +T_17.9 ; + %pop/vec4 1; + %jmp T_17; + .thread T_17, $push; + .scope S_0x62b7183da050; +T_18 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183e5460_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_18.0, 8; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x62b7183e4640_0, 0; + %jmp T_18.1; +T_18.0 ; + %load/vec4 v0x62b7183e5a00_0; + %flag_set/vec4 8; + %jmp/0xz T_18.2, 8; + %load/vec4 v0x62b7183e5000_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_18.4, 8; + %load/vec4 v0x62b7183e4200_0; + %load/vec4 v0x62b7183e4120_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x62b7183e4040_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x62b7183e4640_0, 0; + %jmp T_18.5; +T_18.4 ; + %load/vec4 v0x62b7183e52a0_0; + %parti/s 4, 0, 2; + %cmpi/e 8, 0, 4; + %jmp/0xz T_18.6, 4; + %load/vec4 v0x62b7183e56e0_0; + %assign/vec4 v0x62b7183e4640_0, 0; + %jmp T_18.7; +T_18.6 ; + %load/vec4 v0x62b7183e4ba0_0; + %assign/vec4 v0x62b7183e4640_0, 0; +T_18.7 ; +T_18.5 ; + %jmp T_18.3; +T_18.2 ; + %pushi/vec4 0, 0, 24; + %assign/vec4 v0x62b7183e4640_0, 0; +T_18.3 ; +T_18.1 ; + %jmp T_18; + .thread T_18; + .scope S_0x62b7183aa800; +T_19 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183ead90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_19.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x62b7183eb590_0, 0; + %jmp T_19.1; +T_19.0 ; + %load/vec4 v0x62b7183eb590_0; + %parti/s 2, 0, 2; + %load/vec4 v0x62b7183eb420_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x62b7183eb590_0, 0; +T_19.1 ; + %jmp T_19; + .thread T_19; + .scope S_0x62b7183aa800; +T_20 ; + %wait E_0x62b718301390; + %load/vec4 v0x62b7183ead90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_20.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e9e50_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e9c40_0, 0; + %jmp T_20.1; +T_20.0 ; + %load/vec4 v0x62b7183e9b70_0; + %assign/vec4 v0x62b7183e9c40_0, 0; + %load/vec4 v0x62b7183e9b70_0; + %load/vec4 v0x62b7183e9c40_0; + %nor/r; + %and; + %flag_set/vec4 8; + %jmp/0xz T_20.2, 8; + %load/vec4 v0x62b7183e9e50_0; + %inv; + %assign/vec4 v0x62b7183e9e50_0, 0; +T_20.2 ; +T_20.1 ; + %jmp T_20; + .thread T_20; + .scope S_0x62b7183aa800; +T_21 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183ead90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_21.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x62b7183e9db0_0, 0; + %jmp T_21.1; +T_21.0 ; + %load/vec4 v0x62b7183e9db0_0; + %parti/s 2, 0, 2; + %load/vec4 v0x62b7183e9e50_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x62b7183e9db0_0, 0; +T_21.1 ; + %jmp T_21; + .thread T_21; + .scope S_0x62b7183aa800; +T_22 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183ead90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_22.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x62b7183e9730_0, 0; + %jmp T_22.1; +T_22.0 ; + %load/vec4 v0x62b7183e9730_0; + %parti/s 2, 0, 2; + %load/vec4 v0x62b7183e95f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x62b7183e9730_0, 0; +T_22.1 ; + %jmp T_22; + .thread T_22; + .scope S_0x62b7183aa800; +T_23 ; + %wait E_0x62b71833acf0; + %load/vec4 v0x62b7183ead90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_23.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x62b7183e99e0_0, 0; + %jmp T_23.1; +T_23.0 ; + %load/vec4 v0x62b7183e97d0_0; + %flag_set/vec4 8; + %jmp/0xz T_23.2, 8; + %load/vec4 v0x62b7183e99e0_0; + %inv; + %assign/vec4 v0x62b7183e99e0_0, 0; +T_23.2 ; +T_23.1 ; + %jmp T_23; + .thread T_23; + .scope S_0x62b7183aa800; +T_24 ; + %wait E_0x62b718301390; + %load/vec4 v0x62b7183ead90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_24.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x62b7183e9940_0, 0; + %jmp T_24.1; +T_24.0 ; + %load/vec4 v0x62b7183e9940_0; + %parti/s 2, 0, 2; + %load/vec4 v0x62b7183e99e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x62b7183e9940_0, 0; +T_24.1 ; + %jmp T_24; + .thread T_24; +# The file index is used to find the file name in the following table. +:file_names 7; + "N/A"; + ""; + "-"; + "/mnt/c/Workspace/quartus/video_processing/RTL/video_pipeline.v"; + "/mnt/c/Workspace/quartus/video_processing/RTL/video_dma_master.v"; + "/mnt/c/Workspace/quartus/video_processing/RTL/hdmi_sync_gen.v"; + "/mnt/c/Workspace/quartus/video_processing/RTL/simple_dcfifo.v"; diff --git a/tests/test_dma_master.py b/tests/test_dma_master.py new file mode 100644 index 0000000..cadd7c3 --- /dev/null +++ b/tests/test_dma_master.py @@ -0,0 +1,24 @@ +import os +import sys +from cocotb_test.simulator import run + +def test_dma_master(): + tests_dir = os.path.dirname(os.path.abspath(__file__)) + proj_dir = os.path.dirname(tests_dir) + rtl_dir = os.path.join(proj_dir, "RTL") + + run( + verilog_sources=[ + os.path.join(rtl_dir, "video_dma_master.v") + ], + toplevel="video_dma_master", + module="tb_dma_master", + python_search=[ + os.path.join(tests_dir, "cocotb") + ], + sim="iverilog", + force_compile=True + ) + +if __name__ == "__main__": + test_dma_master() diff --git a/tests/test_fifo.py b/tests/test_fifo.py new file mode 100644 index 0000000..9443b2c --- /dev/null +++ b/tests/test_fifo.py @@ -0,0 +1,24 @@ +import os +import sys +from cocotb_test.simulator import run + +def test_fifo(): + tests_dir = os.path.dirname(os.path.abspath(__file__)) + proj_dir = os.path.dirname(tests_dir) + rtl_dir = os.path.join(proj_dir, "RTL") + + run( + verilog_sources=[ + os.path.join(rtl_dir, "simple_dcfifo.v") + ], + toplevel="simple_dcfifo", + module="tb_fifo", + python_search=[ + os.path.join(tests_dir, "cocotb") + ], + sim="iverilog", + force_compile=True + ) + +if __name__ == "__main__": + test_fifo() diff --git a/tests/test_hdmi_pipeline.py b/tests/test_hdmi_pipeline.py new file mode 100644 index 0000000..7664d56 --- /dev/null +++ b/tests/test_hdmi_pipeline.py @@ -0,0 +1,23 @@ +import os +import sys +from cocotb_test.simulator import run + +def test_hdmi_sync_gen(): + tests_dir = os.path.dirname(os.path.abspath(__file__)) + proj_dir = os.path.dirname(tests_dir) + rtl_dir = os.path.join(proj_dir, "RTL") + + # Standard cocotb-test run call + run( + verilog_sources=[os.path.join(rtl_dir, "hdmi_sync_gen.v")], + toplevel="hdmi_sync_gen", + module="tb_hdmi_sync_gen", + python_search=[ + os.path.join(tests_dir, "cocotb") + ], + sim="iverilog", + force_compile=True + ) + +if __name__ == "__main__": + test_hdmi_sync_gen() diff --git a/tests/test_video_dma.py b/tests/test_video_dma.py new file mode 100644 index 0000000..d6362b1 --- /dev/null +++ b/tests/test_video_dma.py @@ -0,0 +1,22 @@ +import os +import sys +from cocotb_test.simulator import run + +def test_video_dma_master(): + tests_dir = os.path.dirname(os.path.abspath(__file__)) + proj_dir = os.path.dirname(tests_dir) + rtl_dir = os.path.join(proj_dir, "RTL") + + run( + verilog_sources=[os.path.join(rtl_dir, "video_dma_master.v")], + toplevel="video_dma_master", + module="tb_video_dma_master", + python_search=[ + os.path.join(tests_dir, "cocotb") + ], + sim="iverilog", + force_compile=True + ) + +if __name__ == "__main__": + test_video_dma_master() diff --git a/tests/test_video_integration.py b/tests/test_video_integration.py new file mode 100644 index 0000000..522e428 --- /dev/null +++ b/tests/test_video_integration.py @@ -0,0 +1,29 @@ +import os +import sys +from cocotb_test.simulator import run + +def test_video_integration(): + tests_dir = os.path.dirname(os.path.abspath(__file__)) + proj_dir = os.path.dirname(tests_dir) + rtl_dir = os.path.join(proj_dir, "RTL") + + run( + verilog_sources=[ + os.path.join(rtl_dir, "simple_dcfifo.v"), + os.path.join(rtl_dir, "video_dma_master.v"), + os.path.join(rtl_dir, "hdmi_sync_gen.v"), + os.path.join(rtl_dir, "video_pipeline.v") + ], + toplevel="video_pipeline", + module="tb_video_integration", + python_search=[ + os.path.join(tests_dir, "cocotb") + ], + sim="iverilog", + # Pass Define for Simulation Mode (Smaller Frame) + # compile_args=["-DCOCOTB_SIM=1"], + force_compile=True + ) + +if __name__ == "__main__": + test_video_integration() diff --git a/tests/test_video_pipeline.py b/tests/test_video_pipeline.py new file mode 100644 index 0000000..0ec99ce --- /dev/null +++ b/tests/test_video_pipeline.py @@ -0,0 +1,27 @@ +import os +import sys +from cocotb_test.simulator import run + +def test_video_pipeline(): + tests_dir = os.path.dirname(os.path.abspath(__file__)) + proj_dir = os.path.dirname(tests_dir) + rtl_dir = os.path.join(proj_dir, "RTL") + + run( + verilog_sources=[ + os.path.join(rtl_dir, "simple_dcfifo.v"), + os.path.join(rtl_dir, "video_dma_master.v"), + os.path.join(rtl_dir, "hdmi_sync_gen.v"), + os.path.join(rtl_dir, "video_pipeline.v") + ], + toplevel="video_pipeline", + module="tb_video_pipeline", + python_search=[ + os.path.join(tests_dir, "cocotb") + ], + sim="iverilog", + force_compile=True + ) + +if __name__ == "__main__": + test_video_pipeline() From e8e75e0344f8008937350816b1da6267abd18032 Mon Sep 17 00:00:00 2001 From: ByungChang Cha Date: Sat, 14 Feb 2026 10:24:37 -0500 Subject: [PATCH 2/3] feat: Add comprehensive documentation --- .gitignore | 3 + README.md | 37 +++- README_kor.md | 88 +++++++++ TRYERROR.md | 1 + TRYERROR_kor.md | 76 ++++++++ doc/BURST_DMA.md | 1 + doc/BURST_DMA_kor.md | 158 +++++++++++++++ doc/DESIGN.md | 1 + doc/DESIGN_kor.md | 73 +++++++ doc/NIOS.md | 2 + doc/NIOS_kor.md | 77 ++++++++ doc/RESULT.md | 1 + doc/RESULT_kor.md | 133 +++++++++++++ doc/STUDY.md | 53 +++++- doc/STUDY_kor.md | 392 ++++++++++++++++++++++++++++++++++++++ doc/TODO.md | 1 + doc/TODO_kor.md | 70 +++++++ doc/VIDEO_PLAYBACK.md | 2 + doc/VIDEO_PLAYBACK_kor.md | 213 +++++++++++++++++++++ 19 files changed, 1374 insertions(+), 8 deletions(-) create mode 100644 README_kor.md create mode 100644 TRYERROR_kor.md create mode 100644 doc/BURST_DMA_kor.md create mode 100644 doc/DESIGN_kor.md create mode 100644 doc/NIOS_kor.md create mode 100644 doc/RESULT_kor.md create mode 100644 doc/STUDY_kor.md create mode 100644 doc/TODO_kor.md create mode 100644 doc/VIDEO_PLAYBACK_kor.md diff --git a/.gitignore b/.gitignore index 09d0864..334ce7a 100644 --- a/.gitignore +++ b/.gitignore @@ -30,3 +30,6 @@ hc_output/ software/*/ obj/ bin/ +linux_software/image_converter/*.jpg +tests/cocotb/*.bmp +tests/cocotb/*.bin diff --git a/README.md b/README.md index 1709019..b3b3658 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,5 @@ # DE10-Nano Video Processing Project +[**English**] | [**ํ•œ๊ตญ์–ด**](./README_kor.md) ## ๐Ÿ“Œ Project Overview This project implements high-performance video data movement between the FPGA and HPS DDR3 memory on the DE10-Nano (Cyclone V SoC). @@ -53,14 +54,36 @@ graph LR | **DDR3 to DDR3** | Software (w/ Arithmetic) | 0.21 MB/s | Reference | | | **Hardware DMA (BM4/Pipe)** | **125.00 MB/s** | **~585x Speedup** | +## ๐Ÿงช Verification (Cocotb) +To strictly validate the video pipeline before hardware deployment, we utilized **Cocotb** for bit-accurate verification. This process simulates the actual hardware environment and compares the output against a reference image pixel-by-pixel. + +### ๐Ÿ” Verification Process (Step-by-Step) +1. **Image Preloading (`image.raw`)**: + - The Python testbench (`tb_video_integration.py`) reads a raw binary image file and preloads it into a **DDR3 Memory Model**. + - This effectively simulates the Linux environment where the video frame is already validated in physical memory. + +2. **RTL Simulation Execution**: + - The FPGA RTL core (`video_dma_master`, `fifo`, `pipeline`) initiates DMA transactions to fetch data from the memory model. + - Data flows through the processing pipeline and is transmitted according to strict HDMI timing specifications. + +3. **Output Capture (`hdmi_output.bin`)**: + - The testbench monitors the HDMI output signals (`hdmi_de`, `hdmi_d`) and captures valid pixel data into a binary file (`hdmi_output.bin`) during the active video period. + +4. **Automated Integrity Check (`bin2bmp.py`)**: + - A post-simulation script compares the **Captured Output** against the **Original Input** to verify data integrity. + - Pass Condition: **Bit-perfect match** for every pixel in the 960x540 frame. + +> **Note**: This rigorous verification workflow allowed us to identify and resolve critical issues, such as FIFO overflows and CDC (Clock Domain Crossing) errors, prior to hardware synthesis. + ## ๐Ÿ“– Documentation -- [VIDEO_PLAYBACK.md](doc/VIDEO_PLAYBACK.md): **โญ NEW** - qHD video playback implementation, Linux integration, and performance analysis. -- [DESIGN.md](doc/DESIGN.md): Comprehensive system architecture and DDR-to-HDMI pipeline specification. -- [NIOS.md](doc/NIOS.md): Detailed Interactive Menu tree structure and control logic. -- [BURST_DMA.md](doc/BURST_DMA.md): Detailed debugging history, performance benchmarks, and memory protection strategies. -- [STUDY.md](doc/STUDY.md): Technical study notes on HDMI timing, ADV7513, and video processing. -- [RESULT.md](doc/RESULT.md): Official performance benchmark results and hardware status logs. -- [TODO.md](doc/TODO.md): Project roadmap and remaining tasks. +- [VIDEO_PLAYBACK.md](doc/VIDEO_PLAYBACK.md) | [๊ตญ๋ฌธ](doc/VIDEO_PLAYBACK_kor.md): **โญ NEW** - qHD video playback implementation, Linux integration, and performance analysis. +- [DESIGN.md](doc/DESIGN.md) | [๊ตญ๋ฌธ](doc/DESIGN_kor.md): Comprehensive system architecture and DDR-to-HDMI pipeline specification. +- [NIOS.md](doc/NIOS.md) | [๊ตญ๋ฌธ](doc/NIOS_kor.md): Detailed Interactive Menu tree structure and control logic. +- [BURST_DMA.md](doc/BURST_DMA.md) | [๊ตญ๋ฌธ](doc/BURST_DMA_kor.md): Detailed debugging history, performance benchmarks, and memory protection strategies. +- [STUDY.md](doc/STUDY.md) | [๊ตญ๋ฌธ](doc/STUDY_kor.md): Technical study notes on HDMI timing, ADV7513, and video processing. +- [RESULT.md](doc/RESULT.md) | [๊ตญ๋ฌธ](doc/RESULT_kor.md): Official performance benchmark results and hardware status logs. +- [TRYERROR.md](./TRYERROR.md) | [๊ตญ๋ฌธ](./TRYERROR_kor.md): **โญ NEW** - Troubleshooting log for DMA, FIFO, and HDMI integration issues. +- [TODO.md](doc/TODO.md) | [๊ตญ๋ฌธ](doc/TODO_kor.md): Project roadmap and remaining tasks. - [soc_system.qsys](./soc_system.qsys): Platform Designer (Qsys) hardware configuration. - [nios_software/](./nios_software/): Nios II benchmark and verification source code. - [linux_software/](./linux_software/): Linux HPS applications for video playback. diff --git a/README_kor.md b/README_kor.md new file mode 100644 index 0000000..9fc5d89 --- /dev/null +++ b/README_kor.md @@ -0,0 +1,88 @@ +# DE10-Nano ๋น„๋””์˜ค ํ”„๋กœ์„ธ์‹ฑ ํ”„๋กœ์ ํŠธ +[**English**](./README.md) | [**ํ•œ๊ตญ์–ด**] + +## ๐Ÿ“Œ ํ”„๋กœ์ ํŠธ ๊ฐœ์š” +๋ณธ ํ”„๋กœ์ ํŠธ๋Š” DE10-Nano (Cyclone V SoC) ํ”Œ๋žซํผ์—์„œ FPGA์™€ HPS DDR3 ๋ฉ”๋ชจ๋ฆฌ ๊ฐ„์˜ ๊ณ ์„ฑ๋Šฅ ๋น„๋””์˜ค ๋ฐ์ดํ„ฐ ์ด๋™์„ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. +**FPGA-to-HPS AXI Bridge**๋ฅผ ํ™œ์šฉํ•จ์œผ๋กœ์จ ์ผ๋ฐ˜์ ์ธ ํ”„๋ฆฌ๋กœ๋”/๋ธŒ๋ฆฟ์ง€ ์ž ๊ธˆ ๋ฌธ์ œ๋ฅผ ์šฐํšŒํ•˜๊ณ , ์‹ค์‹œ๊ฐ„ ๋น„๋””์˜ค ์ฒ˜๋ฆฌ์— ์ ํ•ฉํ•œ ์•ˆ์ •์ ์ธ ๊ณ ์† DMA ์•ก์„ธ์Šค๋ฅผ ๋‹ฌ์„ฑํ–ˆ์Šต๋‹ˆ๋‹ค. + +## ๐Ÿš€ ์ฃผ์š” ์„ฑ๊ณผ +- **DDR3 ์—ฐ๊ฒฐ์„ฑ ํ™•๋ณด**: ๋ฉ”๋ชจ๋ฆฌ ์•ก์„ธ์Šค ๊ฒฝ๋กœ๋ฅผ ์ž ๊ฒจ ์žˆ๋Š” SDRAM ํฌํŠธ์—์„œ AXI ๋ธŒ๋ฆฟ์ง€๋กœ ์žฌ๋ฐฐ์น˜ํ•˜์—ฌ ์‹œ์Šคํ…œ ํ–‰(Hang) ๋ฌธ์ œ๋ฅผ ์„ฑ๊ณต์ ์œผ๋กœ ํ•ด๊ฒฐํ–ˆ์Šต๋‹ˆ๋‹ค. +- **ํ•˜๋“œ์›จ์–ด DMA ๋งˆ์Šคํ„ฐ**: ๊ณ ์† ๋ฐ์ดํ„ฐ ์ „์†ก์„ ์ˆ˜ํ–‰ํ•˜๊ธฐ ์œ„ํ•ด ์ปค์Šคํ…€ `burst_master` (Avalon-MM)๋ฅผ ํ†ตํ•ฉํ–ˆ์Šต๋‹ˆ๋‹ค. +- **์„ฑ๋Šฅ ์ตœ์ ํ™”**: ์†Œํ”„ํŠธ์›จ์–ด ๊ธฐ๋ฐ˜ ๋ณต์‚ฌ ๋ฃจํ”„ ๋Œ€๋น„ ํ•˜๋“œ์›จ์–ด ๊ตฌ๋™ ๋ฒ„์ŠคํŠธ๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ์•ฝ 30๋ฐฐ์˜ ์ฒ˜๋ฆฌ๋Ÿ‰ ํ–ฅ์ƒ์„ ๋‹ฌ์„ฑํ–ˆ์Šต๋‹ˆ๋‹ค. +- **์•ˆ์ •์ ์ธ ๋ฐ์ดํ„ฐ ์ผ๊ด€์„ฑ**: Nios II์™€ ํ•˜๋“œ์›จ์–ด ๋งˆ์Šคํ„ฐ ๊ฐ„์— ๊ณต์œ ๋˜๋Š” ๋ฐ์ดํ„ฐ์˜ ์‹ ๋ขฐ์„ฑ์„ ์œ„ํ•ด ์ ์ ˆํ•œ ์บ์‹œ ๊ด€๋ฆฌ(`alt_dcache_flush_all`)๋ฅผ ๊ตฌํ˜„ํ–ˆ์Šต๋‹ˆ๋‹ค. +- **๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ ์ตœ์ ํ™”**: SDC์—์„œ ๋น„๋™๊ธฐ ํด๋ก ๊ทธ๋ฃน ์ œ์•ฝ ์กฐ๊ฑด์„ ์ ์šฉํ•˜์—ฌ ํƒ€์ด๋ฐ ์œ„๋ฐ˜(Negative Slack -6.5ns) ๋ฌธ์ œ๋ฅผ ํ•ด๊ฒฐํ–ˆ์Šต๋‹ˆ๋‹ค. +- **๊ณ ๊ธ‰ HDMI ์ œ์–ด**: ์ •๊ตํ•œ ๊ฐ๋งˆ ๋ณด์ •(sRGB, Inverse Gamma 2.2) ๋ฐ ์ปค์Šคํ…€ ์บ๋ฆญํ„ฐ ํƒ€์ผ ๋ Œ๋”๋ง(Mode 7)์„ ๊ตฌํ˜„ํ–ˆ์Šต๋‹ˆ๋‹ค. +- **์•ˆ์ •์ ์ธ ์ฃผ์†Œ ๋งคํ•‘**: Avalon-MM์˜ ๋ฐ”์ดํŠธ-์›Œ๋“œ ์ฃผ์†Œ ์ง€์ • ๋ฌธ์ œ๋ฅผ ์ˆ˜์ •ํ•˜์—ฌ ์‹ ๋ขฐํ•  ์ˆ˜ ์žˆ๋Š” ๋ ˆ์ง€์Šคํ„ฐ ์ œ์–ด๋ฅผ ๋ณด์žฅํ–ˆ์Šต๋‹ˆ๋‹ค. + +### ๐ŸŽฌ ๋น„๋””์˜ค ์žฌ์ƒ (์‹ ๊ทœ!) +- **qHD ํ•ด์ƒ๋„ (960ร—540@60Hz)**: 50MHz ๋ฒ„์Šค ๋Œ€์—ญํญ์— ์ตœ์ ํ™” (๊ฐ€์šฉ 200 MB/s ์ค‘ 124 MB/s ์‚ฌ์šฉ) +- **์ •์  ์ด๋ฏธ์ง€ ๋””์Šคํ”Œ๋ ˆ์ด**: Nios II ์†Œํ”„ํŠธ์›จ์–ด๊ฐ€ DDR3์—์„œ ์ด๋ฏธ์ง€๋ฅผ ๋กœ๋“œํ•˜๊ณ  ํ‘œ์‹œํ•ฉ๋‹ˆ๋‹ค. +- **๋ฆฌ๋ˆ…์Šค ๋น„๋””์˜ค ์žฌ์ƒ**: ๊ณ ์„ฑ๋Šฅ "Store-and-Forward" ์•„ํ‚คํ…์ฒ˜ (RAM Preload) ๊ตฌํ˜„. +- **๋„คํŠธ์›Œํฌ ์ŠคํŠธ๋ฆฌ๋ฐ**: SSH๋ฅผ ํ†ตํ•ด ํ˜ธ์ŠคํŠธ PC๋กœ๋ถ€ํ„ฐ ๋น„๋””์˜ค๋ฅผ ํŒŒ์ดํ•‘ํ•˜๋Š” ๊ธฐ๋Šฅ ์ง€์› (`cat | ssh`). +- **๋“€์–ผ ํด๋ก ์•„ํ‚คํ…์ฒ˜**: CSR(50MHz)๊ณผ Pixel(37.8MHz) ํด๋ก์„ ๋ถ„๋ฆฌํ•˜๊ณ  ์ ์ ˆํ•œ CDC๋ฅผ ์ ์šฉํ–ˆ์Šต๋‹ˆ๋‹ค. +- **V-Sync ๋™๊ธฐํ™”**: ํ•˜๋“œ์›จ์–ด ๋ž˜์นญ์„ ํ†ตํ•œ ํ‹ฐ์–ด๋ง ์—†๋Š”(Tear-free) ํ”„๋ ˆ์ž„ ์—…๋ฐ์ดํŠธ๋ฅผ ๊ตฌํ˜„ํ–ˆ์Šต๋‹ˆ๋‹ค. + +## ๐Ÿ— ์‹œ์Šคํ…œ ์•„ํ‚คํ…์ฒ˜ +```mermaid +graph LR + subgraph FPGA + Nios["Nios II Processor"] + BM["Burst Master (DMA)"] + ASE["Address Span Extender"] + HCP["HDMI Control (RTL)"] + end + + subgraph HPS + AXI["F2H AXI Slave Bridge"] + DDR["DDR3 Memory Controller"] + end + + Nios --> ASE + Nios --> HCP + BM --> ASE + ASE --> AXI + AXI --> DDR +``` + +## ์„ฑ๋Šฅ ์š”์•ฝ + +| ๋ฐ์ดํ„ฐ ๊ฒฝ๋กœ | ๋ฐฉ๋ฒ• | ์ฒ˜๋ฆฌ๋Ÿ‰ | ๊ฒ€์ฆ | +| :--- | :--- | :--- | :--- | +| **OCM to DDR3** | ์†Œํ”„ํŠธ์›จ์–ด ๋ณต์‚ฌ (CPU) | 4.55 MB/s | ๊ธฐ์ค€์ (Baseline) | +| | **ํ•˜๋“œ์›จ์–ด DMA (๋ฒ„์ŠคํŠธ)** | **136.53 MB/s** | **์•ฝ 30๋ฐฐ ํ–ฅ์ƒ** | +| **DDR3 to DDR3** | ์†Œํ”„ํŠธ์›จ์–ด (์‚ฐ์ˆ  ์—ฐ์‚ฐ ํฌํ•จ) | 0.21 MB/s | ์ฐธ์กฐ์šฉ | +| | **ํ•˜๋“œ์›จ์–ด DMA (BM4/ํŒŒ์ดํ”„๋ผ์ธ)** | **125.00 MB/s** | **์•ฝ 585๋ฐฐ ํ–ฅ์ƒ** | + +## ๐Ÿงช ๊ฒ€์ฆ (Cocotb) +ํ•˜๋“œ์›จ์–ด ๋ฐฐ์น˜ ์ „ ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ์„ ์—„๊ฒฉํ•˜๊ฒŒ ๊ฒ€์ฆํ•˜๊ธฐ ์œ„ํ•ด **Cocotb**๋ฅผ ํ™œ์šฉํ•˜์—ฌ ๋น„ํŠธ ๋‹จ์œ„ ์ •ํ™•๋„(Bit-accurate) ๊ฒ€์ฆ์„ ์ˆ˜ํ–‰ํ–ˆ์Šต๋‹ˆ๋‹ค. ์ด ํ”„๋กœ์„ธ์Šค๋Š” ์‹ค์ œ ํ•˜๋“œ์›จ์–ด ํ™˜๊ฒฝ์„ ์‹œ๋ฎฌ๋ ˆ์ด์…˜ํ•˜๊ณ  ์ถœ๋ ฅ ๊ฒฐ๊ณผ๋ฅผ ์ฐธ์กฐ ์ด๋ฏธ์ง€์™€ ํ”ฝ์…€ ๋‹จ์œ„๋กœ ๋น„๊ตํ•ฉ๋‹ˆ๋‹ค. + +### ๐Ÿ” ๊ฒ€์ฆ ํ”„๋กœ์„ธ์Šค (๋‹จ๊ณ„๋ณ„) +1. **์ด๋ฏธ์ง€ ์‚ฌ์ „ ๋กœ๋“œ (`image.raw`)**: + - Python ํ…Œ์ŠคํŠธ๋ฒค์น˜(`tb_video_integration.py`)๊ฐ€ ์›๋ณธ ๋ฐ”์ด๋„ˆ๋ฆฌ ์ด๋ฏธ์ง€ ํŒŒ์ผ์„ ์ฝ์–ด **DDR3 ๋ฉ”๋ชจ๋ฆฌ ๋ชจ๋ธ**์— ์‚ฌ์ „ ๋กœ๋“œํ•ฉ๋‹ˆ๋‹ค. + - ์ด๋Š” ๋น„๋””์˜ค ํ”„๋ ˆ์ž„์ด ๋ฌผ๋ฆฌ ๋ฉ”๋ชจ๋ฆฌ์— ์ด๋ฏธ ์ค€๋น„๋˜์–ด ์žˆ๋Š” ๋ฆฌ๋ˆ…์Šค ํ™˜๊ฒฝ์„ ํšจ๊ณผ์ ์œผ๋กœ ์‹œ๋ฎฌ๋ ˆ์ด์…˜ํ•ฉ๋‹ˆ๋‹ค. + +2. **RTL ์‹œ๋ฎฌ๋ ˆ์ด์…˜ ์‹คํ–‰**: + - FPGA RTL ์ฝ”์–ด(`video_dma_master`, `fifo`, `pipeline`)๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ ๋ชจ๋ธ๋กœ๋ถ€ํ„ฐ ๋ฐ์ดํ„ฐ๋ฅผ ๊ฐ€์ ธ์˜ค๊ธฐ ์œ„ํ•ด DMA ํŠธ๋žœ์žญ์…˜์„ ์‹œ์ž‘ํ•ฉ๋‹ˆ๋‹ค. + - ๋ฐ์ดํ„ฐ๋Š” ์ฒ˜๋ฆฌ ํŒŒ์ดํ”„๋ผ์ธ์„ ๊ฑฐ์ณ ์—„๊ฒฉํ•œ HDMI ํƒ€์ด๋ฐ ๊ทœ๊ฒฉ์— ๋”ฐ๋ผ ์ „์†ก๋ฉ๋‹ˆ๋‹ค. + +3. **์ถœ๋ ฅ ์บก์ฒ˜ (`hdmi_output.bin`)**: + - ํ…Œ์ŠคํŠธ๋ฒค์น˜๋Š” HDMI ์ถœ๋ ฅ ์‹ ํ˜ธ(`hdmi_de`, `hdmi_d`)๋ฅผ ๋ชจ๋‹ˆํ„ฐ๋งํ•˜๊ณ , ํ™œ์„ฑ ๋น„๋””์˜ค ๊ตฌ๊ฐ„ ๋™์•ˆ ์œ ํšจํ•œ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๋ฅผ ๋ฐ”์ด๋„ˆ๋ฆฌ ํŒŒ์ผ(`hdmi_output.bin`)๋กœ ์บก์น˜ํ•ฉ๋‹ˆ๋‹ค. + +4. **์ž๋™ ๋ฌด๊ฒฐ์„ฑ ๊ฒ€์‚ฌ (`bin2bmp.py`)**: + - ์‹œ๋ฎฌ๋ ˆ์ด์…˜ ํ›„์† ์Šคํฌ๋ฆฝํŠธ๊ฐ€ **์บก์ฒ˜๋œ ์ถœ๋ ฅ**๊ณผ **์›๋ณธ ์ž…๋ ฅ**์„ ๋น„๊ตํ•˜์—ฌ ๋ฐ์ดํ„ฐ ๋ฌด๊ฒฐ์„ฑ์„ ๊ฒ€์ฆํ•ฉ๋‹ˆ๋‹ค. + - ํ†ต๊ณผ ์กฐ๊ฑด: 960x540 ํ”„๋ ˆ์ž„์˜ ๋ชจ๋“  ํ”ฝ์…€์— ๋Œ€ํ•ด **๋น„ํŠธ ๋‹จ์œ„๋กœ ์™„๋ฒฝํ•˜๊ฒŒ ์ผ์น˜**ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. + +> **์ฐธ๊ณ **: ์ด๋Ÿฌํ•œ ์—„๊ฒฉํ•œ ๊ฒ€์ฆ ์›Œํฌํ”Œ๋กœ์šฐ๋ฅผ ํ†ตํ•ด ํ•˜๋“œ์›จ์–ด ํ•ฉ์„ฑ ์ „์— FIFO ์˜ค๋ฒ„ํ”Œ๋กœ์šฐ ๋ฐ CDC(ํด๋ก ๋„๋ฉ”์ธ ๊ต์ฐจ) ์˜ค๋ฅ˜์™€ ๊ฐ™์€ ์น˜๋ช…์ ์ธ ๋ฌธ์ œ๋ฅผ ์‹๋ณ„ํ•˜๊ณ  ํ•ด๊ฒฐํ•  ์ˆ˜ ์žˆ์—ˆ์Šต๋‹ˆ๋‹ค. + +## ๐Ÿ“– ๋ฌธ์„œ +- [VIDEO_PLAYBACK.md](doc/VIDEO_PLAYBACK.md) | [๊ตญ๋ฌธ](doc/VIDEO_PLAYBACK_kor.md): **โญ ์‹ ๊ทœ** - qHD ๋น„๋””์˜ค ์žฌ์ƒ ๊ตฌํ˜„, ๋ฆฌ๋ˆ…์Šค ํ†ตํ•ฉ ๋ฐ ์„ฑ๋Šฅ ๋ถ„์„. +- [DESIGN.md](doc/DESIGN.md) | [๊ตญ๋ฌธ](doc/DESIGN_kor.md): ์ „์ฒด ์‹œ์Šคํ…œ ์•„ํ‚คํ…์ฒ˜ ๋ฐ DDR-to-HDMI ํŒŒ์ดํ”„๋ผ์ธ ์‚ฌ์–‘. +- [NIOS.md](doc/NIOS.md) | [๊ตญ๋ฌธ](doc/NIOS_kor.md): ์ƒ์„ธ ์ธํ„ฐ๋ž™ํ‹ฐ๋ธŒ ๋ฉ”๋‰ด ํŠธ๋ฆฌ ๊ตฌ์กฐ ๋ฐ ์ œ์–ด ๋กœ์ง. +- [BURST_DMA.md](doc/BURST_DMA.md) | [๊ตญ๋ฌธ](doc/BURST_DMA_kor.md): ์ƒ์„ธ ๋””๋ฒ„๊น… ์ด๋ ฅ, ์„ฑ๋Šฅ ๋ฒค์น˜๋งˆํฌ ๋ฐ ๋ฉ”๋ชจ๋ฆฌ ๋ณดํ˜ธ ์ „๋žต. +- [STUDY.md](doc/STUDY.md) | [๊ตญ๋ฌธ](doc/STUDY_kor.md): HDMI ํƒ€์ด๋ฐ, ADV7513 ๋ฐ ๋น„๋””์˜ค ์ฒ˜๋ฆฌ์— ๊ด€ํ•œ ๊ธฐ์ˆ  ํ•™์Šต ๋…ธํŠธ. +- [RESULT.md](doc/RESULT.md) | [๊ตญ๋ฌธ](doc/RESULT_kor.md): ๊ณต์‹ ์„ฑ๋Šฅ ๋ฒค์น˜๋งˆํฌ ๊ฒฐ๊ณผ ๋ฐ ํ•˜๋“œ์›จ์–ด ์ƒํƒœ ๋กœ๊ทธ. +- [TRYERROR.md](./TRYERROR.md) | [๊ตญ๋ฌธ](./TRYERROR_kor.md): **โญ ์‹ ๊ทœ** - DMA, FIFO ๋ฐ HDMI ํ†ตํ•ฉ ๊ณผ์ •์—์„œ์˜ ๋ฌธ์ œ ํ•ด๊ฒฐ ๊ธฐ๋ก. +- [TODO.md](doc/TODO.md) | [๊ตญ๋ฌธ](doc/TODO_kor.md): ํ”„๋กœ์ ํŠธ ๋กœ๋“œ๋งต ๋ฐ ๋‚จ์€ ๊ณผ์ œ. +- [soc_system.qsys](./soc_system.qsys): Platform Designer (Qsys) ํ•˜๋“œ์›จ์–ด ๊ตฌ์„ฑ. +- [nios_software/](./nios_software/): Nios II ๋ฒค์น˜๋งˆํฌ ๋ฐ ๊ฒ€์ฆ ์†Œ์Šค ์ฝ”๋“œ. +- [linux_software/](./linux_software/): ๋น„๋””์˜ค ์žฌ์ƒ์„ ์œ„ํ•œ ๋ฆฌ๋ˆ…์Šค HPS ์• ํ”Œ๋ฆฌ์ผ€์ด์…˜. diff --git a/TRYERROR.md b/TRYERROR.md index 7a999f1..e23ed26 100644 --- a/TRYERROR.md +++ b/TRYERROR.md @@ -1,4 +1,5 @@ # Debugging Log: Video DMA & FIFO Integration +[**English**] | [**ํ•œ๊ตญ์–ด**](./TRYERROR_kor.md) This document records the issues encountered and solutions implemented during the verification of the Video DMA pipeline. diff --git a/TRYERROR_kor.md b/TRYERROR_kor.md new file mode 100644 index 0000000..4845623 --- /dev/null +++ b/TRYERROR_kor.md @@ -0,0 +1,76 @@ +# ๋””๋ฒ„๊น… ๋กœ๊ทธ: ๋น„๋””์˜ค DMA ๋ฐ FIFO ํ†ตํ•ฉ +[**English**](./TRYERROR.md) | [**ํ•œ๊ตญ์–ด**] + +์ด ๋ฌธ์„œ๋Š” ๋น„๋””์˜ค DMA ํŒŒ์ดํ”„๋ผ์ธ ๊ฒ€์ฆ ๊ณผ์ •์—์„œ ๋ฐœ์ƒํ•œ ๋ฌธ์ œ๋“ค๊ณผ ๊ทธ์— ๋Œ€ํ•œ ํ•ด๊ฒฐ์ฑ…์„ ๊ธฐ๋กํ•ฉ๋‹ˆ๋‹ค. + +## 1. FIFO ์‚ฌ์šฉ๋Ÿ‰ ๊ณ„์‚ฐ ์˜ค๋ฅ˜ (์น˜๋ช…์  RTL ๋ฒ„๊ทธ) +- **๊ตฌ์„ฑ ์š”์†Œ**: `RTL/simple_dcfifo.v` +- **์ฆ์ƒ**: DMA ๋งˆ์Šคํ„ฐ๊ฐ€ ์˜ˆ์ธก ๋ถˆ๊ฐ€๋Šฅํ•˜๊ฒŒ ๋ฉ”๋ชจ๋ฆฌ ์ฝ๊ธฐ๋ฅผ ์ค‘๋‹จํ•˜๊ฑฐ๋‚˜(`CHECK_FIFO` ์ƒํƒœ์—์„œ ๋ฉˆ์ถค) FIFO ์˜ค๋ฒ„ํ”Œ๋กœ์šฐ๊ฐ€ ๋ฐœ์ƒํ•จ. +- **์›์ธ**: ์„œ๋กœ ๋‹ค๋ฅธ ์ฝ”๋”ฉ ์ฒด๊ณ„๋ฅผ ํ˜ผ์šฉํ•œ ์ž˜๋ชป๋œ ์‚ฐ์ˆ  ์—ฐ์‚ฐ. **๊ทธ๋ ˆ์ด ์ฝ”๋“œ(Gray Code)** ํฌ์ธํ„ฐ์—์„œ **๋ฐ”์ด๋„ˆ๋ฆฌ(Binary)** ํฌ์ธํ„ฐ๋ฅผ ์ง์ ‘ ๋นผ์„œ ์‚ฌ์šฉ๋Ÿ‰(`wrusedw`)์„ ๊ณ„์‚ฐํ•จ. + ```verilog + // BAD CODE + assign wrusedw = wr_ptr_bin - rd_ptr_gray_sync; + ``` + ๊ทธ๋ ˆ์ด ์ฝ”๋“œ๋Š” ๊ฐ€์ค‘์น˜ ๊ธฐ๋ฐ˜์ด ์•„๋‹ˆ๊ธฐ ๋•Œ๋ฌธ์—(์˜ˆ: 3์€ `0010`, 4๋Š” `0110`), ๋บ„์…ˆ ๊ฒฐ๊ณผ๊ฐ€ ๋ฌด์˜๋ฏธํ•œ ๊ฐ’์ด ๋จ. +- **ํ•ด๊ฒฐ์ฑ…**: ๋™๊ธฐํ™”๋œ ์ฝ๊ธฐ ํฌ์ธํ„ฐ๋ฅผ ๋บ„์…ˆ ์ „ ๋ฐ”์ด๋„ˆ๋ฆฌ๋กœ ๋ณ€ํ™˜ํ•˜๋Š” `gray2bin` ํ•จ์ˆ˜๋ฅผ ๊ตฌํ˜„ํ•จ. + ```verilog + // FIXED CODE + wire [ADDR_WIDTH:0] rd_ptr_bin_sync = gray2bin(rd_ptr_gray_sync2); + assign wrusedw = (used_diff[ADDR_WIDTH]) ? {ADDR_WIDTH{1'b1}} : used_diff[ADDR_WIDTH-1:0]; // ํฌํ™”(Saturation) ๋กœ์ง ํฌํ•จ + ``` + +## 2. ์•”์‹œ์  ๋„ท(Net) ์„ ์–ธ ๋ฐ ๋น„ํŠธ ์ ˆ์‚ญ +- **๊ตฌ์„ฑ ์š”์†Œ**: `RTL/video_pipeline.v` +- **์ฆ์ƒ**: ํ†ตํ•ฉ ํ…Œ์ŠคํŠธ๋Š” ์‹คํ–‰๋˜์ง€๋งŒ ๋ฐ์ดํ„ฐ ๊ฒ€์ฆ์ด ์™„์ „ํžˆ ์‹คํŒจํ•จ(์“ฐ๋ ˆ๊ธฐ ๊ฐ’ ๋˜๋Š” 0 ์ˆ˜์‹ ). +- **์›์ธ**: ๋‹ค์ค‘ ๋น„ํŠธ ๋‚ด๋ถ€ ์‹ ํ˜ธ์— ๋Œ€ํ•œ `wire` ์„ ์–ธ ๋ˆ„๋ฝ. + Verilog๋Š” ์„ ์–ธ๋˜์ง€ ์•Š์€ ์‹ ํ˜ธ๋ฅผ ๊ธฐ๋ณธ์ ์œผ๋กœ **1๋น„ํŠธ wire**๋กœ ๊ฐ„์ฃผํ•จ. + 32๋น„ํŠธ `fifo_wr_data`์™€ 9๋น„ํŠธ `fifo_used` ์‹ ํ˜ธ๊ฐ€ ์•”์‹œ์ ์œผ๋กœ 1๋น„ํŠธ๋กœ ์„ ์–ธ๋˜์–ด ์ƒ์œ„ ๋น„ํŠธ๋“ค์ด ์ž๋™์œผ๋กœ ๋ฒ„๋ ค์ง. +- **ํ•ด๊ฒฐ์ฑ…**: ๋ชจ๋“  ๋‚ด๋ถ€ ์—ฐ๊ฒฐ ์‹ ํ˜ธ์— ๋Œ€ํ•ด ๋ช…์‹œ์ ์ธ wire ์„ ์–ธ์„ ์ถ”๊ฐ€ํ•จ. + ```verilog + wire [31:0] fifo_wr_data; + wire [8:0] fifo_used; + // ... + ``` + +## 3. ์‹œ๋ฎฌ๋ ˆ์ด์…˜ 'X' ์ „ํŒŒ ๋ฌธ์ œ +- **๊ตฌ์„ฑ ์š”์†Œ**: `RTL/simple_dcfifo.v` ๋ฐ `cocotb` +- **์ฆ์ƒ**: Python ํ…Œ์ŠคํŠธ๋ฒค์น˜๊ฐ€ `ValueError: Cannot convert Logic('X') to bool` ์—๋Ÿฌ์™€ ํ•จ๊ป˜ ์ถฉ๋Œํ•จ. +- **์›์ธ**: ํ•˜๋“œ์›จ์–ด์—์„œ ๋ ˆ์ง€์Šคํ„ฐ๋Š” ์ดˆ๊ธฐ ์ „์› ํˆฌ์ž… ์‹œ ์•Œ ์ˆ˜ ์—†๋Š” ์ƒํƒœ('X')๋ฅผ ๊ฐ€์ง. ์‹ค์ œ ํ•˜๋“œ์›จ์–ด๋Š” ๋ฆฌ์…‹์„ ํ†ตํ•ด ์•ˆ์ •ํ™”๋˜์ง€๋งŒ, ์‹œ๋ฎฌ๋ ˆ์ด์…˜(Cocotb)์€ 4-์ƒํƒœ ๋กœ์ง์„ ์—„๊ฒฉํ•˜๊ฒŒ ์ ์šฉํ•จ. FIFO ์ถœ๋ ฅ `q`๊ฐ€ ์ฒซ ์ฝ๊ธฐ ์ „๊นŒ์ง€ 'X' ์ƒํƒœ๋ฅผ ์œ ์ง€ํ•˜์—ฌ ํ…Œ์ŠคํŠธ๋ฒค์น˜ ๋น„๊ต๊ธฐ์—์„œ ์ถฉ๋Œ์ด ๋ฐœ์ƒํ•จ. +- **ํ•ด๊ฒฐ์ฑ…**: ์‹œ๋ฎฌ๋ ˆ์ด์…˜ ๋ชฉ์ ์œผ๋กœ ์ถœ๋ ฅ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ `0`์œผ๋กœ ์ดˆ๊ธฐํ™”ํ•˜๋Š” `initial` ๋ธ”๋ก์„ ์ถ”๊ฐ€ํ•จ. + ```verilog + initial begin + q = 0; // X ์ „ํŒŒ ๋ฐฉ์ง€ + end + ``` + +## 4. ํ…Œ์ŠคํŠธ๋ฒค์น˜ ๋ฒ„์Šค ๊ฒฝํ•ฉ (Bus Contention) +- **๊ตฌ์„ฑ ์š”์†Œ**: `tests/cocotb/tb_dma_master.py` (Avalon Memory Model) +- **์ฆ์ƒ**: ๋ฒ„์ŠคํŠธ ์ „์†ก ์ค‘์— ๋ฉ”๋ชจ๋ฆฌ์—์„œ ์ฝ์–ด์˜จ ๋ฐ์ดํ„ฐ๊ฐ€ ์†์ƒ๋˜๊ฑฐ๋‚˜ ์†Œ์‹ค๋จ. +- **์›์ธ**: ์ดˆ๊ธฐ ํ…Œ์ŠคํŠธ๋ฒค์น˜์—์„œ *๋ชจ๋“ * ์ฝ๊ธฐ ์š”์ฒญ์— ๋Œ€ํ•ด ์ƒˆ๋กœ์šด ๋…๋ฆฝ์ ์ธ ๋กœ์ง ์Šค๋ ˆ๋“œ(`cocotb.start_soon`)๋ฅผ ์ƒ์„ฑํ•จ. DMA ํŒŒ์ดํ”„๋ผ์ธ์—์„œ ์š”์ฒญ์ด ๋น ๋ฅด๊ฒŒ ์—ฐ๋‹ฌ์•„ ๋ฐœ์ƒํ•  ๊ฒฝ์šฐ, ์ด ์Šค๋ ˆ๋“œ๋“ค์ด ๊ณต์œ ๋œ `m_readdata` ๋ฒ„์Šค ์‹ ํ˜ธ๋ฅผ ๋™์‹œ์— ๊ตฌ๋™ํ•˜๋ ค๊ณ  ์‹œ๋„ํ•จ(๋ฒ„์Šค ๊ฒฝํ•ฉ ๋ฐœ์ƒ). +- **ํ•ด๊ฒฐ์ฑ…**: ๋ฉ”๋ชจ๋ฆฌ ๋ชจ๋ธ์„ **ํ(Queue)** ๊ธฐ๋ฐ˜์œผ๋กœ ๋ฆฌํŒฉํ† ๋งํ•จ. + 1. `Monitor`: ์ฝ๊ธฐ ์š”์ฒญ์„ `Queue`์— ๋„ฃ์Œ. + 2. `Driver`: ๋‹จ์ผ ์Šค๋ ˆ๋“œ๊ฐ€ `Queue`์—์„œ ์š”์ฒญ์„ ๊บผ๋‚ด ์ฐจ๋ก€๋Œ€๋กœ ๋ฒ„์Šค ์‘๋‹ต์„ ๊ตฌ๋™ํ•จ. + +## 5. ํด๋ก ๋„๋ฉ”์ธ ๊ต์ฐจ(CDC) ๋ฐ ์ง€์—ฐ ์‹œ๊ฐ„ +- **๊ตฌ์„ฑ ์š”์†Œ**: `tests/cocotb/tb_video_integration.py` +- **์ฆ์ƒ**: ํ”„๋ ˆ์ž„ ์‹œ์ž‘ ๋ถ€๋ถ„์—์„œ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ ๋ถˆ์ผ์น˜ ๋ฐœ์ƒ (Pixel 0 ๊ฐ’์ด ํ‹€๋ฆผ). +- **์›์ธ**: ๋น„๋™๊ธฐ FIFO๋Š” ๋ณธ์งˆ์ ์œผ๋กœ **1์‚ฌ์ดํด์˜ ์ฝ๊ธฐ ์ง€์—ฐ(Latency)**์„ ๊ฐ€์ง. `rdreq`๊ฐ€ ํ™œ์„ฑํ™”๋˜๋ฉด ๋ฐ์ดํ„ฐ๋Š” ํ•œ ํด๋ก ๋’ค์— `q`์— ๋‚˜ํƒ€๋‚จ. ํ…Œ์ŠคํŠธ๋ฒค์น˜๊ฐ€ `rdreq`์™€ ๋™์ผํ•œ ์‚ฌ์ดํด์—์„œ `q`๋ฅผ ํ™•์ธํ•˜์—ฌ ์˜ค๋ฅ˜๊ฐ€ ๋ฐœ์ƒํ•จ. +- **ํ•ด๊ฒฐ์ฑ…**: ํ”„๋ ˆ์ž„ ์‹œ์ž‘ ์‹œํ€€์Šค(`0, 1, 2...`)๊ฐ€ ํ•œ ์‚ฌ์ดํด ์ง€์—ฐ๋˜๋”๋ผ๋„ ์ด๋ฅผ ์˜ฌ๋ฐ”๋ฅด๊ฒŒ ์ธ์‹ํ•  ์ˆ˜ ์žˆ๋„๋ก ํ…Œ์ŠคํŠธ๋ฒค์น˜ ํ”ฝ์…€ ์ฒด์ปค๋ฅผ "์ง€์—ฐ ํ—ˆ์šฉ(Latency tolerant)" ๋ฐฉ์‹์œผ๋กœ ์—…๋ฐ์ดํŠธํ•จ. + +## 6. HDMI ํŒŒ์ดํ”„๋ผ์ธ ๊นŠ์ด ๋ถˆ์ผ์น˜ (1ํ”ฝ์…€ ์‹œํ”„ํŠธ) +- **๊ตฌ์„ฑ ์š”์†Œ**: `RTL/hdmi_sync_gen.v` +- **์ฆ์ƒ**: ์‹œ๋ฎฌ๋ ˆ์ด์…˜์—์„œ ํ”ฝ์…€์ด ์˜ค๋ฅธ์ชฝ์œผ๋กœ 1~2์นธ ๋ฐ€๋ ค ๋ณด์ž„ (์˜ˆ: 960๋ฒˆ์งธ ํ”ฝ์…€์ด 0๋ฒˆ ๋ผ์ธ์˜ ๋งˆ์ง€๋ง‰ ํ”ฝ์…€๋กœ ๋‚˜ํƒ€๋‚จ). +- **์›์ธ**: ์ œ์–ด ์‹ ํ˜ธ(`DE`, `HS`, `VS`)๋Š” 3๋‹จ๊ณ„ ํŒŒ์ดํ”„๋ผ์ธ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ๊ฑฐ์น˜์ง€๋งŒ, ํ”ฝ์…€ ๋ฐ์ดํ„ฐ ๊ฒฝ๋กœ๋Š” 2์‚ฌ์ดํด ์ง€์—ฐ๋งŒ์„ ๊ฐ€์ง. ์ด๋กœ ์ธํ•ด ์ œ์–ด ์‹ ํ˜ธ๊ฐ€ ๋ฐ์ดํ„ฐ๋ณด๋‹ค ๋’ค์ฒ˜์ง€๊ฒŒ ๋จ. +- **ํ•ด๊ฒฐ์ฑ…**: `hdmi_sync_gen.v`์—์„œ `hdmi_de`, `hdmi_hs`, `hdmi_vs`์˜ ํŒŒ์ดํ”„๋ผ์ธ ๊นŠ์ด๋ฅผ **2๋‹จ๊ณ„**๋กœ ์ถ•์†Œํ•จ. + +## 7. DMA ๋‹ค์ค‘ ํ”„๋ ˆ์ž„ ๋žฉ์–ด๋ผ์šด๋“œ ์‹คํŒจ +- **๊ตฌ์„ฑ ์š”์†Œ**: `RTL/video_dma_master.v` +- **์ฆ์ƒ**: 0๋ฒˆ ํ”„๋ ˆ์ž„์€ ์ •์ƒ ๊ฒ€์ฆ๋˜์ง€๋งŒ, 1๋ฒˆ ํ”„๋ ˆ์ž„์ด ์ž˜๋ชป๋œ ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ(์ด๋ฏธ์ง€ ์ค‘๊ฐ„)์—์„œ ์‹œ์ž‘ํ•จ. +- **์›์ธ**: DMA ๋งˆ์Šคํ„ฐ์˜ ๊ธฐ๋ณธ ํŒŒ๋ผ๋ฏธํ„ฐ๊ฐ€ `H_RES=1280`, `V_RES=720`์œผ๋กœ ํ•˜๋“œ์ฝ”๋”ฉ๋˜์–ด ์žˆ์—ˆ์Œ. `video_pipeline.v`์—์„œ ์ด๋ฅผ ์žฌ์ •์˜ํ•˜์ง€ ์•Š์•„ DMA๊ฐ€ ํ”„๋ ˆ์ž„ ์ข…๋ฃŒ ์นด์šดํŠธ(921,600 ์›Œ๋“œ)์— ๋„๋‹ฌํ•˜์ง€ ๋ชปํ–ˆ๊ณ , ๋‹ค์Œ V-Sync์—์„œ ์ฃผ์†Œ ๋ฆฌ์…‹์ด ํŠธ๋ฆฌ๊ฑฐ๋˜์ง€ ์•Š์Œ. +- **ํ•ด๊ฒฐ์ฑ…**: `video_pipeline.v`์—์„œ ์ •ํ™•ํ•œ ํŒŒ๋ผ๋ฏธํ„ฐ(`960x540`, ์•ฝ 518,400 ์›Œ๋“œ)๋ฅผ ์ „๋‹ฌํ•˜๋„๋ก ์ˆ˜์ •ํ•จ. + +## 8. ํ…Œ์ŠคํŠธ๋ฒค์น˜ ์ƒ˜ํ”Œ๋ง ์ •ํ™•๋„ (Cocotb) +- **๊ตฌ์„ฑ ์š”์†Œ**: `tests/cocotb/tb_video_integration.py` +- **์ฆ์ƒ**: ์‹œ๋ฎฌ๋ ˆ์ด์…˜ ๊ฒฐ๊ณผ๊ฐ€ ๋ถˆ์•ˆ์ •ํ•˜์—ฌ ๊ฐ€๋” 1ํ”ฝ์…€์”ฉ ๋ฐ€๋ฆฌ๊ฑฐ๋‚˜ ์ •์ƒ์œผ๋กœ ๋‚˜์˜ด. +- **์›์ธ**: ์‹œ๋ฎฌ๋ ˆ์ด์…˜์—์„œ `RisingEdge` ์งํ›„์— ๋ ˆ์ง€์Šคํ„ฐ ์‹ ํ˜ธ๋ฅผ ๋ฐ”๋กœ ์ƒ˜ํ”Œ๋งํ•˜๋ฉด ๋ธํƒ€ ์‚ฌ์ดํด ์ด์Šˆ(๊ฒฝํ•ฉ ์กฐ๊ฑด)๊ฐ€ ๋ฐœ์ƒํ•˜๊ธฐ ์‰ฌ์›€. +- **ํ•ด๊ฒฐ์ฑ…**: `RisingEdge` ์ดํ›„ `await ReadOnly()` ํŠธ๋ฆฌ๊ฑฐ๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ํ˜„์žฌ ๋ธํƒ€ ์‚ฌ์ดํด์˜ ๋ชจ๋“  ์‹ ํ˜ธ๊ฐ€ ์•ˆ์ •ํ™”๋œ ํ›„์— ์ƒ˜ํ”Œ๋ง์„ ์ˆ˜ํ–‰ํ•˜๋„๋ก ๊ตฌํ˜„ํ•จ. diff --git a/doc/BURST_DMA.md b/doc/BURST_DMA.md index 89406d8..d028c78 100644 --- a/doc/BURST_DMA.md +++ b/doc/BURST_DMA.md @@ -1,4 +1,5 @@ # Burst Master DMA: Trial, Error, and Success +[**English**] | [**ํ•œ๊ตญ์–ด**](./BURST_DMA_kor.md) [โฌ…๏ธ Back to README](../README.md) This document records the technical challenges and evolution of the DDR3 connectivity strategy for the DE10-Nano video processing project. diff --git a/doc/BURST_DMA_kor.md b/doc/BURST_DMA_kor.md new file mode 100644 index 0000000..ea3c1fc --- /dev/null +++ b/doc/BURST_DMA_kor.md @@ -0,0 +1,158 @@ +# ๋ฒ„์ŠคํŠธ ๋งˆ์Šคํ„ฐ DMA: ์‹œํ–‰์ฐฉ์˜ค์™€ ์„ฑ๊ณต์˜ ๊ธฐ๋ก +[**English**](./BURST_DMA.md) | [**ํ•œ๊ตญ์–ด**] +[โฌ…๏ธ README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md) + +์ด ๋ฌธ์„œ๋Š” DE10-Nano ๋น„๋””์˜ค ํ”„๋กœ์„ธ์‹ฑ ํ”„๋กœ์ ํŠธ๋ฅผ ์œ„ํ•œ DDR3 ์—ฐ๊ฒฐ ์ „๋žต์˜ ๊ธฐ์ˆ ์  ๊ณผ์ œ์™€ ๋ฐœ์ „ ๊ณผ์ •์„ ๊ธฐ๋กํ•ฉ๋‹ˆ๋‹ค. + +## 1. ์ดˆ๊ธฐ ๋ฌธ์ œ: "DDR ํ–‰(Hang)" ํ˜„์ƒ +Nios II ๋˜๋Š” ๋ฒ„์ŠคํŠธ ๋งˆ์Šคํ„ฐ๊ฐ€ **FPGA-to-SDRAM Bridge (Port 0)**๋ฅผ ํ†ตํ•ด DDR3๋ฅผ ์ฝ์œผ๋ ค๊ณ  ์‹œ๋„ํ•  ๋•Œ ์ „์ฒด Avalon ๋ฒ„์Šค๊ฐ€ ๋ฉˆ์ถ”๋Š” ํ˜„์ƒ์ด ๋ฐœ์ƒํ–ˆ์Šต๋‹ˆ๋‹ค. JTAG UART๊ฐ€ ์‘๋‹ต์„ ๋ฉˆ์ถ”๊ณ  Nios II ํ”„๋กœ์„ธ์„œ๊ฐ€ ์ •์ง€๋˜์—ˆ์Šต๋‹ˆ๋‹ค. + +### ๐Ÿ” ์ง„๋‹จ ๋ฐ ํ™•์ธ +- **๋ ˆ์ง€์Šคํ„ฐ ์ ๊ฒ€**: HPS `sysmgr.f2s_port_en` ๋ ˆ์ง€์Šคํ„ฐ๋Š” ์–ด๋–ค FPGA-to-SDRAM ํฌํŠธ๋ฅผ ํ™œ์„ฑํ™”ํ• ์ง€ ์ œ์–ดํ•ฉ๋‹ˆ๋‹ค. + - **์˜ˆ์ƒ ๊ฐ’**: ํฌํŠธ 0์€ `0x01`, ํฌํŠธ 1์€ `0x02`, ์„ธ ๊ฐœ ๋ชจ๋‘๋Š” `0x07`. + - **๊ฒฐ๊ณผ**: ํ”„๋ฆฌ๋กœ๋”(U-Boot SPL)๊ฐ€ ์ด ๊ฐ’์„ `0x02`(ํฌํŠธ 1๋งŒ ์‚ฌ์šฉ)๋กœ ๊ณ ์ •ํ•ด๋‘์—ˆ์Šต๋‹ˆ๋‹ค. ํฌํŠธ 0์„ ์‚ฌ์šฉํ–ˆ๊ธฐ ๋•Œ๋ฌธ์— ์‹œ์Šคํ…œ์ด ๋ฉˆ์ถ˜ ๊ฒƒ์ด์—ˆ์Šต๋‹ˆ๋‹ค! + +#### ํฌํŠธ ์ƒํƒœ ํ™•์ธ ๋ฐฉ๋ฒ• +1. **U-Boot์—์„œ**: + ```bash + # f2s_port_en ๋ ˆ์ง€์Šคํ„ฐ(0xffd08040)์—์„œ 1์›Œ๋“œ ์ฝ๊ธฐ + md 0xffd08040 1 + ``` +2. **๋ฆฌ๋ˆ…์Šค์—์„œ**: + ```bash + # devmem2 ์œ ํ‹ธ๋ฆฌํ‹ฐ ์‚ฌ์šฉ + devmem2 0xffd08040 + ``` + +--- + +### ๐Ÿ› ๏ธ ๋ถ€ํŒ… ์„ค์ •: ๋ถ€ํŒ… ์ธ์ž (bootargs) +`mem=512M`๊ณผ ๊ฐ™์€ ๋ฉ”๋ชจ๋ฆฌ ์˜ˆ์•ฝ์€ HPS๊ฐ€ ๋น„๋””์˜ค ๋ฒ„ํผ๋ฅผ ๋ฎ์–ด์“ฐ์ง€ ์•Š๋„๋ก ํ•˜๋Š” ๋ฐ ๋งค์šฐ ์ค‘์š”ํ•ฉ๋‹ˆ๋‹ค. + +#### 1. U-Boot์—์„œ (๋Œ€ํ™”ํ˜•) +U-Boot ํ”„๋กฌํ”„ํŠธ์—์„œ ๋ณ€์ˆ˜๋ฅผ ์ง์ ‘ ์ œ์–ดํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค: +- **ํ™•์ธ**: `printenv bootargs` +- **์„ค์ •**: `setenv bootargs 'console=ttyS0,115200 mem=512M root=${mmcroot} rw rootwait'` +- **์ €์žฅ**: `saveenv` (์˜๊ตฌ ๋ณ€๊ฒฝ) + +#### 2. ๋ฆฌ๋ˆ…์Šค์—์„œ (์ •์ ) +๋ถ€ํŠธ๋กœ๋”๋Š” ๋ณดํ†ต SD ์นด๋“œ์˜ FAT ํŒŒํ‹ฐ์…˜์— ์žˆ๋Š” `uEnv.txt`๋ฅผ ์ฝ์Šต๋‹ˆ๋‹ค. +- **์œ„์น˜**: /mnt/boot/uEnv.txt (๋˜๋Š” ์œ ์‚ฌํ•œ ๊ฒฝ๋กœ) +- **๋‚ด์šฉ**: `mmcbootargs` ๋˜๋Š” `bootargs`๋กœ ์‹œ์ž‘ํ•˜๋Š” ๋ผ์ธ์„ ์ฐพ์œผ์„ธ์š”. +- **ํ˜„์žฌ ์ธ์ž ํ™•์ธ**: `cat /proc/cmdline` + +--- + +## 2. ์‹œ๋„ 1: SDRAM ํฌํŠธ 1๋กœ ์ „ํ™˜ +`f2h_sdram0` ๋Œ€์‹  `f2h_sdram1`์„ ์‚ฌ์šฉํ•˜๋„๋ก Qsys๋ฅผ ์ˆ˜์ •ํ–ˆ์Šต๋‹ˆ๋‹ค. +- **๊ฒฐ๊ณผ**: ์—ฌ์ „ํžˆ ์‹คํŒจ. +- **๊ฑธ๋ฆผ๋Œ**: ๋ฆฌ๋ˆ…์Šค ์ปค๋„์˜ `fpga_bridge` ๋“œ๋ผ์ด๋ฒ„(ํŠนํžˆ `br3`)๊ฐ€ ๋ช…์‹œ์ ์œผ๋กœ ํ™œ์„ฑํ™”๋˜์ง€ ์•Š์œผ๋ฉด ๋ธŒ๋ฆฟ์ง€๋ฅผ ๋ฆฌ์…‹ ์ƒํƒœ๋กœ ์œ ์ง€ํ•ฉ๋‹ˆ๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ `/sys/class/fpga_bridge`๋ฅผ ํ†ตํ•œ ๋ธŒ๋ฆฟ์ง€ ์ œ์–ด๋Š” ๋ฃจํŠธ ๊ถŒํ•œ์ด๋‚˜ ํ”„๋ฆฌ๋กœ๋” ์ˆ˜์ • ์—†์ด๋Š” ์ž ๊ฒจ ์žˆ๊ฑฐ๋‚˜ ์ ‘๊ทผ์ด ๋ถˆ๊ฐ€๋Šฅํ–ˆ์Šต๋‹ˆ๋‹ค. + +--- + +## 3. ์‹œ๋„ 2: F2H AXI ๋ธŒ๋ฆฟ์ง€๋กœ ์žฌ๋ฐฐ์น˜ (์„ฑ๊ณต!) +์ „์šฉ SDRAM ํฌํŠธ๋ฅผ ํฌ๊ธฐํ•˜๊ณ  **FPGA-to-HPS AXI Slave Bridge**๋กœ ์ „ํ™˜ํ–ˆ์Šต๋‹ˆ๋‹ค. +- **์ „๋žต**: Qsys์—์„œ AXI ๋ธŒ๋ฆฟ์ง€๋ฅผ ํ™œ์„ฑํ™”ํ•˜๊ณ  ๋ชจ๋“  DDR3 ํŠธ๋ž˜ํ”ฝ์„ HPS L3 ์ธํ„ฐ์ปค๋„ฅํŠธ๋ฅผ ํ†ตํ•ด ๋ผ์šฐํŒ…ํ•ฉ๋‹ˆ๋‹ค. +- **๊ฒฐ๊ณผ**: **์„ฑ๊ณต**. AXI ๋ธŒ๋ฆฟ์ง€๋Š” ์ผ๋ฐ˜์ ์œผ๋กœ GHRD ํ™˜๊ฒฝ์—์„œ ์ดˆ๊ธฐํ™”๋˜์–ด ๊ฐœ๋ฐฉ๋˜์–ด ์žˆ์œผ๋ฏ€๋กœ DDR3์— ๋Œ€ํ•œ ์‹ ๋ขฐํ•  ์ˆ˜ ์žˆ๋Š” ์–‘๋ฐฉํ–ฅ ๊ฒฝ๋กœ๋ฅผ ์ œ๊ณตํ•ฉ๋‹ˆ๋‹ค. + +--- + +## 4. ์†Œํ”„ํŠธ์›จ์–ด ๊ตฌํ˜„ ์‹œ ๊ณผ์ œ + +### ๐Ÿ›‘ ๊ณผ์ œ 1: "์ž๊ฐ€ ํŒŒ๊ดด" ๋ฒ„๊ทธ (OCM ๋ฎ์–ด์“ฐ๊ธฐ) +- **๋ฌธ์ œ**: ์ดˆ๊ธฐ ํ…Œ์ŠคํŠธ ์ฝ”๋“œ๊ฐ€ ๋ฐ์ดํ„ฐ๋ฅผ `ONCHIP_MEMORY2_0_BASE` (0x0) ์ฃผ์†Œ์— ์ผ์Šต๋‹ˆ๋‹ค. +- **์˜ค๋ฅ˜**: Nios II์˜ ๋ฆฌ์…‹ ๋ฒกํ„ฐ์™€ ์ฝ”๋“œ๋Š” ์ฃผ์†Œ `0x0`์— ์œ„์น˜ํ•ฉ๋‹ˆ๋‹ค. ๋ฒ„์ŠคํŠธ ๋งˆ์Šคํ„ฐ ๋ฒค์น˜๋งˆํฌ๊ฐ€ Nios II๊ฐ€ ์‹คํ–‰ ์ค‘์ธ ๋ช…๋ น์–ด๋ฅผ ๋ฎ์–ด์“ฐ๋ฉด์„œ ํฌ๋ž˜์‹œ๊ฐ€ ๋ฐœ์ƒํ–ˆ์Šต๋‹ˆ๋‹ค. +- **ํ•ด๊ฒฐ์ฑ…**: **์ •์  ์ „์—ญ ๋ฐฐ์—ด**(`src_buffer`)์„ ์‚ฌ์šฉํ•˜์—ฌ ๋ง์ปค๊ฐ€ ์•ˆ์ „ํ•œ ๋ฉ”๋ชจ๋ฆฌ ์œ„์น˜๋ฅผ ํ• ๋‹นํ•˜๋„๋ก ํ–ˆ์Šต๋‹ˆ๋‹ค. + +### ๐Ÿ›‘ ๊ณผ์ œ 2: ์บ์‹œ ์ผ๊ด€์„ฑ (๋ณด์ด์ง€ ์•Š๋Š” ๋ฐ์ดํ„ฐ) +- **๋ฌธ์ œ**: Nios II๊ฐ€ OCM์— ๋ฐ์ดํ„ฐ๋ฅผ ์ผ์ง€๋งŒ, ๋ฒ„์ŠคํŠธ ๋งˆ์Šคํ„ฐ(ํ•˜๋“œ์›จ์–ด)๊ฐ€ ์ด์ „ ๊ฐ’์ด๋‚˜ ๋žœ๋คํ•œ ๋ฐ์ดํ„ฐ๋ฅผ ์ฝ์—ˆ์Šต๋‹ˆ๋‹ค. +- **์›์ธ**: ๋ฐ์ดํ„ฐ๊ฐ€ Nios II ๋ฐ์ดํ„ฐ ์บ์‹œ์—๋งŒ ๋จธ๋ฌผ๋Ÿฌ ์žˆ๊ณ  ๋ฌผ๋ฆฌ์ ์ธ OCM RAM์—๋Š” ์•„์ง ๊ธฐ๋ก๋˜์ง€ ์•Š์•˜๊ธฐ ๋•Œ๋ฌธ์ž…๋‹ˆ๋‹ค. +- **ํ•ด๊ฒฐ์ฑ…**: DMA ๋™์ž‘์„ ํŠธ๋ฆฌ๊ฑฐํ•˜๊ธฐ ์ „์— `alt_dcache_flush_all()`์„ ์ถ”๊ฐ€ํ–ˆ์Šต๋‹ˆ๋‹ค. + +### ๐Ÿ›‘ ๊ณผ์ œ 3: ๋ฉ”๋ชจ๋ฆฌ ์šฉ๋Ÿ‰ ์ œํ•œ +- **๋ฌธ์ œ**: 64KB ํ…Œ์ŠคํŠธ ๋ฒ„ํผ ์‚ฌ์šฉ ์‹œ ๋ง์ปค ์˜ค๋ฅ˜(`section .bss is not within region onchip_memory2_0`)๊ฐ€ ๋ฐœ์ƒํ–ˆ์Šต๋‹ˆ๋‹ค. +- **์›์ธ**: DE10-Nano GHRD์˜ OCM์€ ์•ฝ 100KB์ž…๋‹ˆ๋‹ค. ์ฝ”๋“œ + ์Šคํƒ + 64KB ๋ฒ„ํผ๋Š” ์šฉ๋Ÿ‰์„ ์ดˆ๊ณผํ–ˆ์Šต๋‹ˆ๋‹ค. +- **ํ•ด๊ฒฐ์ฑ…**: ๋ฒ„ํผ๋ฅผ **4KB**๋กœ ์ค„์ด๊ณ  ํ…Œ์ŠคํŠธ๋ฅผ **100๋ฒˆ ๋ฐ˜๋ณต**ํ•˜์—ฌ ํƒ€์ด๋ฐ ์ •ํ™•๋„๋ฅผ ์œ ์ง€ํ–ˆ์Šต๋‹ˆ๋‹ค. + +--- + +## 5. ์ตœ์ข… ๊ฒฐ๊ณผ ๋ฐ ๋ฒค์น˜๋งˆํฌ +ํ•˜๋“œ์›จ์–ด ๊ตฌ๋™ DMA๋กœ ์ „ํ™˜ํ•˜๋ฉด์„œ ์„ฑ๋Šฅ์ด ๋น„์•ฝ์ ์œผ๋กœ ํ–ฅ์ƒ๋˜์—ˆ์Šต๋‹ˆ๋‹ค. 4KB ์ „์†ก์„ **100๋ฒˆ ๋ฐ˜๋ณต**ํ•˜์—ฌ ์†Œํ”„ํŠธ์›จ์–ด์™€ ํ•˜๋“œ์›จ์–ด ๊ฒฝ๋กœ ๋ชจ๋‘์— ๋Œ€ํ•ด ์•ˆ์ •์ ์ธ ์ง€ํ‘œ๋ฅผ ์–ป์—ˆ์Šต๋‹ˆ๋‹ค. + +### ๐Ÿ“Š ๋น„๊ต ๋ถ„์„ +| ๋ฐฉ๋ฒ• | ์ด ๋ฐ์ดํ„ฐ | ์‹œ๊ฐ„ (ms) | ์ฒ˜๋ฆฌ๋Ÿ‰ (MB/s) | +| :--- | :--- | :--- | :--- | +| **์†Œํ”„ํŠธ์›จ์–ด ๋ณต์‚ฌ** (CPU ๋ฃจํ”„) | 400 KB | 90.00 ms | 4.55 MB/s | +| **๋ฒ„์ŠคํŠธ ๋งˆ์Šคํ„ฐ (DMA)** | **400 KB** | **3.00 ms** | **136.53 MB/s** | + +### ์™œ `burst_master`๊ฐ€ ํ›จ์”ฌ ๋น ๋ฅธ๊ฐ€์š”? +1. **๋ฒ„์ŠคํŠธ ์ „์†ก**: ํ‘œ์ค€ Nios II I/O ๋ช…๋ น์–ด๋Š” ๋‹จ์ผ ๋น„ํŠธ ํŠธ๋žœ์žญ์…˜(์ฃผ์†Œ -> ๋ฐ์ดํ„ฐ)์„ ์ˆ˜ํ–‰ํ•ฉ๋‹ˆ๋‹ค. ๋ฐ˜๋ฉด `burst_master`๋Š” **์ฃผ์†Œ ํ•˜๋‚˜**๋ฅผ ๋ณด๋‚ด๊ณ  **์ตœ๋Œ€ 64๊ฐœ์˜ ๋ฐ์ดํ„ฐ ์›Œ๋“œ**๋ฅผ ์—ฐ์†ํ•ด์„œ ์ฝ๊ฑฐ๋‚˜ ์จ์„œ ๋ฒ„์Šค ์ ์œ ์œจ์„ ๊ทน๋Œ€ํ™”ํ•ฉ๋‹ˆ๋‹ค. +2. **์ „์šฉ ํ•˜๋“œ์›จ์–ด**: Nios II๊ฐ€ ๋ช…๋ น์–ด๋ฅผ ๊ฐ€์ ธ์˜ค๊ณ  ๋ฃจํ”„ ์นด์šดํ„ฐ๋ฅผ ๊ด€๋ฆฌํ•˜๋Š๋ผ ๋ฐ”์œ ๋™์•ˆ, `burst_master`๋Š” ์ˆœ์ˆ˜ํ•˜๊ฒŒ ๋ฐ์ดํ„ฐ ๊ตฌ๋™ ๋ฐฉ์‹์œผ๋กœ ๋™์ž‘ํ•˜๋ฉฐ ๋‚ด๋ถ€ FIFO๋ฅผ ํ™œ์šฉํ•ด ๋ฒ„ํผ๋ง๊ณผ ํŒŒ์ดํ”„๋ผ์ด๋‹์„ ์ˆ˜ํ–‰ํ•ฉ๋‹ˆ๋‹ค. +3. **AXI ๋ธŒ๋ฆฟ์ง€ ํšจ์œจ์„ฑ**: FPGA-to-HPS AXI ๋ธŒ๋ฆฟ์ง€๋Š” ๊ณ ์„ฑ๋Šฅ ๋ฒ„์ŠคํŠธ์— ์ตœ์ ํ™”๋˜์–ด ์žˆ์–ด, ํ•˜๋“œ์›จ์–ด ๋งˆ์Šคํ„ฐ๊ฐ€ ๋™์ผํ•œ ๊ฒฝ๋กœ๋ฅผ ํ†ตํ•œ ์†Œํ”„ํŠธ์›จ์–ด ๋งˆ์Šคํ„ฐ์˜ ๋‹จ์ผ ๋น„ํŠธ ์•ก์„ธ์Šค๋ณด๋‹ค ํ›จ์”ฌ ๋‚ฎ์€ ์ง€์—ฐ ์‹œ๊ฐ„์œผ๋กœ DDR3์— ๋„๋‹ฌํ•  ์ˆ˜ ์žˆ๊ฒŒ ํ•ด์ค๋‹ˆ๋‹ค. + +--- + +## 6. 2๋‹จ๊ณ„: DDR-to-DDR ํŒŒ์ดํ”„๋ผ์ธ DMA ๋ฐ ๋ฉ”๋ชจ๋ฆฌ ๋ณดํ˜ธ +๋‹จ์ˆœํ•œ ๋ฐ์ดํ„ฐ ์ „์†ก์„ ๋„˜์–ด, 4๋‹จ๊ณ„ ์‚ฐ์ˆ  ํŒŒ์ดํ”„๋ผ์ธ์„ ํฌํ•จํ•˜๋Š” `burst_master_4`๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ํ”ฝ์…€ ์ฒ˜๋ฆฌ ์„ฑ๋Šฅ์„ ์ธก์ •ํ–ˆ์Šต๋‹ˆ๋‹ค. ์ด ํ…Œ์ŠคํŠธ๋Š” ๊ณ„์ˆ˜๋ฅผ ๊ณฑํ•œ ๋’ค 400์œผ๋กœ ๋‚˜๋ˆ„๋Š” ์—ฐ์‚ฐ(`Pixel_Out = (Pixel_In * Coeff) / 400`)์„ ์ˆ˜ํ–‰ํ•˜๋ฉฐ, ์ด๋Š” ๋น„๋””์˜ค ํ•„ํ„ฐ ๋ฐ ์ƒ‰ ๊ณต๊ฐ„ ๋ณ€ํ™˜ ์•Œ๊ณ ๋ฆฌ์ฆ˜์˜ ๊ธฐ์ดˆ๊ฐ€ ๋ฉ๋‹ˆ๋‹ค. ๋˜ํ•œ HPS(ARM/๋ฆฌ๋ˆ…์Šค) ์‹œ์Šคํ…œ ์˜์—ญ์„ ์นจ๋ฒ”ํ•˜์ง€ ์•Š๊ธฐ ์œ„ํ•ด ๋ฉ”๋ชจ๋ฆฌ ๋ณดํ˜ธ ์ „๋žต์„ ๊ตฌํ˜„ํ–ˆ์Šต๋‹ˆ๋‹ค. + +### ๐Ÿ›‘ ๊ณผ์ œ 4: HPS ๋ฉ”๋ชจ๋ฆฌ ์ถฉ๋Œ (0x0 ์ฃผ์†Œ) +- **๋ฌธ์ œ**: ๋ฌผ๋ฆฌ ์ฃผ์†Œ 0x0์€ ARM ๋ฒกํ„ฐ ํ…Œ์ด๋ธ”๊ณผ ์ปค๋„์„ ์œ„ํ•ด ์˜ˆ์•ฝ๋˜์–ด ์žˆ์Šต๋‹ˆ๋‹ค. DMA๋ฅผ ํ†ตํ•ด ์ด ์˜์—ญ์— ์“ฐ๊ธฐ๋ฅผ ์‹œ๋„ํ•˜๋ฉด ์ฆ‰๊ฐ์ ์ธ ์‹œ์Šคํ…œ ํฌ๋ž˜์‹œ๊ฐ€ ๋ฐœ์ƒํ•ฉ๋‹ˆ๋‹ค. +- **ํ•ด๊ฒฐ์ฑ…**: ๋ชจ๋“  DMA ํ…Œ์ŠคํŠธ ์ฃผ์†Œ๋ฅผ **512MB (0x20000000)**๋ถ€ํ„ฐ ์‹œ์ž‘ํ•˜๋Š” ์•ˆ์ „ํ•œ ์˜์—ญ์œผ๋กœ ์˜ฎ๊ฒผ์Šต๋‹ˆ๋‹ค. +- **๊ตฌํ˜„**: ์‹œ์ž‘ ์‹œ `Address Span Extender` ์œˆ๋„์šฐ ๋ฒ ์ด์Šค๋ฅผ `0x20000000`์œผ๋กœ ์ดˆ๊ธฐํ™”ํ•˜์—ฌ Nios II์™€ ํ•˜๋“œ์›จ์–ด DMA ๊ฐ„์˜ ์ •๋ ฌ์„ ๋ณด์žฅํ–ˆ์Šต๋‹ˆ๋‹ค. + +### ๐Ÿ“Š DDR-to-DDR ๋ฒค์น˜๋งˆํฌ (1 MB) +| ๋ฐฉ๋ฒ• | ์ „์†ก ํฌ๊ธฐ | ์‹œ๊ฐ„ | ์ฒ˜๋ฆฌ๋Ÿ‰ | ์†๋„ ํ–ฅ์ƒ | +| :--- | :--- | :--- | :--- | :--- | +| **์†Œํ”„ํŠธ์›จ์–ด ๋ณต์‚ฌ** (๋‚˜๋ˆ—์…ˆ ํฌํ•จ) | 1 MB | 4.683 s | 0.21 MB/s | ๊ธฐ์ค€์  | +| **ํ•˜๋“œ์›จ์–ด DMA** (4๋‹จ๊ณ„) | **1 MB** | **0.008 s** | **125.00 MB/s** | **์•ฝ 585๋ฐฐ** | + +--- + +## 7. ๊ฒฐ๋ก  +**AXI ๋ธŒ๋ฆฟ์ง€**์™€ **๋ฒ„์ŠคํŠธ ๋งˆ์Šคํ„ฐ DMA**์˜ ์กฐํ•ฉ์€ DE10-Nano์—์„œ DDR3 ๋ฆฌ์†Œ์Šค๋ฅผ ํ™œ์šฉํ•˜๋Š” ๊ฐ€์žฅ ์•ˆ์ •์ ์ด๊ณ  ๊ณ ์„ฑ๋Šฅ์ธ ๋ฐฉ๋ฒ•์ž…๋‹ˆ๋‹ค. ๊ฒ€์ฆ๋œ 125 MB/s์˜ ์ฒ˜๋ฆฌ๋Ÿ‰์€ ์‹ค์‹œ๊ฐ„ 720p HD ๋น„๋””์˜ค ์ŠคํŠธ๋ฆฌ๋ฐ์— ์ถฉ๋ถ„ํ•˜๋ฉฐ, ์‚ฐ์ˆ  ํŒŒ์ดํ”„๋ผ์ธ๊ณผ์˜ ์„ฑ๊ณต์ ์ธ ํ†ตํ•ฉ์€ ๊ณ ๊ธ‰ ์ด๋ฏธ์ง€ ์ฒ˜๋ฆฌ ์ž‘์—…์— ๋Œ€ํ•œ ์ค€๋น„๊ฐ€ ๋˜์—ˆ์Œ์„ ์ž…์ฆํ•ฉ๋‹ˆ๋‹ค. + +--- + +## ๋ถ€๋ก: ๋ฆฌ๋ˆ…์Šค HPS FPGA-to-SDRAM ๋ธŒ๋ฆฟ์ง€ ์ „์—ญ ์ˆ˜์ • ๋ฐฉ๋ฒ• +์‹œ์Šคํ…œ ์•ˆ์ •์„ฑ์„ ์œ„ํ•ด ๋ถ€ํŠธ๋กœ๋”(U-Boot)์—์„œ ๋ธŒ๋ฆฟ์ง€ ํฌํŠธ๋ฅผ ๋น„ํ™œ์„ฑํ™”ํ•˜๊ฑฐ๋‚˜ ๋ฆฌ์…‹ ์ƒํƒœ๋กœ ๋‘๋Š” ๊ฒฝ์šฐ๊ฐ€ ๋งŽ์Šต๋‹ˆ๋‹ค. Qsys ์„ค์ •์ด ์˜ฌ๋ฐ”๋ฅธ๋ฐ๋„ DMA๊ฐ€ ๋ฉˆ์ถ˜๋‹ค๋ฉด, ์ด ๋ฆฌ๋ˆ…์Šค C ํ”„๋กœ๊ทธ๋žจ์„ ์‚ฌ์šฉํ•˜์—ฌ ํฌํŠธ ๋ฆฌ์…‹์„ ๊ฐ•์ œ๋กœ ํ•ด์ œํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. + +### [์ˆ˜์ • ์ฝ”๋“œ] bridge_fix.c +```c +#include +#include +#include +#include + +#define REG_BASE 0xFFC20000 // SDR ์ปจํŠธ๋กค๋Ÿฌ ๋ฒ ์ด์Šค ์ฃผ์†Œ +#define REG_SPAN 0x10000 +#define RESET_REG_OFFSET 0x5080 // fpgaportrst ๋ ˆ์ง€์Šคํ„ฐ +#define PORT_EN_OFFSET 0x505C // f2s_port_en ๋ ˆ์ง€์Šคํ„ฐ + +int main() { + int fd; + void *map_base; + volatile unsigned int *reset_reg; + volatile unsigned int *port_en_reg; + + fd = open("/dev/mem", O_RDWR | O_SYNC); + // ... (์ƒ๋žต) + + reset_reg = (volatile unsigned int *)(map_base + RESET_REG_OFFSET); + port_en_reg = (volatile unsigned int *)(map_base + PORT_EN_OFFSET); + + // 1. ๋ชจ๋“  ํฌํŠธ์˜ ๋ฆฌ์…‹ ํ•ด์ œ (fpgaportrst์— 0 ์“ฐ๊ธฐ) + if (*reset_reg != 0) { + *reset_reg = 0x00000000; + } + // ... (์ƒ๋žต) + return 0; +} +``` + +> [!IMPORTANT] +> **ํ˜„์žฌ AXI ๋ธŒ๋ฆฟ์ง€ ์„ค์ •์—์„œ๋„ ์ด ์ฝ”๋“œ๊ฐ€ ํ•„์š”ํ•œ๊ฐ€์š”?** +> ์—„๋ฐ€ํžˆ ๋งํ•˜๋ฉด **์•„๋‹ˆ์š”.** ์„ฑ๊ณตํ•œ '์‹œ๋„ 2'๋Š” ์ด๋Ÿฌํ•œ ์ „์šฉ SDRAM ํฌํŠธ ์ œ์–ด๋ฅผ ์šฐํšŒํ•˜๋Š” **FPGA-to-HPS AXI Slave Bridge**๋ฅผ ์‚ฌ์šฉํ–ˆ์Šต๋‹ˆ๋‹ค. ์ด๊ฒƒ์ด ์‹œ๋„ 2๊ฐ€ ์ฆ‰์‹œ ์„ฑ๊ณตํ•œ ์ด์œ ์ž…๋‹ˆ๋‹ค! +> +> **๊ทธ๋Ÿผ ์™œ ์ด ๋‚ด์šฉ์„ ๋‚จ๊ฒจ๋‘์—ˆ๋‚˜์š”?** +> 1. **์‹œ๋„ 1 ์‚ฌํ›„ ๋ถ„์„**: ํฌํŠธ 0์„ ์‚ฌ์šฉํ•œ ์ฒซ ์‹œ๋„๊ฐ€ ์™œ ๋ฉˆ์ท„๋Š”์ง€ ์ •ํ™•ํžˆ ์„ค๋ช…ํ•ด์ค๋‹ˆ๋‹ค. +> 2. **์„ฑ๋Šฅ ํŠœ๋‹**: ์ „์šฉ SDRAM ํฌํŠธ๋Š” AXI ๋ธŒ๋ฆฟ์ง€๋ณด๋‹ค ์ง€์—ฐ ์‹œ๊ฐ„์ด ๋” ์งง์Šต๋‹ˆ๋‹ค. ๋‚˜์ค‘์— ๊ทนํ•œ์˜ DDR3 ์„ฑ๋Šฅ์ด ํ•„์š”ํ•˜๋‹ค๋ฉด ์ด ํฌํŠธ๋“ค๊ณผ ์ด ์ˆ˜์ • ์ฝ”๋“œ๊ฐ€ ํ•„์š”ํ•  ๊ฒƒ์ž…๋‹ˆ๋‹ค! diff --git a/doc/DESIGN.md b/doc/DESIGN.md index 62ca38c..689d541 100644 --- a/doc/DESIGN.md +++ b/doc/DESIGN.md @@ -1,4 +1,5 @@ # Design Specification: HDMI Video Pipeline +[**English**] | [**ํ•œ๊ตญ์–ด**](./DESIGN_kor.md) [โฌ…๏ธ Back to README](../README.md) Specification diff --git a/doc/DESIGN_kor.md b/doc/DESIGN_kor.md new file mode 100644 index 0000000..546e0bd --- /dev/null +++ b/doc/DESIGN_kor.md @@ -0,0 +1,73 @@ +# ์„ค๊ณ„ ์‚ฌ์–‘: HDMI ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ +[**English**](./DESIGN.md) | [**ํ•œ๊ตญ์–ด**] +[โฌ…๏ธ README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md) + +์ด ๋ฌธ์„œ๋Š” DE10-Nano ํ”Œ๋žซํผ์—์„œ HPS DDR3 ๋ฉ”๋ชจ๋ฆฌ๋กœ๋ถ€ํ„ฐ HDMI ๋””์Šคํ”Œ๋ ˆ์ด ์ธํ„ฐํŽ˜์ด์Šค๋กœ ๋น„๋””์˜ค ๋ฐ์ดํ„ฐ๋ฅผ ์ŠคํŠธ๋ฆฌ๋ฐํ•˜๊ธฐ ์œ„ํ•œ ์•„ํ‚คํ…์ฒ˜ ๋ฐ ๊ธฐ์ˆ  ์„ค๊ณ„๋ฅผ ์„ค๋ช…ํ•ฉ๋‹ˆ๋‹ค. + +## 1. ์‹œ์Šคํ…œ ์•„ํ‚คํ…์ฒ˜ ๋ฐ ๋ฐ์ดํ„ฐ ํ๋ฆ„ + +์‹ค์‹œ๊ฐ„ ์„ฑ๋Šฅ์„ ๋ณด์žฅํ•˜๊ธฐ ์œ„ํ•ด ๋น„๋””์˜ค ๋ฐ์ดํ„ฐ๋Š” ๊ณ ๋Œ€์—ญํญ ๊ฒฝ๋กœ๋ฅผ ํ†ตํ•ด ์ „์†ก๋ฉ๋‹ˆ๋‹ค: +**SD ์นด๋“œ (ARM/๋ฆฌ๋ˆ…์Šค) โžก๏ธ DDR3 ๋ฉ”๋ชจ๋ฆฌ โžก๏ธ ๋น„๋””์˜ค DMA (FPGA) โžก๏ธ HDMI TX (ADV7513)** + +```mermaid +graph LR + subgraph "HPS (ARM Cortex-A9)" + SD[SD ์นด๋“œ ์ด๋ฏธ์ง€] --> SW_Load[์ด๋ฏธ์ง€ ๋กœ๋”] + SW_Load --> DDR[DDR3 ๋ฉ”๋ชจ๋ฆฌ] + end + + subgraph "FPGA (๋กœ์ง)" + DDR --> AXI[F2H AXI ๋ธŒ๋ฆฟ์ง€] + AXI --> V_DMA[๋น„๋””์˜ค DMA ๋งˆ์Šคํ„ฐ] + V_DMA --> FIFO[๋น„๋””์˜ค FIFO] + FIFO --> SGEN[์ปค์Šคํ…€ ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ] + end + + subgraph "์‹œ์Šคํ…œ ์ œ์–ด" + Nios[Nios II ํ”„๋กœ์„ธ์„œ] + Nios --> I2C[I2C ๋งˆ์Šคํ„ฐ] + Nios --> PLL_R[PLL ์žฌ์„ค์ •] + I2C -.-> HDMI_Chip[ADV7513 HDMI TX] + PLL_R -.-> P_CLK[ํ”ฝ์…€ ํด๋ก PLL] + end + + SGEN --> HDMI_Chip + P_CLK --> SGEN +``` + +--- + +## 2. ๊ตฌ์„ฑ ์š”์†Œ๋ณ„ ์—ญํ•  + +### HPS (ARM/๋ฆฌ๋ˆ…์Šค ์ฝ”์–ด) +- **๋ฐ์ดํ„ฐ ํš๋“**: SCP๋ฅผ ํ†ตํ•ด SD ์นด๋“œ๋กœ๋ถ€ํ„ฐ ์ด๋ฏธ์ง€/๋น„๋””์˜ค ์†Œ์Šค๋ฅผ ๋ฆฌ๋ˆ…์Šค ํŒŒ์ผ ์‹œ์Šคํ…œ์œผ๋กœ ์ „์†กํ•ฉ๋‹ˆ๋‹ค. +- **๋ฉ”๋ชจ๋ฆฌ ๋งคํ•‘**: DDR3 ๋ฉ”๋ชจ๋ฆฌ๋ฅผ ์‚ฌ์šฉ์ž ๊ณต๊ฐ„์— ๋งคํ•‘ํ•˜๊ณ , ๋ฏธ๋ฆฌ ์ •์˜๋œ ์˜ˆ์•ฝ ์˜์—ญ(์˜ˆ: 32MB ์˜คํ”„์…‹)์— ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๋ฅผ ์”๋‹ˆ๋‹ค. +- **๊ณ ๋Œ€์—ญํญ**: ARM๊ณผ FPGA ๋กœ์ง ๊ฐ„์˜ ํšจ์œจ์ ์ธ ๋ฐ์ดํ„ฐ ๊ณต์œ ๋ฅผ ์œ„ํ•ด FPGA-to-HPS AXI ๋ธŒ๋ฆฟ์ง€๋ฅผ ํ™œ์šฉํ•ฉ๋‹ˆ๋‹ค. + +### Nios II ํ”„๋กœ์„ธ์„œ (์ œ์–ด ๊ณ„์ธต) +- **์ฃผ๋ณ€ ์žฅ์น˜ ๊ตฌ์„ฑ**: I2C ๋งˆ์Šคํ„ฐ๋ฅผ ํ†ตํ•ด ADV7513 HDMI ํŠธ๋žœ์Šค๋ฏธํ„ฐ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ์ดˆ๊ธฐํ™”ํ•ฉ๋‹ˆ๋‹ค (์ „์› ๊ด€๋ฆฌ, ์ปฌ๋Ÿฌ ํฌ๋งท ์„ค์ • ๋“ฑ). +- **๋™์  ํ•ด์ƒ๋„ ์ œ์–ด**: `Altera PLL Reconfig` IP๋ฅผ ๊ด€๋ฆฌํ•˜์—ฌ ํ”ฝ์…€ ํด๋ก์„ ๋™์ ์œผ๋กœ ์ „ํ™˜ํ•ฉ๋‹ˆ๋‹ค (์˜ˆ: 480p์˜ ๊ฒฝ์šฐ 25.2MHz, 720p์˜ ๊ฒฝ์šฐ 74.25MHz). +- **ํŒŒ์ดํ”„๋ผ์ธ ์˜ค์ผ€์ŠคํŠธ๋ ˆ์ด์…˜**: ๋น„๋””์˜ค DMA๋ฅผ ํŠธ๋ฆฌ๊ฑฐํ•˜๊ณ  ์ „์ฒด ์‹œ์Šคํ…œ ์ƒํƒœ๋ฅผ ๋ชจ๋‹ˆํ„ฐ๋งํ•ฉ๋‹ˆ๋‹ค. + +### FPGA ํŒจ๋ธŒ๋ฆญ (๊ณ ์† ๋ฐ์ดํ„ฐ ๊ฒฝ๋กœ) +- **๋น„๋””์˜ค DMA ๋งˆ์Šคํ„ฐ (MM2ST)**: **Avalon-MM ๋งˆ์Šคํ„ฐ**๋ฅผ ํ†ตํ•ด DDR3์—์„œ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๋ฅผ ๊ฐ€์ ธ์™€ ๊ณ ์† **Avalon-ST (์ŠคํŠธ๋ฆฌ๋ฐ)** ์†Œ์Šค๋กœ ์ถœ๋ ฅํ•˜๋Š” ์ปค์Šคํ…€ DMA ๋ชจ๋“ˆ์ž…๋‹ˆ๋‹ค. +- **์ปค์Šคํ…€ ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ**: ์ŠคํŠธ๋ฆฌ๋ฐ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๋ฅผ ๋Œ€์ƒ ํ•ด์ƒ๋„์— ๋”ฐ๋ฅธ ํ‘œ์ค€ HDMI ํƒ€์ด๋ฐ ์‹ ํ˜ธ(HSync, VSync, Data Enable)๋กœ ๋ณ€ํ™˜ํ•˜๋Š” Verilog ๋ชจ๋“ˆ์ž…๋‹ˆ๋‹ค. +- **์ง€์—ฐ ์‹œ๊ฐ„ ์ตœ์ ํ™”**: F2H AXI ์Šฌ๋ ˆ์ด๋ธŒ ๋ธŒ๋ฆฟ์ง€๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ๊ธฐ์กด์˜ ๋ณ‘๋ชฉ ํ˜„์ƒ์„ ์šฐํšŒํ•˜๊ณ  100MB/s ์ด์ƒ์˜ ์•ˆ์ •์ ์ธ ์ฒ˜๋ฆฌ๋Ÿ‰์„ ๋ณด์žฅํ•ฉ๋‹ˆ๋‹ค. + +--- + +## 3. ๊ธฐ์ˆ ์  ์„ค๊ณ„ ๊ฒฐ์ • ์‚ฌํ•ญ + +1. **ARM ๊ธฐ๋ฐ˜ ๋ฐ์ดํ„ฐ ๋กœ๋”ฉ**: JTAG(HostFS) ๋Œ€๋น„ ๋น„๋””์˜ค ์žฌ์ƒ์— ํ•„์š”ํ•œ ํ›จ์”ฌ ๋” ๋†’์€ ์ „์†ก ์†๋„๋ฅผ ์ œ๊ณตํ•˜๋Š” ARM-๋ฆฌ๋ˆ…์Šค ๊ธฐ๋ฐ˜ ๋กœ๋”ฉ ๋ฐฉ์‹์„ ์„ ํƒํ–ˆ์Šต๋‹ˆ๋‹ค. +2. **์†Œํ”„ํŠธ์›จ์–ด ์ •์˜ ์ œ์–ด (Nios II)**: I2C ๋ฐ PLL ์žฌ๊ตฌ์„ฑ์„ ์†Œํ”„ํŠธ์›จ์–ด๋กœ ๊ตฌํ˜„ํ•จ์œผ๋กœ์จ, ํ•˜๋“œ์›จ์–ด๋ฅผ ์žฌ๊ตฌ์ถ•ํ•˜์ง€ ์•Š๊ณ ๋„ ๋‹ค์–‘ํ•œ ๋””์Šคํ”Œ๋ ˆ์ด ํ•ด์ƒ๋„์™€ ํƒ€์ด๋ฐ ์กฐ์ •์„ ์ง€์›ํ•  ์ˆ˜ ์žˆ๋Š” ์œ ์—ฐ์„ฑ์„ ํ™•๋ณดํ–ˆ์Šต๋‹ˆ๋‹ค. +3. **์ง์ ‘ AXI ์—ฐ๊ฒฐ**: ๋น„๋””์˜ค DMA๊ฐ€ F2H AXI ์Šฌ๋ ˆ์ด๋ธŒ ๋ธŒ๋ฆฟ์ง€์— ์ง์ ‘ ์—ฐ๊ฒฐ๋ฉ๋‹ˆ๋‹ค. ์ด๋ฅผ ํ†ตํ•ด ๊ณ ์† ๋ฐ์ดํ„ฐ ๊ฒฝ๋กœ์—์„œ Address Span Extender์˜ ํ•„์š”์„ฑ์„ ์ œ๊ฑฐํ•˜์—ฌ ์ง€์—ฐ ์‹œ๊ฐ„์„ ์ค„์ด๊ณ  HPS DDR3์˜ ๋ฌผ๋ฆฌ์  ์ฃผ์†Œ ๋งคํ•‘์„ ๊ฐ„์†Œํ™”ํ–ˆ์Šต๋‹ˆ๋‹ค. + +--- + +## 4. ๊ตฌํ˜„ ๋กœ๋“œ๋งต + +1. **Qsys ํ•˜๋“œ์›จ์–ด ํ†ตํ•ฉ**: PLL Reconfig, I2C Master, Video DMA ๋ฐ CVO IP๋ฅผ ์ถ”๊ฐ€ํ•˜๊ณ  ์—ฐ๊ฒฐํ•ฉ๋‹ˆ๋‹ค. +2. **์ตœ์ƒ์œ„ RTL ํ†ตํ•ฉ**: Qsys ์‹œ์Šคํ…œ ํฌํŠธ์™€ ๋ฌผ๋ฆฌ์  HDMI ์ถœ๋ ฅ ํ•€์„ ์—ฐ๊ฒฐํ•ฉ๋‹ˆ๋‹ค. +3. **Nios II ๋“œ๋ผ์ด๋ฒ„ ๊ฐœ๋ฐœ**: ADV7513 I2C ๋“œ๋ผ์ด๋ฒ„ ๋ฐ PLL ์ œ์–ด API๋ฅผ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. +4. **ARM ์ด๋ฏธ์ง€ ๋กœ๋”**: ์ด๋ฏธ์ง€ ๋ฒ„ํผ๋ฅผ DDR3๋กœ ์ „์†กํ•˜๊ธฐ ์œ„ํ•œ ๋ฆฌ๋ˆ…์Šค ์ธก ์œ ํ‹ธ๋ฆฌํ‹ฐ๋ฅผ ๊ฐœ๋ฐœํ•ฉ๋‹ˆ๋‹ค. +5. **์‹œ์Šคํ…œ ๊ฒ€์ฆ**: ๋‹ค์–‘ํ•œ ํ•ด์ƒ๋„์— ๋Œ€ํ•ด ํƒ€์ด๋ฐ์„ ํ™•์ธํ•˜๊ณ  ์ตœ์ข… ๋””์Šคํ”Œ๋ ˆ์ด ํ…Œ์ŠคํŠธ๋ฅผ ์ˆ˜ํ–‰ํ•ฉ๋‹ˆ๋‹ค. diff --git a/doc/NIOS.md b/doc/NIOS.md index 032d0ed..587d724 100644 --- a/doc/NIOS.md +++ b/doc/NIOS.md @@ -1,4 +1,6 @@ # Nios II Interactive Menu System +[**English**] | [**ํ•œ๊ตญ์–ด**](./NIOS_kor.md) +[โฌ…๏ธ Back to README](../README.md) This document describes the structure and functionality of the interactive console menu used for controlling the HDMI video pipeline. diff --git a/doc/NIOS_kor.md b/doc/NIOS_kor.md new file mode 100644 index 0000000..33033a9 --- /dev/null +++ b/doc/NIOS_kor.md @@ -0,0 +1,77 @@ +# Nios II ๋Œ€ํ™”ํ˜• ๋ฉ”๋‰ด ์‹œ์Šคํ…œ +[**English**](./NIOS.md) | [**ํ•œ๊ตญ์–ด**] +[โฌ…๏ธ README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md) + +์ด ๋ฌธ์„œ๋Š” HDMI ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ์„ ์ œ์–ดํ•˜๋Š” ๋ฐ ์‚ฌ์šฉ๋˜๋Š” ๋Œ€ํ™”ํ˜• ์ฝ˜์†” ๋ฉ”๋‰ด์˜ ๊ตฌ์กฐ์™€ ๊ธฐ๋Šฅ์„ ์„ค๋ช…ํ•ฉ๋‹ˆ๋‹ค. + +## ๐Ÿ“Œ ๊ฐœ์š” +์ด ์• ํ”Œ๋ฆฌ์ผ€์ด์…˜์€ JTAG UART ๊ธฐ๋ฐ˜์˜ ๋Œ€ํ™”ํ˜• ๋ฉ”๋‰ด๋ฅผ ์ œ๊ณตํ•˜์—ฌ ์‚ฌ์šฉ์ž๊ฐ€ ์‹ค์‹œ๊ฐ„์œผ๋กœ DMA ์„ฑ๋Šฅ ํ…Œ์ŠคํŠธ๋ฅผ ์ˆ˜ํ–‰ํ•˜๊ณ , ํ•˜๋“œ์›จ์–ด๋ฅผ ์ดˆ๊ธฐํ™”ํ•˜๋ฉฐ, RTL ํŒจํ„ด ์ œ๋„ค๋ ˆ์ดํ„ฐ๋ฅผ ์ œ์–ดํ•  ์ˆ˜ ์žˆ๋„๋ก ํ•ฉ๋‹ˆ๋‹ค. + +## ๐ŸŒณ ๋ฉ”๋‰ด ํŠธ๋ฆฌ ๊ตฌ์กฐ +์‹œ์Šคํ…œ์˜ ๋ณต์žก์„ฑ ์ฆ๊ฐ€์— ๋”ฐ๋ผ ๋ฉ”๋‰ด๋Š” ๊ณ„์ธต ๊ตฌ์กฐ๋กœ ๊ตฌ์„ฑ๋˜์–ด ์žˆ์Šต๋‹ˆ๋‹ค. + +### 1. ๋ฉ”์ธ ๋ฉ”๋‰ด +์‹œ์Šคํ…œ ์ „๋ฐ˜์˜ ํ…Œ์ŠคํŠธ์™€ ํ•˜๋“œ์›จ์–ด ์ดˆ๊ธฐํ™”๋ฅผ ๋‹ด๋‹นํ•˜๋Š” ์ตœ์ƒ์œ„ ๋ฉ”๋‰ด์ž…๋‹ˆ๋‹ค. + +- **[1] DMA ํ…Œ์ŠคํŠธ (OCM to DDR3)**: 4KB ๋ฐ์ดํ„ฐ ์ด๋™ ์„ฑ๋Šฅ์„ ์ธก์ •ํ•ฉ๋‹ˆ๋‹ค. +- **[2] ๋ฒ„์ŠคํŠธ ํ…Œ์ŠคํŠธ (DDR3 to DDR3)**: ํŒŒ์ดํ”„๋ผ์ธ ์ฒ˜๋ฆฌ๋ฅผ ํฌํ•จํ•œ 1MB ๋ฐ์ดํ„ฐ ์ด๋™ ์„ฑ๋Šฅ์„ ์ธก์ •ํ•ฉ๋‹ˆ๋‹ค. +- **[3] HDMI ์ดˆ๊ธฐํ™”**: I2C๋ฅผ ํ†ตํ•ด ADV7513์„ 720p ๋ชจ๋“œ๋กœ ์„ค์ •ํ•ฉ๋‹ˆ๋‹ค. +- **[4] ์ปฌ๋Ÿฌ ๋ฐ” ์ƒ์„ฑ**: DDR3 ํ”„๋ ˆ์ž„ ๋ฒ„ํผ์— ํ…Œ์ŠคํŠธ ํŒจํ„ด์„ ์ž‘์„ฑํ•ฉ๋‹ˆ๋‹ค. +- **[5] RTL ํŒจํ„ด ๋ณ€๊ฒฝ**: ๋‚ด๋ถ€ RTL ํŒจํ„ด ์ƒ์„ฑ(Red, Green, Blue ๋“ฑ)์„ ์œ„ํ•œ ํ•˜์œ„ ๋ฉ”๋‰ด์ž…๋‹ˆ๋‹ค. +- **[6] ๊ฐ๋งˆ ๋ณด์ • ์„ค์ •**: **[์‹ ๊ทœ]** LUT ๋ฐ ํ† ๊ธ€ ์ œ์–ด๋ฅผ ์œ„ํ•œ ์ค‘์ฒฉ ํ•˜์œ„ ๋ฉ”๋‰ด์ž…๋‹ˆ๋‹ค. +- **[C] ์ปค์Šคํ…€ ์บ๋ฆญํ„ฐ ๋กœ๋“œ**: ํƒ€์ผ ๋ Œ๋”๋ง์„ ์œ„ํ•œ 16x16 ๋น„ํŠธ๋งต์„ ์—…๋กœ๋“œํ•ฉ๋‹ˆ๋‹ค. +- **[r] RTL ๋ฆฌ์…‹**: ํŒจํ„ด ์ œ๋„ค๋ ˆ์ดํ„ฐ๋ฅผ ๊ธฐ๋ณธ ์ƒํƒœ๋กœ ๋˜๋Œ๋ฆฝ๋‹ˆ๋‹ค. +- **[q] ์ข…๋ฃŒ**: ์• ํ”Œ๋ฆฌ์ผ€์ด์…˜์„ ์ข…๋ฃŒํ•ฉ๋‹ˆ๋‹ค. + +--- + +### 2. ๊ฐ๋งˆ ๋ณด์ • ํ•˜์œ„ ๋ฉ”๋‰ด (์ค‘์ฒฉ) +๋ฉ”์ธ ๋ฉ”๋‰ด์˜ `[6]`๋ฒˆ ์˜ต์…˜์„ ํ†ตํ•ด ์ง„์ž…ํ•˜๋ฉฐ, ํ•˜๋“œ์›จ์–ด ๋ฃฉ์—… ํ…Œ์ด๋ธ”(LUT) ์„ค์ •์„ ๊ด€๋ฆฌํ•ฉ๋‹ˆ๋‹ค. + +- **[1] ํ™œ์„ฑํ™” ํ† ๊ธ€**: ๊ฐ๋งˆ ํ•˜๋“œ์›จ์–ด ๋ธ”๋ก์˜ ON/OFF ์ƒํƒœ๋ฅผ ์‹ค์‹œ๊ฐ„์œผ๋กœ ์ „ํ™˜ํ•ฉ๋‹ˆ๋‹ค. +- **[2] Gamma 2.2 ๋กœ๋“œ**: ์ผ๋ฐ˜์ ์ธ ๋””์Šคํ”Œ๋ ˆ์ด๋ฅผ ์œ„ํ•œ ํ‘œ์ค€ ์ „๋ ฅ ๋ฒ•์น™(Power-law) LUT์ž…๋‹ˆ๋‹ค. +- **[3] sRGB Gamma ๋กœ๋“œ**: ์•”๋ถ€ ํ‘œํ˜„๋ ฅ์„ ๊ฐœ์„ ํ•˜๊ธฐ ์œ„ํ•œ ์กฐ๊ฐ๋ณ„ ์„ ํ˜•/์ „๋ ฅ ํ•จ์ˆ˜ LUT์ž…๋‹ˆ๋‹ค. +- **[4] Inverse Gamma 2.2 ๋กœ๋“œ**: ์„ ํ˜• ํŒจ๋„์—์„œ ๊ฒ€์€์ƒ‰์ด "๋“ค๋œจ๋Š”" ํ˜„์ƒ์„ ๋ฐฉ์ง€ํ•˜๊ธฐ ์œ„ํ•œ ํŠน์ˆ˜ LUT์ž…๋‹ˆ๋‹ค. +- **[b] ๋’ค๋กœ ๊ฐ€๊ธฐ**: ๋ฉ”์ธ ๋ฉ”๋‰ด๋กœ ๋Œ์•„๊ฐ‘๋‹ˆ๋‹ค. + +## ๐Ÿ“ ๋ฉ”๋‰ด ์ƒ˜ํ”Œ (์‹ค์ œ ์‹คํ–‰ ๋กœ๊ทธ) + +```text +DE10-Nano Video/DMA Test Environment Initialized +Checking Timer... Timer OK! (Delta=161197) +Initializing Span Extender to 0x20000000... Done. + +========== DE10-Nano HDMI Pipeline Menu ========== + [1] Perform OCM-to-DDR DMA Test (4KB) + [2] Perform DDR-to-DDR Burst Master Test (1MB) + [3] Initialize HDMI (ADV7513 via I2C) + [4] Generate 720p Color Bar Pattern in DDR3 + [5] Change RTL Test Pattern (Red, Green, Blue, etc.) + [6] Gamma Correction Settings (Table, Toggle, Standard) + [C] Load Custom Character Bitmap + [r] Reset RTL Pattern Generator + [q] Quit +-------------------------------------------------- +Select an option: 1 + +--- [TEST 1] OCM to DDR DMA (burst_master_0) --- +Starting SW Copy (4KB x 100)... Done (4179649 cycles, ~4.6 MB/s) +Starting HW DMA (4KB x 100)... Done (167027 cycles, ~116.9 MB/s) +Speedup: 25 x +SUCCESS: OCM to DDR Verified! + +Select an option: 6 + +--- Gamma Correction Settings --- + [1] Toggle Enable (Current: OFF) + [2] Load Gamma 2.2 (Standard) + [3] Load sRGB Gamma (Standard) + [4] Load Inverse Gamma 2.2 (for Linear Panel) + [b] Back to Main Menu +Enter choice: 1 +Gamma Correction Enabled +``` + +--- +> [!TIP] +> ์‹œ์Šคํ…œ๊ณผ ์ƒํ˜ธ์ž‘์šฉํ•˜๋ ค๋ฉด JTAG UART ํ„ฐ๋ฏธ๋„(`nios2-terminal`)์„ ์‚ฌ์šฉํ•˜์„ธ์š”. ๋ชจ๋“  ์ž…๋ ฅ์€ ๋Œ€์†Œ๋ฌธ์ž๋ฅผ ๊ตฌ๋ถ„ํ•˜์ง€ ์•Š์œผ๋ฉฐ ์ฆ‰์‹œ ์ฒ˜๋ฆฌ๋ฉ๋‹ˆ๋‹ค. diff --git a/doc/RESULT.md b/doc/RESULT.md index db5044a..f6305ee 100644 --- a/doc/RESULT.md +++ b/doc/RESULT.md @@ -1,4 +1,5 @@ # Video Processing Pipeline - Test Results +[**English**] | [**ํ•œ๊ตญ์–ด**](./RESULT_kor.md) [โฌ…๏ธ Back to README](../README.md) diff --git a/doc/RESULT_kor.md b/doc/RESULT_kor.md new file mode 100644 index 0000000..effaae4 --- /dev/null +++ b/doc/RESULT_kor.md @@ -0,0 +1,133 @@ +# ๋น„๋””์˜ค ํ”„๋กœ์„ธ์‹ฑ ํŒŒ์ดํ”„๋ผ์ธ - ํ…Œ์ŠคํŠธ ๊ฒฐ๊ณผ +[**English**](./RESULT.md) | [**ํ•œ๊ตญ์–ด**] + +[โฌ…๏ธ README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md) + +์ด ๋ฌธ์„œ๋Š” DE10-Nano ๋น„๋””์˜ค ํ”„๋กœ์„ธ์‹ฑ ํŒŒ์ดํ”„๋ผ์ธ์— ๋Œ€ํ•œ ์„ฑ๋Šฅ ๋ฒค์น˜๋งˆํฌ ๋ฐ ํ•˜๋“œ์›จ์–ด ๊ฒ€์ฆ ๊ฒฐ๊ณผ๋ฅผ ๊ธฐ๋กํ•ฉ๋‹ˆ๋‹ค. + +## 1. DMA ์„ฑ๋Šฅ ๋ฒค์น˜๋งˆํฌ + +### ๋ฒ„์ŠคํŠธ ๋งˆ์Šคํ„ฐ ์„ฑ๋Šฅ (2026-02-12) + +| ํ…Œ์ŠคํŠธ ์ผ€์ด์Šค | ํฌ๊ธฐ | ์†Œํ”„ํŠธ์›จ์–ด (ํด๋ก) | ํ•˜๋“œ์›จ์–ด (ํด๋ก) | MB/s (ํ•˜๋“œ์›จ์–ด) | ์†๋„ ํ–ฅ์ƒ | +| :--- | :--- | :--- | :--- | :--- | :--- | +| OCM to DDR | 4KB x 100 | 4,185,427 | 166,211 | 117.5 | **25๋ฐฐ** | +| DDR to DDR | 1MB | 207,071,817 | 393,942 | 126.9 | **525๋ฐฐ** | + +> [!NOTE] +> DMA (Burst Master 4)๋Š” CPU ๋ถ€ํ•˜๋ฅผ ํš๊ธฐ์ ์œผ๋กœ ์ค„์—ฌ์ฃผ๋ฉฐ, 1MB ์ „์†ก ์‹œ 500๋ฐฐ ์ด์ƒ์˜ ์„ฑ๋Šฅ ํ–ฅ์ƒ์„ ์ œ๊ณตํ•ฉ๋‹ˆ๋‹ค. + +## 2. ๋น„๋””์˜ค ์ถœ๋ ฅ ๊ฒ€์ฆ + +### 540p (qHD) ๊ตฌํ˜„ (2026-02-14) + +**ํ•ด์ƒ๋„**: 960ร—540 @ 60Hz +**ํ”ฝ์…€ ํด๋ก**: 37.8336 MHz +**๋Œ€์—ญํญ**: 124 MB/s (50MHz ๋ฒ„์Šค ๊ฐ€๋™๋ฅ  62%) + +#### โœ… ๊ฒ€์ฆ๋œ ๊ธฐ๋Šฅ + +| ๊ธฐ๋Šฅ | ์ƒํƒœ | ์ƒ์„ธ ๋‚ด์šฉ | +|---------|--------|---------| +| **์ •์  ์ด๋ฏธ์ง€ ๋””์Šคํ”Œ๋ ˆ์ด** | โœ… ํ†ต๊ณผ | Nios II๊ฐ€ DDR3์—์„œ ์ด๋ฏธ์ง€๋ฅผ ์„ฑ๊ณต์ ์œผ๋กœ ๋กœ๋“œ ๋ฐ ํ‘œ์‹œํ•จ | +| **๋น„๋””์˜ค ์žฌ์ƒ (๋ฆฌ๋ˆ…์Šค)** | โœ… ํ†ต๊ณผ | HPS `/dev/mem`์„ ํ†ตํ•œ ๋”๋ธ” ๋ฒ„ํผ๋ง ์ŠคํŠธ๋ฆฌ๋ฐ ํ™•์ธ | +| **V-Sync ๋™๊ธฐํ™”** | โœ… ํ†ต๊ณผ | ํ‹ฐ์–ด๋ง ์—†๋Š” ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ ๋ž˜์นญ(Latching) ํ™•์ธ | +| **๊ฐ๋งˆ ๋ณด์ •** | โœ… ํ†ต๊ณผ | sRGB ๋ฐ Inverse Gamma 2.2 LUT ์ •์ƒ ๋™์ž‘ | +| **ํŒจํ„ด ์ƒ์„ฑ** | โœ… ํ†ต๊ณผ | ์ปฌ๋Ÿฌ, ๊ทธ๋ฆฌ๋“œ, ์บ๋ฆญํ„ฐ ํƒ€์ผ ๋“ฑ 8๊ฐ€์ง€ ๋ชจ๋“œ ๋ชจ๋‘ ํ™•์ธ | +| **๋“€์–ผ ํด๋ก CDC** | โœ… ํ†ต๊ณผ | CSR(50MHz) ๋ฐ Pixel(37.8MHz) ๋„๋ฉ”์ธ ์•ˆ์ •์„ฑ ํ™•์ธ | + +#### ์„ฑ๋Šฅ ์ฐธ๊ณ  ์‚ฌํ•ญ +- **์ดˆ๊ธฐ ์žฌ์ƒ**: ๋ฆฌ๋ˆ…์Šค ํŽ˜์ด์ง€ ์บ์‹œ ํ™œ์„ฑํ™” ์‹œ 60fps ์œ ์ง€ +- **์ง€์† ์žฌ์ƒ**: SD ์นด๋“œ ๋ณ‘๋ชฉ์œผ๋กœ ์ธํ•ด 10-15fps๋กœ ์ €ํ•˜ (ํ•„์š” 124 MB/s vs ๊ฐ€์šฉ ~20 MB/s) +- **RAM ์‚ฌ์ „ ๋กœ๋“œ (์‹ ๊ทœ)**: โœ… **60fps ์•ˆ์ •์  ์žฌ์ƒ** (์•ฝ 4.1์ดˆ ์žฌ์ƒ ์‹œ๊ฐ„ ์ œํ•œ) +- **ํ”„๋ ˆ์ž„ ๋ฒ„ํผ ํฌ๊ธฐ**: ํ”„๋ ˆ์ž„๋‹น 2,073,600 ๋ฐ”์ดํŠธ (์•ฝ 2MB) +- **๋ฉ”๋ชจ๋ฆฌ ๋ฐฐ์น˜**: 0x20000000 ๊ธฐ์ค€ 512MB ์˜ˆ์•ฝ ์˜์—ญ ์‚ฌ์šฉ + +## 3. ํ•˜๋“œ์›จ์–ด ์ดˆ๊ธฐํ™” ์ƒํƒœ + +### ํ˜„์žฌ ๊ตฌ์„ฑ +- **HDMI PLL**: 37.8336 MHz (540p60)์— ๊ณ ์ •(Locked) +- **ADV7513 IC**: I2C๋ฅผ ํ†ตํ•œ ๊ตฌ์„ฑ ์„ฑ๊ณต +- **๋ฉ”๋ชจ๋ฆฌ ๋งต**: 0x30000000 (512MB ์˜ˆ์•ฝ ์˜์—ญ)์— ํ”„๋ ˆ์ž„ ๋ฒ„ํผ ์œ„์น˜ +- **HPS ๋ธŒ๋ฆฟ์ง€**: LWHPS2FPGA๋ฅผ ํ†ตํ•ด 0xFF240000์˜ HDMI CSR์— ์—ฐ๊ฒฐ๋จ + +### Qsys ์—ฐ๊ฒฐ์„ฑ +``` +hps_0.h2f_lw_axi_master โ†’ mm_bridge_0.s0 โ†’ hdmi_sync_mm.s0 (Base: 0x40000) +``` + +## 4. ์‹คํ–‰ ๋กœ๊ทธ + +### DMA ๋ฒค์น˜๋งˆํฌ ๋กœ๊ทธ +```text +--- [TEST 1] OCM to DDR DMA (burst_master_0) --- +Starting SW Copy (4KB x 100)... Done (4185427 cycles, ~4.6 MB/s) +Starting HW DMA (4KB x 100)... Done (166211 cycles, ~117.5 MB/s) +Speedup: 25 x +SUCCESS: OCM to DDR Verified! + +--- [TEST 2] DDR to DDR DMA (Burst Master 4) --- +Transfer Size: 1 MB +Initializing DDR3 data... Done. +Starting SW Copy (1MB)... Done (207071817 cycles, ~0.2 MB/s) +Starting HW DMA (1MB)... Done (393942 cycles, ~126.9 MB/s) +Speedup: 525 x +Verifying HW Output... +SUCCESS: DDR to DDR Verified! (Coeff=800) +``` + +### HDMI ์ดˆ๊ธฐํ™” ๋กœ๊ทธ +```text +Waiting for PLL Lock (37.83 MHz)... +PLL Locked! Initializing ADV7513 HDMI Transmitter... +HDMI Controller Configured. Ready for Video! + +Generating 540p Pattern in DDR3... Done! (Total 518400 pixels written) +``` + +### ๋น„๋””์˜ค ์žฌ์ƒ ๋กœ๊ทธ (๋ฆฌ๋ˆ…์Šค) +```text +DE10-Nano Linux Video Player (Double Buffered / RAM Preload) +Video: video_qhd.bin (960x540) +Mapped Frame Buffers: + Buffer A (Virtual): 0xb6f00000 (Physical: 0x30000000) + Buffer B (Virtual): 0xb7100000 (Physical: 0x30200000) +Mapped CSR Base: 0xb6e00000 +Started Playback (Double Buffering)... +......... +``` + +## 5. ๊ณ ๊ธ‰ ๊ธฐ๋Šฅ ๊ฒ€์ฆ + +### ๊ฐ๋งˆ ๋ณด์ • โœ… +- **Mode 7 (์บ๋ฆญํ„ฐ ํƒ€์ผ)**: ๋™์  ๋ฌด์ง€๊ฐœ ์ƒ‰์ƒ ํšจ๊ณผ ํ™•์ธ +- **๊ฐ๋งˆ LUT ๋กœ๋”ฉ**: sRGB ๋ฐ Inverse Gamma 2.2 ๊ฒ€์ฆ ์™„๋ฃŒ +- **์‹ค์‹œ๊ฐ„ ํ† ๊ธ€**: CSR์„ ํ†ตํ•œ ๊ฐ๋งˆ ํ™œ์„ฑํ™”/๋น„ํ™œ์„ฑํ™” ๋™์ž‘ ํ™•์ธ + +### ํƒ€์ด๋ฐ ๋ถ„์„ โœ… +- **Setup Slack**: ์–‘์ˆ˜ (์œ„๋ฐ˜ ์—†์Œ) +- **Hold Slack**: ์–‘์ˆ˜ (์œ„๋ฐ˜ ์—†์Œ) +- **ํด๋ก ๋„๋ฉ”์ธ ๊ต์ฐจ (CDC)**: SDC๋ฅผ ํ†ตํ•ด ์ ์ ˆํžˆ ์ œ์•ฝ๋จ +- **V-Sync ๋ž˜์นญ**: ์ƒ์Šน ์—ฃ์ง€์—์„œ ์‰๋„์šฐ ํฌ์ธํ„ฐ ์—…๋ฐ์ดํŠธ ํ™•์ธ + +## 6. ์•Œ๋ ค์ง„ ์ œํ•œ ์‚ฌํ•ญ +- **SD ์นด๋“œ ๋Œ€์—ญํญ**: ์ง€์† ์žฌ์ƒ ์‹œ ์•ฝ 10-15fps๋กœ ์ œํ•œ๋จ +- **๋ฉ”๋ชจ๋ฆฌ ์ œ์•ฝ**: 512MB DDR3 ์˜ˆ์•ฝ ์˜์—ญ ์‚ฌ์šฉ (์‚ฌ์ „ ๋กœ๋“œ ์‹œ ์ตœ๋Œ€ ์•ฝ 250 ํ”„๋ ˆ์ž„) +- **์˜ค๋””์˜ค ๋ฏธ์ง€์›**: ํ˜„์žฌ ๋น„๋””์˜ค ์ „์šฉ์œผ๋กœ ๊ตฌํ˜„๋จ + +## 7. ํ–ฅํ›„ ๊ณ„ํš + +### 4๋‹จ๊ณ„: ๋Œ€์—ญํญ ํ™•์žฅ +**๋ชฉํ‘œ**: 720p@60Hz (ํ•„์š” ๋Œ€์—ญํญ 222 MB/s) ์ง€์› + +**์ ‘๊ทผ ๋ฐฉ์‹**: +- ๋ฒ„์Šค ํญ์„ 4๋ฐ”์ดํŠธ์—์„œ 8/16๋ฐ”์ดํŠธ๋กœ ํ™•์žฅ +- ํด๋ก ์ฃผํŒŒ์ˆ˜๋Š” 50MHz ์œ ์ง€ +- ๋ชฉํ‘œ ๋Œ€์—ญํญ: 400 MB/s (50MHz @ 8-byte ๊ธฐ์ค€) + +**๊ธฐ๋Œ€ ํšจ๊ณผ**: +- 720p@60Hz๋ฅผ 80%์˜ ์—ฌ์œ  ๋Œ€์—ญํญ์œผ๋กœ ์ฒ˜๋ฆฌ ๊ฐ€๋Šฅ +- ์„ฑ๋Šฅ ๋งˆ์ง„ ๊ฐœ์„  ๋ฐ ํ–ฅํ›„ ๊ณ ํ•ด์ƒ๋„ ๋Œ€์‘ ๊ฐ€๋Šฅ + +--- +*์ตœ์ข… ์—…๋ฐ์ดํŠธ: 2026-02-14* diff --git a/doc/STUDY.md b/doc/STUDY.md index f77df14..68a5795 100644 --- a/doc/STUDY.md +++ b/doc/STUDY.md @@ -1,4 +1,5 @@ # Study Notes: HDMI Video Pipeline Implementation +[**English**] | [**ํ•œ๊ตญ์–ด**](./STUDY_kor.md) [โฌ…๏ธ Back to README](../README.md) This document provides technical details required to implement a custom HDMI video pipeline on the DE10-Nano, specifically focusing on 1280x720 (720p) resolution. @@ -300,7 +301,57 @@ By repeating this at 30 or 60 times per second, you get a full-speed movie playi ## 16. Real-time Decoding: MP4 and CPU Limits Handling compressed formats like **MP4 (H.264)** is much more CPU-intensive than just copying raw pixel data. -### Can ARM (Cortex-A9) handle it? +### ๐Ÿš€ Solution: "No-Install FFmpeg" & Pipe Method (Recommended) +Instead of dealing with complex library installations, using a **Static Build** version is the most efficient way. You simply download a single file and run it. + +**1. Download on PC** +The DE10-Nano uses the **ARMv7 (32bit)** architecture (armhf). Download the following file on your PC and transfer it to the SD card. +- **Filename**: `ffmpeg-release-armhf-static.tar.xz` +- **Source**: [John Van Sickle - FFmpeg Static Builds](https://johnvansickle.com/ffmpeg/) + +**2. Install on DE10-Nano** +```bash +# Extract the archive +tar -xvf ffmpeg-release-armhf-static.tar.xz + +# Move to the directory +cd ffmpeg-*-armhf-static + +# Verify execution +./ffmpeg -version +``` + +**3. Interfacing with C Code (Pipe Method)** +You can elegantly solve this using Linux **Pipes (|)** without needing any library headers. +- **FFmpeg**: Decodes the video and outputs to **Standard Output (stdout)**. +- **C Program**: Reads from **Standard Input (stdin)** and writes to memory. + +**Terminal Command:** +```bash +# ffmpeg reads mp4 -> converts to raw RGBA -> sends via pipe -> player receives and writes to memory +./ffmpeg -i input.mp4 -f rawvideo -pix_fmt rgba - | ./player +``` + +**C Code Modification (Read from stdin):** +Use Standard Input (file descriptor `0` or `stdin`) instead of `fopen`. + +```c +// player.c core part +unsigned char buffer[960 * 540 * 4]; // One frame buffer (qHD) + +while(1) { + // 1. Read one frame from Standard Input (stdin) + // fread automatically blocks until data is available + int bytes_read = fread(buffer, 1, sizeof(buffer), stdin); + + if (bytes_read < sizeof(buffer)) break; // End of stream + + // 2. Copy read data to FPGA memory (mmap) - Double buffering logic needed + memcpy(fb_ptr, buffer, sizeof(buffer)); +} +``` + +### CPU Limits Context (Reference) - **Software Decoding**: Using libraries like **FFmpeg (libav codec)**, the dual-core 800MHz A9 can handle 480p or basic 720p at 24/30fps. However, reaching 60fps for 720p/1080p via pure software is very difficult. - **NEON Acceleration**: To make it work, the code must use the **NEON SIMD engine** inside the Cortex-A9 cores. This allows the CPU to process multiple data points in parallel, which is critical for video decoding. - **The Bottleneck**: The HPS on Cyclone V doesn't have a dedicated hard-wired H.264 decoder (VPU). Therefore, the CPU must do all the heavy lifting (Calculating DCT, Entropy coding, etc.). diff --git a/doc/STUDY_kor.md b/doc/STUDY_kor.md new file mode 100644 index 0000000..51baf8b --- /dev/null +++ b/doc/STUDY_kor.md @@ -0,0 +1,392 @@ +# ํ•™์Šต ๋…ธํŠธ: HDMI ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ ๊ตฌํ˜„ +[**English**](./STUDY.md) | [**ํ•œ๊ตญ์–ด**] +[โฌ…๏ธ README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md) + +์ด ๋ฌธ์„œ๋Š” DE10-Nano์—์„œ ์ปค์Šคํ…€ HDMI ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ์„ ๊ตฌํ˜„ํ•˜๊ธฐ ์œ„ํ•ด ํ•„์š”ํ•œ ๊ธฐ์ˆ ์  ์„ธ๋ถ€ ์‚ฌํ•ญ์„ ๋‹ค๋ฃจ๋ฉฐ, ํŠนํžˆ 1280x720 (720p) ํ•ด์ƒ๋„์— ์ดˆ์ ์„ ๋งž์ถฅ๋‹ˆ๋‹ค. + +## 1. 720p (1280x720 @ 60Hz) ๋น„๋””์˜ค ํƒ€์ด๋ฐ +์•ˆ์ •์ ์ธ ์ด๋ฏธ์ง€๋ฅผ ์ถœ๋ ฅํ•˜๋ ค๋ฉด ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ(Sync Generator)๊ฐ€ 720p ํ•ด์ƒ๋„์— ๋Œ€ํ•œ CEA-861 ํ‘œ์ค€์„ ์ค€์ˆ˜ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. + +| ํŒŒ๋ผ๋ฏธํ„ฐ | ์ˆ˜ํ‰ (ํ”ฝ์…€) | ์ˆ˜์ง (๋ผ์ธ) | +| :--- | :--- | :--- | +| **๊ฐ€์‹œ ์˜์—ญ (Visible Area)** | 1280 | 720 | +| **ํ”„๋ก ํŠธ ํฌ์น˜ (Front Porch)** | 110 | 5 | +| **์‹ฑํฌ ํŽ„์Šค (Sync Pulse)** | 40 | 5 | +| **๋ฐฑ ํฌ์น˜ (Back Porch)** | 220 | 20 | +| **์ด ์˜์—ญ (Total Area)** | 1650 | 750 | +| **ํ”ฝ์…€ ํด๋ก** | **74.25 MHz** | - | + +- **์žฌ์ƒ๋ฅ  (Refresh Rate)**: $1650 \times 750 \times 60 \text{ Hz} \approx 74.25 \text{ MHz}$. +- **๋ฐ์ดํ„ฐ ์ธ์—์ด๋ธ” (DE)**: ๊ฐ€์‹œ ์˜์—ญ($0 \leq X < 1280$ ๋ฐ $0 \leq Y < 720$) ๋‚ด์—์„œ๋งŒ High ์ƒํƒœ๋ฅผ ์œ ์ง€ํ•ฉ๋‹ˆ๋‹ค. + +## 2. ADV7513 HDMI ํŠธ๋žœ์Šค๋ฏธํ„ฐ ๊ตฌ์„ฑ (I2C) +ADV7513์€ ๋น„๋””์˜ค ์‹ ํ˜ธ๋ฅผ ์ „์†กํ•˜๊ธฐ ์ „์— I2C๋ฅผ ํ†ตํ•ด ์ดˆ๊ธฐํ™”๋˜์–ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. + +- **I2C ์Šฌ๋ ˆ์ด๋ธŒ ์ฃผ์†Œ**: `0x72` (๋ณด๋“œ์— ๋”ฐ๋ผ `0x7A`์ผ ์ˆ˜๋„ ์žˆ์Œ). +- **ํ•ต์‹ฌ ๋ ˆ์ง€์Šคํ„ฐ**: + - `0x41[6]`: **์ „์› ์ œ์–ด (Power Down Control)**. ๋น„ํŠธ 6์ด `0`์ด๋ฉด "Power Up"์„ ์˜๋ฏธํ•ฉ๋‹ˆ๋‹ค. ๊ธฐ๋ณธ๊ฐ’์€ ๋ณดํ†ต 1(๋Œ€๊ธฐ ๋ชจ๋“œ)์ž…๋‹ˆ๋‹ค. + - `0x16[5:4]`: **์ปฌ๋Ÿฌ ๊นŠ์ด (Color Depth)**. `00`์€ ์ฑ„๋„๋‹น 8๋น„ํŠธ(์ด 24๋น„ํŠธ RGB)๋ฅผ ์„ ํƒํ•ฉ๋‹ˆ๋‹ค. + - `0x16[3:0]`: **๋น„๋””์˜ค ํฌ๋งท**. `0000`์€ ํ‘œ์ค€ RGB 4:4:4 ์ž…๋ ฅ์„ ์„ ํƒํ•ฉ๋‹ˆ๋‹ค. + - `0xAF[1]`: **HDCP/HDMI ๋ชจ๋“œ**. ๋น„ํŠธ 1์ด `1`์ด๋ฉด HDMI ๋ชจ๋“œ๋ฅผ ํ™œ์„ฑํ™”ํ•ฉ๋‹ˆ๋‹ค(์˜ค๋””์˜ค ๋ฐ ์ธํฌํŒจํ‚ท ์ „์†ก์— ํ•„์š”). + - `0x98, 0x9A...`: **๊ณ ์ • ๋ ˆ์ง€์Šคํ„ฐ (Magic Registers)**. ํ”„๋กœ๊ทธ๋ž˜๋ฐ ๊ฐ€์ด๋“œ์— ๋”ฐ๋ผ ๋‚ด๋ถ€ ์•„๋‚ ๋กœ๊ทธ ํšŒ๋กœ๊ฐ€ ์ •์ƒ ๋™์ž‘ํ•˜๊ธฐ ์œ„ํ•ด ํŠน์ • ๊ฐ’(์˜ˆ: `0x98=0x03`)์ด ์„ค์ •๋˜์–ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. + +### Nios II ๊ตฌํ˜„ ์˜ˆ์‹œ +C ์ฝ”๋“œ์—์„œ ์ดˆ๊ธฐํ™” ์‹œ ์ด๋Ÿฌํ•œ ์„ค์ •์„ ์ˆ˜ํ–‰ํ•˜๋Š” I2C ์“ฐ๊ธฐ ํ•จ์ˆ˜๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. + +```c +void hdmi_init() { + printf("ADV7513 HDMI ํŠธ๋žœ์Šค๋ฏธํ„ฐ ์ดˆ๊ธฐํ™” ์ค‘...\n"); + + // 1. ๋””๋ฐ”์ด์Šค ์ „์› ์ผœ๊ธฐ (Reg 0x41์˜ ๋น„ํŠธ 6 ํด๋ฆฌ์–ด) + hdmi_i2c_write(0x41, 0x10); // ๋น„ํŠธ 6=0, ๋‹ค๋ฅธ ๋น„ํŠธ๋Š” ์นฉ ๋ฆฌ๋น„์ „์— ๋”ฐ๋ผ ๋‹ค๋ฆ„ + + // 2. ์ž…๋ ฅ ํฌ๋งท ์„ค์ • (RGB 4:4:4, 8๋น„ํŠธ) + hdmi_i2c_write(0x16, 0x00); + + // 3. HDMI ๋ชจ๋“œ ์„ ํƒ (Reg 0xAF ๋น„ํŠธ 1 = 1) + hdmi_i2c_write(0xAF, 0x06); // ํ‘œ์ค€ HDMI ๋ชจ๋“œ + + // 4. ๊ณ ์ • ์„ค์ • ์‹œํ€€์Šค (์•ˆ์ •์ ์ธ ๋™์ž‘์„ ์œ„ํ•ด ํ•„์ˆ˜) + hdmi_i2c_write(0x98, 0x03); + hdmi_i2c_write(0x9A, 0xE0); + hdmi_i2c_write(0x9C, 0x30); + hdmi_i2c_write(0x9D, 0x61); + + printf("HDMI ์ปจํŠธ๋กค๋Ÿฌ ๊ตฌ์„ฑ ์™„๋ฃŒ.\n"); +} +``` + +## 3. ์ปค์Šคํ…€ ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ ๋กœ์ง (Verilog) +์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ๋Š” ์ˆ˜ํ‰ ๋ฐ ์ˆ˜์ง ์œ„์น˜๋ฅผ ๊ด€๋ฆฌํ•˜๊ธฐ ์œ„ํ•ด ๋‘ ๊ฐœ์˜ ์ค‘์ฒฉ๋œ ์นด์šดํ„ฐ๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. + +### ์นด์šดํ„ฐ ๋กœ์ง +```verilog +always @(posedge pix_clk or posedge reset) begin + if (reset) begin + h_cnt <= 0; + v_cnt <= 0; + end else begin + if (h_cnt == H_TOTAL - 1) begin + h_cnt <= 0; + if (v_cnt == V_TOTAL - 1) + v_cnt <= 0; + else + v_cnt <= v_cnt + 1; + end else begin + h_cnt <= h_cnt + 1; + end + end +end +``` + +### ์‹ ํ˜ธ ์ƒ์„ฑ +- **HSync**: `h_cnt`๊ฐ€ ์ˆ˜ํ‰ ๋™๊ธฐ ํŽ„์Šค ๋ฒ”์œ„ ๋‚ด์— ์žˆ์„ ๋•Œ ํ™œ์„ฑํ™”(๋ณดํ†ต Low)๋ฉ๋‹ˆ๋‹ค. +- **VSync**: `v_cnt`๊ฐ€ ์ˆ˜์ง ๋™๊ธฐ ํŽ„์Šค ๋ฒ”์œ„ ๋‚ด์— ์žˆ์„ ๋•Œ ํ™œ์„ฑํ™”(๋ณดํ†ต Low)๋ฉ๋‹ˆ๋‹ค. +- **Data Enable (DE)**: `h_cnt < 1280` ์ด๊ณ  `v_cnt < 720`์ผ ๋•Œ High๊ฐ€ ๋ฉ๋‹ˆ๋‹ค. + +## 4. ์ธํ„ฐํŽ˜์ด์Šค ๋ฐ ๋ฐฑํ”„๋ ˆ์…”(Back-pressure) ๋ฉ”์ปค๋‹ˆ์ฆ˜ +ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๊ฐ€ ์ถœ๋ ฅ๋˜์–ด์•ผ ํ•  ๋•Œ๋งŒ ๊ฐ€์ ธ์˜ค๋„๋ก ํ•˜๊ธฐ ์œ„ํ•ด **Avalon-ST ํ•ธ๋“œ์…ฐ์ดํฌ**๋ฅผ ์‚ฌ์šฉํ•œ ๋ฐฑํ”„๋ ˆ์…” ๋ฉ”์ปค๋‹ˆ์ฆ˜์„ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. + +### ํ•ธ๋“œ์…ฐ์ดํฌ ์‹ ํ˜ธ์˜ ์—ญํ•  +- **`asi_data`**: 24๋น„ํŠธ RGB ํ”ฝ์…€ ๋ฐ์ดํ„ฐ. +- **`asi_valid`**: FIFO์— ์ตœ์†Œ ํ•˜๋‚˜์˜ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๊ฐ€ ์žˆ์„ ๋•Œ High๊ฐ€ ๋ฉ๋‹ˆ๋‹ค. +- **`asi_ready`**: **์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ**์— ์˜ํ•ด ์ œ์–ด๋ฉ๋‹ˆ๋‹ค. ๊ฐ€์‹œ ์˜์—ญ(Active display period) ๋™์•ˆ์—๋งŒ High๊ฐ€ ๋ฉ๋‹ˆ๋‹ค. + +### ๋ฐฑํ”„๋ ˆ์…” ๋กœ์ง +์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ๋Š” "์†Œ๋น„์ž(Consumer)" ์—ญํ• ์„ ํ•˜๋ฉฐ ํ˜„์žฌ ์Šค์บ”๋ผ์ธ ์œ„์น˜์— ๋”ฐ๋ผ "์ƒ์‚ฐ์ž(Producer)"(๋น„๋””์˜ค DMA/FIFO)์˜ ๋ฐ์ดํ„ฐ ํ๋ฆ„์„ ์ œ์–ดํ•ฉ๋‹ˆ๋‹ค. + +| ํŒŒ์ดํ”„๋ผ์ธ ์ƒํƒœ | ๋ฐ์ดํ„ฐ ์ธ์—์ด๋ธ” (DE) | ์ธํ„ฐํŽ˜์ด์Šค `ready` | ๋™์ž‘ | +| :--- | :---: | :---: | :--- | +| **๊ฐ€์‹œ ์˜์—ญ** | 1 | 1 | ๋งค ํด๋ก ์‚ฌ์ดํด๋งˆ๋‹ค FIFO์—์„œ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๋ฅผ ๊ฐ€์ ธ์˜ด. | +| **ํฌ์น˜ / ์‹ฑํฌ ์˜์—ญ** | 0 | 0 | ๋ฐ์ดํ„ฐ ๊ฐ€์ ธ์˜ค๊ธฐ ์ค‘์ง€; FIFO์™€ DMA๋Š” ํ˜„์žฌ ์ƒํƒœ์—์„œ ๋Œ€๊ธฐ. | + +### ๋ฐฑํ”„๋ ˆ์…”์˜ ์ „ํŒŒ +1. **์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ**๋Š” ๋ธ”๋žญํ‚น ๊ตฌ๊ฐ„ ๋™์•ˆ `ready`๋ฅผ ๋น„ํ™œ์„ฑํ™”ํ•ฉ๋‹ˆ๋‹ค. +2. **DCFIFO** ์ถœ๋ ฅ์—์„œ ๋ฐ์ดํ„ฐ ๊ณต๊ธ‰์ด ์ค‘๋‹จ๋˜์–ด ๋‚ด๋ถ€ ๋ฐ์ดํ„ฐ ๋ ˆ๋ฒจ์ด ์ƒ์Šนํ•ฉ๋‹ˆ๋‹ค. +3. **DCFIFO**๊ฐ€ ๊ฐ€๋“ ์ฐจ๊ฑฐ๋‚˜ ์ž„๊ณ„๊ฐ’์— ๋„๋‹ฌํ•˜๋ฉด **๋น„๋””์˜ค DMA**์— ๋Œ€๊ณ  `ready`๋ฅผ ๋น„ํ™œ์„ฑํ™”ํ•ฉ๋‹ˆ๋‹ค. +4. **๋น„๋””์˜ค DMA**๋Š” DDR3์— ๋Œ€ํ•œ Avalon-MM ์ฝ๊ธฐ ํŠธ๋žœ์žญ์…˜์„ ์ผ์‹œ ์ค‘์ง€ํ•ฉ๋‹ˆ๋‹ค. + +## 5. HDMI ํŠธ๋žœ์Šค๋ฏธํ„ฐ (ADV7513)์˜ ์—ญํ•  +ADV7513์€ FPGA ๋กœ์ง๊ณผ ๋ชจ๋‹ˆํ„ฐ๋ฅผ ์—ฐ๊ฒฐํ•˜๋Š” ๊ณ ์„ฑ๋Šฅ HDMI ํŠธ๋žœ์Šค๋ฏธํ„ฐ์ž…๋‹ˆ๋‹ค. + +### ๋™์ž‘ ์›๋ฆฌ +- **ํด๋ก ์ƒ˜ํ”Œ๋ง**: `HDMI_TX_CLK`์˜ ๋งค ์—ฃ์ง€์—์„œ 24๋น„ํŠธ RGB ๋ฐ์ดํ„ฐ์™€ ๋™๊ธฐ ์‹ ํ˜ธ(HSync, VSync, DE)๋ฅผ ์ƒ˜ํ”Œ๋งํ•ฉ๋‹ˆ๋‹ค. +- **TMDS ๋ณ€ํ™˜**: ์ด๋Ÿฌํ•œ ๋ณ‘๋ ฌ ์‹ ํ˜ธ๋“ค์„ HDMI ์ผ€์ด๋ธ”์„ ํ†ตํ•ด ์ „์†ก๋˜๋Š” ๊ณ ์† **TMDS (Transition Minimized Differential Signaling)** ํŽ˜์–ด๋กœ ์ธ์ฝ”๋”ฉํ•ฉ๋‹ˆ๋‹ค. +- **๋ฐ์ดํ„ฐ ์ธ์—์ด๋ธ” (DE)์˜ ์ค‘์š”์„ฑ**: ์นฉ์€ `DE` ์‹ ํ˜ธ์— ํฌ๊ฒŒ ์˜์กดํ•ฉ๋‹ˆ๋‹ค. `DE`๊ฐ€ High์ผ ๋•Œ๋Š” ์ž…๋ ฅ์„ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๋กœ ์ฒ˜๋ฆฌํ•˜๊ณ , Low์ผ ๋•Œ๋Š” ์˜ค๋””์˜ค ๋ฐ์ดํ„ฐ๋‚˜ ๋ณด์กฐ ํŒจํ‚ท์„ ์ŠคํŠธ๋ฆผ์— ํฌํ•จ์‹œํ‚ฌ ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. + +### I2C ์ดˆ๊ธฐํ™”๊ฐ€ ํ•„์ˆ˜์ธ ์ด์œ  +์‹ฑํฌ ์‹ ํ˜ธ๋ฅผ ์ž˜ ๋”ฐ๋ผ๊ฐ€๋”๋ผ๋„ ๋‹ค์Œ ์„ค์ •์ด ์™„๋ฃŒ๋˜๊ธฐ ์ „์—๋Š” ์•„๋ฌด๊ฒƒ๋„ ์ถœ๋ ฅํ•˜์ง€ ์•Š์Šต๋‹ˆ๋‹ค: +1. **์ „์› ์ผœ๊ธฐ**: ๋Œ€๊ธฐ ๋ชจ๋“œ์—์„œ ๊นจ์šฐ๊ธฐ ์œ„ํ•œ I2C ๋ช…๋ น์„ ๋ณด๋‚ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +2. **์‹ ํ˜ธ ๋งคํ•‘**: 24๋น„ํŠธ๊ฐ€ ์–ด๋–ป๊ฒŒ ๋งคํ•‘๋˜๋Š”์ง€(์˜ˆ: RGB 4:4:4 ๋˜๋Š” YCbCr) ์•Œ๋ ค์ค˜์•ผ ํ•ฉ๋‹ˆ๋‹ค. +3. **HDMI ๋ชจ๋“œ**: DVI ๋ชจ๋“œ๊ฐ€ ์•„๋‹Œ HDMI ๋ชจ๋“œ๋ฅผ ๋ช…์‹œ์ ์œผ๋กœ ํ™œ์„ฑํ™”ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. + +์š”์•ฝํ•˜์ž๋ฉด, Nios II๊ฐ€ I2C๋ฅผ ํ†ตํ•ด ์นฉ์„ ์ดˆ๊ธฐํ™”ํ•˜๋ฉด, ์ด๋Š” FPGA์˜ ํƒ€์ด๋ฐ๊ณผ ํ”ฝ์…€์„ ํ™”๋ฉด์— ์ง์ ‘ ํˆฌ์˜ํ•˜๋Š” "ํˆฌ๋ช…ํ•œ ํŒŒ์ดํ”„" ์—ญํ• ์„ ํ•˜๊ฒŒ ๋ฉ๋‹ˆ๋‹ค. + +## 6. ์‹ฌํ™” ์ฃผ์ œ: ADV7513 ์—†์ด HDMI ๊ตฌํ˜„ํ•˜๊ธฐ? +์ „์šฉ ์นฉ ์—†์ด HDMI๋ฅผ ๊ตฌํ˜„ํ•˜๋Š” ๊ฒƒ๋„ ๊ฐ€๋Šฅํ•˜์ง€๋งŒ, ํ›จ์”ฌ ๋” ๋งŽ์€ FPGA ๋กœ์ง๊ณผ ํŠน์ • ํ•˜๋“œ์›จ์–ด ๊ธฐ๋Šฅ์ด ํ•„์š”ํ•ฉ๋‹ˆ๋‹ค. + +### ์ง์ ‘ HDMI ์ถœ๋ ฅ์„ ์œ„ํ•œ ์š”๊ตฌ ์‚ฌํ•ญ +- **TMDS ์ธ์ฝ”๋”ฉ (RTL)**: ๋””์ง€ํ„ธ RGB ๋ฐ์ดํ„ฐ๋ฅผ Verilog์˜ 8b/10b ์ธ์ฝ”๋”ฉ ์•Œ๊ณ ๋ฆฌ์ฆ˜์„ ์‚ฌ์šฉํ•˜์—ฌ 10๋น„ํŠธ TMDS ์บ๋ฆญํ„ฐ๋กœ ๋ณ€ํ™˜ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +- **์ง๋ ฌํ™” (10:1)**: HDMI๋Š” ์ง๋ ฌ ํ”„๋กœํ† ์ฝœ์ด๋ฏ€๋กœ 10๋น„ํŠธ ๋ณ‘๋ ฌ ๋ฐ์ดํ„ฐ๋ฅผ ํ”ฝ์…€ ํด๋ก์˜ 10๋ฐฐ ์†๋„๋กœ ์ง๋ ฌํ™”ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. 720p(74.25 MHz)์˜ ๊ฒฝ์šฐ ๋น„ํŠธ๋ ˆ์ดํŠธ๋Š” ๋ ˆ์ธ๋‹น **742.5 Mbps**์— ๋‹ฌํ•ฉ๋‹ˆ๋‹ค. +- **์ฐจ๋™ I/O**: FPGA๋Š” HDMI ์ปค๋„ฅํ„ฐ๋ฅผ ์ง์ ‘ ๊ตฌ๋™ํ•˜๊ธฐ ์œ„ํ•ด ๋ฌผ๋ฆฌ์  ํ•€์—์„œ ์ฐจ๋™ ์ถœ๋ ฅ ํ‘œ์ค€(TMDS ๋˜๋Š” LVDS ๋“ฑ)์„ ์ง€์›ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +- **๋ ˆ๋ฒจ ์‹œํ”„ํŒ… (Level Shifting)**: HDMI๋Š” 3.3V ์‹ ํ˜ธ๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. FPGA IO ๋ฑ…ํฌ ์ „์••์ด ๋‹ค๋ฅผ ๊ฒฝ์šฐ ๋ ˆ๋ฒจ ์‹œํ”„ํ„ฐ๊ฐ€ ํ•„์š”ํ•ฉ๋‹ˆ๋‹ค. + +### ๋ณต์žก๋„ ๋น„๊ต +| ๊ธฐ๋Šฅ | ADV7513 ์‚ฌ์šฉ (๋ณธ ํ”„๋กœ์ ํŠธ) | ํŠธ๋žœ์Šค๋ฏธํ„ฐ ๋ฏธ์‚ฌ์šฉ (์ง์ ‘ ๊ตฌ๋™) | +| :--- | :--- | :--- | +| **FPGA ๋กœ์ง** | ๋‹จ์ˆœ ๋ณ‘๋ ฌ ์ธํ„ฐํŽ˜์ด์Šค | ๋ณต์žกํ•œ TMDS + SERDES | +| **ํด๋กํ‚น** | ํ”ฝ์…€ ํด๋ก (74.25 MHz) | 10๋ฐฐ ํด๋ก (742.5 MHz) | +| **๋‚œ์ด๋„** | โ˜…โ˜†โ˜†โ˜†โ˜† | โ˜…โ˜…โ˜…โ˜…โ˜† | + +ADV7513์„ ์‚ฌ์šฉํ•จ์œผ๋กœ์จ HDMI ํ”„๋กœํ† ์ฝœ์˜ ์ €์ˆ˜์ค€ ๋ฌผ๋ฆฌ ๊ณ„์ธต ๋Œ€์‹  **๋น„๋””์˜ค ์ฒ˜๋ฆฌ ๋กœ์ง**(DMA, ํ•„ํ„ฐ, ํŒจํ„ด ์ƒ์„ฑ ๋“ฑ)์— ๋” ์ง‘์ค‘ํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. + +## 7. 8b/10b ์ธ์ฝ”๋”ฉ์ด๋ž€ ๋ฌด์—‡์ธ๊ฐ€? +8b/10b ์ธ์ฝ”๋”ฉ์€ ๊ณ ์† ์ง๋ ฌ ํ†ต์‹ ์—์„œ ํŠน์ • ๋ฌผ๋ฆฌ ๊ณ„์ธต์˜ ๋ชฉํ‘œ๋ฅผ ๋‹ฌ์„ฑํ•˜๊ธฐ ์œ„ํ•ด 8๋น„ํŠธ ์‹ฌ๋ณผ์„ 10๋น„ํŠธ ์‹ฌ๋ณผ๋กœ ๋งคํ•‘ํ•˜๋Š” ๋ผ์ธ ์ฝ”๋“œ์ž…๋‹ˆ๋‹ค. + +### ์™œ 8๋น„ํŠธ ๋ฐ์ดํ„ฐ๋ฅผ ์œ„ํ•ด 10๋น„ํŠธ๋ฅผ ์‚ฌ์šฉํ•˜๋Š”๊ฐ€? +1. **DC ๋ฐธ๋Ÿฐ์‹ฑ (DC ํŽธํ–ฅ ๋ฐฉ์ง€)**: + - ์‹ ํ˜ธ๊ฐ€ '1' ๋˜๋Š” '0' ์ƒํƒœ๋ฅผ ๋„ˆ๋ฌด ์˜ค๋ž˜ ์œ ์ง€ํ•˜๋ฉด ์ „์†ก ๋ผ์ธ์ด๋‚˜ AC ๊ฒฐํ•ฉ ์ปคํŒจ์‹œํ„ฐ์— ์ „ํ•˜๊ฐ€ ์Œ“์ž…๋‹ˆ๋‹ค. + - 8b/10b๋Š” ์‹œ๊ฐ„์— ๋”ฐ๋ฅธ '1'๊ณผ '0'์˜ ๊ฐœ์ˆ˜๋ฅผ ๋Œ€๋žต ๊ฐ™๊ฒŒ ์œ ์ง€ํ•˜์—ฌ ํ‰๊ท  DC ๋ ˆ๋ฒจ์„ 0์œผ๋กœ ๋งŒ๋“ญ๋‹ˆ๋‹ค. +2. **ํด๋ก ๋ณต๊ตฌ (์ง€์†์ ์ธ ์ „์ด ๋ฐœ์ƒ)**: + - HDMI์™€ ๊ฐ™์€ ์ง๋ ฌ ๋งํฌ๋Š” ๋ฐ์ดํ„ฐ ๋ ˆ์ธ๋‹น ๋ณ„๋„์˜ ํด๋ก ๋ผ์ธ์„ ๋ณด๋‚ด์ง€ ์•Š์Šต๋‹ˆ๋‹ค. ์ˆ˜์‹ ๊ธฐ๋Š” ๋ฐ์ดํ„ฐ์—์„œ ํด๋ก์„ "์ถ”์ถœ"ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. + - 8b/10b๋Š” ์ˆ˜์‹ ๊ธฐ์˜ PLL์ด ๋น„ํŠธ์ŠคํŠธ๋ฆผ์— ๊ณ ์ •(Lock)๋œ ์ƒํƒœ๋ฅผ ์œ ์ง€ํ•  ์ˆ˜ ์žˆ๋„๋ก ์ถฉ๋ถ„ํ•œ ์ „์ด(0์—์„œ 1 ๋˜๋Š” 1์—์„œ 0)๋ฅผ ๋ณด์žฅํ•ฉ๋‹ˆ๋‹ค. + +### TMDS (HDMI ๋ฒ„์ „) +HDMI๋Š” **TMDS (Transition Minimized Differential Signaling)**๋ผ๊ณ  ๋ถˆ๋ฆฌ๋Š” ํŠน์ˆ˜ ๋ฒ„์ „์„ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. +- **1๋‹จ๊ณ„**: ์ „์ด ํšŸ์ˆ˜๋ฅผ ์ตœ์†Œํ™”ํ•˜๊ธฐ ์œ„ํ•œ XOR ๋˜๋Š” XNOR ์—ฐ์‚ฐ (EMI ๊ฐ์†Œ ๋ชฉ์ ). +- **2๋‹จ๊ณ„**: ํ‰๊ท  ์ „์•• ๋ ˆ๋ฒจ์„ ์œ ์ง€ํ•˜๊ธฐ ์œ„ํ•ด ๋ฐ์ดํ„ฐ๋ฅผ ์„ ํƒ์ ์œผ๋กœ ๋ฐ˜์ „์‹œ์ผœ DC ๋ฐธ๋Ÿฐ์‹ฑ์„ ์ˆ˜ํ–‰ํ•ฉ๋‹ˆ๋‹ค. + +์ด ๊ณผ์ •์„ ํ†ตํ•ด ๋‹จ์ˆœํ•œ 8๋น„ํŠธ RGB ์ปฌ๋Ÿฌ ๊ฐ’์€ ๋‹จ ํ•˜๋‚˜์˜ ๋น„ํŠธ๋„ ์žƒ์ง€ ์•Š๊ณ  ์ˆ˜ ๋ฏธํ„ฐ์˜ HDMI ์ผ€์ด๋ธ”์„ ํ†ต๊ณผํ•  ์ˆ˜ ์žˆ๋Š” ๊ฒฌ๊ณ ํ•œ 10๋น„ํŠธ ํŒจํ‚ท์œผ๋กœ ๋ณ€ํ™˜๋ฉ๋‹ˆ๋‹ค. + +## 8. ์ „๋ฌธ์  ๋งฅ๋ฝ: LVDS vs HDMI/TMDS +์‚ฐ์—… ๋ฐ ์ „๋ฌธ ํ™˜๊ฒฝ์—์„œ๋Š” ๋…ธํŠธ๋ถ ํŒจ๋„์ด๋‚˜ TV T-CON ๋ณด๋“œ์™€ ๊ฐ™์€ ๋‚ด๋ถ€ ๋””์Šคํ”Œ๋ ˆ์ด ์—ฐ๊ฒฐ์— **LVDS (Low Voltage Differential Signaling)**๊ฐ€ ์ž์ฃผ ์‚ฌ์šฉ๋ฉ๋‹ˆ๋‹ค. + +### LVDS (Low Voltage Differential Signaling) +- **ํด๋กํ‚น**: HDMI/TMDS๊ฐ€ 10๋น„ํŠธ ์ธ์ฝ”๋”ฉ(10:1)์„ ์‚ฌ์šฉํ•˜๋Š” ๋ฐ˜๋ฉด, ํ‘œ์ค€ LVDS๋Š” ์ข…์ข… **7:1 ์ง๋ ฌํ™”** (OpenLDI ํ‘œ์ค€)๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. +- **๋ฐ์ดํ„ฐ ๋ฐ€๋„**: ํด๋ก ์‚ฌ์ดํด๋‹น ๋ ˆ์ธ๋‹น 7๋น„ํŠธ์˜ ๋ฐ์ดํ„ฐ๋ฅผ ๋ณด๋ƒ…๋‹ˆ๋‹ค. +- **UHD์˜ ๊ณผ์ œ**: UHD (3840x2160)์˜ ๊ฒฝ์šฐ ๋ฐ์ดํ„ฐ ๋ ˆ์ดํŠธ๊ฐ€ ์ฒœ๋ฌธํ•™์ (~12Gbps)์ด์–ด์„œ ๋‹จ์ผ LVDS ๋ ˆ์ธ์œผ๋กœ๋Š” ๊ฐ๋‹นํ•  ์ˆ˜ ์—†์Šต๋‹ˆ๋‹ค. +- **UHD๋ฅผ ์œ„ํ•œ ํ•ด๊ฒฐ์ฑ…**: ์ œ์กฐ์‚ฌ๋“ค์€ **๋ฉ€ํ‹ฐ ๋ ˆ์ธ LVDS**(๋“€์–ผ, ์ฟผ๋“œ ๋˜๋Š” 8๋ ˆ์ธ)๋ฅผ ์‚ฌ์šฉํ•˜๊ฑฐ๋‚˜, ๋ ˆ์ธ๋‹น ๋” ๋†’์€ ์†๋„(์ตœ๋Œ€ 4Gbps)๋ฅผ ๋‚ผ ์ˆ˜ ์žˆ๊ณ  8b/10b ์ธ์ฝ”๋”ฉ์„ ์‚ฌ์šฉํ•˜๋Š” **V-by-One HS**์™€ ๊ฐ™์€ ์ตœ์‹  ํ‘œ์ค€์œผ๋กœ ์ „ํ™˜ํ•ฉ๋‹ˆ๋‹ค. + +### ์ธํ„ฐํŽ˜์ด์Šค ๋น„๊ต +| ์ธํ„ฐํŽ˜์ด์Šค | ์ธ์ฝ”๋”ฉ | ์ง๋ ฌํ™” | ์ฃผ์š” ์‚ฌ์šฉ ์‚ฌ๋ก€ | +| :--- | :--- | :--- | :--- | +| **HDMI/TMDS** | 8b/10b (TMDS) | 10:1 | ์™ธ๋ถ€ ๋ชจ๋‹ˆํ„ฐ, TV | +| **ํ‘œ์ค€ LVDS** | ์—†์Œ (Raw) | 7:1 | ๋…ธํŠธ๋ถ/TV ๋‚ด๋ถ€ ํŒจ๋„ | + +### V-by-One HS (UHD/4K์˜ ํ‘œ์ค€) +THine Electronics์—์„œ ๊ฐœ๋ฐœํ•œ **V-by-One HS**๋Š” ํ˜„๋Œ€ 4K/8K TV์—์„œ ๋ฉ”์ธ ๋ณด๋“œ์™€ T-CON(ํƒ€์ด๋ฐ ์ปจํŠธ๋กค๋Ÿฌ)์„ ์—ฐ๊ฒฐํ•˜๋Š” ์‚ฌ์‹ค์ƒ์˜ ํ‘œ์ค€์ž…๋‹ˆ๋‹ค. + +- **์ธ์ฝ”๋”ฉ**: LVDS์˜ "Raw" 7:1 ํฌ๋งท์—์„œ ํฌ๊ฒŒ ๋ฐœ์ „ํ•œ **8b/10b ์ธ์ฝ”๋”ฉ**์„ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. ์ด๋Š” DC ๋ฐธ๋Ÿฐ์Šค๋ฅผ ๋ณด์žฅํ•˜๊ณ  AC ๊ฒฐํ•ฉ์„ ๊ฐ„์†Œํ™”ํ•ฉ๋‹ˆ๋‹ค. +- **ํด๋ก ๋ณต๊ตฌ (CDR)**: ๋ณ„๋„์˜ ํด๋ก ํŽ˜์–ด๊ฐ€ ํ•„์š”ํ•œ LVDS์™€ ๋‹ฌ๋ฆฌ, V-by-One HS๋Š” ๋ฐ์ดํ„ฐ ์ŠคํŠธ๋ฆผ์— ํด๋ก์„ ๋‚ด์žฅ(Clock Data Recovery)ํ•˜์—ฌ EMI์™€ ์ผ€์ด๋ธ” ์ˆ˜๋ฅผ ํฌ๊ฒŒ ์ค„์ž…๋‹ˆ๋‹ค. +- **์†๋„**: LVDS๊ฐ€ 1Gbps ๋ถ€๊ทผ์—์„œ ํ•œ๊ณ„์— ๋ถ€๋”ชํžˆ๋Š” ๋ฐ˜๋ฉด, V-by-One HS๋Š” **๋ ˆ์ธ๋‹น ์ตœ๋Œ€ 4Gbps**๊นŒ์ง€ ๊ฐ€๋Šฅํ•ฉ๋‹ˆ๋‹ค. +- **ํšจ์œจ์„ฑ**: 4K 60Hz 10๋น„ํŠธ ํŒจ๋„์˜ ๊ฒฝ์šฐ ์•ฝ 24์Œ์˜ LVDS๊ฐ€ ํ•„์š”ํ•˜์ง€๋งŒ, V-by-One HS๋Š” ๋‹จ **8๊ฐœ ๋ ˆ์ธ**์œผ๋กœ ์ถฉ๋ถ„ํ•ฉ๋‹ˆ๋‹ค. + +## 9. ์„ฑ๊ณต์˜ ์ฒ™๋„: ์•„์ด ๋‹ค์ด์–ด๊ทธ๋žจ (Eye Diagram) +**์•„์ด ๋‹ค์ด์–ด๊ทธ๋žจ**์€ HDMI, LVDS, V-by-One๊ณผ ๊ฐ™์€ ๊ณ ์† ๋””์ง€ํ„ธ ๋งํฌ์˜ ์‹ ํ˜ธ ๋ฌด๊ฒฐ์„ฑ(Signal Integrity)์„ ํ‰๊ฐ€ํ•˜๋Š” ์‹œ๊ฐ์  ๋„๊ตฌ์ž…๋‹ˆ๋‹ค. + +### ๋ฌด์—‡์ธ๊ฐ€? +- ์˜ค์‹ค๋กœ์Šค์ฝ”ํ”„์—์„œ ๋ฐ์ดํ„ฐ ์‹ ํ˜ธ์˜ ์—ฌ๋Ÿฌ ์ฃผ๊ธฐ๋ฅผ ๊ฒน์ณ์„œ ์ƒ์„ฑํ•ฉ๋‹ˆ๋‹ค. +- ์‹ ํ˜ธ๊ฐ€ ์•ˆ์ •์ ์ด๊ณ  ๋…ธ์ด์ฆˆ/์ง€ํ„ฐ๊ฐ€ ์ ์œผ๋ฉด ๊ฒฐ๊ณผ ์ด๋ฏธ์ง€๊ฐ€ ์—ด๋ ค ์žˆ๋Š” "๋ˆˆ"์ฒ˜๋Ÿผ ๋ณด์ž…๋‹ˆ๋‹ค. + +### ํ•ด์„ ๋ฐฉ๋ฒ• +- **๋ˆˆ์˜ ๋†’์ด (Eye Height)**: ๋…ธ์ด์ฆˆ ๋งˆ์ง„์„ ๋‚˜ํƒ€๋ƒ…๋‹ˆ๋‹ค. ๋†’์ด๊ฐ€ ๋†’์„์ˆ˜๋ก '0'๊ณผ '1'์„ ๊ตฌ๋ถ„ํ•˜๊ธฐ ์‰ฝ์Šต๋‹ˆ๋‹ค. +- **๋ˆˆ์˜ ํญ (Eye Width)**: ์ง€ํ„ฐ์™€ ํƒ€์ด๋ฐ ๋งˆ์ง„์„ ๋‚˜ํƒ€๋ƒ…๋‹ˆ๋‹ค. ํญ์ด ๋„“์„์ˆ˜๋ก ํƒ€์ด๋ฐ์ด ์•ˆ์ •์ ์ž„์„ ์˜๋ฏธํ•ฉ๋‹ˆ๋‹ค. +- **๋ˆˆ์˜ ๋‹ซํž˜ (Eye Closing)**: ๋ˆˆ์ด ๋‹ซํžˆ๊ฑฐ๋‚˜ ํ๋ฆฟํ•˜๋‹ค๋ฉด ์‹ ํ˜ธ์— ๊ฐ„์„ญ(ํฌ๋กœ์Šคํ† ํฌ, ๋ฐ˜์‚ฌ ๋˜๋Š” ๊ฐ์‡„)์ด ๋„ˆ๋ฌด ๋งŽ์•„ ์ˆ˜์‹ ๊ธฐ๊ฐ€ ๋ฐ์ดํ„ฐ๋ฅผ ๋ณต๊ตฌํ•˜์ง€ ๋ชปํ•  ๊ฐ€๋Šฅ์„ฑ์ด ํผ์„ ์˜๋ฏธํ•ฉ๋‹ˆ๋‹ค. + +### HDMI์™€์˜ ์—ฐ๊ฒฐ +HDMI ์ปดํ”Œ๋ผ์ด์–ธ์Šค ํ…Œ์ŠคํŠธ๋Š” "์•„์ด ๋งˆ์Šคํฌ(Eye Mask)"๋ฅผ ์—„๊ฒฉํ•˜๊ฒŒ ๊ทœ์ •ํ•ฉ๋‹ˆ๋‹ค. ๊ฒฐ๊ณผ ๋‹ค์ด์–ด๊ทธ๋žจ์ด ์ด ์ค‘์•™ ์˜์—ญ์„ ์นจ๋ฒ”ํ•˜์ง€ ์•Š์•„์•ผ ํ‘œ์ค€์„ ์ค€์ˆ˜ํ•˜๋Š” ์œ ํšจํ•œ ์‹ ํ˜ธ๋กœ ๊ฐ„์ฃผ๋ฉ๋‹ˆ๋‹ค. + +์•„์ด ๋‹ค์ด์–ด๊ทธ๋žจ์„ ์ดํ•ดํ•˜๋Š” ๊ฒƒ์€ ์—ฌ๋Ÿฌ๋ถ„์˜ ๊ณ ์† Verilog ๋กœ์ง๊ณผ ๋ฌผ๋ฆฌ์  PCB ๋ ˆ์ด์•„์›ƒ์ด ์™„๋ฒฝํ•˜๊ฒŒ ์กฐํ™”๋ฅผ ์ด๋ฃจ์–ด ์ž‘๋™ํ•˜๊ณ  ์žˆ์Œ์„ ์ž…์ฆํ•˜๋Š” ๊ถ๊ทน์ ์ธ ๋ฐฉ๋ฒ•์ž…๋‹ˆ๋‹ค! + +## 10. ํ•˜๋“œ์›จ์–ด ์—”์ง„: SERDES +**SERDES**๋Š” **Serializer / Deserializer**์˜ ์•ฝ์ž์ž…๋‹ˆ๋‹ค. ๋ณ‘๋ ฌ ๋ฐ์ดํ„ฐ๋ฅผ ์ง๋ ฌ ๋ฐ์ดํ„ฐ๋กœ(๋˜๋Š” ๊ทธ ๋ฐ˜๋Œ€๋กœ) ๋ณ€ํ™˜ํ•˜์—ฌ ๊ณ ์† ์ „์†ก์„ ๊ฐ€๋Šฅํ•˜๊ฒŒ ํ•˜๋Š” ํ•ต์‹ฌ ํ•˜๋“œ์›จ์–ด ๋ธ”๋ก์ž…๋‹ˆ๋‹ค. + +### ๋ณธ ํ”„๋กœ์ ํŠธ์™€์˜ ๊ด€๊ณ„ +1. **์ง๋ ฌํ™” (TX ์ธก)**: FPGA(๋˜๋Š” HDMI ์นฉ) ๋‚ด๋ถ€์—์„œ 10๋น„ํŠธ ๋˜๋Š” 8๋น„ํŠธ ๋ณ‘๋ ฌ ๋ฐ์ดํ„ฐ๊ฐ€ ๋งค์šฐ ๋†’์€ ํด๋ก ์†๋„๋กœ ๋™์ž‘ํ•˜๋Š” ์‹œํ”„ํŠธ ๋ ˆ์ง€์Šคํ„ฐ๋กœ ์ž…๋ ฅ๋˜์–ด, ์ฐจ๋™ ํŽ˜์–ด๋ฅผ ํ†ตํ•ด ๋น„ํŠธ ๋‹จ์œ„๋กœ ํ•˜๋‚˜์”ฉ ๋‚˜๊ฐ‘๋‹ˆ๋‹ค. +2. **๋ณ‘๋ ฌํ™” (RX ์ธก)**: ๋ชจ๋‹ˆํ„ฐ์˜ ์ˆ˜์‹ ๊ธฐ๋Š” ๊ทธ ๋น„ํŠธ ์ŠคํŠธ๋ฆผ์„ ๋ฐ›์•„ ํด๋ก ๋ฐ์ดํ„ฐ ๋ณต๊ตฌ(CDR)๋ฅผ ํ†ตํ•ด ๋ณ‘๋ ฌ 10๋น„ํŠธ/8๋น„ํŠธ ์‹ฌ๋ณผ๋กœ ์žฌ๊ตฌ์„ฑํ•ฉ๋‹ˆ๋‹ค. + +### ์ฃผ์š” ํŠน์ง• +- **PISO / SIPO**: ์ „์†ก์„ ์œ„ํ•œ Parallel-In Serial-Out(PISO)๊ณผ ์ˆ˜์‹ ์„ ์œ„ํ•œ Serial-In Parallel-Out(SIPO). +- **ํ†ตํ•ฉ**: ์ผ๋ฐ˜ ํŒจ๋ธŒ๋ฆญ ๋กœ์ง์€ ์ถฉ๋ถ„ํžˆ ๋น ๋ฅด๊ฒŒ ํ† ๊ธ€ํ•  ์ˆ˜ ์—†๊ธฐ ๋•Œ๋ฌธ์—(์˜ˆ: >1 Gbps), ๋งŽ์€ ํ•˜์ด์—”๋“œ FPGA์—์„œ๋Š” SERDES๋ฅผ ์ „์šฉ "Hard IP" ๋ธ”๋ก์œผ๋กœ ์ œ๊ณตํ•ฉ๋‹ˆ๋‹ค. +- **๋ชจ๋“  ๊ฒƒ์˜ ํ•ต์‹ฌ**: HDMI (10:1), LVDS (7:1), V-by-One ๋ชจ๋‘ SERDES๋ฅผ ๊ธฐ๋ณธ "๋ฌผ๋ฆฌ ์—”์ง„"์œผ๋กœ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. + +**8b/10b ์ธ์ฝ”๋”ฉ**(๋กœ์ง), **SERDES**(ํ•˜๋“œ์›จ์–ด ์—”์ง„), ๊ทธ๋ฆฌ๊ณ  **์•„์ด ๋‹ค์ด์–ด๊ทธ๋žจ**(๊ฒ€์ฆ)์„ ๊ฒฐํ•ฉํ•จ์œผ๋กœ์จ ๊ณ ์† ๋””์ง€ํ„ธ ์„ค๊ณ„์˜ ์„ธ ์š”์†Œ๋ฅผ ์™„์„ฑํ•˜๊ฒŒ ๋ฉ๋‹ˆ๋‹ค! + +## 11. IP vs ์ปค์Šคํ…€ ๊ตฌํ˜„ ๋ฐ ๋ผ์ด์„ ์Šค +์—…๊ณ„์—์„œ IP(Intellectual Property)๋ฅผ ์‚ฌ์šฉํ• ์ง€ ์•„๋‹ˆ๋ฉด ์ปค์Šคํ…€ RTL์„ ์ž‘์„ฑํ• ์ง€๋Š” ์ค‘์š”ํ•œ ์—”์ง€๋‹ˆ์–ด๋ง ๊ฒฐ์ • ์‚ฌํ•ญ์ž…๋‹ˆ๋‹ค. + +### Hard IP vs Soft IP +- **Hard IP (SERDES/ํŠธ๋žœ์‹œ๋ฒ„)**: ๊ณ ์† ๋ฌผ๋ฆฌ ๊ณ„์ธต์—๋Š” ๋ฐ˜๋“œ์‹œ FPGA์˜ Hard IP๋ฅผ ์‚ฌ์šฉํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. ์šฐ๋ฆฌ๊ฐ€ ํ•˜๋Š” ๊ฒƒ์ฒ˜๋Ÿผ ์ผ๋ฐ˜ Verilog ๋กœ์ง์€ ์ˆ˜ Gbps๋กœ ํ† ๊ธ€ํ•  ์ˆ˜ ์—†๊ธฐ ๋•Œ๋ฌธ์ž…๋‹ˆ๋‹ค. +- **Soft IP (ํ”„๋กœํ† ์ฝœ ์ปจํŠธ๋กค๋Ÿฌ)**: ๋กœ์ง ๋ถ€๋ถ„(HDMI ์ปจํŠธ๋กค๋Ÿฌ, TMDS ์ธ์ฝ”๋”)์— ๋Œ€ํ•ด์„œ๋Š” ์ƒ์šฉ IP๋ฅผ ๊ตฌ๋งคํ•˜๊ฑฐ๋‚˜ ์ง์ ‘ ์ž‘์„ฑํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ๋ณธ ํ”„๋กœ์ ํŠธ์ฒ˜๋Ÿผ ์ง์ ‘ ์ž‘์„ฑํ•˜๋Š” ๊ฒƒ์€ ๋น„์šฉ์„ ์ ˆ๊ฐํ•˜๊ณ  ๊นŠ์€ ๊ธฐ์ˆ ์  ์ง€์‹์„ ์–ป์„ ์ˆ˜ ์žˆ๋Š” ํ›Œ๋ฅญํ•œ ๋ฐฉ๋ฒ•์ž…๋‹ˆ๋‹ค! + +### ๋ผ์ด์„ ์Šค ๋ฐ ๋กœ์—ดํ‹ฐ +- **ํ‘œ์ค€ ๋ผ์ด์„ ์Šค**: HDMI ์ด๋ฆ„๊ณผ ๋กœ๊ณ ๋ฅผ ์‚ฌ์šฉํ•˜๋ ค๋ฉด HDMI Adopter๊ฐ€ ๋˜์–ด ์—ฐํšŒ๋น„ ๋ฐ ๋กœ์—ดํ‹ฐ(์˜ˆ: ์žฅ์น˜๋‹น $0.04 - $0.15)๋ฅผ ์ง€๋ถˆํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +- **IP ๋น„์šฉ**: Synopsys๋‚˜ Cadence ๊ฐ™์€ ํšŒ์‚ฌ์˜ ์ƒ์šฉ HDMI IP๋Š” ์ˆ˜์ฒœ๋งŒ ์›์— ๋‹ฌํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. +- **์ปค์Šคํ…€ RTL์„ ์ž‘์„ฑํ•˜๋Š” ์ด์œ **: ์ง์ ‘ ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ๋ฅผ ์ž‘์„ฑํ•˜๊ณ  ๊ธฐ๋ณธ AXI/Avalon ์ธํ„ฐํŽ˜์ด์Šค๋ฅผ ์‚ฌ์šฉํ•จ์œผ๋กœ์จ ๊ฐ’๋น„์‹ผ ๋ผ์ด์„ ์Šค ๋น„์šฉ์„ ํ”ผํ•˜๊ณ  ์‹œ์Šคํ…œ์˜ "์†์‚ด"์„ ๋ฐฐ์šธ ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. + +## 12. ๋น„๊ต: ๊ธฐ์กด VGA vs ํ˜„๋Œ€์  HDMI +DE1๊ณผ ๊ฐ™์€ ๋ณด๋“œ์—์„œ VGA ์ถœ๋ ฅ์„ ํ•ด๋ณธ ๊ฒฝํ—˜์ด ์žˆ๋‹ค๋ฉด ์ต์ˆ™ํ•œ ๊ฐœ๋…๋„ ์žˆ๊ฒ ์ง€๋งŒ, ํ›จ์”ฌ ๋” ๋†’์€ ์ˆ˜์ค€์˜ ๋„์ „ ๊ณผ์ œ๋“ค์ด ์กด์žฌํ•ฉ๋‹ˆ๋‹ค. + +| ๊ธฐ๋Šฅ | VGA (๊ธฐ์กด/DE1) | HDMI (ADV7513/DE10-Nano) | +| :--- | :--- | :--- | +| **๋ฌผ๋ฆฌ ๊ณ„์ธต** | ์•„๋‚ ๋กœ๊ทธ (์ €ํ•ญ ์‚ฌ๋‹ค๋ฆฌ/DAC) | ๋””์ง€ํ„ธ ์ง๋ ฌ (ํŠธ๋žœ์‹œ๋ฒ„ ์นฉ์„ ํ†ตํ•œ TMDS) | +| **๋™๊ธฐ ๋กœ์ง** | HSync/VSync ์ œ๋„ค๋ ˆ์ดํ„ฐ | ๋™์ผํ•˜์ง€๋งŒ **๋ฐ์ดํ„ฐ ์ธ์—์ด๋ธ”(DE)**๋„ ํ•„์š” | +| **์„ค์ •** | ํ•˜๋“œ์›จ์–ด ์ „์šฉ (๋ฐฐ์„ ) | **H/W + S/W** (I2C ๊ตฌ์„ฑ ํ•„์š”) | +| **์†Œ์Šค** | ์ฃผ๋กœ ROM/๋‚ด๋ถ€ RAM | **DMA(AXI)๋ฅผ ํ†ตํ•œ ์™ธ๋ถ€ DDR3** | +| **ํ•ด์ƒ๋„** | ์ฃผ๋กœ 640x480 (25MHz) | **1280x720 (74.25MHz)** ๋˜๋Š” ๊ทธ ์ด์ƒ | + +### HDMI๊ฐ€ ๋” ๋ฐœ์ „๋œ ํ˜•ํƒœ์ธ ์ด์œ : +1. **์ œ์–ด ๋กœ์ง**: Nios II ๋“œ๋ผ์ด๋ฒ„๋ฅผ ํ†ตํ•ด ADV7513์„ ๊ด€๋ฆฌํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. RTL์ด ์™„๋ฒฝํ•˜๋”๋ผ๋„ I2C๊ฐ€ ์‹คํŒจํ•˜๋ฉด ๊ฒ€์€ ํ™”๋ฉด๋งŒ ๋‚˜์˜ต๋‹ˆ๋‹ค. +2. **์‹œ์Šคํ…œ ๋งฅ๋ฝ**: ๋ฒ„์ŠคํŠธ DMA๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ DDR3์—์„œ ํ”ฝ์…€์„ ๊ฐ€์ ธ์˜ค๋Š” ๊ฒƒ์€ ์ž‘์€ ๋‚ด๋ถ€ ๋ฒ„ํผ์—์„œ ์ฝ๋Š” ๊ฒƒ๋ณด๋‹ค ํ›จ์”ฌ ๋ณต์žกํ•ฉ๋‹ˆ๋‹ค. +3. **์‹ ํ˜ธ ๋ฌด๊ฒฐ์„ฑ**: ๊ณ ์† ๋””์ง€ํ„ธ ์‹ ํ˜ธ(74.25MHz ์ด์ƒ)๋Š” ๊ธฐ์กด VGA๋ณด๋‹ค ํƒ€์ด๋ฐ ์ง€์—ฐ๊ณผ ์Šคํ(Skew)์— ํ›จ์”ฌ ๋” ๋ฏผ๊ฐํ•ฉ๋‹ˆ๋‹ค. + +## 13. ๋ฉ”๋ชจ๋ฆฌ ์„ ํƒ: SRAM vs DDR3 +DE1 VGA์™€ ๊ฐ™์€ ์ด์ „ ํ”„๋กœ์ ํŠธ์—์„œ๋Š” ๋‹จ์ˆœํ•จ ๋•Œ๋ฌธ์— **SRAM**์„ ์ž์ฃผ ์‚ฌ์šฉํ–ˆ์ง€๋งŒ, ํ˜„๋Œ€์ ์ธ ๋น„๋””์˜ค ์ฒ˜๋ฆฌ๋Š” **DDR3**์˜ ๋Œ€์šฉ๋Ÿ‰์„ ํ•„์š”๋กœ ํ•ฉ๋‹ˆ๋‹ค. + +| ๊ธฐ๋Šฅ | ๊ธฐ์กด SRAM (DE1) | ํ˜„๋Œ€์  DDR3 (DE10-Nano) | +| :--- | :--- | :--- | +| **๋ณต์žก๋„** | ๋‹จ์ˆœ (์ง์ ‘ ์ฃผ์†Œ/๋ฐ์ดํ„ฐ ์ œ์–ด) | ๋งค์šฐ ๋ณต์žก (DDR ์ปจํŠธ๋กค๋Ÿฌ/AXI ํ”„๋กœํ† ์ฝœ) | +| **์šฉ๋Ÿ‰** | ๋งค์šฐ ์ž‘์Œ (์˜ˆ: 512KB) | ๋งค์šฐ ํผ (1GB) | +| **์ง€์—ฐ ์‹œ๊ฐ„** | ๋งค์šฐ ๋‚ฎ์Œ (๊ณ ์ •) | ๋†’์Œ/๊ฐ€๋ณ€์  (๋ฒ„์ŠคํŠธ ๋ฐ FIFO ํ•„์š”) | +| **์—ฐ๊ฒฐ** | FPGA ํ•€์—์„œ ์ง์ ‘ ์นฉ์œผ๋กœ | HPS ๋ธŒ๋ฆฟ์ง€ ๋ฐ ์ธํ„ฐ์ปค๋„ฅํŠธ ๋กœ์ง ๊ฒฝ์œ  | + +- **DDR3 ๊ตฌํ˜„**: ๋‹จ์ˆœํ•œ FSM์œผ๋กœ DDR3๋ฅผ ์ง์ ‘ ๊ตฌ๋™ํ•  ์ˆ˜ ์—†๊ธฐ์—, **๋ฒ„์ŠคํŠธ DMA**๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ๋ฐ์ดํ„ฐ๋ฅผ ๋ญ‰์น˜๋กœ ๊ฐ€์ ธ์˜ค๊ณ  **FIFO**๋ฅผ ์‚ฌ์šฉํ•ด ๊ฐ€๋ณ€์ ์ธ ์ง€์—ฐ ์‹œ๊ฐ„์„ ๋ฉ”์›€์œผ๋กœ์จ ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ๊ฐ€ ํ•„์š”ํ•  ๋•Œ ํ•ญ์ƒ ํ”ฝ์…€์ด ์ค€๋น„๋˜๋„๋ก ํ•ฉ๋‹ˆ๋‹ค. + +## 14. ๋ถ€๋“œ๋Ÿฌ์šด ๋น„๋””์˜ค: ๋”๋ธ” ๋ฒ„ํผ๋ง (Double Buffering) +"ํ™”๋ฉด ์ฐข์–ด์ง(Screen Tearing)" ํ˜„์ƒ์„ ๋ฐฉ์ง€ํ•˜๊ธฐ ์œ„ํ•ด DDR3 ๊ธฐ๋ฐ˜ ๋น„๋””์˜ค ์‹œ์Šคํ…œ์—์„œ๋Š” **๋”๋ธ” ๋ฒ„ํผ๋ง**์ด ํ•„์ˆ˜์ ์ž…๋‹ˆ๋‹ค. + +### ๋ฌธ์ œ: ํ™”๋ฉด ์ฐข์–ด์ง +- ๋น„๋””์˜ค DMA๊ฐ€ ์ฝ๊ณ  ์žˆ๋Š” ๋™์•ˆ ARM์ด๋‚˜ Nios II๊ฐ€ DDR3 ๋ฉ”๋ชจ๋ฆฌ๋ฅผ ์—…๋ฐ์ดํŠธํ•˜๋ฉด, ํ™”๋ฉด ์ƒ๋‹จ์—๋Š” *์ƒˆ๋กœ์šด* ํ”„๋ ˆ์ž„์ด, ํ•˜๋‹จ์—๋Š” *์ด์ „* ํ”„๋ ˆ์ž„์ด ๋ณด์ผ ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. + +### ํ•ด๊ฒฐ์ฑ…: ํ”„๋ก ํŠธ ๋ฐ ๋ฐฑ ๋ฒ„ํผ +- **ํ”„๋ก ํŠธ ๋ฒ„ํผ (Front Buffer)**: ํ˜„์žฌ ๋น„๋””์˜ค DMA๊ฐ€ ์ฝ์–ด์„œ ๋ชจ๋‹ˆํ„ฐ์— ํ‘œ์‹œํ•˜๊ณ  ์žˆ๋Š” ๋ฉ”๋ชจ๋ฆฌ ์˜์—ญ. +- **๋ฐฑ ๋ฒ„ํผ (Back Buffer)**: ๋‹ค์Œ ํ”„๋ ˆ์ž„์ด ์ค€๋น„/๊ทธ๋ ค์ง€๊ณ  ์žˆ๋Š” ๋ณ„๋„์˜ ๋ฉ”๋ชจ๋ฆฌ ์˜์—ญ. +- **๋ฒ„ํผ ์Šค์™€ํ•‘ (V-Sync ์ „ํ™˜)**: ๋ฐฑ ๋ฒ„ํผ๊ฐ€ ์ค€๋น„๋˜๋ฉด **์ˆ˜์ง ๋ธ”๋žญํ‚น ๊ตฌ๊ฐ„ (V-Sync)**์„ ๊ธฐ๋‹ค๋ ค DMA์˜ ์‹œ์ž‘ ์ฃผ์†Œ๋ฅผ ์—…๋ฐ์ดํŠธํ•ฉ๋‹ˆ๋‹ค. ์ด๋ฅผ ํ†ตํ•ด ํ”ฝ์…€์ด ๊ทธ๋ ค์ง€์ง€ ์•Š๋Š” ์‹œ์ ์—๋งŒ ์ „ํ™˜๋˜๋„๋ก ๋ณด์žฅํ•ฉ๋‹ˆ๋‹ค. + +ํ˜„๋Œ€ ์‹œ์Šคํ…œ์—์„œ 1GB์— ๋‹ฌํ•˜๋Š” DDR3 ๊ณต๊ฐ„์€ ๋‘ ๊ฐœ์˜ 32MB ์˜์—ญ์„ ํ• ๋‹นํ•˜๊ธฐ์— ์ถฉ๋ถ„ํ•ฉ๋‹ˆ๋‹ค. ์ด ๊ธฐ์ˆ ์€ ๋น„๋””์˜ค๋ฅผ ๊นจ๋—ํ•˜๊ณ  ๋ถ€๋“œ๋Ÿฝ๊ฒŒ ๋งŒ๋“ค์–ด์ฃผ๋Š” ํ•ต์‹ฌ์ž…๋‹ˆ๋‹ค. + +## 15. ๋น„๋””์˜ค ๋ฐ์ดํ„ฐ ๋กœ๋”ฉ: SD ์นด๋“œ โžก๏ธ DDR3 +๋Œ€๋Ÿ‰์˜ ๋น„๋””์˜ค ๋ฐ์ดํ„ฐ๋‚˜ ์ด๋ฏธ์ง€ ์‹œํ€€์Šค๋ฅผ DDR3์— ๋„ฃ๋Š” ๊ฐ€์žฅ ์‹ค์‹œ๊ฐ„์ ์ธ ๋ฐฉ๋ฒ•์€ ๋ฆฌ๋ˆ…์Šค๊ฐ€ ๊ตฌ๋™๋˜๋Š” **ARM Cortex-A9 (HPS)**์„ ์‚ฌ์šฉํ•˜๋Š” ๊ฒƒ์ž…๋‹ˆ๋‹ค. + +### ํŒŒ์ดํ”„๋ผ์ธ +1. **์ €์žฅ**: SCP ๋“ฑ์„ ํ†ตํ•ด ๋น„๋””์˜ค ํŒŒ์ผ์„ SD ์นด๋“œ๋กœ ๋ณต์‚ฌํ•ฉ๋‹ˆ๋‹ค. +2. **์ฝ๊ธฐ**: ๋ฆฌ๋ˆ…์Šค์—์„œ C ๋˜๋Š” Python ์•ฑ์œผ๋กœ ํŒŒ์ผ์„ ์ฝ์Šต๋‹ˆ๋‹ค. +3. **๋งคํ•‘**: `/dev/mem`์— `mmap()`์„ ์‚ฌ์šฉํ•˜์—ฌ ๋ฌผ๋ฆฌ DDR3 ์ฃผ์†Œ(์˜ˆ: `0x20000000`)๋ฅผ ์•ฑ์˜ ๊ฐ€์ƒ ์ฃผ์†Œ ๊ณต๊ฐ„์œผ๋กœ ๋งคํ•‘ํ•ฉ๋‹ˆ๋‹ค. +4. **์“ฐ๊ธฐ**: ํŒŒ์ผ ๋ฒ„ํผ๋กœ๋ถ€ํ„ฐ ๋งคํ•‘๋œ DDR3 ์˜์—ญ์œผ๋กœ ํ”ฝ์…€ ๋ฐ์ดํ„ฐ๋ฅผ ๋ณต์‚ฌํ•ฉ๋‹ˆ๋‹ค. + +์ด ๊ณผ์ •์„ ์ดˆ๋‹น 30๋ฒˆ ๋˜๋Š” 60๋ฒˆ ๋ฐ˜๋ณตํ•˜๋ฉด SD ์นด๋“œ์—์„œ HDMI ๋ชจ๋‹ˆํ„ฐ๋กœ ์ง์ ‘ ์˜ํ™”๊ฐ€ ์žฌ์ƒ๋ฉ๋‹ˆ๋‹ค! + +## 16. ์‹ค์‹œ๊ฐ„ ๋””์ฝ”๋”ฉ: MP4์™€ CPU์˜ ํ•œ๊ณ„ +**MP4 (H.264)**์™€ ๊ฐ™์€ ์••์ถ• ํฌ๋งท์„ ์ฒ˜๋ฆฌํ•˜๋Š” ๊ฒƒ์€ ๋‹จ์ˆœํžˆ ์›๋ณธ ๋ฐ์ดํ„ฐ๋ฅผ ๋ณต์‚ฌํ•˜๋Š” ๊ฒƒ๋ณด๋‹ค ํ›จ์”ฌ ๋” CPU ์ง‘์•ฝ์ ์ธ ์ž‘์—…์ž…๋‹ˆ๋‹ค. + +### ๐Ÿš€ ํ•ด๊ฒฐ์ฑ…: "์„ค์น˜ ์—†๋Š” FFmpeg" ๋‹ค์šด๋กœ๋“œ ๋ฐ ํŒŒ์ดํ”„ ํ™œ์šฉ (๊ฐ•๋ ฅ ์ถ”์ฒœ) +๋‹ค๋ฅธ ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๋ฅผ ๋ณต์žกํ•˜๊ฒŒ ์„ค์น˜ํ•  ํ•„์š” ์—†์ด, ํŒŒ์ผ ํ•˜๋‚˜๋งŒ ๋ฐ›์•„์„œ ์‹คํ–‰ํ•˜๋Š” **Static Build** ๋ฒ„์ „์„ ์‚ฌ์šฉํ•˜๋Š” ๊ฒƒ์ด ๊ฐ€์žฅ ํšจ์œจ์ ์ž…๋‹ˆ๋‹ค. + +**1. PC์—์„œ ๋‹ค์šด๋กœ๋“œ** +DE10-Nano๋Š” **ARMv7 (32bit)** ์•„ํ‚คํ…์ฒ˜(armhf)๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. PC์—์„œ ์•„๋ž˜ ํŒŒ์ผ์„ ๋‹ค์šด๋กœ๋“œํ•˜์—ฌ SD์นด๋“œ๋กœ ์˜ฎ๊ธฐ์„ธ์š”. +- **ํŒŒ์ผ๋ช…**: `ffmpeg-release-armhf-static.tar.xz` +- **์ถœ์ฒ˜**: [John Van Sickle - FFmpeg Static Builds](https://johnvansickle.com/ffmpeg/) + +**2. DE10-Nano์—์„œ ์„ค์น˜** +```bash +# ์••์ถ• ํ’€๊ธฐ +tar -xvf ffmpeg-release-armhf-static.tar.xz + +# ํด๋” ์ด๋™ +cd ffmpeg-*-armhf-static + +# ์‹คํ–‰ ํ™•์ธ +./ffmpeg -version +``` + +**3. C ์ฝ”๋“œ์™€ ์—ฐ๋™ (ํŒŒ์ดํ”„ ๊ธฐ๋ฒ•)** +๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ ํ—ค๋” ํŒŒ์ผ ์—†์ด ๋ฆฌ๋ˆ…์Šค์˜ **ํŒŒ์ดํ”„(|)** ๊ธฐ๋Šฅ์„ ์‚ฌ์šฉํ•˜๋ฉด ์•„์ฃผ ์šฐ์•„ํ•˜๊ฒŒ ํ•ด๊ฒฐ๋ฉ๋‹ˆ๋‹ค. +- **FFmpeg**: ์˜์ƒ์„ ๋””์ฝ”๋”ฉํ•ด์„œ **ํ‘œ์ค€ ์ถœ๋ ฅ(stdout)**์œผ๋กœ ๋‚ด๋ณด๋ƒ…๋‹ˆ๋‹ค. +- **C ํ”„๋กœ๊ทธ๋žจ**: **ํ‘œ์ค€ ์ž…๋ ฅ(stdin)**์œผ๋กœ ๋ฐ›์•„์„œ ๋ฉ”๋ชจ๋ฆฌ์— ์”๋‹ˆ๋‹ค. + +**ํ„ฐ๋ฏธ๋„ ๋ช…๋ น์–ด:** +```bash +# ffmpeg๊ฐ€ mp4๋ฅผ ์ฝ์Œ -> raw RGBA๋กœ ๋ณ€ํ™˜ -> ํŒŒ์ดํ”„๋กœ ์ „์†ก -> player๊ฐ€ ๋ฐ›์•„์„œ ๋ฉ”๋ชจ๋ฆฌ์— ๊ธฐ๋ก +./ffmpeg -i input.mp4 -f rawvideo -pix_fmt rgba - | ./player +``` + +**C ์ฝ”๋“œ ์ˆ˜์ • (stdin ์ฝ๊ธฐ):** +`fopen` ๋Œ€์‹  ํ‘œ์ค€ ์ž…๋ ฅ(ํŒŒ์ผ ๋””์Šคํฌ๋ฆฝํ„ฐ `0` ๋˜๋Š” `stdin`)์„ ์‚ฌ์šฉํ•˜๋ฉด ๋ฉ๋‹ˆ๋‹ค. + +```c +// player.c ํ•ต์‹ฌ ๋ถ€๋ถ„ +unsigned char buffer[960 * 540 * 4]; // ํ•œ ํ”„๋ ˆ์ž„ ๋ฒ„ํผ (qHD ๊ธฐ์ค€) + +while(1) { + // 1. ํ‘œ์ค€ ์ž…๋ ฅ(stdin)์—์„œ ํ•œ ํ”„๋ ˆ์ž„ ์ฝ๊ธฐ + // fread๋Š” ๋ฐ์ดํ„ฐ๊ฐ€ ์˜ฌ ๋•Œ๊นŒ์ง€ ์ž๋™์œผ๋กœ ๋Œ€๊ธฐ(Blocking)ํ•ฉ๋‹ˆ๋‹ค. + int bytes_read = fread(buffer, 1, sizeof(buffer), stdin); + + if (bytes_read < sizeof(buffer)) break; // ๋ฐ์ดํ„ฐ ์ŠคํŠธ๋ฆผ ์ข…๋ฃŒ + + // 2. ์ฝ์€ ๋ฐ์ดํ„ฐ๋ฅผ FPGA ๋ฉ”๋ชจ๋ฆฌ(mmap)๋กœ ๋ณต์‚ฌ (๋”๋ธ” ๋ฒ„ํผ๋ง ๋กœ์ง ์ ์šฉ ํ•„์š”) + memcpy(fb_ptr, buffer, sizeof(buffer)); +} +``` + +### ๊ธฐ์กด CPU ํ•œ๊ณ„ (์ฐธ๊ณ ) +- **์†Œํ”„ํŠธ์›จ์–ด ๋””์ฝ”๋”ฉ**: FFmpeg ๊ฐ™์€ ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๋ฅผ ์‚ฌ์šฉํ•˜๋ฉด ๋“€์–ผ ์ฝ”์–ด 800MHz A9์€ 480p ๋˜๋Š” ๊ธฐ๋ณธ 720p๋ฅผ 24/30fps๋กœ ์ฒ˜๋ฆฌํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ํ•˜์ง€๋งŒ ์ˆœ์ˆ˜ ์†Œํ”„ํŠธ์›จ์–ด๋กœ 720p/1080p 60fps์— ๋„๋‹ฌํ•˜๊ธฐ๋Š” ๋งค์šฐ ์–ด๋ ต์Šต๋‹ˆ๋‹ค. +- **NEON ๊ฐ€์†**: ์ด๋ฅผ ๊ฐ€๋Šฅํ•˜๊ฒŒ ํ•˜๋ ค๋ฉด Cortex-A9 ๋‚ด๋ถ€์˜ **NEON SIMD ์—”์ง„**์„ ์‚ฌ์šฉํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +- **๋ณ‘๋ชฉ ํ˜„์ƒ**: Cyclone V์˜ HPS์—๋Š” ์ „์šฉ H.264 ํ•˜๋“œ์›จ์–ด ๋””์ฝ”๋”(VPU)๊ฐ€ ์—†์Šต๋‹ˆ๋‹ค. ๋”ฐ๋ผ์„œ CPU๊ฐ€ ๋ชจ๋“  ๋ฌด๊ฑฐ์šด ๊ณ„์‚ฐ(DCT, ์—”ํŠธ๋กœํ”ผ ์ฝ”๋”ฉ ๋“ฑ)์„ ์ˆ˜ํ–‰ํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. + +## 17. ๋””์••์ถ• ํ›„์˜ ํฌ๋งท: Raw ๋น„๋””์˜ค +MP4 ํŒŒ์ผ์˜ "์••์ถ•์„ ํ’€๋ฉด" **Raw ๋น„๋””์˜ค**๋ฅผ ์–ป๊ฒŒ ๋ฉ๋‹ˆ๋‹ค. ์ด๋Š” ์••์ถ• ์—†์ด ๋ชจ๋“  ํ”ฝ์…€์ด ๋ฉ”๋ชจ๋ฆฌ์— ํ‰๋ฉด์ ์œผ๋กœ ๋ฐฐ์น˜๋œ ์ƒํƒœ๋ฅผ ์˜๋ฏธํ•ฉ๋‹ˆ๋‹ค. + +### ๋Œ€ํ‘œ์ ์ธ Raw ํฌ๋งท +1. **RGB888 (24๋น„ํŠธ)**: + - ๊ฐ ํ”ฝ์…€ = 1๋ฐ”์ดํŠธ Red + 1๋ฐ”์ดํŠธ Green + 1๋ฐ”์ดํŠธ Blue. + - FPGA์˜ 24๋น„ํŠธ RGB ๋ฒ„์Šค์™€ ์ง์ ‘ ์ผ์น˜ํ•˜์—ฌ ์ถ”๊ฐ€ ๋ณ€ํ™˜์ด ํ•„์š” ์—†์Šต๋‹ˆ๋‹ค. +2. **YUV422 / YUV420**: + - ์ธ๊ฐ„์˜ ์‹œ๊ฐ ์ธ์ง€ ๋ฐฉ์‹์„ ํ™œ์šฉํ•ด ๋ฐ๊ธฐ ๋Œ€๋น„ ์ƒ‰์ƒ ์ •๋ณด๋ฅผ ์ค„์—ฌ ์šฉ๋Ÿ‰์„ ํ™•๋ณดํ•ฉ๋‹ˆ๋‹ค. + - **์žฅ์ **: ์›๋ณธ RGB๋ณด๋‹ค ์šฉ๋Ÿ‰์ด ์ž‘์Šต๋‹ˆ๋‹ค. + - **๋‹จ์ **: HDMI ์นฉ์„ ์œ„ํ•ด ๋‹ค์‹œ RGB888๋กœ ๋ฐ”๊พธ๊ธฐ ์œ„ํ•œ "์ปฌ๋Ÿฌ ๊ณต๊ฐ„ ๋ณ€ํ™˜๊ธฐ (CSC)"๊ฐ€ FPGA์— ํ•„์š”ํ•ฉ๋‹ˆ๋‹ค. + +## 18. ํ•˜๋“œ์›จ์–ด ์ตœ์ ํ™”: YUV422 to RGB888 CSC +ํŒŒ์ดํ”„๋ผ์ธ์— **์ปฌ๋Ÿฌ ๊ณต๊ฐ„ ๋ณ€ํ™˜๊ธฐ (CSC)**๋ฅผ ํ†ตํ•ฉํ•˜๋ฉด ๋น„๋””์˜ค๋ฅผ RGB888(ํ”ฝ์…€๋‹น 24๋น„ํŠธ) ๋Œ€์‹  YUV422(16๋น„ํŠธ)๋กœ ์ €์žฅํ•  ์ˆ˜ ์žˆ์–ด **DDR3 ๋Œ€์—ญํญ์„ 33% ์ ˆ์•ฝ**ํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ์ด ๋ชจ๋“ˆ์„ ์ถ”๊ฐ€ํ•จ์œผ๋กœ์จ ๋” ๋†’์€ ํ•ด์ƒ๋„๋ฅผ ์ฒ˜๋ฆฌํ•˜๊ฑฐ๋‚˜ ๋‹ค๋ฅธ HPS ์ž‘์—…์„ ์œ„ํ•œ ๋Œ€์—ญํญ ์—ฌ์œ ๋ฅผ ํ™•๋ณดํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค! + +## 19. ์‹œ๊ฐ์  ํ’ˆ์งˆ: ๊ฐ๋งˆ ๋ณด์ • ($\gamma$) +**๊ฐ๋งˆ ๋ณด์ •**์€ ํ”ฝ์…€ ๊ฐ’๊ณผ ์ธ๊ฐ„์˜ ๋ˆˆ์ด ๋Š๋ผ๋Š” ์‹ค์ œ ๋ฐ๊ธฐ ์‚ฌ์ด์˜ ๋น„์„ ํ˜• ๊ด€๊ณ„๋ฅผ ๋ณด์ƒํ•˜๋Š” ๊ณผ์ •์ž…๋‹ˆ๋‹ค. + +### ์™œ ํ•„์š”ํ•œ๊ฐ€? +- **์ธ๊ฐ„์˜ ์ธ์ง€**: ์šฐ๋ฆฌ ๋ˆˆ์€ ๋ฐ์€ ํ†ค๋ณด๋‹ค ์–ด๋‘์šด ํ†ค์˜ ๋ณ€ํ™”์— ๋” ๋ฏผ๊ฐํ•ฉ๋‹ˆ๋‹ค. +- **๋””์Šคํ”Œ๋ ˆ์ด ์‘๋‹ต**: ๋ชจ๋‹ˆํ„ฐ๋Š” ๋น„์„ ํ˜•์  ์‘๋‹ต($Intensity \propto Voltage^\gamma$)์„ ๊ฐ€์ง‘๋‹ˆ๋‹ค. +- ๊ฐ๋งˆ ๋ณด์ •($\gamma=2.2$)์ด ์—†์œผ๋ฉด ์ด๋ฏธ์ง€๊ฐ€ ๋„ˆ๋ฌด ๋ฐ๊ฒŒ ๋ณด์ด๊ฑฐ๋‚˜ ์ค‘๊ฐ„ ํ†ค์˜ ๋Œ€๋น„๊ฐ€ ์ž˜๋ชป ๋‚˜ํƒ€๋‚  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. + +### FPGA ๊ตฌํ˜„: ๋ฃฉ์—… ํ…Œ์ด๋ธ” (LUT) +์‹ค์‹œ๊ฐ„์œผ๋กœ ๋ณต์žกํ•œ ์ˆ˜ํ•™ ๊ณต์‹์„ ๊ณ„์‚ฐํ•˜๋Š” ๋Œ€์‹  **LUT**๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. +1. **์‚ฌ์ „ ๊ณ„์‚ฐ**: PC์—์„œ ๋ชจ๋“  ์ž…๋ ฅ์— ๋Œ€ํ•œ ๋ณด์ •๋œ ์ถœ๋ ฅ๊ฐ’์„ ๋ฏธ๋ฆฌ ๊ณ„์‚ฐํ•ฉ๋‹ˆ๋‹ค. +2. **๋ฉ”๋ชจ๋ฆฌ ๋งต**: ์ด 256๊ฐœ ๊ฐ’์„ FPGA ๋‚ด๋ถ€์˜ ์ž‘์€ Dual-Port RAM์— ์ €์žฅํ•ฉ๋‹ˆ๋‹ค. +3. **ํ†ตํ•ฉ**: HDMI ํŠธ๋žœ์Šค๋ฏธํ„ฐ ์ง์ „์— ๋ฐฐ์น˜ํ•˜์—ฌ ์ตœ์ข… ์ถœ๋ ฅ ํ™”์งˆ์„ ๋ฏธ์„ธ ์กฐ์ •ํ•ฉ๋‹ˆ๋‹ค. + +### ๊ณก์„ ์˜ ๋ชจ์–‘: ์œ„๋กœ ๋ณผ๋ก ($\cap$) +๋ชจ๋‹ˆํ„ฐ์˜ ๋น„์„ ํ˜• ์‘๋‹ต์„ ๋งž์ถ”๊ธฐ ์œ„ํ•ด, ์ธ์ฝ”๋”ฉ ๊ณก์„ ์€ **์œ„๋กœ ๋ณผ๋ก($\cap$)**ํ•œ ๋ชจ์–‘์ด์–ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +- **๋ชจ๋‹ˆํ„ฐ ์‘๋‹ต (๋ฌผ๋ฆฌ)**: $I = V^{2.2}$. **์•„๋ž˜๋กœ ๋ณผ๋ก($\cup$)**ํ•˜๋ฉฐ, ์–ด๋‘์šด ์ƒํƒœ๋ฅผ ์˜ค๋ž˜ ์œ ์ง€ํ•˜๋‹ค ๊ธ‰๊ฒฉํžˆ ๋ฐ์•„์ง‘๋‹ˆ๋‹ค. +- **FPGA ์ธ์ฝ”๋”ฉ (์ˆ˜ํ•™)**: $V = I^{1/2.2} \approx I^{0.45}$. **์œ„๋กœ ๋ณผ๋ก($\cap$)**ํ•˜๋ฉฐ, ์–ด๋‘์šด ์˜์—ญ์—์„œ ๋น ๋ฅด๊ฒŒ ๋ฐ์•„์ง€๋‹ค ์™„๋งŒํ•ด์ง‘๋‹ˆ๋‹ค. + +์–ด๋‘์šด ์˜์—ญ์„ ๋ฏธ๋ฆฌ ๋ฐํ˜€์ฃผ๋Š” ์ด "๋ณผ๋กํ•œ" ๋ชจ์–‘์„ LUT์— ์ ์šฉํ•จ์œผ๋กœ์จ, ๋ชจ๋‹ˆํ„ฐ์˜ "์˜ค๋ชฉํ•œ" ์‘๋‹ต์ด ์ด๋ฅผ ๋‹ค์‹œ ๋Œ์–ด๋‚ด๋ ธ์„ ๋•Œ ์šฐ๋ฆฌ ๋ˆˆ์— ์ •ํ™•ํ•˜๊ฒŒ ๋ณด์ด๊ฒŒ ๋ฉ๋‹ˆ๋‹ค. โœจ + +## 20. ์‚ฌ๋ก€ ์—ฐ๊ตฌ: GHRD ๋ฆฌ๋ˆ…์Šค UI๋Š” ์–ด๋–ป๊ฒŒ ์ž‘๋™ํ•˜๋Š”๊ฐ€? +GHRD์—์„œ ๋ณด๋Š” ๋ฆฌ๋ˆ…์Šค ๋ฐ์Šคํฌํ†ฑ ํ™”๋ฉด์€ ์šฐ๋ฆฌ๊ฐ€ ๋ฐฐ์šด ๋‚ด์šฉ์˜ ์™„๋ฒฝํ•œ ์˜ˆ์‹œ์ž…๋‹ˆ๋‹ค. + +### ๋ฉ”์ปค๋‹ˆ์ฆ˜: ๋ฆฌ๋ˆ…์Šค ํ”„๋ ˆ์ž„๋ฒ„ํผ (Framebuffer) +1. **๋ฉ”๋ชจ๋ฆฌ ํ• ๋‹น**: ๋ถ€ํŒ… ์‹œ ์ปค๋„์ด DDR3์˜ ํŠน์ • ์˜์—ญ(์˜ˆ: 32MB)์„ `fb0` ์šฉ๋„๋กœ ์˜ˆ์•ฝํ•ฉ๋‹ˆ๋‹ค. +2. **Qsys IP**: FPGA ํŒจ๋ธŒ๋ฆญ ๋‚ด์˜ **Intel VIP Frame Reader** IP๊ฐ€ ์ด DDR3 ์˜์—ญ์—์„œ ํ”ฝ์…€์„ ๊ฐ€์ ธ์™€ **Avalon-ST ๋น„๋””์˜ค ์ŠคํŠธ๋ฆผ**์œผ๋กœ ๋ณ€ํ™˜ํ•ฉ๋‹ˆ๋‹ค. +3. **์ถœ๋ ฅ**: ์ด ์ŠคํŠธ๋ฆผ์€ CVO IP๋ฅผ ํ†ตํ•ด ๋™๊ธฐ ์‹ ํ˜ธ๋ฅผ ์ƒ์„ฑํ•˜๊ณ  ADV7513์œผ๋กœ ์ „๋‹ฌ๋ฉ๋‹ˆ๋‹ค. + +### ๋™๊ธฐํ™”: ์Šค์™€ํ•‘ ์ฒ˜๋ฆฌ +๋ฆฌ๋ˆ…์Šค ๋“œ๋ผ์ด๋ฒ„๋Š” ํ”„๋ ˆ์ž„ ๋ฆฌ๋”๊ฐ€ ๊ทธ๋ ค์ง€๋Š” ๋„์ค‘์˜ ํ”„๋ ˆ์ž„์„ ์ฝ์ง€ ์•Š๋„๋ก **V-Sync ์ธํ„ฐ๋ŸฝํŠธ**๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ๊ด€๋ฆฌํ•ฉ๋‹ˆ๋‹ค. ํ”„๋ ˆ์ž„ ๋ฆฌ๋”๊ฐ€ ํ•œ ํ”„๋ ˆ์ž„์„ ๋‹ค ์ฝ์œผ๋ฉด ARM CPU์— ์ธํ„ฐ๋ŸฝํŠธ๋ฅผ ๋ณด๋‚ด๊ณ , ์ด๋ฅผ ๋ฐ›์€ ๋“œ๋ผ์ด๋ฒ„๋Š” "์ด์ œ ์ƒˆ ํ”„๋ ˆ์ž„์œผ๋กœ ์ „ํ™˜ํ•ด๋„ ์•ˆ์ „ํ•˜๋‹ค"๋Š” ๊ฒƒ์„ ์ธ์ง€ํ•˜๊ณ  ์ฃผ์†Œ๋ฅผ ์—…๋ฐ์ดํŠธํ•ฉ๋‹ˆ๋‹ค. + +์šฐ๋ฆฌ๋Š” ์ง€๊ธˆ ์ด ๋ชจ๋“  ๋ณต์žกํ•œ ๋“œ๋ผ์ด๋ฒ„ ๊ณผ์ •์„ **Nios II์™€ ์ปค์Šคํ…€ ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ**๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ์ˆ˜๋™์œผ๋กœ ์ œ์–ดํ•˜๋ฉฐ ๋ฐฐ์šฐ๊ณ  ์žˆ๋Š” ๊ฒƒ์ž…๋‹ˆ๋‹ค! + +## 21. ์—ญ์‚ฌ์  ๋งฅ๋ฝ: 8086 ํ…์ŠคํŠธ ๋ชจ๋“œ +8086/DOS ์‹œ๋Œ€์— ํ…์ŠคํŠธ๋ฅผ ํ‘œ์‹œํ•˜๋Š” ๊ฒƒ์€ ํ•˜๋“œ์›จ์–ด์— ์ „์šฉ **ํ…์ŠคํŠธ ๋ชจ๋“œ**๊ฐ€ ์žˆ์—ˆ๊ธฐ ๋•Œ๋ฌธ์— CPU ์ž…์žฅ์—์„œ ํ›จ์”ฌ ๊ฐ„๋‹จํ–ˆ์Šต๋‹ˆ๋‹ค. + +### ์บ๋ฆญํ„ฐ ๋ฉ”๋ชจ๋ฆฌ (0xB8000) +์ˆ˜๋ฐฑ๋งŒ ๊ฐœ์˜ ํ”ฝ์…€์„ ๊ด€๋ฆฌํ•˜๋Š” ๋Œ€์‹ , CPU๋Š” `80x25` ์บ๋ฆญํ„ฐ ๊ฒฉ์ž๋งŒ ๊ด€๋ฆฌํ•˜๋ฉด ๋˜์—ˆ์Šต๋‹ˆ๋‹ค. ๋ฌผ๋ฆฌ ์ฃผ์†Œ **`0xB8000`**๋ถ€ํ„ฐ ์‹œ์ž‘ํ•˜๋Š” ๋ฉ”๋ชจ๋ฆฌ์— ๊ฐ ๋ฌธ์ž๋‹น 2๋ฐ”์ดํŠธ(ASCII ์ฝ”๋“œ + ์†์„ฑ)๋ฅผ ์“ฐ๋ฉด ํ•˜๋“œ์›จ์–ด๊ฐ€ ์ด๋ฅผ ์‹ค์‹œ๊ฐ„์œผ๋กœ ํ”ฝ์…€ ํŒจํ„ด์œผ๋กœ ๋ณ€ํ™˜ํ•ด ์ถœ๋ ฅํ–ˆ์Šต๋‹ˆ๋‹ค. + +ํ˜„๋Œ€ ์‹œ์Šคํ…œ์—์„œ๋Š” ์ด๋Ÿฌํ•œ ํ•˜๋“œ์›จ์–ด "ํ…์ŠคํŠธ ๋ชจ๋“œ"๊ฐ€ ๋” ์ด์ƒ ์กด์žฌํ•˜์ง€ ์•Š์Šต๋‹ˆ๋‹ค. ๋ฆฌ๋ˆ…์Šค ํ„ฐ๋ฏธ๋„์—์„œ ๋ณด๋Š” ํ…์ŠคํŠธ๋„ ๊ฒฐ๊ตญ ARM์ด๋‚˜ Nios II๊ฐ€ ํฐํŠธ ๋น„ํŠธ๋งต์„ ์‚ฌ์šฉํ•˜์—ฌ **ํ”ฝ์…€ ๋‹จ์œ„๋กœ ์ผ์ผ์ด ๊ทธ๋ฆฐ ๊ฒฐ๊ณผ**์ž…๋‹ˆ๋‹ค! diff --git a/doc/TODO.md b/doc/TODO.md index 3f19f84..796f47d 100644 --- a/doc/TODO.md +++ b/doc/TODO.md @@ -1,4 +1,5 @@ # TODO: Advanced Video Processing Roadmap +[**English**] | [**ํ•œ๊ตญ์–ด**](./TODO_kor.md) [Back to README](../README.md) This roadmap outlines the steps to build a high-performance video pipeline, from basic color bars to advanced real-time image processing. diff --git a/doc/TODO_kor.md b/doc/TODO_kor.md new file mode 100644 index 0000000..64da2cf --- /dev/null +++ b/doc/TODO_kor.md @@ -0,0 +1,70 @@ +# TODO: ๊ณ ๊ธ‰ ๋น„๋””์˜ค ํ”„๋กœ์„ธ์‹ฑ ๋กœ๋“œ๋งต +[**English**](./TODO.md) | [**ํ•œ๊ตญ์–ด**] +[README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md) + +์ด ๋กœ๋“œ๋งต์€ ๊ธฐ์ดˆ์ ์ธ ์ปฌ๋Ÿฌ ๋ฐ” ์ถœ๋ ฅ๋ถ€ํ„ฐ ๊ณ ๊ธ‰ ์‹ค์‹œ๊ฐ„ ์ด๋ฏธ์ง€ ํ”„๋กœ์„ธ์‹ฑ์— ์ด๋ฅด๊ธฐ๊นŒ์ง€ ๊ณ ์„ฑ๋Šฅ ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ์„ ๊ตฌ์ถ•ํ•˜๊ธฐ ์œ„ํ•œ ๋‹จ๊ณ„๋ฅผ ๊ฐœ๋žต์ ์œผ๋กœ ์„ค๋ช…ํ•ฉ๋‹ˆ๋‹ค. + +## 1๋‹จ๊ณ„: ๊ธฐ๋ฐ˜ ๊ตฌ์ถ• (Nios II ํŒจํ„ด ๋ฐ DMA) โœ… +- [x] **DDR3 ํŒจํ„ด ์ƒ์„ฑ**: DDR3(0x2000_0000)๋ฅผ 720p ์ปฌ๋Ÿฌ๋ฐ”๋กœ ์ฑ„์šฐ๋Š” Nios II ์ฝ”๋“œ๋ฅผ ์ž‘์„ฑํ•ฉ๋‹ˆ๋‹ค. +- [x] **ํ•˜๋“œ์›จ์–ด DMA ๋งˆ์Šคํ„ฐ**: ๊ณ ์† DDR3 ์•ก์„ธ์Šค๋ฅผ ์œ„ํ•œ `burst_master`๋ฅผ ๊ตฌํ˜„ํ•˜๊ณ  ๊ฒ€์ฆํ•ฉ๋‹ˆ๋‹ค. +- [x] **์„ฑ๋Šฅ ๋ฒค์น˜๋งˆํฌ**: ์†Œํ”„ํŠธ์›จ์–ด ๋ณต์‚ฌ ๋Œ€๋น„ 500๋ฐฐ ์ด์ƒ์˜ ์„ฑ๋Šฅ ํ–ฅ์ƒ์„ ํ™•์ธํ•ฉ๋‹ˆ๋‹ค. + +## 2๋‹จ๊ณ„: ํ•˜๋“œ์›จ์–ด ํ™•์žฅ (RTL ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ ๋ฐ ๊ณ ๊ธ‰ ์ œ์–ด) โœ… +- [x] **์ปค์Šคํ…€ ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ**: H/V ๋™๊ธฐํ™” ๋ฐ DE๋ฅผ ์ง€์›ํ•˜๋Š” `hdmi_sync_gen.v`๋ฅผ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. +- [x] **RTL ํŒจํ„ด**: ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ์— ๋‚ด์žฅ ํŒจํ„ด(Greyscale, Grid, Character Tile)์„ ์ถ”๊ฐ€ํ•ฉ๋‹ˆ๋‹ค. +- [x] **๊ณ ๊ธ‰ ๊ฐ๋งˆ ๋ณด์ •**: sRGB ๋ฐ Inverse Gamma 2.2 LUT๋ฅผ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. +- [x] **Nios II ํ•˜์œ„ ๋ฉ”๋‰ด**: ์‹ค์‹œ๊ฐ„ ๊ฐ๋งˆ ๋ฐ ํŒจํ„ด ์ œ์–ด๋ฅผ ์œ„ํ•œ ์ค‘์ฒฉ ๋ฉ”๋‰ด๋ฅผ ์ƒ์„ฑํ•ฉ๋‹ˆ๋‹ค. +- [x] **ํƒ€์ด๋ฐ ๋ฐ ์ฃผ์†Œ ์ง€์ • ์ˆ˜์ •**: SDC ํƒ€์ด๋ฐ ์œ„๋ฐ˜ ๋ฐ Avalon-MM ์ฃผ์†Œ ๋งคํ•‘ ๋ฒ„๊ทธ๋ฅผ ํ•ด๊ฒฐํ•ฉ๋‹ˆ๋‹ค. +- [x] **๋™์  ์ปฌ๋Ÿฌ๋ง**: ์บ๋ฆญํ„ฐ ๋ Œ๋”๋ง์— ์ขŒํ‘œ ๊ธฐ๋ฐ˜ ๋ฌด์ง€๊ฐœ ํšจ๊ณผ๋ฅผ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. + +## 3๋‹จ๊ณ„: qHD ๋น„๋””์˜ค ์ถœ๋ ฅ โœ… +- [x] **ํ•ด์ƒ๋„ ์ตœ์ ํ™”**: ๋Œ€์—ญํญ ์ค€์ˆ˜๋ฅผ ์œ„ํ•ด 720p์—์„œ qHD(960ร—540@60Hz)๋กœ ๋ณ€๊ฒฝํ•ฉ๋‹ˆ๋‹ค. +- [x] **๋“€์–ผ ํด๋ก ์•„ํ‚คํ…์ฒ˜**: CSR(50MHz)๊ณผ Pixel(37.8MHz) ํด๋ก ๋„๋ฉ”์ธ์„ ๋ถ„๋ฆฌํ•˜๊ณ  CDC๋ฅผ ์ ์šฉํ•ฉ๋‹ˆ๋‹ค. +- [x] **์ •์  ์ด๋ฏธ์ง€ ๋””์Šคํ”Œ๋ ˆ์ด**: Nios II๊ฐ€ DMA๋ฅผ ํ†ตํ•ด DDR3์—์„œ ์ด๋ฏธ์ง€๋ฅผ ๋กœ๋“œํ•˜๊ณ  ํ‘œ์‹œํ•ฉ๋‹ˆ๋‹ค. +- [x] **๋ฆฌ๋ˆ…์Šค ๋น„๋””์˜ค ํ”Œ๋ ˆ์ด์–ด**: HPS๊ฐ€ `/dev/mem` ๋”๋ธ” ๋ฒ„ํผ๋ง์„ ์‚ฌ์šฉํ•˜์—ฌ ๋น„๋””์˜ค๋ฅผ ์ŠคํŠธ๋ฆฌ๋ฐํ•ฉ๋‹ˆ๋‹ค. +- [x] **V-Sync ๋™๊ธฐํ™”**: ํ‹ฐ์–ด๋ง ์—†๋Š” ์—…๋ฐ์ดํŠธ๋ฅผ ์œ„ํ•œ ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ ๋ž˜์นญ์„ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. +- [x] **Qsys HPS ๋ธŒ๋ฆฟ์ง€**: ๋ฆฌ๋ˆ…์Šค ์ œ์–ด๋ฅผ ์œ„ํ•ด `h2f_lw_axi_master`๋ฅผ HDMI CSR์— ์—ฐ๊ฒฐํ•ฉ๋‹ˆ๋‹ค. + +## 4๋‹จ๊ณ„: ๋น„๋””์˜ค ์žฌ์ƒ ์ตœ์ ํ™” ๋ฐ ๋Œ€์—ญํญ ํ™•์žฅ โณ +- [ ] **๋ฒ„์Šค ํญ ํ™•์žฅ**: ๋ฒ„์Šค ํญ์„ 4๋ฐ”์ดํŠธ์—์„œ 8/16๋ฐ”์ดํŠธ๋กœ ํ™•์žฅํ•ฉ๋‹ˆ๋‹ค. (๋ชฉํ‘œ: 50MHz์—์„œ 400 MB/s) + - ๋ชฉํ‘œ: ์—ฌ์œ  ๋Œ€์—ญํญ์„ ํ™•๋ณดํ•œ ์ƒํƒœ์—์„œ 720p@60Hz (222 MB/s) ์ง€์› + - ํด๋ก ์ฃผํŒŒ์ˆ˜๋Š” 50MHz ์œ ์ง€ + - burst_master์˜ Avalon-MM ์ธํ„ฐํŽ˜์ด์Šค ๋„ˆ๋น„ ์ˆ˜์ • +- [ ] **RAM ์‚ฌ์ „ ๋กœ๋“œ ๋ชจ๋“œ**: ์งง์€ ๋น„๋””์˜ค(4-5์ดˆ)์— ๋Œ€ํ•ด 60fps๋ฅผ ๋ณด์žฅํ•˜๋Š” ์‚ฌ์ „ ๋กœ๋“œ ์ „๋žต์„ ๋ณต๊ตฌํ•ฉ๋‹ˆ๋‹ค. +- [ ] **ํ•ด์ƒ๋„ ์Šค์ผ€์ผ๋ง**: ์ง€์†์ ์ธ SD ์นด๋“œ ์ŠคํŠธ๋ฆฌ๋ฐ์„ ์œ„ํ•œ 480p/360p ๋ชจ๋“œ๋ฅผ ์ถ”๊ฐ€ํ•ฉ๋‹ˆ๋‹ค. +- [ ] **๋น„๋””์˜ค ์••์ถ• ์ง€์›**: H.264/MJPEG ํ•˜๋“œ์›จ์–ด ๋””์ฝ”๋” ํ†ตํ•ฉ์„ ๊ฒ€ํ† ํ•ฉ๋‹ˆ๋‹ค. +- [ ] **์˜ค๋””์˜ค ํ†ตํ•ฉ**: ๋น„๋””์˜ค์™€ ๋™๊ธฐํ™”๋œ I2S ์˜ค๋””์˜ค ์žฌ์ƒ ๊ธฐ๋Šฅ์„ ์ถ”๊ฐ€ํ•ฉ๋‹ˆ๋‹ค. +- [ ] **์„ฑ๋Šฅ ํ”„๋กœํŒŒ์ผ๋ง**: `ftrace`๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ์ฝ๊ธฐ ์ง€์—ฐ ์‹œ๊ฐ„์„ ์ธก์ •ํ•˜๊ณ  ์ตœ์ ํ™”ํ•ฉ๋‹ˆ๋‹ค. + +## 5๋‹จ๊ณ„: ์‹ค์‹œ๊ฐ„ ํ”„๋กœ์„ธ์‹ฑ (๋ผ์ธ ๋ฒ„ํผ ๋ฐ ํ•„ํ„ฐ) +- [ ] **๋ผ์ธ ๋ฒ„ํผ ์„ค๊ณ„**: 3x3 ์œˆ๋„์šฐ ์ฒ˜๋ฆฌ๋ฅผ ์œ„ํ•œ ๋“€์–ผ ํฌํŠธ RAM ๊ธฐ๋ฐ˜ ๋ผ์ธ ๋ฒ„ํผ๋ฅผ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. +- [ ] **ํ”„๋กœ์„ธ์‹ฑ ์ฝ”์–ด**: `video_processing_core.v` ๊ตฌํ˜„ + - [ ] **๊ทธ๋ ˆ์ด์Šค์ผ€์ผ/์ด์ง„ํ™”**: ๊ธฐ๋ณธ์ ์ธ ํ”ฝ์…€ ๋‹จ์œ„ ์ฒ˜๋ฆฌ + - [ ] **Sobel ์—ฃ์ง€ ๊ฒ€์ถœ**: ๋ผ์ธ ๋ฒ„ํผ๋ฅผ ํ™œ์šฉํ•œ ๊ณ ์† ๊ณต๊ฐ„ ํ•„ํ„ฐ๋ง + - [ ] **๊ฐ€์šฐ์‹œ์•ˆ ๋ธ”๋Ÿฌ**: ๋…ธ์ด์ฆˆ ์ œ๊ฑฐ๋ฅผ ์œ„ํ•œ ์Šค๋ฌด๋”ฉ ํ•„ํ„ฐ +- [ ] **์‹ค์‹œ๊ฐ„ ์ „ํ™œ**: ์ œ์–ด ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ํ†ตํ•ด ์ฒ˜๋ฆฌ๋œ ์˜์ƒ๊ณผ ์›๋ณธ ์˜์ƒ ์‚ฌ์ด๋ฅผ ์ „ํ™˜ํ•ฉ๋‹ˆ๋‹ค. + +## 6๋‹จ๊ณ„: ๊ณ ๊ธ‰ ๊ธฐ๋Šฅ +- [ ] **๊ณต๊ฐ„ ๋””๋”๋ง (Spatial Dithering)**: ๋ฐด๋”ฉ ํ˜„์ƒ์„ ์ค„์ด๊ธฐ ์œ„ํ•œ Bayer Matrix ๊ธฐ๋ฐ˜ ๋””๋”๋ง์„ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค. +- [ ] **๋ฆฌ๋ˆ…์Šค DRM/KMS ํ†ตํ•ฉ**: ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ์„ ํ‘œ์ค€ ๋ฆฌ๋ˆ…์Šค ๋””์Šคํ”Œ๋ ˆ์ด ์žฅ์น˜๋กœ ๋งคํ•‘ํ•ฉ๋‹ˆ๋‹ค. +- [ ] **์นด๋ฉ”๋ผ ์ž…๋ ฅ**: ์‹ค์‹œ๊ฐ„ ์ฒ˜๋ฆฌ๋ฅผ ์œ„ํ•œ MIPI CSI-2 ์นด๋ฉ”๋ผ ์ธํ„ฐํŽ˜์ด์Šค ์ถ”๊ฐ€๋ฅผ ๊ฒ€ํ† ํ•ฉ๋‹ˆ๋‹ค. +- [ ] **AI ๊ฐ€์†**: ํ•˜๋“œ์›จ์–ด ๊ธฐ๋ฐ˜ AI ์ธ์‹ ์ฝ”์–ด(YOLO ๋“ฑ) ํ†ตํ•ฉ์„ ๊ฒ€ํ† ํ•ฉ๋‹ˆ๋‹ค. + +## ํ•˜๋“œ์›จ์–ด/Qsys ์š”๊ตฌ ์‚ฌํ•ญ (๊ณตํ†ต) โœ… +- [x] **ํด๋กํ‚น**: 37.83 MHz ํ”ฝ์…€ ํด๋ก PLL + SDC ์ œ์•ฝ ์กฐ๊ฑด +- [x] **I2C ์ œ์–ด**: Nios II๋ฅผ ํ†ตํ•œ ADV7513 ์ดˆ๊ธฐํ™” +- [x] **์ตœ์ƒ์œ„ ๋ฐฐ์„ **: `DE10_NANO_SoC_GHRD.v`์—์„œ HDMI_TX ํ•€ ํ• ๋‹น +- [x] **HPS ๋ธŒ๋ฆฟ์ง€**: ๋ฆฌ๋ˆ…์Šค CSR ์•ก์„ธ์Šค๋ฅผ ์œ„ํ•œ Lightweight AXI ๋ธŒ๋ฆฟ์ง€ + +## ์•Œ๋ ค์ง„ ๋ฌธ์ œ ๋ฐ ์ œํ•œ ์‚ฌํ•ญ +- **SD ์นด๋“œ ๋ณ‘๋ชฉ**: ์›๋ณธ ๋น„๋””์˜ค๋Š” 124 MB/s๋ฅผ ํ•„์š”๋กœ ํ•˜๋‚˜, SD ์นด๋“œ๋Š” ์•ฝ 20 MB/s๋งŒ ์ œ๊ณตํ•จ + - ์˜ํ–ฅ: ์ง€์† ์žฌ์ƒ ์‹œ ์•ฝ 10-15 fps๋กœ ์ œํ•œ๋จ + - ํ•ด๊ฒฐ์ฑ…: ์งง์€ ํด๋ฆฝ์€ RAM ์‚ฌ์ „ ๋กœ๋“œ๋ฅผ ์‚ฌ์šฉํ•˜๊ฑฐ๋‚˜ ํ•ด์ƒ๋„๋ฅผ ๋‚ฎ์ถค +- **๋ฉ”๋ชจ๋ฆฌ ์ œ์•ฝ**: ๋น„๋””์˜ค์šฉ์œผ๋กœ ์˜ˆ์•ฝ๋œ 512MB DDR3๋Š” ์‚ฌ์ „ ๋กœ๋“œ ์‹œ ์•ฝ 250 ํ”„๋ ˆ์ž„์œผ๋กœ ์ œํ•œ๋จ +- **์˜ค๋””์˜ค ๋ฏธ์ง€์›**: ํ˜„์žฌ ๋น„๋””์˜ค ์ „์šฉ์œผ๋กœ ๊ตฌํ˜„๋จ + +## ๋ฌธ์„œํ™” ํ˜„ํ™ฉ +- [x] ์ƒ์„ธ ๊ตฌํ˜„ ๋‚ด์šฉ์„ ๋‹ด์€ `VIDEO_PLAYBACK.md` ์ž‘์„ฑ ์™„๋ฃŒ +- [x] qHD ์„ฑ๊ณผ๋ฅผ ๋ฐ˜์˜ํ•˜์—ฌ `README.md` ์—…๋ฐ์ดํŠธ ์™„๋ฃŒ +- [ ] ์ƒ์„ธ ์ธก์ •๊ฐ’์„ ํฌํ•จํ•œ ์„ฑ๋Šฅ ๋ฒค์น˜๋งˆํฌ ๋ฌธ์„œ ์ž‘์„ฑ +- [ ] ์ผ๋ฐ˜์ ์ธ ๋ฌธ์ œ ํ•ด๊ฒฐ์„ ์œ„ํ•œ ํŠธ๋Ÿฌ๋ธ”์ŠˆํŒ… ๊ฐ€์ด๋“œ ์ถ”๊ฐ€ diff --git a/doc/VIDEO_PLAYBACK.md b/doc/VIDEO_PLAYBACK.md index be5b62b..f0f5844 100644 --- a/doc/VIDEO_PLAYBACK.md +++ b/doc/VIDEO_PLAYBACK.md @@ -1,4 +1,6 @@ # ๐ŸŽฌ Video Playback Implementation +[**English**] | [**ํ•œ๊ตญ์–ด**](./VIDEO_PLAYBACK_kor.md) +[โฌ…๏ธ Back to README](../README.md) ## Overview diff --git a/doc/VIDEO_PLAYBACK_kor.md b/doc/VIDEO_PLAYBACK_kor.md new file mode 100644 index 0000000..a1e7bac --- /dev/null +++ b/doc/VIDEO_PLAYBACK_kor.md @@ -0,0 +1,213 @@ +# ๐ŸŽฌ ๋น„๋””์˜ค ์žฌ์ƒ ๊ตฌํ˜„ +[**English**](./VIDEO_PLAYBACK.md) | [**ํ•œ๊ตญ์–ด**] +[โฌ…๏ธ README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md) + +## ๊ฐœ์š” +์ด ๋ฌธ์„œ๋Š” ์ •์  ์ด๋ฏธ์ง€ ๋””์Šคํ”Œ๋ ˆ์ด์™€ ๋ฆฌ๋ˆ…์Šค ์„œ๋ฒ„๋กœ๋ถ€ํ„ฐ์˜ ๋™์  ๋น„๋””์˜ค ์ŠคํŠธ๋ฆฌ๋ฐ์„ ํฌํ•จํ•˜์—ฌ, DE10-Nano FPGA ๋ณด๋“œ์—์„œ ๊ตฌํ˜„๋œ **qHD (960x540@60Hz) ๋น„๋””์˜ค ์žฌ์ƒ**์— ๋Œ€ํ•ด ์„ค๋ช…ํ•ฉ๋‹ˆ๋‹ค. + +## ๐Ÿ“ ํ•ด์ƒ๋„: qHD (960x540) + +### ์™œ qHD์ธ๊ฐ€? +์›๋ž˜ ๋ชฉํ‘œ๋Š” 720p (1280x720@60Hz)์˜€์œผ๋ฉฐ, ์ด๋Š” **222 MB/s**์˜ ๋Œ€์—ญํญ์„ ํ•„์š”๋กœ ํ•ฉ๋‹ˆ๋‹ค. +``` +1280 ร— 720 ร— 4 ๋ฐ”์ดํŠธ ร— 60 fps = 222 MB/s +``` + +๊ทธ๋Ÿฌ๋‚˜ 50MHz ์‹œ์Šคํ…œ ๋ฒ„์Šค๋Š” ์ตœ๋Œ€ **200 MB/s**๋งŒ ์ œ๊ณตํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. +``` +50 MHz ร— 4 ๋ฐ”์ดํŠธ = 200 MB/s +``` + +์—ฌ์œ  ์žˆ๋Š” ๋Œ€์—ญํญ๊ณผ ์•ˆ์ •์ ์ธ 60Hz ์ถœ๋ ฅ์„ ์œ ์ง€ํ•˜๊ธฐ ์œ„ํ•ด ํ•ด์ƒ๋„๋ฅผ **qHD (960ร—540)**๋กœ ๋‚ฎ์ถ”์—ˆ์Šต๋‹ˆ๋‹ค. +``` +960 ร— 540 ร— 4 ๋ฐ”์ดํŠธ ร— 60 fps = 124 MB/s โœ… (๊ฐ€์šฉ ๋Œ€์—ญํญ์˜ 62% ์‚ฌ์šฉ) +``` + +### ํƒ€์ด๋ฐ ํŒŒ๋ผ๋ฏธํ„ฐ + +| ํŒŒ๋ผ๋ฏธํ„ฐ | ๊ฐ’ | +|-----------|-------| +| **ํ”ฝ์…€ ํด๋ก** | 37.8336 MHz | +| **H_VISIBLE** | 960 | +| **H_FRONT** | 48 | +| **H_SYNC** | 32 | +| **H_BACK** | 80 | +| **H_TOTAL** | 1120 | +| **V_VISIBLE** | 540 | +| **V_FRONT** | 3 | +| **V_SYNC** | 5 | +| **V_BACK** | 15 | +| **V_TOTAL** | 563 | +| **ํ”„๋ ˆ์ž„ ๋ ˆ์ดํŠธ** | 60.00 Hz | + +## ๐Ÿ–ผ๏ธ ์ •์  ์ด๋ฏธ์ง€ ๋””์Šคํ”Œ๋ ˆ์ด + +### Nios II ์†Œํ”„ํŠธ์›จ์–ด +Nios II ํ”„๋กœ์„ธ์„œ๋Š” DDR3 ๋ฉ”๋ชจ๋ฆฌ์—์„œ ์ •์  ์ด๋ฏธ์ง€๋ฅผ ๋กœ๋“œํ•˜์—ฌ HDMI ์ถœ๋ ฅ์œผ๋กœ ํ‘œ์‹œํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. + +**๋ฉ”๋ชจ๋ฆฌ ๋งต:** +- ํ”„๋ ˆ์ž„ ๋ฒ„ํผ ์ฃผ์†Œ: `0x30000000` (๋ฆฌ๋ˆ…์Šค์—์„œ ์˜ˆ์•ฝ๋œ 512MB ์˜์—ญ) +- ํ”„๋ ˆ์ž„ ํฌ๊ธฐ: `960 ร— 540 ร— 4 = 2,073,600 ๋ฐ”์ดํŠธ` (์•ฝ 2MB) + +**์†Œํ”„ํŠธ์›จ์–ด ํ๋ฆ„:** +1. DMA(`burst_master`)๋ฅผ ํ†ตํ•ด ์ด๋ฏธ์ง€ ๋ฐ์ดํ„ฐ๋ฅผ DDR3๋กœ ๋กœ๋“œ +2. HDMI ์‹ฑํฌ ์ œ๋„ค๋ ˆ์ดํ„ฐ ๋ ˆ์ง€์Šคํ„ฐ ๊ตฌ์„ฑ +3. ๋ชจ๋“œ๋ฅผ DMA ์ŠคํŠธ๋ฆผ(Mode 8)์œผ๋กœ ์„ค์ • +4. ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ๋ฅผ `0x30000000`์œผ๋กœ ์„ค์ • +5. ์—ฐ์† DMA ๋ชจ๋“œ ํ™œ์„ฑํ™” + +## ๐ŸŽฅ ๋ฆฌ๋ˆ…์Šค ๋น„๋””์˜ค ์žฌ์ƒ + +### ์•„ํ‚คํ…์ฒ˜ +```mermaid +graph LR + A[MP4 ๋น„๋””์˜ค] -->|video2raw.py| B[์›๋ณธ RGB ๋ฐ”์ด๋„ˆ๋ฆฌ] + B -->|SD ์นด๋“œ| C[DE10-Nano ๋ฆฌ๋ˆ…์Šค] + C -->|video_player.c| D[DDR3 ๋ฉ”๋ชจ๋ฆฌ
0x30000000] + D -->|DMA ์ฝ๊ธฐ| E[HDMI ์ถœ๋ ฅ] + F[HPS CSR
0xFF240000] -.->|ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ
์—…๋ฐ์ดํŠธ| E +``` + +### ๊ตฌ์„ฑ ์š”์†Œ + +#### 1. ๋น„๋””์˜ค ๋ณ€ํ™˜ (`video2raw.py`) +ํ‘œ์ค€ ๋น„๋””์˜ค ํŒŒ์ผ(MP4, AVI)์„ FPGA์— ์ ํ•ฉํ•œ ์›๋ณธ RGB ํฌ๋งท์œผ๋กœ ๋ณ€ํ™˜ํ•ฉ๋‹ˆ๋‹ค. + +**๊ธฐ๋Šฅ:** +- qHD(960ร—540)๋กœ ํ•ด์ƒ๋„ ์กฐ์ ˆ +- BGRA ํฌ๋งท(ํ”ฝ์…€๋‹น 32๋น„ํŠธ)์œผ๋กœ ๋ณ€ํ™˜ +- ํ”„๋ ˆ์ž„ ์ œํ•œ ์˜ต์…˜ (`--frames N`) + +**์‚ฌ์šฉ๋ฒ•:** +```bash +python video2raw.py input.mp4 --frames 300 +``` + +#### 2. ๋น„๋””์˜ค ํ”Œ๋ ˆ์ด์–ด (`video_player.c`) +SD ์นด๋“œ์—์„œ DDR3๋กœ ๋น„๋””์˜ค ํ”„๋ ˆ์ž„์„ ์ŠคํŠธ๋ฆฌ๋ฐํ•˜๋Š” ๋ฆฌ๋ˆ…์Šค ์• ํ”Œ๋ฆฌ์ผ€์ด์…˜์œผ๋กœ, ๋”๋ธ” ๋ฒ„ํผ๋ง์„ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. + +**๋ฉ”๋ชจ๋ฆฌ ๋งคํ•‘:** +- ํ”„๋ ˆ์ž„ ๋ฒ„ํผ A: `0x30000000` (๋ฌผ๋ฆฌ ์ฃผ์†Œ) +- ํ”„๋ ˆ์ž„ ๋ฒ„ํผ B: `0x30200000` (๋ฌผ๋ฆฌ ์ฃผ์†Œ, +2MB ์˜คํ”„์…‹) +- HDMI CSR: `0xFF240000` (๋ฌผ๋ฆฌ ์ฃผ์†Œ, LWHPS2FPGA ๋ธŒ๋ฆฟ์ง€ ๊ฒฝ์œ ) + +**๋”๋ธ” ๋ฒ„ํผ๋ง ํ๋ฆ„:** +1. N๋ฒˆ์งธ ํ”„๋ ˆ์ž„์„ ๋ฐฑ ๋ฒ„ํผ(A ๋˜๋Š” B)์— ๋กœ๋“œ +2. HDMI ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ CSR์„ ๋ฐฑ ๋ฒ„ํผ ์ฃผ์†Œ๋กœ ์—…๋ฐ์ดํŠธ +3. ํ”„๋ก ํŠธ/๋ฐฑ ์ธ๋ฑ์Šค ๊ต์ฒด +4. ์•ฝ 16.6ms ๋Œ€๊ธฐ (60fps ๋ชฉํ‘œ) +5. ๋ฐ˜๋ณต + +**ํ•ต์‹ฌ ๊ตฌํ˜„ ์ƒ์„ธ:** +- **์ˆœํ™˜ ์ฝ๊ธฐ**: ํŒŒ์ผ ๋(EOF) ๋„๋‹ฌ ์‹œ ํŒŒ์ผ์„ ์ฒ˜์Œ์œผ๋กœ ๋˜๊ฐ์•„ ์ž๋™์œผ๋กœ ๋น„๋””์˜ค๋ฅผ ๋ฃจํ”„ ์žฌ์ƒํ•ฉ๋‹ˆ๋‹ค. +- **์ ์‘ํ˜• ๋Œ€๊ธฐ(Adaptive Sleep)**: ์‹ค์ œ ์ฝ๊ธฐ ์‹œ๊ฐ„์— ๋”ฐ๋ผ ๋Œ€๊ธฐ ์‹œ๊ฐ„์„ ์กฐ์ •ํ•ฉ๋‹ˆ๋‹ค. +- **์ง์ ‘ ๋ฉ”๋ชจ๋ฆฌ ์•ก์„ธ์Šค**: ์ œ๋กœ ์นดํ”ผ(Zero-copy) ์ „์†ก์„ ์œ„ํ•ด `mmap()`๊ณผ `/dev/mem`์„ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. + +## ๐ŸŽฌ ๋น„๋””์˜ค ์žฌ์ƒ ๊ตฌํ˜„ (RAM ์‚ฌ์ „ ๋กœ๋“œ ๋ฐฉ์‹) + +### ๊ฐœ์š” +**SD ์นด๋“œ ๋Œ€์—ญํญ ๋ณ‘๋ชฉ ํ˜„์ƒ (~20MB/s)**์„ ๊ทน๋ณตํ•˜๊ธฐ ์œ„ํ•ด, ๋น„๋””์˜ค ํ”Œ๋ ˆ์ด์–ด๋Š” ์ด์ œ **Store-and-Forward** ์•„ํ‚คํ…์ฒ˜(RAM ์‚ฌ์ „ ๋กœ๋“œ)๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. ์‹ค์‹œ๊ฐ„์œผ๋กœ SD ์นด๋“œ์—์„œ ์ŠคํŠธ๋ฆฌ๋ฐํ•˜๋Š” ๋Œ€์‹ , ์žฌ์ƒ ์‹œ์ž‘ ์ „ ์ „์ฒด ๋น„๋””์˜ค ํด๋ฆฝ์„ **512MB ์˜ˆ์•ฝ DDR3 ๋ฉ”๋ชจ๋ฆฌ**์— ๋ชจ๋‘ ๋กœ๋“œํ•ฉ๋‹ˆ๋‹ค. + +**์žฅ์ :** +- โœ… **์™„๋ฒฝํ•œ 60fps ์žฌ์ƒ**: ์žฌ์ƒ ์ค‘ I/O ์ง€์—ฐ์ด ์ „ํ˜€ ๋ฐœ์ƒํ•˜์ง€ ์•Š์Šต๋‹ˆ๋‹ค. +- โœ… **๋„คํŠธ์›Œํฌ ์ŠคํŠธ๋ฆฌ๋ฐ ์ง€์›**: SSH๋ฅผ ํ†ตํ•ด PC์—์„œ FPGA ๋ฉ”๋ชจ๋ฆฌ๋กœ ์ง์ ‘ ๋น„๋””์˜ค๋ฅผ ํŒŒ์ดํ•‘ํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค (`cat | ssh`). +- โŒ **์žฌ์ƒ ์‹œ๊ฐ„ ์ œํ•œ**: 512MB RAM ์ œํ•œ์œผ๋กœ ์ธํ•ด ์ตœ๋Œ€ ์•ฝ 4.1์ดˆ(250 ํ”„๋ ˆ์ž„)๊นŒ์ง€๋งŒ ๊ฐ€๋Šฅํ•ฉ๋‹ˆ๋‹ค. + +### ์‚ฌ์šฉ ๊ฐ€์ด๋“œ + +#### 1. ํ˜ธ์ŠคํŠธ ์ŠคํŠธ๋ฆฌ๋ฐ (๊ถŒ์žฅ) ๐Ÿ“ก +PC์˜ ๋น„๋””์˜ค ํŒŒ์ผ์„ SSH๋ฅผ ํ†ตํ•ด FPGA ๋ฉ”๋ชจ๋ฆฌ๋กœ ์ง์ ‘ ์ŠคํŠธ๋ฆฌ๋ฐํ•ฉ๋‹ˆ๋‹ค. SD ์นด๋“œ๋กœ ๋ณต์‚ฌํ•  ํ•„์š”๊ฐ€ ์—†์Šต๋‹ˆ๋‹ค! + +**Windows (CMD):** +```cmd +type video_qhd.bin | ssh root@192.168.x.x "./video_player -" +``` + +**Linux / macOS:** +```bash +cat video_qhd.bin | ssh root@192.168.x.x "./video_player -" +``` +*์ฐธ๊ณ : `-` ์ธ์ž๋Š” ํ”Œ๋ ˆ์ด์–ด์—๊ฒŒ ํ‘œ์ค€ ์ž…๋ ฅ(stdin)์œผ๋กœ๋ถ€ํ„ฐ ์ฝ๋„๋ก ์ง€์‹œํ•ฉ๋‹ˆ๋‹ค.* + +#### 2. ๋กœ์ปฌ ํŒŒ์ผ ์žฌ์ƒ +ํŒŒ์ผ์ด ์ด๋ฏธ SD ์นด๋“œ์— ์žˆ๋Š” ๊ฒฝ์šฐ: +```bash +./video_player video_qhd.bin +``` + +### ๊ธฐ์ˆ  ๊ตฌํ˜„ ์ƒ์„ธ + +#### ์•„ํ‚คํ…์ฒ˜ +1. **๋กœ๋“œ ๋‹จ๊ณ„**: ์ž…๋ ฅ ์ŠคํŠธ๋ฆผ(ํŒŒ์ผ ๋˜๋Š” Stdin)์„ ์ฝ์–ด `0x20000000`๋ถ€ํ„ฐ DDR3์— ์ˆœ์ฐจ์ ์œผ๋กœ ๊ธฐ๋กํ•ฉ๋‹ˆ๋‹ค. +2. **์žฌ์ƒ ๋‹จ๊ณ„**: DDR3์— ๋กœ๋“œ๋œ ํ”„๋ ˆ์ž„์„ ๋ฃจํ”„ํ•˜๋ฉฐ 16.6ms๋งˆ๋‹ค HDMI ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ CSR์„ ์—…๋ฐ์ดํŠธํ•ฉ๋‹ˆ๋‹ค. + +#### ๋ฉ”๋ชจ๋ฆฌ ๋งต +- **์˜ˆ์•ฝ RAM ๋ฒ ์ด์Šค**: `0x20000000` (1GB ์‹œ์Šคํ…œ RAM ์ค‘ ์ƒ์œ„ 512MB) +- **ํ”„๋ ˆ์ž„ ํฌ๊ธฐ**: 2,073,600 ๋ฐ”์ดํŠธ (960x540 RGBA) +- **์šฉ๋Ÿ‰**: ์•ฝ 258 ํ”„๋ ˆ์ž„ (์ด 535MB์ด๋‚˜ ์•ˆ์ „ํ•˜๊ฒŒ 512MB๋กœ ์ œํ•œ) + +#### ์ปค๋„ ์„ค์ • +๋ฆฌ๋ˆ…์Šค ์ปค๋„์ด ์ƒ์œ„ 512MB๋ฅผ ์˜ˆ์•ฝํ•˜๋„๋ก ์„ค์ •๋˜์–ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +- **๋ถ€ํŒ… ์ธ์ž(Boot Args)**: `mem=512M` +- **๊ฒฐ๊ณผ**: ๋ฆฌ๋ˆ…์Šค๋Š” `0x00000000-0x1FFFFFFF`๋ฅผ ์‚ฌ์šฉํ•˜๊ณ , ๋น„๋””์˜ค ํ”Œ๋ ˆ์ด์–ด๋Š” `0x20000000-0x3FFFFFFF`๋ฅผ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค. + +## โš ๏ธ ์„ฑ๋Šฅ ์ œํ•œ ์‚ฌํ•ญ + +### SD ์นด๋“œ ๋ณ‘๋ชฉ ํ˜„์ƒ +**ํ•„์š” ๋Œ€์—ญํญ**: 124 MB/s (60fps qHD ๊ธฐ์ค€) +**์ผ๋ฐ˜์ ์ธ SD ์นด๋“œ ์ฝ๊ธฐ ์†๋„**: 20-40 MB/s + +**๊ด€์ฐฐ๋œ ๋™์ž‘:** +1. **์ดˆ๊ธฐ ๋‹จ๊ณ„**: ๋ถ€๋“œ๋Ÿฌ์šด ์žฌ์ƒ (๋ฆฌ๋ˆ…์Šค ํŽ˜์ด์ง€ ์บ์‹œ๊ฐ€ ๋ฒ„ํผ๋ง๋œ ๋ฐ์ดํ„ฐ ์ œ๊ณต) +2. **์ง€์† ๋‹จ๊ณ„**: ์บ์‹œ ์†Œ์ง„ ์‹œ ๋Š๊น€ ํ˜„์ƒ ๋ฐœ์ƒ (์‹ค์ œ ์•ฝ 10-15 fps) + +**ํ•ด๊ฒฐ ๋ฐฉ์•ˆ:** +1. **RAM ์‚ฌ์ „ ๋กœ๋“œ (ํ˜„์žฌ ๋ฐฉ์‹)**: ์žฌ์ƒ ์ „ ์ „์ฒด ๋น„๋””์˜ค๋ฅผ DDR3๋กœ ๋กœ๋“œ +2. **ํ•ด์ƒ๋„ ๋‚ฎ์ถค**: SD ์นด๋“œ ๋Œ€์—ญํญ์— ๋งž๊ฒŒ 480p ์ดํ•˜๋กœ ์ถ•์†Œ +3. **๋‚ฎ์€ FPS ์ˆ˜์šฉ**: ๊ธด ๋น„๋””์˜ค ์ง€์›์„ ์œ„ํ•œ ํ˜„์žฌ์˜ ๋Œ€์•ˆ + +## ๐Ÿ”ง ํ•˜๋“œ์›จ์–ด ์ˆ˜์ • ์‚ฌํ•ญ + +### RTL ๋ณ€๊ฒฝ ์‚ฌํ•ญ + +#### 1. ๋“€์–ผ ํด๋ก ์•„ํ‚คํ…์ฒ˜ ([hdmi_sync_gen.v](../RTL/hdmi_sync_gen.v)) +- `clk` (50MHz): CSR ๋ ˆ์ง€์Šคํ„ฐ ์•ก์„ธ์Šค์šฉ +- `clk_pixel` (37.8MHz): HDMI ํƒ€์ด๋ฐ ์ƒ์„ฑ์šฉ +- ๋™๊ธฐํ™” ์ฒด์ธ์„ ์‚ฌ์šฉํ•œ ์ ์ ˆํ•œ ํด๋ก ๋„๋ฉ”์ธ ๊ต์ฐจ(CDC) ๊ตฌํ˜„ + +#### 2. ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ ๋ž˜์นญ (Latching) +๋ธŒ์ด์‹ฑํฌ(V-Sync) ์—ฃ์ง€์—์„œ ์‰๋„์šฐ ํฌ์ธํ„ฐ๋ฅผ ์—…๋ฐ์ดํŠธํ•˜์—ฌ ํ‹ฐ์–ด๋ง ์—†๋Š” ๋น„๋””์˜ค๋ฅผ ๋ณด์žฅํ•ฉ๋‹ˆ๋‹ค. + +### ๊ฒ€์ฆ +Cocotb ํ…Œ์ŠคํŠธ๋ฒค์น˜๋ฅผ ํ†ตํ•ด ๋‹ค์Œ ์‚ฌํ•ญ๋“ค์„ ๊ฒ€์ฆํ–ˆ์Šต๋‹ˆ๋‹ค: +- โœ… ๋“€์–ผ ํด๋ก ๋„๋ฉ”์ธ ๋™๊ธฐํ™” +- โœ… DMA ์ฝ๊ธฐ ํƒ€์ด๋ฐ ์ •๋ ฌ +- โœ… FIFO ๊นŠ์ด ์ ์ ˆ์„ฑ (1024 ์—”ํŠธ๋ฆฌ) +- โœ… ๋‹ค์ค‘ ํ”„๋ ˆ์ž„ ์บก์ฒ˜ ์ •ํ™•์„ฑ +- โœ… V-Sync ๊ธฐ๋ฐ˜ ํ”„๋ ˆ์ž„ ํฌ์ธํ„ฐ ๋ž˜์นญ + +## ๐Ÿ“Š ๊ฒฐ๊ณผ + +### ์„ฑ๊ณผ ์š”์•ฝ + +| ๊ธฐ๋Šฅ | ์ƒํƒœ | ์ƒ์„ธ ๋‚ด์šฉ | +|---------|--------|---------| +| **์ •์  ์ด๋ฏธ์ง€ (Nios II)** | โœ… ์ •์ƒ ๋™์ž‘ | DMA๋ฅผ ํ†ตํ•œ 960ร—540 RGB ์ด๋ฏธ์ง€ ์ถœ๋ ฅ | +| **๋น„๋””์˜ค ์žฌ์ƒ (๋ฆฌ๋ˆ…์Šค)** | โœ… ์ •์ƒ ๋™์ž‘ | ๋”๋ธ” ๋ฒ„ํผ๋ง ๊ธฐ๋ฐ˜ ์ŠคํŠธ๋ฆฌ๋ฐ | +| **ํ”„๋ ˆ์ž„ ๋ ˆ์ดํŠธ (์บ์‹œ๋จ)** | โœ… 60fps | ์ดˆ๊ธฐ ์žฌ์ƒ ์‹œ ์›ํ™œํ•จ | +| **ํ”„๋ ˆ์ž„ ๋ ˆ์ดํŠธ (์ง€์†๋จ)** | โš ๏ธ 10-15fps | SD ์นด๋“œ ์†๋„ ์ œํ•œ | +| **V-Sync ๋™๊ธฐํ™”** | โœ… ์ •์ƒ ๋™์ž‘ | ํ‹ฐ์–ด๋ง ํ˜„์ƒ ์—†์Œ | +| **์‹ฌ๋ฆฌ์Šค ๋ฃจํ”„** | โœ… ์ •์ƒ ๋™์ž‘ | ์ˆœํ™˜ ํŒŒ์ผ ์ฝ๊ธฐ ๊ตฌํ˜„ | + +## ๐Ÿ“ ๊ตํ›ˆ +1. **๋Œ€์—ญํญ ์˜ˆ์‚ฐ ์ˆ˜๋ฆฝ**: ์ดˆ๊ธฐ ๋‹จ๊ณ„์—์„œ ํ”ฝ์…€ ํด๋ก ์š”๊ตฌ ์‚ฌํ•ญ๊ณผ ๋ฒ„์Šค ๋Œ€์—ญํญ์„ ๋ฐ˜๋“œ์‹œ ํ™•์ธํ•ด์•ผ ํ•ฉ๋‹ˆ๋‹ค. +2. **ํด๋ก ๋„๋ฉ”์ธ ๊ต์ฐจ**: ์•ˆ์ •์ ์ธ ๋“€์–ผ ํด๋ก ๋น„๋””์˜ค ํŒŒ์ดํ”„๋ผ์ธ์„ ๊ตฌ์ถ•ํ•˜๋Š” ๋ฐ ํ•„์ˆ˜์ ์ž…๋‹ˆ๋‹ค. +3. **V-Sync ๋™๊ธฐํ™”**: ํ”„๋ ˆ์ž„ ๋ฒ„ํผ๋ฅผ ๊ต์ฒดํ•  ๋•Œ ํ‹ฐ์–ด๋ง ์—†๋Š” ์—…๋ฐ์ดํŠธ๋ฅผ ์œ„ํ•ด ๋งค์šฐ ์ค‘์š”ํ•ฉ๋‹ˆ๋‹ค. +4. **SD ์นด๋“œ ํ•œ๊ณ„**: ์›๋ณธ ๋น„๋””์˜ค๋Š” ๋ง‰๋Œ€ํ•œ ๋Œ€์—ญํญ์„ ํ•„์š”๋กœ ํ•˜๋ฏ€๋กœ, ์ง€์†์ ์ธ ์žฌ์ƒ์„ ์œ„ํ•ด์„œ๋Š” ์••์ถ• ๊ธฐ์ˆ ์ด๋‚˜ ํ•ด์ƒ๋„ ํƒ€ํ˜‘์ด ํ•„์š”ํ•ฉ๋‹ˆ๋‹ค. + +## ๐Ÿ”— ์ฐธ๊ณ  ๋ฌธํ—Œ +- [HDMI Timing Calculator](http://tinyvga.com/vga-timing) +- [ADV7513 Programming Guide](https://www.analog.com/media/en/technical-documentation/user-guides/ADV7513_Programming_Guide.pdf) + +--- +**[โฌ…๏ธ README๋กœ ๋Œ์•„๊ฐ€๊ธฐ](../README_kor.md)** From fcb7c6011851ecde3adb7fd7e77cc7316d9208ee Mon Sep 17 00:00:00 2001 From: ByungChang Cha Date: Sat, 14 Feb 2026 18:07:32 -0500 Subject: [PATCH 3/3] Create CLAUD.md --- CLAUD.md | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 CLAUD.md diff --git a/CLAUD.md b/CLAUD.md new file mode 100644 index 0000000..daced9b --- /dev/null +++ b/CLAUD.md @@ -0,0 +1,65 @@ +# CLAUDE.md + +Behavioral guidelines to reduce common LLM coding mistakes. Merge with project-specific instructions as needed. + +**Tradeoff:** These guidelines bias toward caution over speed. For trivial tasks, use judgment. + +## 1. Think Before Coding + +**Don't assume. Don't hide confusion. Surface tradeoffs.** + +Before implementing: +- State your assumptions explicitly. If uncertain, ask. +- If multiple interpretations exist, present them - don't pick silently. +- If a simpler approach exists, say so. Push back when warranted. +- If something is unclear, stop. Name what's confusing. Ask. + +## 2. Simplicity First + +**Minimum code that solves the problem. Nothing speculative.** + +- No features beyond what was asked. +- No abstractions for single-use code. +- No "flexibility" or "configurability" that wasn't requested. +- No error handling for impossible scenarios. +- If you write 200 lines and it could be 50, rewrite it. + +Ask yourself: "Would a senior engineer say this is overcomplicated?" If yes, simplify. + +## 3. Surgical Changes + +**Touch only what you must. Clean up only your own mess.** + +When editing existing code: +- Don't "improve" adjacent code, comments, or formatting. +- Don't refactor things that aren't broken. +- Match existing style, even if you'd do it differently. +- If you notice unrelated dead code, mention it - don't delete it. + +When your changes create orphans: +- Remove imports/variables/functions that YOUR changes made unused. +- Don't remove pre-existing dead code unless asked. + +The test: Every changed line should trace directly to the user's request. + +## 4. Goal-Driven Execution + +**Define success criteria. Loop until verified.** + +Transform tasks into verifiable goals: +- "Add validation" โ†’ "Write tests for invalid inputs, then make them pass" +- "Fix the bug" โ†’ "Write a test that reproduces it, then make it pass" +- "Refactor X" โ†’ "Ensure tests pass before and after" + +For multi-step tasks, state a brief plan: +``` +1. [Step] โ†’ verify: [check] +2. [Step] โ†’ verify: [check] +3. [Step] โ†’ verify: [check] +``` + +Strong success criteria let you loop independently. Weak criteria ("make it work") require constant clarification. + +--- + +**These guidelines are working if:** fewer unnecessary changes in diffs, fewer rewrites due to overcomplication, and clarifying questions come before implementation rather than after mistakes.