From eae9da70643e4a2a1be11a6091b4619745582e56 Mon Sep 17 00:00:00 2001 From: WDrijver Date: Sat, 7 Feb 2026 10:48:45 +0100 Subject: [PATCH 1/3] Enabled debug flag on sagasd --- .gitignore | 1 + arch/m68k-amiga/boot/romlog.txt | 4 ++-- arch/m68k-amiga/devs/sagasd/sd.h | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 9f01f0cc39..8534e84f30 100644 --- a/.gitignore +++ b/.gitignore @@ -2155,3 +2155,4 @@ workbench/tools/InstallAROS/strings.h workbench/tools/SysExplorer/strings.h workbench/tools/WiMP/strings.h arch/m68k-amiga/boot/romlog.txt +arch/m68k-amiga/boot/romlog.txt diff --git a/arch/m68k-amiga/boot/romlog.txt b/arch/m68k-amiga/boot/romlog.txt index ae841c513d..fea4d642bb 100644 --- a/arch/m68k-amiga/boot/romlog.txt +++ b/arch/m68k-amiga/boot/romlog.txt @@ -1,3 +1,3 @@ Idx Name Size VMA LMA File off Algn - 0 .rom 0007a2a0 00f80000 00f80000 00080000 2**2 - 1 .ext 0007d90e 00e00000 00e00000 00002000 2**2 + 0 .rom 00078c9c 00f80000 00f80000 0007c000 2**2 + 1 .ext 0007822a 00e00000 00e00000 00002000 2**2 diff --git a/arch/m68k-amiga/devs/sagasd/sd.h b/arch/m68k-amiga/devs/sagasd/sd.h index 866bd41996..ccf5a241db 100644 --- a/arch/m68k-amiga/devs/sagasd/sd.h +++ b/arch/m68k-amiga/devs/sagasd/sd.h @@ -51,7 +51,7 @@ #define IOStdReq(io) ((struct IOStdReq *)io) #if APOLLO_DEBUG -#define DEBUG 0 +#define DEBUG 1 #else #define DEBUG 0 #endif From 4dd899d09fa4fac0679e55d65e54ae0c5a9508b7 Mon Sep 17 00:00:00 2001 From: WDrijver Date: Mon, 2 Mar 2026 14:30:32 +0100 Subject: [PATCH 2/3] fs-cache --- arch/m68k-amiga/boot/romlog.txt | 4 +- rom/devs/ata/ata.c | 259 +++++++++++++++++++----- rom/devs/ata/ata.h | 11 +- rom/devs/ata/ata_init.c | 13 ++ rom/devs/ata/scsiemu.c | 111 ++++++++-- version | 2 +- workbench/libs/lowlevel/elapsedtime.c | 2 +- workbench/system/find/findgroup_class.h | 17 +- 8 files changed, 342 insertions(+), 77 deletions(-) mode change 100755 => 100644 rom/devs/ata/ata.c mode change 100755 => 100644 rom/devs/ata/ata.h mode change 100755 => 100644 rom/devs/ata/scsiemu.c diff --git a/arch/m68k-amiga/boot/romlog.txt b/arch/m68k-amiga/boot/romlog.txt index fea4d642bb..21025b312d 100644 --- a/arch/m68k-amiga/boot/romlog.txt +++ b/arch/m68k-amiga/boot/romlog.txt @@ -1,3 +1,3 @@ Idx Name Size VMA LMA File off Algn - 0 .rom 00078c9c 00f80000 00f80000 0007c000 2**2 - 1 .ext 0007822a 00e00000 00e00000 00002000 2**2 + 0 .rom 0007a2a0 00f80000 00f80000 00082000 2**2 + 1 .ext 0007f23e 00e00000 00e00000 00002000 2**2 diff --git a/rom/devs/ata/ata.c b/rom/devs/ata/ata.c old mode 100755 new mode 100644 index ca514d3ce4..ec13e6fe02 --- a/rom/devs/ata/ata.c +++ b/rom/devs/ata/ata.c @@ -92,26 +92,62 @@ static void cmd_Read32(struct IORequest *io, LIBBASETYPEPTR LIBBASE) struct ata_Bus *bus = unit->au_Bus; struct ataBase *base = bus->ab_Base; ULONG unitNum = unit->au_UnitNum; - + ULONG CACHE_SIZE8 = base->CACHE_SIZE8; + base->myway = ( base->myway +1) & 7; // 8 way for good + ULONG start; ULONG i; for (start = 0, i = 0; i < count; i++) { - ULONG blockAdr = (block + i) & CACHE_MASK; - UQUAD blockTag = (block + i) & ~CACHE_MASK; - - if ((unitNum < (1<<9)) && - (base->ata_CacheTags[blockAdr] == (blockTag | unitNum))) /* cache hit */ + ULONG blockAdr = (block + i) & (CACHE_SIZE8-1); // MASK + ULONG blockAdr0 = blockAdr; + ULONG blockAdr1 = blockAdr + CACHE_SIZE8; + ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2; + ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3; + ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4; + ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5; + ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6; + ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7; + + UQUAD blockTag = (block + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; // MASKING + + if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr0] == blockTag )) /* cache hit */ { - CopyMem(base->ata_CacheData + blockAdr*512, IOStdReq(io)->io_Data + i*512, 512); + CopyMem(base->ata_CacheData + blockAdr0 * 512, IOStdReq(io)->io_Data + i*512, 512); start = i + 1; - } - else + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr1] == blockTag )) /* cache hit */ { + CopyMem(base->ata_CacheData + blockAdr1 * 512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr2] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr2 * 512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr3] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr3 * 512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr4] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr4 * 512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr5] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr5 * 512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr6] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr6 * 512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr7] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr7 * 512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + } else { i = count; break; - } + } } if (start != i) @@ -128,11 +164,13 @@ static void cmd_Read32(struct IORequest *io, LIBBASETYPEPTR LIBBASE) for (ULONG j = start; j < i; j++) { - ULONG blockAdr = (block + j) & CACHE_MASK; + ULONG blockAdr = (block + j) & (CACHE_SIZE8-1); + blockAdr += CACHE_SIZE8 * (base->myway &7); // random 4 way + CopyMem(IOStdReq(io)->io_Data + j*512, base->ata_CacheData + blockAdr*512, 512); - blockAdr = (block + j) & CACHE_MASK; - ULONG blockTag = (block + j) & ~CACHE_MASK; - base->ata_CacheTags[blockAdr] = blockTag | unitNum; + UQUAD blockTag = (block + j) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; + base->ata_CacheTags[blockAdr] = blockTag; + } } cnt = count << unit->au_SectorShift; @@ -199,27 +237,70 @@ static void cmd_Read64(struct IORequest *io, LIBBASETYPEPTR LIBBASE) struct ata_Bus *bus = unit->au_Bus; struct ataBase *base = bus->ab_Base; ULONG unitNum = unit->au_UnitNum; + ULONG CACHE_SIZE8 = base->CACHE_SIZE8; + + base->myway = (base->myway +1) & 7; // 7 way for good ULONG start; ULONG i; + for (start = 0, i = 0; i < count; i++) { - ULONG blockAdr = (block + i) & CACHE_MASK; - UQUAD blockTag = (block + i) & ~CACHE_MASK; - - if ((unitNum < (1<<9)) && - (base->ata_CacheTags[blockAdr] == (blockTag | unitNum))) /* cache hit */ + ULONG blockAdr = (block + i) & (CACHE_SIZE8-1); //MASK + ULONG blockAdr0 = blockAdr; + ULONG blockAdr1 = blockAdr + CACHE_SIZE8; + ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2; + ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3; + ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4; + ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5; + ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6; + ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7; + + UQUAD blockTag = (block + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; //MASKING + + if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr0] == blockTag )) /* cache hit */ { - CopyMem(base->ata_CacheData + blockAdr*512, IOStdReq(io)->io_Data + i*512, 512); + CopyMem(base->ata_CacheData + blockAdr0*512, IOStdReq(io)->io_Data + i*512, 512); start = i + 1; - } - else + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr1] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr1*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr2] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr2*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr3] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr3*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr4] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr4*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr5] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr5*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr6] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr6*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr7] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr7*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + } else { i = count; break; } } + + + + if (start != i) { /* Call the Unit's access funtion */ @@ -234,12 +315,12 @@ static void cmd_Read64(struct IORequest *io, LIBBASETYPEPTR LIBBASE) for (ULONG j = start; j < i; j++) { - ULONG blockAdr = (block + j) & CACHE_MASK; + ULONG blockAdr = (block + j) & (CACHE_SIZE8-1); // MASK + blockAdr += CACHE_SIZE8 * (base->myway & 7); // random 8 way CopyMem(IOStdReq(io)->io_Data + j*512, base->ata_CacheData + blockAdr*512, 512); - blockAdr = (block + j) & CACHE_MASK; - ULONG blockTag = (block + j) & ~CACHE_MASK; - base->ata_CacheTags[blockAdr] = blockTag | unitNum; - } + UQUAD blockTag = (block + j) & ~(((UQUAD)CACHE_SIZE8)-1) |unitNum; + base->ata_CacheTags[blockAdr] = blockTag; + } } cnt = count << unit->au_SectorShift; } @@ -261,19 +342,55 @@ static void cmd_Read64(struct IORequest *io, LIBBASETYPEPTR LIBBASE) { struct ata_Bus *bus = unit->au_Bus; struct ataBase *base = bus->ab_Base; - ULONG unitNum = unit->au_UnitNum; + ULONG CACHE_SIZE8 = base->CACHE_SIZE8; + ULONG unitNum = unit->au_UnitNum; ULONG start; ULONG i; for (start = 0, i = 0; i < count; i++) { - ULONG blockAdr = (block + i) & CACHE_MASK; - UQUAD blockTag = (block + i) & ~CACHE_MASK; - - if ((unitNum < (1<<9)) && - (base->ata_CacheTags[blockAdr] == (blockTag | unitNum ))) /* cache hit */ + ULONG blockAdr = (block + i) & (CACHE_SIZE8-1); //MASK + ULONG blockAdr0 = blockAdr; + ULONG blockAdr1 = blockAdr + CACHE_SIZE8; + ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2; + ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3; + ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4; + ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5; + ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6; + ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7; + UQUAD blockTag = (block + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum ; + + if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr0] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr0*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr1] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr1*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr2] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr2*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr3] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr3*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr4] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr4*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr5] == blockTag )) /* cache hit */ { - CopyMem(base->ata_CacheData + blockAdr*512, IOStdReq(io)->io_Data + i*512, 512); + CopyMem(base->ata_CacheData + blockAdr5*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr6] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr6*512, IOStdReq(io)->io_Data + i*512, 512); + start = i + 1; + }else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr7] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr7*512, IOStdReq(io)->io_Data + i*512, 512); start = i + 1; } else @@ -281,6 +398,9 @@ static void cmd_Read64(struct IORequest *io, LIBBASETYPEPTR LIBBASE) i = count; break; } + + + } if (start != i) @@ -297,12 +417,12 @@ static void cmd_Read64(struct IORequest *io, LIBBASETYPEPTR LIBBASE) for (ULONG j = start; j < i; j++) { - ULONG blockAdr = (block + j) & CACHE_MASK; + ULONG blockAdr = (block + j) & (CACHE_SIZE8-1); + blockAdr += CACHE_SIZE8 * (base->myway &7); // random 8 way CopyMem(IOStdReq(io)->io_Data + j*512, base->ata_CacheData + blockAdr*512, 512); - blockAdr = (block + j) & CACHE_MASK; - ULONG blockTag = (block + j) & ~CACHE_MASK; - base->ata_CacheTags[blockAdr] = blockTag | unitNum; - } + UQUAD blockTag = (block + j) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; + base->ata_CacheTags[blockAdr] = blockTag; + } } cnt = count << unit->au_SectorShift; } @@ -365,13 +485,36 @@ static void cmd_Write32(struct IORequest *io, LIBBASETYPEPTR LIBBASE) if ((unit->au_SectorShift == 9) && ((unit->au_XferModes & AF_XFER_PACKET)==0)) { - struct ata_Bus *bus = unit->au_Bus; - struct ataBase *base = bus->ab_Base; + struct ata_Bus *bus = unit->au_Bus; + struct ataBase *base = bus->ab_Base; + ULONG CACHE_SIZE8 = base->CACHE_SIZE8; + + ULONG unitNum = unit->au_UnitNum; + for (int i = 0; i < count; i++) { - ULONG blockAdr = (block + i) & CACHE_MASK; - base->ata_CacheTags[blockAdr] = 0xfffffffffffffffful; + ULONG blockAdr = (block + i) & (CACHE_SIZE8-1); // MASK + ULONG blockAdr0 = blockAdr; + ULONG blockAdr1 = blockAdr + CACHE_SIZE8; + ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2; + ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3; + ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4; + ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5; + ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6; + ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7; + + UQUAD blockTag = (block + i) & ~(((QUAD)CACHE_SIZE8)-1) | unitNum; + if( base->ata_CacheTags[blockAdr0] == blockTag ){ base->ata_CacheTags[blockAdr0] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr1] == blockTag ){ base->ata_CacheTags[blockAdr1] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr2] == blockTag ){ base->ata_CacheTags[blockAdr2] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr3] == blockTag ){ base->ata_CacheTags[blockAdr3] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr4] == blockTag ){ base->ata_CacheTags[blockAdr4] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr5] == blockTag ){ base->ata_CacheTags[blockAdr5] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr6] == blockTag ){ base->ata_CacheTags[blockAdr6] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr7] == blockTag ){ base->ata_CacheTags[blockAdr7] = 0xfffffffffffffffful; } } + + } IOStdReq(io)->io_Actual = cnt; @@ -450,11 +593,31 @@ static void cmd_Write64(struct IORequest *io, LIBBASETYPEPTR LIBBASE) { struct ata_Bus *bus = unit->au_Bus; struct ataBase *base = bus->ab_Base; - for (int i = 0; i < count; i++) + ULONG CACHE_SIZE8 = base->CACHE_SIZE8; + ULONG unitNum = unit->au_UnitNum; + for (int i = 0; i < count ; i++) { - ULONG blockAdr = (block + i) & CACHE_MASK; - base->ata_CacheTags[blockAdr] = 0xfffffffffffffffful; + ULONG blockAdr = (block + i) & (CACHE_SIZE8-1); // MASK + ULONG blockAdr0 = blockAdr; + ULONG blockAdr1 = blockAdr + CACHE_SIZE8; + ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2; + ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3; + ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4; + ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5; + ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6; + ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7; + UQUAD blockTag = (block + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; + if( base->ata_CacheTags[blockAdr0] == blockTag ){ base->ata_CacheTags[blockAdr0] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr1] == blockTag ){ base->ata_CacheTags[blockAdr1] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr2] == blockTag ){ base->ata_CacheTags[blockAdr2] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr3] == blockTag ){ base->ata_CacheTags[blockAdr3] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr4] == blockTag ){ base->ata_CacheTags[blockAdr4] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr5] == blockTag ){ base->ata_CacheTags[blockAdr5] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr6] == blockTag ){ base->ata_CacheTags[blockAdr6] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr7] == blockTag ){ base->ata_CacheTags[blockAdr7] = 0xfffffffffffffffful; } } + + } IOStdReq(io)->io_Actual = cnt; @@ -598,7 +761,7 @@ static void cmd_AddChangeInt(struct IORequest *io, LIBBASETYPEPTR LIBBASE) ForeachNode(&unit->au_SoftList, msg) { - D(bug("[ATA%02ld] : Handler Entry added in unit->au_SoftList: handler = %x | unit = %d\n", ((struct ata_Unit*)io->io_Unit)->au_UnitNum, (struct Interrupt *)IOStdReq(msg)->io_Data, unit->au_UnitNum)); + D(bug("[ATA%02ld] Handler Entry added in unit->au_SoftList: handler = %x | unit = %d\n", ((struct ata_Unit*)io->io_Unit)->au_UnitNum, (struct Interrupt *)IOStdReq(msg)->io_Data, unit->au_UnitNum);) } io->io_Flags &= ~IOF_QUICK; @@ -1391,4 +1554,4 @@ void BusTaskCode2(struct ata_Bus *bus, struct ataBase *ATABase) bus->ab_Flags &= ~(UNITF_INTASK | UNITF_ACTIVE); } } -} \ No newline at end of file +} diff --git a/rom/devs/ata/ata.h b/rom/devs/ata/ata.h old mode 100755 new mode 100644 index 5a93a29a4f..1db98d6656 --- a/rom/devs/ata/ata.h +++ b/rom/devs/ata/ata.h @@ -39,14 +39,7 @@ #define TASK_PRI 10 #define TIMEOUT 30 -#if VAMPIRECARDSERIES==2 -#define CACHE_SIZE_BITS 14 /* V2 = 2^14 * 512 byte blocks = 8Mb */ -#else -#define CACHE_SIZE_BITS 17 /* V4 = 2^17 * 512 byte blocks = 64Mb */ -#endif - -#define CACHE_SIZE (1<>3)-1) #if APOLLO_DEBUG #define DEBUG 1 @@ -121,6 +114,8 @@ struct ataBase */ UBYTE *ata_CacheData; UQUAD *ata_CacheTags; + ULONG myway; + ULONG CACHE_SIZE8; ULONG ata_ItersPer100ns; diff --git a/rom/devs/ata/ata_init.c b/rom/devs/ata/ata_init.c index c4855bc3ff..e1fd2cd941 100644 --- a/rom/devs/ata/ata_init.c +++ b/rom/devs/ata/ata_init.c @@ -221,6 +221,19 @@ static int ATA_init(struct ataBase *ATABase) DATAINIT(bug("[ATA--] %s: MemPool @ %p\n", __func__, ATABase->ata_MemPool)); + // Was bin ich? + // + ULONG CACHE_SIZE = (1<<20); // 512 MB + volatile UBYTE *wasbinich=0xDFF3FC; + UBYTE ichbin = *wasbinich; + if ( ichbin==0x08) { // Einhorn + CACHE_SIZE = (1<<20); // 512 MB + }else{ + CACHE_SIZE = (1<<17); // 64 MB + } + ATABase->CACHE_SIZE8 = (CACHE_SIZE>>3); // set size of 1 way of (8way cache) + + /* * ata drive cache memory allocation */ diff --git a/rom/devs/ata/scsiemu.c b/rom/devs/ata/scsiemu.c old mode 100755 new mode 100644 index cd511b93f9..41670816e7 --- a/rom/devs/ata/scsiemu.c +++ b/rom/devs/ata/scsiemu.c @@ -52,26 +52,80 @@ static UBYTE scsi_read32(struct ata_Unit *unit, APTR data, ULONG offset, ULONG l { struct ata_Bus *bus = unit->au_Bus; struct ataBase *base = bus->ab_Base; - ULONG unitNum = unit->au_UnitNum; + ULONG CACHE_SIZE8 = base->CACHE_SIZE8; + + ULONG unitNum = unit->au_UnitNum; + + base->myway = ( base->myway+1) & 7; // 8 way for good + ULONG start; ULONG i; for (start = 0, i = 0; i < len; i++) { - ULONG blockAdr = (offset + i) & CACHE_MASK; - UQUAD blockTag = (offset + i) & ~CACHE_MASK; + ULONG blockAdr = (offset + i) & (CACHE_SIZE8-1); //MASK + ULONG blockAdr0 = blockAdr; + ULONG blockAdr1 = blockAdr + CACHE_SIZE8; + ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2; + ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3; + ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4; + ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5; + ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6; + ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7; + + + + UQUAD blockTag = (offset + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; + // 8 way disk cache 512 MB default + // + if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr0] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr0*512, data + i*512, 512); + start = i + 1; - if ((unitNum < (1<<9)) && - (base->ata_CacheTags[blockAdr] == (blockTag | unitNum))) /* cache hit */ + } + else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr1] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr1*512, data + i*512, 512); + start = i + 1; + } + else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr2] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr2*512, data + i*512, 512); + start = i + 1; + } + else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr3] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr3*512, data + i*512, 512); + start = i + 1; + } + else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr4] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr4*512, data + i*512, 512); + start = i + 1; + } + else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr5] == blockTag )) /* cache hit */ { - CopyMem(base->ata_CacheData + blockAdr*512, data + i*512, 512); + CopyMem(base->ata_CacheData + blockAdr5*512, data + i*512, 512); + start = i + 1; + } + else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr6] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr6*512, data + i*512, 512); + start = i + 1; + } + else if ((unitNum < (1<<9)) && (base->ata_CacheTags[blockAdr7] == blockTag )) /* cache hit */ + { + CopyMem(base->ata_CacheData + blockAdr7*512, data + i*512, 512); start = i + 1; } else { i = len; break; - } + } + + } if (start != i) { @@ -86,12 +140,14 @@ static UBYTE scsi_read32(struct ata_Unit *unit, APTR data, ULONG offset, ULONG l for (ULONG j = start; j < i; j++) { - ULONG blockAdr = (offset + j) & CACHE_MASK; + + ULONG blockAdr = (offset + j) & (CACHE_SIZE8-1); + blockAdr += CACHE_SIZE8 * (base->myway & 7); // random 8 way CopyMem(data + j*512, base->ata_CacheData + blockAdr*512, 512); - blockAdr = (offset + j) & CACHE_MASK; - ULONG blockTag = (offset + j) & ~CACHE_MASK; - base->ata_CacheTags[blockAdr] = blockTag | unitNum; - } + UQUAD blockTag = (offset + j) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; + base->ata_CacheTags[blockAdr] = blockTag; + + } } *outlen = len << unit->au_SectorShift; return io_Error; @@ -118,12 +174,35 @@ static UBYTE scsi_write32(struct ata_Unit *unit, APTR data, ULONG offset, ULONG { struct ata_Bus *bus = unit->au_Bus; struct ataBase *base = bus->ab_Base; - - for (int i = 0; i < len; i++) + ULONG CACHE_SIZE8 = base->CACHE_SIZE8; + + ULONG unitNum = unit->au_UnitNum; + + for (int i = 0; i < len ; i++ ) { - ULONG blockAdr = (offset + i) & CACHE_MASK; - base->ata_CacheTags[blockAdr] = 0xfffffffffffffffful; + ULONG blockAdr = (offset + i) & (CACHE_SIZE8-1); // MASK + ULONG blockAdr0 = blockAdr; + ULONG blockAdr1 = blockAdr + CACHE_SIZE8; + ULONG blockAdr2 = blockAdr + CACHE_SIZE8*2; + ULONG blockAdr3 = blockAdr + CACHE_SIZE8*3; + ULONG blockAdr4 = blockAdr + CACHE_SIZE8*4; + ULONG blockAdr5 = blockAdr + CACHE_SIZE8*5; + ULONG blockAdr6 = blockAdr + CACHE_SIZE8*6; + ULONG blockAdr7 = blockAdr + CACHE_SIZE8*7; + + UQUAD blockTag = (offset + i) & ~(((UQUAD)CACHE_SIZE8)-1) | unitNum; + if( base->ata_CacheTags[blockAdr0] == blockTag ){ base->ata_CacheTags[blockAdr0] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr1] == blockTag ){ base->ata_CacheTags[blockAdr1] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr2] == blockTag ){ base->ata_CacheTags[blockAdr2] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr3] == blockTag ){ base->ata_CacheTags[blockAdr3] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr4] == blockTag ){ base->ata_CacheTags[blockAdr4] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr5] == blockTag ){ base->ata_CacheTags[blockAdr5] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr6] == blockTag ){ base->ata_CacheTags[blockAdr6] = 0xfffffffffffffffful; } + if( base->ata_CacheTags[blockAdr7] == blockTag ){ base->ata_CacheTags[blockAdr7] = 0xfffffffffffffffful; } + } + + } err = unit->au_Write32(unit, offset, len, data, outlen); diff --git a/version b/version index cea7efb494..ae1748dc3f 100755 --- a/version +++ b/version @@ -1 +1 @@ -Release 9.51 +Release 9.6 diff --git a/workbench/libs/lowlevel/elapsedtime.c b/workbench/libs/lowlevel/elapsedtime.c index db485ff0af..94d906820e 100644 --- a/workbench/libs/lowlevel/elapsedtime.c +++ b/workbench/libs/lowlevel/elapsedtime.c @@ -49,7 +49,7 @@ SubTime(&b, tlast); *tlast = a; - return b.tv_secs*1000 + b.tv_micro/1000; + return (b.tv_secs << 16) | (b.tv_micro*1024/15625); // Patch by Apollo Team (@Morten) AROS_LIBFUNC_EXIT } /* ElapsedTime */ diff --git a/workbench/system/find/findgroup_class.h b/workbench/system/find/findgroup_class.h index 61d9fe9148..2974a2cc8a 100644 --- a/workbench/system/find/findgroup_class.h +++ b/workbench/system/find/findgroup_class.h @@ -2,10 +2,25 @@ #define FINDGROUP_CLASS_H /* - Copyright © 2016, The AROS Development Team. All rights reserved. + Copyright � 2016, The AROS Development Team. All rights reserved. $Id$ */ +#if APOLLO_DEBUG +#define DEBUG 1 +#else +#define DEBUG 0 +#endif + +#if DEBUG +#include +#define DD(x) x +#define bug kprintf +#else +#define DD(x) +#define bug +#endif + #include #include From 1200c44e70969fab7e597287283cb5a817e57cc7 Mon Sep 17 00:00:00 2001 From: WDrijver Date: Mon, 2 Mar 2026 14:32:28 +0100 Subject: [PATCH 3/3] RC01 --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index ae1748dc3f..a683fd198b 100755 --- a/version +++ b/version @@ -1 +1 @@ -Release 9.6 +Release 9.6-RC01